Level switching circuit for controlling a power switch

Abstract

A level shifting device (100) for controlling a power switch includes a switch (140), a control pulse transmission channel (150), a noise transmission channel (130), and a noise suppression circuit (170). The device has two embodiments: in one embodiment, the device further comprises a current generator (120); in another embodiment, the apparatus includes a switchable current generator (1120). The result is that the device achieves a high degree of noise immunity with almost no power consumption.

Description

Technical Field

[0001] The proposed invention is related to power electronics and can be used in secondary power supplies, frequency converters, HVAC systems, and other industrial and consumer devices. The proposed design is intended to be used in power switches to transfer low-level pulse signals to high voltage levels to control the power switches which can be composed of MOSFETs, silicon carbide (SiC) FETs, gallium nitride (GaN) FETs, insulated gate bipolar transistors (IGBTs), etc. Background Art

[0002] Today, power electronics technology uses power switches in many cases - semiconductor devices that perform pulse switching by turning power circuits off and on.

[0003] The power switches are controlled by low level pulses while high voltage transistors are used to switch the power circuits.

[0004] The widely used power switch has two high voltage transistors, one of which (the high level transistor) can be connected to the high voltage power supply. The conversion of the low voltage pulse signal controlled by the transistor to a high level is completed by a level conversion circuit (LSC), which can include an RS flip-flop.

[0005] As is known to all, power switches generate high-intensity pulse interference during operation, which is caused by high-level transistor switching or breakdown of these transistors (in this case, multi-pulse interference will be generated) or other reasons. The input of the RS flip-flop is easily affected by these interferences, which will cause the RS flip-flop to respond incorrectly, causing catastrophic failure of the power switch and the device using the flip-flop as a whole.

[0006] The immunity of LSCs to switching and other disturbances is measured by the acceptable disturbance rise rate dV / dt [V / ns] for a particular device. For most LSCs using RS triggers, the standard value for this value is dV / dt = 50V / ns. However, in modern power electronics, high-speed SiCFETs and GaNFETs are increasingly used, and it is necessary to ensure that their dV / dt is as high as 200V / ns. Therefore, it is a challenge to develop LSCs without RS triggers for power switches with high disturbance rise rates dV / dt [V / ns], which brings opportunities for the development of trouble-free power electronic devices.

[0007] To facilitate further explanation, some of the terms used are explained below.

[0008] The upper transistor, ie the upper transistor - the high voltage transistor of the power switch, is connected to the high voltage source via one of its electrodes directly or via a capacitor.

[0009] The lower transistor, ie the lower transistor - the high voltage transistor of the power switch, is connected to the common conductor of the LSC via one of its electrodes.

[0010] Upper floating high voltage - the power supply of the device, its level relative to the LSC common line depends on whether there is a control pulse.

[0011] Upper floating bias voltage - the voltage at the junction of the upper and lower transistors, whose level relative to the LSC common line depends on the presence or absence of a control pulse.

[0012] Switch closed - the resistance of the switch is very small.

[0013] Switch open - switch resistance is high.

[0014] The first electrode of the transistor - the drain of the field effect transistor and the collector of the bipolar transistor.

[0015] The second control electrode of the transistor - the gate of a field effect transistor and the base of a bipolar transistor.

[0016] The third electrode of the transistor - the source of the field effect transistor and the emitter of the bipolar transistor.

[0017] Controllable Current Generator - A current generator having a control input, the value of the current depending on the presence or absence of a pulse at the control input.

[0018] Many LSC designs are known in the art.

[0019] For example, many integrated circuits (see International Rectifier - Current Limited Single Channel Driver" IR2125(S) & (PbF) Data Sheet, No. PD60017 Rev.Q, September 12, 2004 or Semiconductor - "FAN7083-GF085 High-Side Gate Driver with Reset", September 2017, Revision 2, and many others) have adopted this design, which includes a dual-output short pulse generator, first and second switches, first and second resistors, a dual-input pulse filter, an RS flip-flop, an output stage and a first terminal for receiving a low-voltage power supply.

[0020] In the design (simulation device), the input terminal of the short pulse generator is electrically connected to the second terminal of the simulation device; the second control terminal of the first switch is connected to the first output terminal of the short pulse generator; the second control terminal of the second switch is connected to the second output terminal of the short pulse generator;

[0021] The first terminals of the first and second switches are connected to the third terminal of the device simulation, and the third terminals of the first and second switches are connected to the first terminals of the first and second resistors, respectively;

[0022] The second terminals of the first and second resistors are connected to the fourth terminal of the device simulation; the connection point of the switch and the resistor is connected to the input of the pulse filter, and its output is connected to the input of the RS trigger; the output of the RS trigger is connected to the output stage, and its output is connected to the fifth terminal of the device simulation, and the power supply terminal of the output stage is connected to the fourth and sixth terminals of the device simulation.

[0023] The common feature of the first proposed technical design and the device simulation is a switch. Meanwhile, the second control terminal of the switch is connected to the control input terminal of the device.

[0024] The common feature of the second proposed technical design and the device simulation is also a switch. At the same time, the second control terminal of the switch is connected to the control input terminal of the device.

[0025] The known device has the disadvantage of low immunity to interference in the presence of high-intensity internal and external interference (dV / dt values ​​not exceeding 50 V / nsec). At the same time, the inclusion of an RS trigger in the structure of the analog device can lead to catastrophic failure of the power switch and the entire device.

[0026] Also known is a device simulation technology design disclosed by Zhang Yunwu et al. in the article "An Improved Noise-Resistant Level Shifting Structure for 600V High-Voltage Integrated Circuits" published in the 34th issue of the "Journal of Semiconductors" on June 6, 2013.

[0027] The device (see publication Figure 1 )include

[0028] A short pulse generator with two outputs; a first and a second switch; a first and a second resistor; a pulse filter with two inputs; an RS trigger; a first and a second diode, respectively connected in parallel with the first and the second resistor; an interference suppression circuit; and a first terminal for receiving a low voltage power supply.

[0029] In the device, the input terminal of the short pulse generator is connected to the second terminal of the analog device; the second control terminal of the first switch is connected to the first output terminal of the short pulse generator; the second control terminal of the second switch is connected to the second output terminal of the short pulse generator;

[0030] The first terminals of the first and second switches are connected to the third terminal of the analog device;

[0031] The third ends of the first and second switches are respectively connected to the first ends of the first and second resistors and the input end of the interference suppression circuit, and the output end of the interference suppression circuit is connected to the input end of the pulse filter; the second ends of the first and second resistors are connected to the fourth end of the device simulation; the output end of the pulse filter is connected to the input end of the RS trigger; the output end of the RS trigger is connected to the fifth end of the device simulation, which is the output end of the device.

[0032] The common features of the first proposed technical design and the device simulation are the switch and the interference suppression circuit, and the connection of the second control terminal of the switch to the control input terminal of the device.

[0033] The common features of the second proposed technical design and the device simulation are the switch and the interference suppression circuit, and the connection of the second control terminal of the switch to the control input terminal of the device.

[0034] However, the device simulation device does not provide sufficient interference immunity in the presence of high-intensity internal and external interferences, because according to the above reference, dV / dt does not exceed 65V / ns.

[0035] Also known is a fast voltage level converter circuit disclosed in US9,564,882, published on February 7, 2017. The analog circuit includes (see publication Figure 3 a): a current generator, an inverter, a first and a second switch, a first and a second resistor, a first and a second capacitor, a current setter (such as Figure 3 b) and the first and second diodes.

[0036] The output end of the current setter is connected to the control input end of the current generator; the input end of the current generator is connected to the first ends of the first and second switches; the output end of the current generator is connected to the common line of the circuit; the second control end of the first switch is directly connected to the control input end of the circuit, and the second control end of the second switch is connected to the control input end of the circuit through an inverter.

[0037] The third terminals of the first and second switches are connected to the first terminals of the first and second resistors, respectively.

[0038] The first terminal and the second terminal of the second terminal are connected to a circuit terminal receiving power. The anodes of the diodes are connected to each other and to the output of the circuit, and the cathodes of the first and second diodes are connected to the first and second terminals of the first and second resistors, respectively.

[0039] The first and second capacitors are connected in parallel with the first and second resistors, respectively.

[0040] The common features of the first proposed technology design and circuit simulation are a current generator and a switch. The input terminal of the current generator is connected to a first terminal of the switch, the output terminal of the current generator is connected to a common line of the circuit, and the second control terminal of the switch is connected to a control input terminal of the circuit.

[0041] The second common feature of the proposed technology design and the circuit simulation is a switch. The second control terminal of the switch is connected to the control input terminal of the circuit.

[0042] One disadvantage of circuit simulation is the increased energy consumption caused by the two resistors through which a current constantly flows, caused by a voltage equal to the potential difference between the fourth and third terminals of the circuit, which can be as high as several hundred volts.

[0043] Another drawback of analog circuits is that the parasitic capacitance of the transistors used for the first and second switches can cause current surges. These surges can cause one of the switches to crash or produce erroneous circuit output signals.

[0044] The LSC disclosed in US Patent No. 9,264,022 published on February 16, 2016 is considered to be the closest simulation device (prototype). Figure 1 As shown, the Figure 1 Correspondingly, it includes a current setter, a current generator, a first and a second surge suppression circuit, a first and a second inverter, a first and a second switch, a first and a second resistor, an output stage and a first terminal for receiving a low voltage power supply. The output terminal of the current setter is connected to the control input terminal of the current generator, the first and the second input terminals of the current generator are respectively connected to the first terminals of the first and the second switches, and the output terminal of the current generator is connected to the third terminal of the device prototype.

[0045] Connected to the first terminals of the first and second switches are first and second surge suppression circuits, respectively.

[0046] The second control terminal of the first switch is connected to the second terminal of the device prototype through the first inverter. The second control terminal of the second switch is connected to the second terminal of the device prototype through the first and second inverters connected in series.

[0047] The third terminals of the first and second switches are connected to the first terminals of the first and second resistors, respectively, and the second terminals of the first and second resistors are connected to the fourth terminal of the device prototype. The connection point of the switches and the resistors is connected to the input terminal of the output stage, the output terminal of the output stage is connected to the fifth terminal of the device prototype, and the power supply input terminal of the output stage is connected to the fourth and sixth terminals of the device prototype.

[0048] The common features of the first proposed technology design and the device prototype are a current generator and a switch.

[0049] The input end of the current generator is connected to the first end of the switch, the output end of the current generator is connected to the third end of the device, and the second control end of the switch is connected to the second end of the device.

[0050] The common feature of the second proposed technical design and the device prototype is a switch. Therefore, the second control terminal of the switch is connected to the second terminal of the device.

[0051] A disadvantage of this arrangement is that it increases energy consumption due to the constant alternating flow of current through the first and second resistors, the current being caused by the potential difference between the fourth and third terminals of the circuit, which can be as high as several hundred volts. Summary of the invention

[0052] The object of the present invention is to overcome the disadvantages of the known devices and to provide an LSC with a stronger anti-interference capability and a lower power consumption (comparable to the power consumption of an LSC using an RS trigger).

[0053] The technical achievements that can be achieved by the circuit of the present invention are unachievable by the known circuits, and the circuit can not only suppress high-intensity pulse interference with a high rise rate, but also reduce power consumption.

[0054] It is believed that the prior art designs have failed to achieve the above technical results because their goals are either to operate stably under high-intensity pulse interference with a high rise rate (at the expense of increased power consumption) or to reduce power consumption (at the expense of reduced fault safety), while achieving both goals simultaneously is not a problem.

[0055] In the first embodiment of the proposed LSC (also referred to as "device") for controlling a power switch, the above technical achievements are achieved by additionally providing an interference transmission channel, a control pulse transmission channel and an interference suppression circuit in the first device consisting of a current setter, a current generator, a surge suppression circuit, a switch and an output stage.

[0056] The output end of the current setter is connected to the control input end of the current generator; the input end of the current generator is connected to the first end of the switch; the output end of the current generator is connected to the third end of the first device; the second control end of the switch is connected to the second end of the first device; and the first end of the switch is connected to the surge suppression circuit. The first terminal, the second terminal and the third terminal of the first device are respectively used to receive a low voltage power supply, a control pulse and a common wire connecting the first device, while the fourth terminal, the fifth terminal and the sixth terminal of the first device are respectively used to connect the power supply of the previous floating voltage, the control electrode of the upper transistor of the power switch and the power supply of the previous floating bias voltage.

[0057] In addition, the third end of the switch is connected to the input end of the control pulse transmission channel, and the power input end of the switch, the power input end of the interference transmission channel and the power input end of the current setter are all connected to the first end of the first device. The control pulse transmission channel, the interference transmission channel and the output stage are connected in parallel to the fourth and sixth terminals of the first device. The output ends of the control pulse transmission channel and the interference transmission channel are connected to the input end of the interference suppression circuit, the output end of the interference suppression circuit is connected to the input end of the output stage, and the output end of the output stage is connected to the fifth terminal of the first device.

[0058] In the first embodiment of the device, another factor that contributes to the above technical achievement is that, when there is no pulse interference, the control pulse entering the second terminal of the first device closes the switch to ensure that the current flows through the current generator and the control pulse transmission channel. 0 The value of is set by the current setter, and a sufficiently small value can be selected to generate negligible dissipated power during the control pulse even when a high voltage power supply is used. A positive pulse relative to the potential of the sixth terminal of the first device is generated at the output end of the control pulse transmission channel connected to the first input end of the interference suppression circuit. At this time, the output end of the interference transmission channel connected to the second input end of the interference suppression circuit maintains the potential of the sixth terminal of the first device.

[0059] In the interference suppression circuit, the output signals of these channels are subtracted to form a positive pulse which is added to the output stage. Due to the pulse, the output stage transfers the potential of the fourth terminal of the first device (sufficient to control the upper transistor of the power switch) to the fifth terminal of the first device, which is used to connect the control electrode of the upper transistor of the power switch.

[0060] When there is no control pulse at the second terminal of the first device, no positive pulse will appear at the output end of the control pulse transmission channel, and accordingly, no pulse for controlling the upper transistor of the power switch will appear at the fifth terminal of the first device.

[0061] When a high-intensity pulse interference appears at the sixth terminal of the first device, it enters the second input terminal of the interference suppression circuit through the interference transmission channel. The high-intensity pulse interference enters the first input terminal of the interference suppression circuit through the control pulse transmission channel. The above input signals cancel each other in the interference suppression circuit, thereby suppressing the high-intensity pulse interference regardless of the presence of the control pulse.

[0062] Therefore, since the interference transmission channel, the control pulse transmission channel and the interference suppression circuit are included in the first embodiment of the present device, it is possible to suppress high-intensity pulse interference with a high rise rate and achieve moderate power consumption (about 2-3 watts), which is considered to be non-obvious and meets the patentability requirements.

[0063] The above technical achievements are achieved in a second embodiment (further "second device") of the proposed LSC for controlling a power switch by additionally providing a controllable current generator, an interference transmission channel, a control pulse transmission channel and an interference suppression circuit in a second device consisting of a current setter, a surge suppression circuit, a switch and an output stage.

[0064] The output end of the current setter is connected to the control input end of the controllable current generator, the input end of the controllable current generator is connected to the first end of the switch, the output end of the controllable current generator is connected to the third end of the second device, the second control end of the switch and the pulse input end of the controllable current generator are connected to the second end of the second device, and the surge suppression circuit is connected to the first end of the switch.

[0065] In addition, the third end of the switch is connected to the input end of the control pulse transmission channel, and the power input end of the switch, the interference transmission channel and the current setter is connected to the first end of the second device.

[0066] The control pulse transmission channel, the interference transmission channel and the output stage are connected in parallel to the fourth and sixth terminals of the second device. The output ends of the control pulse transmission channel and the interference transmission channel are connected to the input end of the interference suppression circuit, and the output ends thereof are connected to the input end of the output stage.

[0067] The output end of the output stage is connected to the fifth terminal of the second device, and the low voltage power supply and the control pulse are respectively applied to the first and second terminals of the second device, and the third terminal of the second device is connected to the common conductor of the second device.

[0068] In the second embodiment of the device, another factor contributing to the achievement of the above technical results is that, in the absence of pulse interference, the control pulse on the second terminal of the second device closes the switch to ensure that the current flows through the controllable current generator and the control pulse transmission channel. 0 The value of is set by the current setter and can be chosen small enough to provide negligible power dissipation during the control pulse, even when using a high voltage supply.

[0069] The control pulse also enters the controllable current generator, making the current I 0 The voltage increases momentarily so as to rapidly charge the capacitance of the transistor forming part of the switch, thereby causing the second set of devices to respond faster than the first.

[0070] At the output end of the control pulse transmission channel connected to the first input end of the interference suppression circuit, a positive pulse relative to the potential of the sixth terminal of the second device is generated. At this time, the potential of the sixth terminal of the second device is maintained at the output end of the interference transmission channel connected to the second input end of the interference suppression circuit.

[0071] In the interference suppression circuit, the output signals of these channels are subtracted to form a positive pulse which is added to the output stage. Due to the pulse, the output stage transfers the potential of the fourth terminal of the second device (sufficient to control the upper transistor of the power switch) to the fifth terminal of the second device, which is used to connect the control electrode of the upper transistor of the power switch.

[0072] When there is no control pulse at the second terminal of the second device, no positive pulse will appear at the output end of the control pulse transmission channel, and accordingly, no pulse for controlling the upper transistor of the power switch will appear at the fifth terminal of the second device.

[0073] When a high-intensity pulse interference appears at the sixth terminal of the second device, it enters the second input terminal of the interference suppression circuit through the interference transmission channel. Through the control pulse transmission channel, the high-intensity pulse interference enters the first input terminal of the interference suppression circuit. The above input signals cancel each other in the interference suppression circuit, thereby suppressing the high-intensity pulse interference, regardless of the presence of the control pulse.

[0074] Therefore, since the interference transmission channel, the control pulse transmission channel, the interference suppression circuit and the controllable current generator are included in the second embodiment of the present device, the suppression of high-intensity pulse interference also achieves a high rise rate, moderate (about 2-3 watts) power consumption and faster operating speed.

[0075] This was considered non-obvious and met the patentability requirement for the second device.

[0076] An analysis of known designs in the prior art showed that none of them included all of the limitations of the proposed device or its distinctive features, indicating that they met the novelty and inventive step criteria. BRIEF DESCRIPTION OF THE DRAWINGS

[0077] The present invention is further explained by the accompanying drawings, which illustrate some embodiments of the proposed LSC for controlling the power switch. The accompanying drawings are included for a better understanding of the present invention, are included in the disclosure of the present invention, constitute a part of the present invention, and together with the description are used to explain the operating mode of the present invention.

[0078] Figure 1 A prototype (prior art) is shown.

[0079] Figure 2a is a block diagram of one possible embodiment of the apparatus 100a.

[0080] Figure 2b is a block diagram of another possible embodiment of the apparatus 100b.

[0081] Figure 3 One possible embodiment of a switch 140 is shown.

[0082] Figure 4 One possible embodiment of the surge suppression circuit 160 is shown.

[0083] Figure 5a is one of the possible embodiments of the interference suppression circuit 170a.

[0084] Figure 5b is another possible implementation of the interference suppression circuit 170b.

[0085] Figure 6 is one of the possible embodiments of the output stage 180 .

[0086] Figure 7a One of the possible embodiments of the current generator 120 according to the first embodiment of the device is shown.

[0087] Figure 7b Another possible embodiment of the controllable current generator 1120 according to the second embodiment of the device is shown.

[0088] Figure 8 One of the possible embodiments of controlling the pulse transmission channel 150 is shown.

[0089] Fig. 9 One possible embodiment of the interference transmission channel 130 is shown, which is similar to Figure 8 The embodiments in are similar.

[0090] Fig.10a and Figure 2a Compared with the block diagram of a possible embodiment of the apparatus 100a, a more detailed diagram is disclosed. Figure 3 , 4 , 5a, 6, 7a, 8 and 9.

[0091] Fig.10b and Figure 2b Compared to the block diagram of another possible embodiment of the device 100b, a more detailed diagram is disclosed. Figure 3 , Figure 4 , Figure 5a , Figure 6 , Figure 7b , Figure 8 and Fig. 9 Components in . DETAILED DESCRIPTION

[0092] The specific implementation method of the present invention is described below with reference to the accompanying drawings.

[0093] When applied to transistors rather than contacts and switches, the term "open circuit" and its derivatives mean "in the conducting state", while the term "closed circuit" and its derivatives mean "in the non-conducting state".

[0094] In the specification or claims, when one element is "connected" to another element, it means direct connection or electrical connection through a third element.

[0095] In addition, the term “comprise” and its derivatives (“comprising,” “including,” “including” and other similar terms) will be understood to imply the inclusion of these elements but not the exclusion of any other elements unless specifically stated otherwise.

[0096] Figure 2a An LSC for controlling a power switch or device according to a first embodiment thereof is shown, wherein the LSC as a whole is designated as 100a. The LSC includes a current setter 110, a current generator 120, an interference transmission channel 130, a switch 140, a control pulse transmission channel 150, a surge suppression circuit 160, an interference suppression circuit 170, and an output stage 180.

[0097] Figure 2a Also shown are power switch elements that do not belong to the LSC 100a - a low-voltage power source 5, a high-voltage power source 6, an upper power switch transistor 7a, a lower power switch transistor 7b and a floating low-voltage power source 8, wherein the floating low-voltage power source 8 may specifically include a diode and a boost capacitor, both of which are not shown.

[0098] The input 101Vcc of the LSC 100a is connected to the low voltage power input 115 of the current setter 110, the low voltage power input 135 of the interference transmission channel 130, and the low voltage power input 143 of the switch 140. The output terminal 117 of the current setter 110 is connected to the control input terminal 126 of the current generator 120. The control input 102IN of the LSC 100a is connected to the second control terminal 145 of the switch 140 and the second control terminal 165 of the surge suppression circuit 160. The first terminal 127 of the current generator 120 and the first terminal of the surge suppression circuit 160 are connected to each other and to the terminal 103GND of the LSC 100a for connecting the common line of the LSC 100a. The second terminal 129 of the current generator 120 and the second terminal 169 of the surge suppression circuit 160 are connected to each other and to the first terminal 147 of the switch 140, and the third terminal 149 of the switch 140 is connected to the input terminal 151 of the control pulse transmission channel 150.

[0099] The output terminal 159 of the control pulse transmission channel 150 is connected to the first input terminal 171 of the interference suppression circuit 170, and the output terminal 139 of the interference transmission channel 130 is connected to the second input terminal 175 of the interference suppression circuit 170. The output terminal 179 of the interference suppression circuit 170 is connected to the input terminal 181 of the output stage 180, and the output terminal 189 of the output stage 180 is connected to the fifth terminal 105 of the LSC 100a for connecting the control electrode of the upper transistor 7a of the power switch.

[0100] The terminal 104 of the LSC 100a for connecting the floating upper stage high voltage power source Vb is respectively connected to the interference transmission channel 130, the control pulse transmission channel 150, the interference suppression circuit 170 and the power input terminals 133, 153, 173 and 183 of the output stage 180.

[0101] The terminal 106 for connecting the floating upper bias voltage Vs in the LSC 100a is connected to the terminals 137, 157, 177 and 187 of the interference transmission channel 130, the control pulse transmission channel 150, the interference suppression circuit 170 and the output stage 180, respectively.

[0102] According to the LSC proposed in the second embodiment, Figure 2b As shown, where the LSC as a whole is designated as 100b. Figure 2b The components of the LSC and their interconnections are shown in Figure 2a The components shown and their interconnections are identical, except that a controllable current generator 1120 is used instead of the current generator 120, the pulse input terminal 1125 of the controllable current generator 1120 being connected to the control terminal 102 of the LSC 100b.

[0103] Figure 3 One possible implementation of the switch 140 in the device is shown. It can be part of any device implementing the proposed LSC. Figure 3 The switch 140 , the p-type first field effect transistor 340 , the n-type second field effect transistor 350 , and the resistor 360 are shown in FIG.

[0104] The first terminal 365 of the resistor 360 is connected to the low voltage power input terminal 143 of the switch 140.

[0105] The gate 345 of the first field effect transistor 340 is connected to the second control terminal 145 of the switch 140.

[0106] The gate 355 of the second field effect transistor 350 is connected to the second terminal 367 of the resistor 360 and the source 347 of the first field effect transistor 340.

[0107] The drain 343 of the first field effect transistor 340 and the source 357 of the second field effect transistor 350 are connected to the first terminal 147 of the switch 140 , and the drain 353 of the second field effect transistor 350 is connected to the third terminal 149 of the switch 140 .

[0108] Figure 4 Shown is one possible implementation of a surge suppression circuit 160 in the proposed LSC. This circuit can be part of any device implementing the proposed LSC. Figure 4 Designated in the circuit shown are: the entire circuit 160. A transistor 460 and a Zener diode 430. The gate 465 of the transistor 460 is connected to the second control input 165 of the circuit 160. The anode 432 of the Zener diode 430 is connected to the drain 463 of the transistor 460, the cathode 435 of the Zener diode 430 is connected to the second terminal 169 of the surge suppression circuit 160, and the source 467 of the transistor 460 is connected to the first terminal 167 of the surge suppression circuit 160.

[0109] Figure 5a A possible implementation of the interference suppression circuit 170a in the present device is shown. It can be a part of any device implementing the proposed LSC. Figure 5a 1 and 10 show a p-type field effect transistor 570a and a resistor 510a. A first input terminal 171 of the interference suppression circuit 170a is connected to a source 571a of the field effect transistor 570a, a second input terminal 175 of the interference suppression circuit 170a is connected to a gate 575a of the field effect transistor 570a, a terminal 179 of the interference suppression circuit 170a is connected to a drain 577a of the field effect transistor 570a and a first terminal 511a of the resistor 510a, and a second terminal 513a of the resistor 510a is connected to a terminal 177 of the interference suppression circuit 170a.

[0110] Figure 5b is another possible implementation of the interference suppression circuit 170b in the present device. It can be a part of any device implementing the proposed LSC. Figure 5b 1 and 2 are shown as first, second and third p-type field effect transistors 570b, 520, 530 and resistor 510b. The first input terminal 171 of the interference suppression circuit 170b is connected to the source 571b of the first p-type field effect transistor 570b, and the second input terminal 175 of the interference suppression circuit 170b is connected to the gate 575b of the first p-type field effect transistor 570b.

[0111] The drain 577b of the first p-type field effect transistor 570b is connected to the drain 527 of the second p-type field effect transistor 520 and to the connection points of the gates 525 and 535 of the second p-type field effect transistor 520 and the third p-type field effect transistor 530, respectively. The source 521 of the second p-type field effect transistor 520 and the source 531 of the third p-type field effect transistor 530 are connected to each other and to the power supply input terminal 173 of the interference suppression circuit 170. Therefore, the pair of p-type field effect transistors 520 and 530 and their connection form a current mirror.

[0112] The output terminal 179 of the interference suppression circuit 170b is connected to the drain 537 of the third p-type field effect transistor 530 and the first end 511b of the resistor 510b, while the second end 513b of the resistor 510b is connected to the terminal 177 of the interference suppression circuit 170b.

[0113] Figure 6 Shown is one of the possible implementations of the output stage 180. It can be part of any device implementing the proposed LSC.

[0114] Figure 6 Shown in FIG. 1 are: an output stage 180 and a Schmitt trigger 650 .

[0115] The first input terminal 181 of the output stage 180 is connected to the input terminal 651 of the Schmitt trigger 650. The output terminal 655 of the Schmitt trigger 650 is connected to the terminal 189 of the output stage 180. The power input terminal 652 of the Schmitt trigger 650 is connected to the power input terminal 183 of the output stage 180, and the terminal 654 of the Schmitt trigger 650 for connecting the LSC common line is connected to the terminal 187 of the output stage 180.

[0116] Figure 7a One of the current generators that may be realized according to the first embodiment of the proposed LSC is shown. It can be part of any device that realizes the first embodiment of the LSC. Figure 7a Shown in FIG. 1 are: the entire current generator 120 , a first transistor 730 , and a second transistor 740 .

[0117] The drain 733 of the first transistor 730 and the connection point of the gate 735 of the first transistor 730 and the gate 745 of the second transistor 740 are connected to the control input 126 of the current generator 120. The drain 743 of the second transistor 740 is connected to the second terminal 129 of the current generator 120. The source 737 of the first transistor 730 and the source 747 of the second transistor 740 are connected to each other and to the first terminal 127 of the current generator 120.

[0118] Figure 7bOne of the current generators that may be used according to the proposed second embodiment of the LSC is shown. It can be part of any device implementing the second embodiment of the LSC. Figure 7b Shown are: a controllable current generator as a whole 1120, a first transistor 730, a second transistor 740, a third transistor 720, a driven multivibrator 710, and a first resistor 750, a second resistor 770 and a third resistor 760 having terminals 751 and 753, 771 and 773, 761 and 763, respectively.

[0119] The drain 733 of the first transistor 730 and the connection point of the gate 735 of the first transistor 730 and the gate 745 of the second transistor 740 are connected to the control input 126 of the controllable current generator 1120 .

[0120] The drain 743 of the second transistor 740 is connected to the second terminal 129 of the controllable current generator 1120 .

[0121] The source 737 of the first transistor 730 is connected to the first terminal 127 of the controllable current generator 1120 via a first resistor 750 , and the source 747 of the second transistor 740 is connected to the same terminal 127 via a second resistor 770 .

[0122] A terminal 763 of the third resistor 760 is connected to a common point of the second resistor 770 and the source 747 of the second transistor 740 .

[0123] The terminal 761 of the third resistor 760 is connected to the drain 723 of the third transistor 720. In turn, the gate 725 of the third transistor 720 is connected to the output terminal 719 of the controlled multi-frequency oscillator 710, the source 727 of the third transistor 720 is connected to the first terminal 127 of the controllable current generator 1120, and the input terminal 711 of the controlled multi-frequency oscillator 710 is connected to the pulse input terminal 1125 of the controllable current generator 1120.

[0124] Figure 8 One of the possible implementations of the control pulse transmission channel 150 in the proposed LSC is shown. It can be a part of any device implementing LSC. Figure 8 Shown in the figure are: the control pulse transmission channel as a whole - 150, the first field effect transistor 870, the second field effect transistor 880, the third field effect transistor 890, the low voltage power source 8030, its positive electrode 8031, its negative electrode 8033, the first resistor 801, the second resistor 802, the third resistor 803 and the fourth resistor 804.

[0125] The gate 875 of the first field effect transistor 870 is connected to the positive electrode 8031 ​​of the low voltage power source 8030 , the source 877 of the first field effect transistor 870 is connected to the second terminal 812 of the first resistor 801 , and the first terminal 811 thereof is connected to the input end 151 of the control pulse transmission channel 150 .

[0126] The drain 873 of the first field effect transistor 870 is connected to the drain 883 of the second field effect transistor 880, and is respectively connected to the connection points of the gates 885 and 895 of the second field effect transistor 880 and the third field effect transistor 890. The source 887 of the second field effect transistor 880 is connected to the first terminal 831 of the third resistor 803, and the second terminal 832 thereof is connected to the power input terminal 153 of the control pulse transmission channel 150.

[0127] The drain 893 of the third field effect transistor 890 is connected to the second terminal 822 of the second resistor 802 and the output terminal 159 of the control pulse transmission channel 150, while the source 897 of the third field effect transistor 890 is connected to the first terminal 841 of the fourth resistor 804, and the second terminal 842 thereof is connected to the power input terminal 153 of the control pulse transmission channel 150. The first terminal 821 of the second resistor 802 is connected to the negative electrode 8033 of the low voltage power source 8030 and the terminal 157 of the control pulse transmission channel 150.

[0128] Fig. 9 One possible implementation of the interference transmission channel 130 in the required LSC is shown. It can be part of any device implementing LSC. Fig. 9 The following are specified: the interference transmission channel as a whole - 130, the first field effect transistor 970, the second field effect transistor 980, the third field effect transistor 990, and the fourth field effect transistor 9010. The low voltage power source is specified as 9030, its positive pole - 9031, its negative pole - 9033, and the resistors - the first 901, the second 902, the third 903, and the fourth 904.

[0129] The gate 9015 and the source 9017 of the fourth field effect transistor 9010 are connected to each other and to the low voltage power input 135 , and the drain 9013 of the fourth field effect transistor 9010 is connected to the first terminal 911 of the first resistor 901 .

[0130] The second terminal 932 of the third resistor 903 and the second terminal 942 of the fourth resistor 904 are connected to each other and to the power input terminal 133 of the interference transmission channel 130. The drain 993 of the third field effect transistor 990 is connected to the output terminal 139 of the interference transmission channel 130. The first terminal 921 of the second resistor 902 is connected to the terminal 137 of the interference transmission channel 130.

[0131] Other connections between the elements of the interference transmission channel 130 are similar to those in the control pulse transmission channel 150 .

[0132] Fig.10a Shown Figure 2a The components included in the functional unit and their connections are suitable for a possible implementation of the first embodiment (LSC) of the proposed device.

[0133] The LSC is named as 100 a and includes: a current setter 110 , a current generator 120 , an interference transmission channel 130 , a switch 140 , a control pulse transmission channel 150 , a surge suppression circuit 160 , an interference suppression circuit 170 and an output stage 180 .

[0134] Fig.10a Also shown are the following elements of the power switch, which do not constitute the LSC 100a: a low-voltage power supply 5, a high-voltage power supply 6, an upper transistor 7a of the power switch, a lower transistor 7b of the power switch, and a floating low-voltage power supply 8, wherein the floating low-voltage power supply 8 may specifically include a diode and a boost capacitor (neither of which are shown).

[0135] The input 101Vcc of the device 100a is connected to the low voltage power input 115 of the current setter 110, the low voltage power input 135 of the interference transmission channel 130, and the low voltage power input 143 of the switch 140. The output 117 of the current setter 110 (including the resistor 112) is connected to the control input 126 of the current generator 120.

[0136] The current generator 120 includes a current mirror and is composed of two transistors 730 and 740, the gates of which are connected to each other, to the drain of the transistor 730 and to the control input terminal 126 of the current generator 120. The sources of the transistors 730 and 740 are connected to each other and to the first terminal 127 of the current generator 120.

[0137] The drain of transistor 740 is connected to the second terminal 129 of current generator 120, which in turn is connected to the second terminal 169 of surge suppression circuit 160 and the first terminal 147 of switch 140. Surge suppression circuit 160 comprises transistor 460 and Zener diode 430, the gate of transistor 460 being connected to the second control terminal 165 of surge suppression circuit 160, which terminal 165 is also connected to the control input 102 of device 100a and the second control terminal 145 of switch 140. The drain of transistor 460 is connected to the anode of Zener diode 430, and the cathode of which is connected to the second terminal 169 of surge suppression circuit 160. The source of transistor 460 is connected to the first terminal 167 of surge suppression circuit 160, which terminal 167 is connected to the terminal 103 of device 100a for connecting the common line of LSC and the first terminal 127 of current generator 120.

[0138] The switch 140 includes a p-type field effect transistor 340 and an n-type field effect transistor 350. The gate of the p-type field effect transistor 340 is connected to the second control terminal 145 of the switch 140, the source of the transistor is connected to the first terminal 147 of the switch 140 and the source of the n-type field effect transistor 350, and the drain of the n-type field effect transistor 350 is connected to the third terminal 149 of the switch 140. The drain of the p-type field effect transistor 340 is connected to the gate of the n-type field effect transistor 350, and is connected to the low voltage power input terminal 143 of the switch 140 through the resistor 360. The control terminal 145 of the switch 140 is connected to the control input terminal 102IN of the device 100a, and the third terminal 149 of the switch is connected to the input terminal 151 of the control pulse transmission channel 150.

[0139] The control pulse transmission channel 150 includes a first field effect transistor 870, two transistors that together form a current mirror, a second field effect transistor 880 and a third field effect transistor 890, a low voltage power supply 8030, a first resistor 801, a second resistor 802, a third resistor 803 and a fourth resistor 804. Connected to the input terminal 151 of the control pulse transmission channel 150 is the first resistor 801, and the first field effect transistor 870, the second field effect transistor 880 connected in series therewith, and the third resistor 803 connected to the power input terminal 153 of the control pulse transmission channel 150. Connected to the terminal 157 of the control pulse transmission channel 150 is the second resistor 802, the third field effect transistor 890 connected in series therewith, and the fourth resistor 803 also connected to the power input terminal 153 of the control pulse transmission channel 150.

[0140] Also connected to the terminal 157 of the control pulse transmission channel 150 is the negative electrode of the low voltage power source 8030 , and the positive electrode thereof is connected to the gate of the first field effect transistor 870 .

[0141] The gate of the second field effect transistor 880 and the gate of the third field effect transistor 890 are connected to each other, and are respectively connected to the drain of the first field effect transistor 870 and the source of the second field effect transistor 880. The connection point between the drain of the third field effect transistor 890 and the second resistor 802 is connected to the output terminal 159 of the control pulse transmission channel 150.

[0142] The interference transmission channel 130 includes a first field effect transistor 970, two transistors that together form a current mirror - a second field effect transistor 980 and a third field effect transistor 990, a fourth field effect transistor 9010, a low voltage power supply 9030, a first resistor 901, a second resistor 902, a third resistor 903 and a fourth resistor 904.

[0143] The fourth field effect transistor 9010 is connected to the low voltage power input terminal 135 of the interference signal transmission channel 130, and the first resistor 901, the first field effect transistor 970, the second field effect transistor 980 are connected in series therewith, and the third resistor 903 is connected to the power input terminal 133 of the interference signal transmission channel 130. The second resistor 902 is connected to the terminal 137 of the interference signal transmission channel 130, and the third field effect transistor 990 and the fourth resistor 904 are connected in series therewith, and the latter is also connected to the power input terminal 133 of the interference signal transmission channel 130. The negative electrode of the low voltage power supply 9030 is also connected to the terminal 137 of the interference transmission channel 130, and the positive electrode thereof is connected to the gate of the first field effect transistor 970. The gate of the second field effect transistor 980 and the gate of the third field effect transistor 990 are connected to each other, and are respectively connected to the drain of the first field effect transistor 970 and the source of the second field effect transistor 980. The drain of the third field effect transistor 990 and the connection point of the second resistor 902 are connected to the output terminal 139 of the interference transmission channel 130, and the gate and source of the fourth field effect transistor 9010 are connected to each other.

[0144] The interference suppression circuit 170 includes a p-channel field effect transistor 570a and a resistor 510a. The source of the p-channel field effect transistor 570a is connected to the first input terminal 171 of the interference suppression circuit 170, and the gate of the p-channel field effect transistor 570a is connected to the second input terminal 175 of the interference suppression circuit 170. The drain of the p-channel field effect transistor 570a is connected to the output terminal 179 of the interference suppression circuit 170, and the resistor 510a is connected between the output terminal 179 and the terminal 177 of the interference suppression circuit 170.

[0145] The output stage 180 includes a Schmitt trigger 650, the input terminal of the Schmitt trigger 650 is connected to the input terminal 181 of the output stage 180, the output terminal of the Schmitt trigger 650 is connected to the output terminal 189 of the output stage 180, and the power input terminal of the Schmitt trigger 650 is respectively connected to the power input terminal 183 and the terminal 187 of the output stage 180.

[0146] The output terminal 159 of the control pulse transmission channel 150 is connected to the first input terminal 171 of the interference suppression circuit 170, and the second input terminal 175 thereof is connected to the output terminal 139 of the interference transmission channel 130. The output terminal 179 of the interference suppression circuit 170 is connected to the input terminal 181 of the output stage 180, and the output terminal 189 thereof is connected to the terminal 105 of the device 100a for connecting the control electrode of the upper transistor 7a of the power switch.

[0147] Terminal 104 of device 100a is used to connect to floating upper power supply voltage Vb, and is respectively connected to power supply input terminals 133, 153, 173 and 183 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170 and output stage 180.

[0148] In this embodiment, the power input terminal 173 of the interference suppression circuit 170 is not used.

[0149] Terminal 106 of device 100a is used to connect to floating upper bias voltage Vs and is respectively connected to power input terminals 137, 157, 177 and 187 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170 and output stage 180.

[0150] Fig.10b Shown Figure 2b The components and their connections of the functional unit shown are a possible implementation of the second embodiment of the proposed device (LSC).

[0151] The LSC 100 b includes a current setter 110 , a controllable current generator 1120 , an interference transmission channel 130 , a switch 140 , a control pulse transmission channel 150 , a surge suppression circuit 160 , an interference suppression circuit 170 a and an output stage 180 .

[0152] Fig.10b Also shown are the following elements of the power switch, which do not constitute the LSC 100b: a low-voltage power supply 5, a high-voltage power supply 6, an upper transistor 7a of the power switch, a lower transistor 7b of the power switch, and a floating low-voltage power supply 8, wherein the floating low-voltage power supply 8 may specifically include a diode and a boost capacitor, both of which are not shown.

[0153] The input 101Vcc of the device 100a is connected to the low voltage power input 115 of the current setter 110, the low voltage power input 135 of the interference transmission channel 130, and the low voltage power input 143 of the switch 140. The output 117 of the current setter 110 (including the resistor 112) is connected to the control input 126 of the controllable current generator 1120.

[0154] Fig.10b The controllable current generator 1120 includes a first transistor 730 , a second transistor 740 , a third transistor 720 , a driving multi-frequency oscillator 710 , a first resistor 750 , a second resistor 770 and a third resistor 760 .

[0155] The gates of the first and second transistors 730 and 740 are connected to each other and to the drain of the first transistor 730 and the control input terminal 126 of the controllable current generator 1120 .

[0156] The drain of the second transistor 740 is connected to the second terminal 129 of the controllable current generator 1120 .

[0157] The source of the first transistor 730 is connected to the first terminal 127 of the controllable current generator 1120 via a first resistor 750 , and the source of the second transistor 740 is connected to the same first terminal 127 of the controllable current generator 1120 via a second resistor 770 .

[0158] One terminal of the third resistor 760 of the controllable current generator 1120 is connected to the source of the second transistor 740 and the common point of the second resistor 770, and the other terminal of the third resistor 760 is connected to the drain of the third transistor 720. In addition, the gate of the third transistor 720 is connected to the output terminal of the driven multi-frequency oscillator 710, the source of the third transistor 720 is connected to the first terminal 127 of the controllable current generator 1120, and the input terminal of the driven multi-frequency oscillator 710 is connected to the pulse input terminal 1125 of the controllable current generator 1120, and the pulse input terminal 1125 is connected to the control input terminal 102IN of the LSC 100b.

[0159] The switch 140 includes a p-type field effect transistor 340 and an n-type field effect transistor 350. The gate of the p-type field effect transistor 340 is connected to the second control terminal 145 of the switch 140, the source of the transistor is connected to the first terminal 147 of the switch 140 and the source of the n-type field effect transistor 350, and the drain of the n-type field effect transistor 350 is connected to the third terminal 149 of the switch 140. The drain of the p-type field effect transistor 340 is connected to the gate of the n-type field effect transistor 350, and is connected to the low voltage power supply input terminal 143 of the switch 140 through the resistor 360. The control terminal 145 of the switch 140 is connected to the control input 102IN of the device 100a, and the third terminal 149 of the switch is connected to the input 151 of the control pulse transmission channel 150.

[0160] The control pulse transmission channel 150 includes a first field effect transistor 870, two transistors that together form a current mirror, a second field effect transistor 880 and a third field effect transistor 890, a low voltage power supply 8030, a first resistor 801, a second resistor 802, a third resistor 803 and a fourth resistor 804. Connected to the input terminal 151 of the control pulse transmission channel 150 is the first resistor 801, and the first field effect transistor 870, the second field effect transistor 880 connected in series therewith, and the third resistor 803 connected to the power input terminal 153 of the control pulse transmission channel 150. Connected to the terminal 157 of the control pulse transmission channel 150 is the second resistor 802, the third field effect transistor 890 connected in series therewith, and the fourth resistor 803 also connected to the power input terminal 153 of the control pulse transmission channel 150.

[0161] Also connected to the terminal 157 of the control pulse transmission channel 150 is the negative electrode of the low voltage power source 8030 , and the positive electrode thereof is connected to the gate of the first field effect transistor 870 .

[0162] The gate of the second field effect transistor 880 and the gate of the third field effect transistor 890 are connected to each other, and are respectively connected to the drain of the first field effect transistor 870 and the source of the second field effect transistor 880. The connection point between the drain of the third field effect transistor 890 and the second resistor 802 is connected to the output terminal 159 of the control pulse transmission channel 150.

[0163] The interference transmission channel 130 includes a first field effect transistor 970, two transistors that together form a current mirror - a second field effect transistor 980 and a third field effect transistor 990, a fourth field effect transistor 9010, a low voltage power source 9030, a first resistor 901, a second resistor 902, a third resistor 903 and a fourth resistor 904.

[0164] Connected to the low voltage power input terminal 135 of the interference transmission channel 130 is the fourth field effect transistor 9010, and connected in series with the first resistor 901, the first field effect transistor 970, the second field effect transistor 980 and the third resistor 903 connected to the power input terminal 133 of the interference transmission channel 130.

[0165] Connected to the terminal 137 of the interference signal transmission channel 130 are the second resistor 902 and the third field effect transistor 990 and the fourth resistor 904 connected in series therewith, the latter also being connected to the power input terminal 133 of the interference signal transmission channel 130. Also connected to the terminal 137 of the interference transmission channel 130 is the negative electrode of the low voltage power supply 9030, whose positive electrode is connected to the gate of the first field effect transistor 970. The gate of the second field effect transistor 980 and the gate of the third field effect transistor 990 are connected to each other, and are respectively connected to the drain of the first field effect transistor 970 and the source of the second field effect transistor 980. The connection point between the drain of the third field effect transistor 990 and the second resistor 902 is connected to the output terminal 139 of the interference transmission channel 130, and the gate and source of the fourth field effect transistor 9010 are connected to each other.

[0166] The interference suppression circuit 170 includes a p-channel field effect transistor 570a and a resistor 510a. The source of the p-channel field effect transistor 570a is connected to the first input terminal 171 of the interference suppression circuit 170, and the gate of the p-channel field effect transistor 570a is connected to the second input terminal 175 of the interference suppression circuit 170. The drain of the p-channel field effect transistor 570a is connected to the output terminal 179 of the interference suppression circuit 170, and the resistor 510a is connected between the output terminal 179 and the terminal 177 of the interference suppression circuit 170.

[0167] The output stage 180 includes a Schmitt trigger 650, the input terminal of the Schmitt trigger 650 is connected to the input terminal 181 of the output stage 180, the output terminal of the Schmitt trigger 650 is connected to the output terminal 189 of the output stage 180, and the power input terminal of the Schmitt trigger 650 is respectively connected to the power input terminal 183 and the terminal 187 of the output stage 180.

[0168] The output terminal 159 of the control pulse transmission channel 150 is connected to the first input terminal 171 of the interference suppression circuit 170, and the second input terminal 175 thereof is connected to the output terminal 139 of the interference transmission channel 130. The output terminal 179 of the interference suppression circuit 170 is connected to the input terminal 181 of the output stage 180, and the output terminal 189 thereof is connected to the terminal 105 of the LSC 100b for connecting the control electrode of the upper transistor 7a of the power switch.

[0169] Terminal 104 of device 100b is used to connect to floating upper power supply voltage Vb, and is respectively connected to power supply input terminals 133, 153, 173 and 183 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170 and output stage 180.

[0170] In this embodiment, the power input terminal 173 of the interference suppression circuit 170 is not used.

[0171] Terminal 106 of device 100b is used to connect the floating upper level bias voltage Vs, which is respectively connected to power input terminals 137, 157, 177 and 187 of interference transmission channel 130, control pulse transmission channel 150, interference suppression circuit 170 and output stage 180.

[0172] Operation of the Invention

[0173] According to the first embodiment of the present device, the working principle of LSC 100a is as follows (see Figure 2a ).

[0174] When the control pulse IN enters the control input terminal 102 and further enters the second control terminal 145 of the switch 140, the switch 140 is closed, and the current I 0 The current starts to flow along the following circuit: terminal 104 of LSC 100a connected to the floating upper power supply voltage, power input terminal 153 of control pulse transmission channel 150, control pulse transmission channel 150, switch 140, current generator 120, first terminal 127 of current generator 120, terminal 103 of LSC 100a (for connecting the common wire of LSC 100a).

[0175] The circuit is closed because the common line of LSC 100a is connected to the source of transistor 7b and the negative terminal of high voltage power supply 6 (of which LSC 100a is not a part).

[0176] The current I 0 The value of is determined by the current generator 120 through its control input 126 from the output 117 of the current setter 110. In turn, the low voltage power supply input 115 of the current setter 110 is connected to the input 101 of the LSC 100a, wherein the low voltage power supply Vcc comes from the low voltage power supply 5, which is not a part of the LSC 100a.

[0177] The value of the low voltage power source Vcc may be in the range of 4.5-5.5V with respect to the common line potential of the LSC 100a.

[0178] Relative to the potential Vs of the terminal 106 of the LSC 100a, the value of the power supply voltage Vb of the upper transistor of the power switch (floating power supply 8) can be in the range of 12-18V, and the value of the high voltage power supply Vhh (high voltage power supply 6) can be in the range of 500-600V, or in other ranges depending on the working environment of the power switch.

[0179] Due to the action of the current generator 120, the I0 flowing along the "terminal 104 - terminal 103 of LSC 100a" loop remains stable during the control pulse IN, and its value is set at an extremely low level (eg, several mA) by the current setter 110 to reduce power consumption.

[0180] The most common current setter is a series connection of a constant voltage source and a constant resistor, such as the current setter disclosed in the above-mentioned US 9,564,882 B2, although more complex schematics may also be used.

[0181] During the control pulse IN and under interference-free conditions, the output terminal 159 of the control pulse transmission channel 150 generates a pulse of positive polarity relative to the voltage Vs at the terminal 106 of the LSC 100a, which is applied to the first input terminal 171 of the interference suppression circuit 170. The output voltage at the output terminal 139 of the interference transmission channel 130 is equal to the potential Vs at the terminal 106 of the LSC 100a under the considered conditions, and due to the connection between the terminal 106 and the terminal 137 of the interference transmission channel 130, this voltage is applied to the second input terminal 175 of the interference suppression circuit 170. The positive polarity pulse formed at the output terminal 179 of the interference suppression circuit 170 enters the input terminal 181 of the output stage 180. It causes the output stage 180 to send the positive polarity pulse as a pulse Vh from its output terminal 189 to the terminal 105 of the LSC 100a for controlling the upper transistor of the power switch.

[0182] After the control pulse IN ends, the switch 140 opens, the current in the "terminal 104-terminal 103 of LSC 100a" circuit stops flowing, and the pulses at the output terminal 159 of the control pulse transmission channel 150 and the output terminal 179 of the interference suppression circuit 170 and the pulse Vh at the output terminal 105 of the LSC 100a end.

[0183] When a large pulse interference characterized by a high rise rate dV / dt, usually caused by the switching transistor of the power switch, appears at the terminal 106 of the LSC 100a, its pulse reaches the terminals 137 and 157 of the interference transmission channel 130 and the control pulse transmission channel 150 respectively at the same time.

[0184] Due to the high characteristics of channels 130 and 150 (and taking into account switch 140), interference pulses arrive at their output terminals 139 and 159 and input terminals 171 and 175 of interference suppression circuit 170 at the same time and with equal amplitudes. Therefore, these pulses are mutually compensated in interference suppression circuit 170, and there is almost no large pulse interference at output terminal 179 of interference suppression circuit 170, output terminal 189 of output stage 180 and output terminal 105 of LSC 100a, regardless of whether control pulse IN is present or not.

[0185] In this way, in normal operating mode, suppression of large pulse interference with high rise rate and moderate power consumption can be ensured at the same time, thus achieving the claimed technical results.

[0186] According to the second embodiment of the present device, the working principle of LSC 100b in one possible implementation is as follows (see Figure 2b ).

[0187] When the control pulse IN enters the control input terminal 102 of the LSC 100b and further enters the second control terminal 145 of the switch 140, the switch 140 is closed and the current I0 starts to flow along the circuit: terminal 104 of the LSC 100b connected to the floating upper power supply voltage - power input terminal 153 of the control pulse transmission channel 150 - control pulse transmission channel 150 - switch 140 - controllable current generator 1120 - first terminal 127 of the controllable current generator 1120 - terminal 103 of the LSC 100b for connecting the common wire of the LSC 100b.

[0188] The circuit is closed by connecting the common lead of LSC 100b to the source of transistor 7b and the cathode of high voltage power supply 6, while transistor 7b and the cathode are not part of LSC 100b.

[0189] The current I 0 The value of is determined by the controllable current generator 1120 through its control input 126 from the output 117 of the current setter 110. In turn, the low voltage power supply input 115 of the current setter 110 is connected to the input 101 of the LSC 100b, wherein the low voltage power supply Vcc comes from the low voltage power supply 5, which is not a part of the LSC 100b.

[0190] The value of the low voltage power supply Vcc may be in the range of 4.5-5.5V relative to the potential of the LSC common line.

[0191] Relative to the potential Vs of the terminal 106 of the LSC 100b, the power supply voltage Vb of the upper transistor of the power switch (floating power supply 8) can have a value in the range of 12-18V, while the value of the high voltage power supply Vhh (high voltage power supply 6) can have a value in the range of 500-600V, or other ranges depending on the operating environment of the power switch.

[0192] The above-mentioned I0 flowing along the "terminal 104 - terminal 103 of LSC 100b" circuit is kept stable during the control pulse IN due to the controllable current generator 1120, and its value is set at an extremely low level (e.g., several mA) by the current setter 110 to reduce power consumption.

[0193] The most common current setter is a series connection of a constant voltage source and a constant resistor, such as the current setter disclosed in the above-mentioned US 9,564,882 B2, although more complex schematics are possible.

[0194] However, the control pulse IN is also a pulse input 1125 from the control input 102 of the LSC 100b to the controllable current generator 1120. In a short time, this will cause the current to rise sharply along the "terminal 104-terminal 103 of the LSC 100b" circuit, reaching a maximum value I at the beginning of the control pulse IN. 1 =5...15I 0 The current rise time is less than one percent of the duration of the control pulse IN. The current I 1 Charging the capacitance of switch 140 helps improve the high-speed performance of LSC 100b. 1 The duration is short and the power consumed by the device hardly changes.

[0195] During the control pulse IN and under interference-free conditions, the output terminal 159 of the control pulse transmission channel 150 generates a pulse of positive polarity relative to the voltage Vs at the terminal 106 of the LSC 100b, which is applied to the first input terminal 171 of the interference suppression circuit 170. The output voltage at the output terminal 139 of the interference transmission channel 130 is equal to the potential Vs at the terminal 106 of the LSC 100b under the considered conditions, and due to the connection between the terminal 106 and the terminal 137 of the interference transmission channel 130, this voltage is applied to the second input terminal 175 of the interference suppression circuit 170. The positive polarity pulse formed at the output terminal 179 of the interference suppression circuit 170 enters the input terminal 181 of the output stage 180. It causes the output stage 180 to send the positive polarity pulse as a pulse Vh from its output terminal 189 to the terminal 105 of the LSC 100b for controlling the upper transistor of the power switch.

[0196] After the control pulse IN ends, the switch 140 opens, the current in the "terminal 104-terminal 103 of LSC 100a" circuit stops flowing, and the pulses at the output terminal 159 of the control pulse transmission channel 150 and the output terminal 179 of the interference suppression circuit 170 and the pulse Vh at the output terminal 105 of the LSC 100b end.

[0197] When a large pulse interference characterized by a high rise rate dV / dt, usually caused by the switching transistor of the power switch, appears at the LSC 100b terminal 106, its pulse reaches the terminals 137 and 157 of the interference transmission channel 130 and the control pulse transmission channel 150 respectively at the same time.

[0198] Due to the high characteristics of channels 130 and 150 (and taking into account switch 140), the interference pulses arrive at their output terminals 139 and 159 and at the input terminals 171 and 175 of the interference suppression circuit 170 at the same time and with equal amplitude. Therefore, these pulses are mutually compensated in the interference suppression circuit 170, and there is almost no large pulse interference at the output terminal 179 of the interference suppression circuit 170, the output terminal 189 of the output stage 180, and the output terminal 105 of the LSC 100b.

[0199] In this way, in the normal operating mode, it is possible to simultaneously ensure the suppression of large pulse interference with a high rise rate and moderate power consumption, thereby achieving the claimed technical results. In addition, since the current rise time flowing through the controllable current generator 1120, the switch 140 and the control pulse transmission channel 150 at the beginning of the control pulse IN is short, it is possible to ensure that the response time of the LSC is improved.

[0200] The required components of the LSC may be implemented in various ways.

[0201] Specifically, Figure 3 A possible implementation of the switch 140 is shown, which can be used in both embodiments of the proposed design, and its working principle is as follows (see also Figure 2a , 2b ).

[0202] When the control pulse IN enters the second control terminal 145, the transistor 340 is closed, and the resistance between the first electrode 343 and the third electrode 347 increases. At the same time, since the potential Vcc of the low-voltage power supply input terminal 143 reaches the second control electrode 355 of the transistor 340 through the resistor 360, the transistor 350 is in an off state. Therefore, the current flows through the switch 140 along the following circuit: the third terminal 149 of the switch 140-the first electrode 353 of the transistor 350-the third electrode 357 of the transistor 350-the first terminal 147 of the switch 140, that is, the switch 140 is closed.

[0203] After the control pulse IN ends, the transistor 340 is turned on, the resistance between the first electrode 343 and the third electrode 347 becomes low, and the potential difference between the second electrode, the control electrode 355 and the third electrode 357 of the transistor 350 is close to zero. This causes the transistor 350 to close, the current loop flowing between the terminals 149 and 147 is disconnected, and the switch 140 is turned on.

[0204] Since the low resistance of open transistor 340 shorts out the high capacitance of transistor 350 , transistor 340 in switch 140 speeds up the closing of the switch, thereby increasing the overall speed of the LSC.

[0205] Figure 4Shown is a possible implementation of the surge suppression circuit 160 in the LSC, which can be used in both versions of the proposed design. In many prior art devices (e.g., analog devices (see US 9,564,882 B2)), at the leading edge of the control pulse IN, due to the cross capacitance of the transistor 350 of the switch 140, a voltage surge appears at the drain 353 of the transistor 350 and is transferred to the third electrode 357 of the transistor 350. This surge may cause the input barrier of the transistor 350 to break down and cause the claimed LSC to fail completely.

[0206] In the prototype (US 9,264,022), a surge suppression circuit was used in parallel with the current generator. The surge suppression circuit 160 in the claimed LSC is also connected in parallel with the current generator 120 (see Figure 2a ) or in parallel with the controllable current generator 1120 (see Figure 2b ), but unlike the prototype, it includes a Zener diode 430 and a transistor 460 connected in series.

[0207] according to Figure 4 The implemented surge suppression circuit 160 operates as follows (see also Figure 2a , 2b ).

[0208] The control pulse IN is output from the control input terminal 102 of the desired LSC to the second control input terminal 165 connected to the gate 465 of the transistor 460, and turns on the transistor. Since the cathode 435 of the Zener diode 430 is connected to the third electrode 357 of the transistor 350 of the switch 140 through the second terminal 169 of the surge suppression circuit 160 and the first terminal 147 of the switch 140 (see Figure 3 ), at which time the potential of the third electrode 357 of the transistor 350 is equal to the voltage of the cathode 435 of the Zener diode 430, which is composed of the voltage across the turned-on transistor 460 plus the stable voltage of the Zener diode 430, and is several volts.

[0209] The voltage on the second (control) electrode 355 of the transistor 350 is equal to the potential Vcc of the low-voltage power source 5 at the low-voltage power input terminal 143 of the switch 140. The potential difference between the second (control) electrode 355 of the transistor 350 and the cathode 435 of the Zener diode 430 is very small, so in this case, it is impossible for the transistor 350 to have input barrier breakdown.

[0210] When the control pulse IN ends, the transistor 460 is turned on, thereby cutting off the connection between the Zener diode 430 and the first terminal 167 of the surge suppression circuit 160, preventing the Zener diode 430 from failing due to the potential Vcc of the low-voltage power supply 5 reaching the cathode 435 of the Zener diode 430 from the low-voltage power supply input terminal 143 of the switch 140 through the short-circuit transistor 340.

[0211] Figure 8 Shown is a possible implementation of the control pulse transmission channel 150, which can be used in both embodiments of the proposed design, and its working principle is as follows.

[0212] When the control pulse IN appears at the control input terminal 102 (see Figure 2a , 2b ) and passes through the second (control) terminal 145 of the switch 140, the latter is closed and forms a loop, so that the current flows from the power input terminal 153 of the control pulse transmission channel 150 to the first terminal 127 of the current generator 120 (see Figure 2a ) or the first end 127 of the controllable current generator 1120 (see Figure 2b ).

[0213] The current flows in the control pulse transmission channel 150 along the following circuit (see Figure 8 ): power supply input terminal 153 - third resistor 803 - second transistor 880 - first transistor 870 - first resistor 801 - input terminal 151 of control pulse transmission channel 150 .

[0214] When the control pulse IN appears, the first transistor 870 is in a conducting state under the voltage of the DC voltage source 8030 and contributes to the fast response of the circuit as a buffer stage.

[0215] The transistor pair consisting of the second transistor 880 and the third transistor 890 forms a current mirror, so when current flows through the second transistor 880, current also flows through the third transistor 890, and the current value is determined by the nominal ratio of the third resistor 803 and the fourth resistor 804. This current generates a voltage drop across the resistor 802, which is transmitted to the terminal 159 as an output pulse of the control pulse transmission channel 150, and the amplitude of the pulse exceeds the specified value of the potential Vs of the terminal 157.

[0216] If a high-intensity pulse interference appears at the terminal 157 of the control pulse transmission channel 150 during the existence of the control pulse IN, a surge current will appear in the circuit of the power supply input terminal 153-the third resistor 803-the second transistor 880-the first transistor 870-the first resistor 801-the input terminal 151 of the control pulse transmission channel 150. At the same time, due to the effect of the current mirror, the pulse interference current also flows through the fourth resistor 804 and the third transistor 890, generating an additional voltage drop on the second resistor 802. This voltage drop is added to the output pulse voltage of the control pulse transmission channel 150, and is transmitted to the output terminal 159 as an output signal containing the sum of the control pulse and the high-intensity pulse interference.

[0217] If there is no control pulse IN at the control input 102 of the desired LSC and the switch 140 is open (see Figure 2a , 2b ), there is no current in the circuit between the power input 153 and the input terminal 151 of the control pulse transmission channel 150 (see Figure 8 ). Similarly, there is no current in the circuit between the power input terminal 153 and the terminal 157 of the control pulse transmission channel 150. Therefore, the control pulse transmission channel 150 does not output pulses.

[0218] However, if a high-intensity pulse interference appears at the terminal 157 of the control pulse transmission channel 150 in the absence of a control pulse, a surge current appears again in the circuit of the power input terminal 153-the third resistor 803-the second transistor 880-the first transistor 870-the first resistor 801-the input terminal 151 of the control pulse transmission channel 150. In addition, due to the effect of the current mirror, the pulse interference current also flows through the fourth resistor 804 and the third transistor 890, generating an additional voltage drop on the second resistor 802. This voltage drop is transmitted to the output terminal 159 as an output signal containing the pulse interference.

[0219] Therefore, during the control pulse IN period, the output terminal 159 of the control pulse transmission channel 150 always outputs the control pulse. If a high-intensity pulse interference occurs, an interference pulse is added to the output control pulse. When there is no control pulse IN, the output terminal 159 of the control pulse transmission channel 150 does not output the control pulse. When a high-intensity pulse interference occurs, an interference pulse appears at the output terminal 159.

[0220] Fig. 9 The figure shows a possible implementation of the interference transmission channel 130, which can be used in two embodiments of the present design scheme. Its working principle is similar to that of the control pulse transmission channel 150, but has the following particularities:

[0221] 1) The control pulse does not enter the interference transmission channel 130, but its fourth transistor 9010 (permanently closed due to the connection of the second (control) electrode 9015 and the third electrode 9017) is similar to the transistor 350 of the switch 140 (see Figure 3 ). Therefore, the circuit parameters are: power input terminal 133 - third resistor 903 - second transistor 980 - first transistor 970 - first resistor 901 - fourth transistor 9010 and Figure 8 The corresponding circuit in the control pulse transmission channel 150 is similar (and considering Figure 3The switch 140 in the interference transmission channel 130 is used as the switch 140 in the interference transmission channel 130, but when the control pulse exists or does not exist, no current flows in the circuit. No current flows through the following circuits: power supply input terminal 133-fourth resistor 904-third transistor 990-second resistor 902-terminal 137 of the interference transmission channel 130. Therefore, the output pulse of the interference transmission channel 130 will neither appear when the control pulse IN exists nor appear at the output terminal 139 when the control pulse IN does not exist.

[0222] 2) When high-intensity pulse interference occurs at the terminal 137 of the interference transmission channel 130 , the working principle of the channel 130 is similar to that of the control pulse transmission channel 150 . When high-intensity pulse interference occurs, the interference pulse always appears at the output terminal 139 of the interference transmission channel 130 .

[0223] Therefore, there are no control pulses at the output end 139 of the interfering transmission channel 130 at all times, and interfering pulses only appear when a high-intensity pulse interference occurs at the terminal 137 .

[0224] Since the operating principles of the control pulse transmission channel 130 and the interference pulse transmission channel 150 are similar (considering the switch 140 ), the interference pulses at the input terminals 171 and 175 of the interference suppression circuit 170 have a high degree of similarity.

[0225] Figure 5a A possible version of the interference suppression circuit 170a in LSC is shown. If there is no interference, the circuit works as follows.

[0226] When the control pulse IN enters the control input terminal 102 of the LSC, the control pulse transmission channel 150 (see Figure 2a , 2b ) will appear a pulse with an amplitude exceeding the set value of the potential Vs of the terminal 157 at the output terminal 159. The pulse enters the first input terminal 171 of the interference suppression circuit 170a and passes through the third electrode 571a of the transistor 570a. At the same time, the voltage from the output terminal 139 of the interference transmission channel 130 to the second input terminal 175 of the circuit 170a is equal to the potential Vs of the LSC terminal 106, and the voltage is transmitted to the second control electrode 575a of the transistor 570a.

[0227] Due to the potential difference between the input terminals 171 and 175, a differential pulse of positive polarity is formed on the resistor 510a of the interference suppression circuit 170a and is transmitted to the output terminal 179 of the circuit 170a.

[0228] If there is no control pulse IN, the voltages on the source 571a and the second control electrode 575a of the transistor 570a are equal, and a zero differential signal formed on the resistor 510a of the interference suppression circuit 170a connected to the first electrode 577a of the transistor 570a is transmitted to the output terminal 179 of the circuit 170a.

[0229] When the control pulse and the high-intensity pulse interference appear at the output terminal 159 of the control pulse transmission channel 150 at the same time and are transmitted to the input terminal 171 of the circuit 170a, the output terminal 139 of the interference transmission circuit 130 (and the second input terminal 175 of the interference suppression circuit 170a) will also appear high-intensity pulse interference, and its amplitude and shape are similar to those of the input terminal 171. In this case, the pulse interferences at the input terminals 171 and 175 are subtracted, and a differential signal of a positive polarity and set amplitude pulse is formed on the resistor 510a connected to the first electrode 577a of the transistor 570a of the interference suppression circuit 170a, and the positive pulse is transmitted to the output terminal 179 of the circuit 170a.

[0230] If high-intensity pulse interference occurs in the absence of a control pulse, the voltages on the third electrode 571a and the second control electrode 575a of the transistor 570a are equal, forming a zero-difference signal on the resistor 510a connected to the first electrode 577a of the transistor 570a and transmitted to the output terminal 179 of the interference suppression circuit 170a.

[0231] Therefore, if there is a control pulse at the input terminal 171 of the interference suppression circuit 170a, a differential signal as a positive pulse will be formed at its output terminal 179 regardless of whether there is a high-intensity pulse interference.

[0232] If there is no control pulse at the input terminal 171 of the interference suppression circuit 170a, a zero differential signal will be formed at its output terminal 179 regardless of whether there is a high-intensity pulse interference.

[0233] This means that high-intensity pulse interference does not enter the input terminal 181 of the output stage 180 at all (see Figure 2a , 2b ), and therefore will not enter the output terminal Vh of the LSC, thereby providing high fault safety when high-intensity pulse interference with a high rise rate occurs.

[0234] Figure 5b The interference suppression circuit 170b in can be used in two embodiments of the proposed LSC, and its working principle is as follows.

[0235] In the absence of high-intensity pulse interference, when the control pulse IN enters the control input terminal 102 of the LSC, a pulse with an amplitude exceeding the set value of the potential Vs of the terminal 157 will appear at the output terminal 159 of the control pulse transmission channel 150 (see Figure 2a , 2b ).

[0236] This pulse enters the first input terminal 171 of the interference suppression circuit 170b and passes through the third electrode 571b of the transistor 570b. At the same time, the voltage from the output terminal 139 of the interference transmission channel 130 to the second input terminal 175 of the circuit 170b is equal to the required potential Vs of the LSC terminal 106, which is transmitted to the second control electrode 575b of the transistor 570b. Due to the potential difference between the input terminals 171 and 175, the transistor 570b is open-circuited and the current flows along the circuit: power supply input terminal 173-transistor 520-transistor 570b-first input terminal 171 of the interference suppression circuit 170. Since the pair of transistors 520 and 530 and their connection form a current mirror, the same current flows along another circuit: power supply input terminal 173-transistor 530-resistor 510b-terminal 177 of the interference suppression circuit 170b.

[0237] At this time, the differential signal formed on the resistor 510 b is a positive polarity pulse and enters the output terminal 179 .

[0238] When the control pulse IN is missing, the voltages on the third electrode 571 b and the second control electrode 575 b of the transistor 570 b are equal, and a homodyne signal is formed on the resistor 510 b, which enters the output terminal 179 .

[0239] When the output terminal 159 of the control pulse transmission channel 150 has both control pulses and high-intensity pulse interference, these pulse interferences pass through the input terminal 171 of the interference suppression circuit 170b, and at the same time, the output terminal 139 of the interference transmission channel 130 (and the second input terminal 175 of the interference suppression circuit 170b) also has high-intensity pulse interference, whose shape and amplitude are similar to the interference at the input terminal 171. In this case, the pulse interferences at the input terminals 171 and 175 are subtracted, and a pulse differential signal with a positive polarity and a set amplitude is formed on the resistor 510b and transmitted to the output terminal 179 of the circuit 170b.

[0240] If a high-intensity pulse interference occurs without a control pulse, the voltages of the third electrode 571b and the second control electrode 575b of the transistor 570b are equal, forming a zero differential signal on the resistor 510b and transmitting it to the output terminal 179 of the interference suppression circuit 170b.

[0241] Therefore, if there is a control pulse at the input terminal 171 of the interference suppression circuit 170b, a differential signal as a positive pulse will be formed at its output terminal 179 regardless of whether there is a high-intensity pulse interference.

[0242] If there is no control pulse at the input terminal 171 of the interference suppression circuit 170b, a zero differential signal will be formed at its output terminal 179 regardless of whether there is a high-intensity pulse interference.

[0243] This means that high-intensity pulse interference does not enter the input terminal 181 of the output stage 180 (see Figure 2, 2b) at all, and therefore does not enter the output terminal Vh of the LSC, thereby providing high fault safety when high-intensity pulse interference with a high rise rate occurs.

[0244] Figure 6 A possible implementation of the output stage 180 is shown, which can be used for two embodiments of the proposed LSC, and its operation principle is as follows.

[0245] By means of interference suppression circuit 170 (see Figure 2a , 2b ) The control pulse for clearing interference reaches the input terminal 181 of the output stage 180, and further reaches the input terminal 651 of the Schmitt trigger 650 that converts the analog input signal into a digital output signal. The control pulse enters the output terminal 189 of the output stage 180 (and further enters the output terminal 105 of the so-called LSC) from the output terminal 655 of the Schmitt trigger 650. The pulse has a sharp enough edge to turn on the upper-stage transistor 7a of the power switch (such as Figure 2a , 2b shown, not part of the LSC).

[0246] Figure 7a Shown is a possible implementation of a current generator 120 forming a current mirror according to the first embodiment of the LSC.

[0247] In this current generator, the first transistor 730 and the second transistor 740 are identical.

[0248] The working principle of the current generator 120 is as follows.

[0249] Current setter 110 (see Figure 2a ) flows in the current generator 120 along the following circuit: control input terminal 126-first transistor 730-first terminal 127 of the current generator 120. The potential difference between the second (control) electrode 735 and the third electrode 737 of the first transistor 730 is equal to the potential difference between the second (control) electrode 745 and the third electrode 747 of the second transistor 740, so the current I 0 (equal to the input current) flows through the second transistor 740. This current is permanent and has nothing to do with the parameters of the load connected to the second terminal of the current generator 120.

[0250] Figure 7bA possible implementation of the controllable current generator 1120 according to the second embodiment of the LSC is shown, and its working principle is as follows.

[0251] By the current setting device 110 (see also Figure 2b ) generates an input current I 0 The current flows through the following circuit in the controllable current generator 1120: the control input terminal 126 of the controllable current generator 1120 - the first transistor 730 - the first resistor 750 - the first terminal 127 of the controllable current generator 1120. If the resistances of the first resistor 750 and the second resistor 770 are equal, the transistor 740 will also flow a current I equal to the input current. 0 This current is continuous and has nothing to do with the parameters of the load connected to the second terminal 129 of the controllable current generator 1120 .

[0252] When the control pulse IN reaches the input terminal 711 of the driving multivibrator 710 from the pulse input terminal of the controllable current generator 1120, a short pulse is generated at the multivibrator output terminal 719, whose length is a fraction of the duration of the pulse IN. This pulse reaches the second control electrode 725 of the third transistor 720 and turns it on. Since the resistance of the third transistor 720 in the off state is very small, the terminal 761 of the third resistor 760 - through the first electrode 723 and the third electrode 727 of the third transistor 720 - is actually immediately connected to the first terminal 127 of the controllable current generator 1120, and the third resistor 760 is connected in parallel to the second resistor 770 of the controllable current generator 1120. Typically, the resistance of the third resistor 760 is 5...15 times smaller than the resistance of the second resistor 770, so that the current through the controllable current generator 1120 increases at approximately the same rate to I 1 =5...15I 0 After the short pulse at the output 719 of the driven multivibrator 710 ends, the third transistor 720 is turned off, the resistance between its first electrode 723 and the third electrode 727 becomes very high, and the third resistor 760 is disconnected from the first terminal 127 of the controllable current generator 1120. Therefore, during the remaining duration of the control pulse IN, the current I 0 Flows through the controllable current generator 1120.

[0253] Fig.10a The LSC 100a shown is one of its possible embodiments. According to the first embodiment of the present device, the LSC 100a has Figure 3 , Figure 4 , Figure 5a , Figure 6 , Figure 7a , Figure 8 and Fig. 9The components shown work as follows.

[0254] When the control pulse IN enters the control input terminal 102 of the LSC 100a and further appears at the second control terminal 145 of the switch 140, the transistor 340 is closed and the resistance between its first and third electrodes becomes very high. At the same time, since the potential Vcc of the low voltage power supply input terminal 143 of the switch 140 is transmitted to the second (control) electrode of the transistor 340 through the resistor 360, the transistor 350 is in the off state. Therefore, the current flows through the transistor 350 (and therefore also through the switch 140) along the following circuit: the power supply input terminal 153 of the control pulse transmission channel 150 - the third resistor 803, the second transistor 880, the first transistor 870 and the first resistor 801 of the control pulse transmission channel 150 - the transistor 350 of the switch 140 - the transistor 740 of the current generator 120 - the first terminal 127 of the current generator 120 - the terminal 103 of the LSC 100a for connecting the common line of the LSC. Since the common line of LSC is connected to the source of transistor 7b and the negative electrode of high voltage power supply 6, the circuit is closed.

[0255] After the control pulse IN ends, the transistor 350 of the switch 140 is turned on, the resistance between the first electrode 353 (drain) and the third electrode 357 (source) becomes low, and the potential difference between the second control electrode 355 (gate) and the third electrode 357 of the transistor 350 of the switch 140 approaches zero. Therefore, the transistor 350 is closed, the switch 140 is now open, and the above-mentioned current flow circuit is also disconnected.

[0256] Transistor 340 in switch 140 can speed up the closing process of the switch because the resistance of the open transistor 340 is very small and can shunt the high input capacitance of transistor 350, thereby increasing the overall speed of LSC 100a.

[0257] I flows during the control pulse IN 0 The value is determined by the current generator 120:

[0258] I 0 =(V cc -Vd) / R 112 ,

[0259] Among them, Vcc is a low voltage power supply input to the first terminal 101 of the LSC 100a from the low voltage power supply 5 not included in the LSC 100a; Vd is a voltage between the second (control) electrode and the third electrode of the transistor 730 of the current generator 120; R112 is the resistance of the resistor 112 of the current setter 110.

[0260] The value of the low voltage power supply Vcc may be in the range of 4.5...5V relative to the potential of the LSC common line, and the value of I0 is set at an extremely low level (eg, several mA) by the current setter 110 to reduce power consumption.

[0261] The surge suppression circuit 160 is used to prevent the input barrier of the transistor 350 of the switch 140 from being broken down, which may cause the transistor 350 and the entire LSC 100a to fail. At the leading edge of the control pulse IN, a voltage surge is generated on the first electrode of the transistor 350 and is transferred to the third electrode of the transistor 350 of the switch 140 through the cross capacitance of the transistor, thereby causing the breakdown.

[0262] The working principle of the surge suppression circuit 160 is as follows.

[0263] The control pulse IN enters the second (control) input terminal 165 connected to the second electrode of the transistor 460 from the control input terminal 102 of the LSC 100a, and turns on the transistor 460. The anode of the Zener diode 430 is connected to the third electrode of the transistor 350 of the switch 140 through the second terminal 169 of the surge suppression circuit 160 and the first terminal 147 of the switch 140. At this time, the potential of the third electrode of the transistor 350 is equal to the voltage of the anode of the Zener diode 430. This voltage includes the voltage on the open transistor 460 and the stable voltage of the Zener diode 430, which is equivalent to several volts. The voltage on the second (control) electrode of the transistor 350 is equal to the potential Vcc of the low voltage power supply 5 on the low voltage power supply input terminal 143 of the switch 140. The potential difference between the second (control) electrode of the transistor 350 and the anode of the Zener diode 430 is very small, so the input barrier of the transistor 350 is unlikely to be broken down.

[0264] When the control pulse IN ends, the transistor 460 is closed, disconnecting the Zener diode 460 from the first terminal 167 of the surge suppression circuit 160, thereby preventing the Zener diode 460 from failing due to the potential Vcc of the low-voltage power supply 5 entering the anode of the Zener diode 430 from the low-voltage power supply input terminal 143 of the switch 140 through the short-circuit transistor 340.

[0265] Control pulse transmission channel 150 (see Figure 8 ) works as follows.

[0266] During the control pulse IN and when there is no interference (case 1), a pulse with positive polarity relative to the voltage Vs on the terminal 106 of the LSC 100a is generated at the output terminal 159 of the control pulse transmission channel 150 and passes through the first input terminal 171 of the interference suppression circuit 170.

[0267] The pulse is generated as follows: when the control pulse IN appears at the control input terminal 102 of the LSC 100a and is transmitted to the second control terminal 145 of the switch 140, the switch 140 is closed, thereby forming a loop for the current flowing from the power input terminal 153 of the control pulse transmission channel 150 to the first terminal 127 of the current generator 120.

[0268] The current flows in the control pulse transmission channel 150 along the following loop: power supply input terminal 153 −third resistor 803 −second transistor 880 −first transistor 870 −first resistor 801 −input terminal 151 .

[0269] When the control pulse IN appears, the first transistor 870 is disconnected under the voltage of the DC voltage source 8030, and acts as a buffer stage to ensure that the circuit has sufficient operating speed.

[0270] The pair of transistors, the second transistor 880 and the third transistor 890, form a current mirror, so when current flows through the second transistor 880, current also flows through the third transistor 890. The value of this current is determined by the nominal ratio of the third resistor 803 and the fourth resistor 804. This current generates a voltage drop across the resistor 802, which is transmitted to the terminal 159 as an output pulse of the control pulse transmission channel 150, and the amplitude of the pulse exceeds the specified value of the potential Vs of the terminal 157.

[0271] If a high-intensity pulse interference appears on the terminal 157 of the control pulse transmission channel 150 during the existence of the control pulse IN (case 2), a surge current appears in the circuit of the power supply input terminal 153-the third resistor 803-the second transistor 880-the first transistor 870-the first resistor 801-the input terminal 151 of the control pulse transmission channel 150. At the same time, due to the effect of the current mirror, the pulse interference current also flows through the fourth resistor 804 and the third transistor 890, and generates an additional voltage drop on the second resistor 802. This voltage drop is added to the output pulse voltage of the control pulse transmission channel 150, and is transmitted to the output terminal 159 as an output signal containing the sum of the control pulse and the high-intensity pulse interference.

[0272] When there is no control pulse IN at the control input terminal 102 of the LSC 100a (case 3), the switch 140 will cut off the current loop between the power input terminal 153 and the input terminal 151 of the control pulse transmission channel 150. Similarly, the current will not flow through the fourth resistor 804-the third transistor 890-the second resistor 802, and the control pulse transmission channel 150 will not output a pulse.

[0273] If a high-intensity pulse interference occurs at the terminal 157 of the control pulse transmission channel 150 in the absence of a control pulse (Case 4), a surge current occurs in the circuit of the power supply input terminal 153-the third resistor 803-the second transistor 880-the first transistor 870-the first resistor 801-the input terminal 151 of the control pulse transmission channel 150. In addition, due to the effect of the current mirror, the pulse interference current also flows through the fourth resistor 804 and the third transistor 890, generating an additional voltage drop on the second resistor 802.

[0274] Therefore, during the control pulse IN, the output terminal 159 of the control pulse transmission channel 150 always outputs the control pulse (case 1). If a high-intensity pulse interference occurs (case 2), an interference pulse is added to the output control pulse. When there is no control pulse IN, the output terminal 159 of the control pulse transmission channel 150 does not output the control pulse (case 3). However, when a high-intensity pulse interference occurs, an interference pulse appears at the output terminal 159 (case 4).

[0275] The working principle of the interference transmission channel 130 is similar to that of the control pulse transmission channel 150, but has the following particularities:

[0276] 1) The control pulse does not enter the interference transmission channel 130, but it has a fourth transistor 9010 (permanently closed due to the connection of the second (control) electrode and the third electrode), similar to the transistor 350 of the switch 140.

[0277] Therefore, the circuit parameters in the interference transmission circuit 130: power input terminal 133-third resistor 903-second transistor 980-first transistor 970-first resistor 901-fourth transistor 9010 are similar to the corresponding circuit in the control pulse transmission channel 150 (and taking into account the transistor 350), except that no current flows through the circuit when there is a control pulse or no control pulse. No current flows through the following circuits respectively: power input terminal 133-fourth resistor 904-third transistor 990-second resistor 902-terminal 137 of the interference transmission channel 130. Therefore, when the control pulse IN exists or does not exist, the output pulse of the interference transmission channel 130 will not appear on the output terminal 139.

[0278] 2) When high-intensity pulse interference occurs at the terminal 137 of the interference transmission channel 130 , the working principle of the channel 130 is similar to that of the control pulse transmission channel 150 . When high-intensity pulse interference occurs, the interference pulse always appears at the output terminal 139 of the interference transmission channel 130 .

[0279] Therefore, there is no control pulse at the output end 139 of the interference transmission channel 130 at all times, and the interference pulse will only appear when a high-intensity pulse interference appears at the terminal 137.

[0280] Since the operating principles of the control pulse transmission channel 130 and the interference pulse transmission channel 150 are similar (considering the transistor 350 ), the interference pulses at the input terminals 171 and 175 of the interference suppression circuit 170 a have a high degree of similarity.

[0281] From the output terminal 159 of the control pulse transmission channel 150 , the output control pulse in case 1 or the output control pulse in case 2 and the interference pulse are sent to the first input terminal 171 of the interference suppression circuit 170a , which is connected to the third electrode of the transistor 570 .

[0282] In the second and fourth cases, the interference pulse enters the second input terminal 175 of the interference suppression circuit 170a from the output terminal 139 of the interference transmission channel 130.

[0283] When a control pulse and a high-intensity pulse interference appear simultaneously at input terminals 171 and 175 (located at the third electrode and the second (control) electrode of transistor 570, respectively), the pulse interference is subtracted at these input terminals, and a positive differential signal of a set amplitude appears on resistor 510 of the interference suppression circuit 170a, which is connected to the first electrode 577 of transistor 570, and the differential signal passes through the output terminal 179 of the interference suppression circuit 170a.

[0284] If high-intensity pulse interference occurs in the absence of a control pulse, the voltages on the third electrode and the second electrode (i.e., the control electrode) of transistor 570 are equal, forming a zero differential signal on the resistor 510 connected to the first electrode 577 of transistor 570 and transmitted to the output terminal 179 of the interference suppression circuit 170a.

[0285] Therefore, if there is a control pulse at the input terminal 171 of the interference suppression circuit 170a (case 1 or 2), a differential signal as a positive pulse will be formed at its output terminal 179 regardless of whether there is high-intensity pulse interference; and if there is no control pulse at the input terminal 171 of the interference suppression circuit 170a (case 3 or 4), a zero differential signal will be formed at its output terminal 179 regardless of whether there is high-intensity pulse interference.

[0286] The differential signal enters the input terminal 181 of the output stage 180 composed of the Schmitt trigger 650 from the output terminal 179 of the interference suppression circuit 170a, and the analog input signal is converted into a digital output signal. From the output terminal 189 of the output stage 180, the digital signal (representing the pulse for controlling the upper transistor of the power switch) is output to the output terminal 105 of the required LSC, which has a sharp enough edge to turn on the upper transistor 7a of the power switch (such as Fig.10a shown, not part of the LSC).

[0287] In this way, the device according to the first embodiment can simultaneously compensate for high-intensity pulse interference with a high rise rate (because the interference for control pulses and interference is respectively subtracted through the same transmission channels 150 and 130), and moderate power consumption in normal operating mode (because the current flowing through the current generator 120, the switch 140 and the control pulse transmission channel 150 can be set at an extremely low level (for example, a few milliamperes)), thereby achieving the claimed technical results.

[0288] exist Fig.10b In one possible embodiment shown, the required LSC (according to the second embodiment of the proposed device, Figure 3 , 4 , 5a, 6, 7b, 8 and 9) work as follows.

[0289] When the control pulse IN enters the control input terminal 102 of the LSC 100b and further appears at the second control terminal 145 of the switch 140, the transistor 340 is turned off and the resistance between its first and third electrodes becomes very high. At the same time, since the potential Vcc of the low voltage power supply input terminal 143 of the switch 140 is transmitted to the second (control) electrode of the transistor 340 through the resistor 360, the transistor 350 is in the off state. Therefore, the current flows through the transistor 350 (and therefore also through the switch 140) along the following circuit: the power supply input terminal 153 of the control pulse transmission channel 150 - the third resistor 803, the second transistor 880, the first transistor 870 and the first resistor 801 of the control pulse transmission channel 150 - the transistor 350 of the switch 140 - the transistor 740 of the controllable current generator 1120 - the first terminal 127 of the controllable current generator 1120 - the terminal 103 of the LSC 100b, which is used to connect the common wire of the LSC. Since this common wire of the LSC is connected to the common wire of the LSC Fig.10b The source of transistor 7b shown in FIG. 1 is connected to the negative electrode of high voltage power supply 6 but is not part of LSC 100b, so the circuit is closed.

[0290] After the control pulse IN ends, the transistor 340 of the switch 140 is turned on, the resistance between the first electrode (drain) and the third electrode (source) becomes low, and the potential difference between the second electrode (control electrode) (gate) and the third electrode of the transistor 350 of the switch 140 approaches zero. Therefore, the transistor 350 is closed, the switch 140 is now open, and the above-mentioned current flow circuit is also disconnected.

[0291] Transistor 340 in switch 140 speeds up the closing process of the switch because the small resistance of opening transistor 340 shunts the high input capacitance of transistor 350, thereby increasing the overall operating speed of LSC 100b.

[0292] The value of I0 flowing during the control pulse IN is determined by the controllable current generator 1120:

[0293] I 0 =(Vcc-Vd) / R112,

[0294] Among them, Vcc is a low voltage power supply input to the first terminal 101 of LSC 100b from a low voltage power supply 5 not included in LSC 100b; Vd is a voltage between the second (control) electrode and the third electrode of the transistor 730 of the controllable current generator 1120; R112 is the resistance of the resistor 112 of the current setter 110.

[0295] The value of the low voltage power supply Vcc can be in the range of 4.5...5.5V relative to the potential of the circuit common wire, and I 0 The value of is set at an extremely low level (eg, several mA) by the current setter 110 to reduce power consumption.

[0296] When the control pulse IN reaches the driven multivibrator 710 from the pulse input of the controllable current generator 1120, a short pulse is generated at the output of the multivibrator, the pulse length of which is a fraction of the duration of the pulse IN. This pulse turns on the third transistor 720, which connects the third resistor 760 in parallel with the second resistor 770 of the controllable current generator 1120. Typically, the resistance of the third resistor 760 is 5...15 times smaller than the resistance of the second resistor 770, so the current through the controllable current generator 1120 increases at approximately the same rate, reaching I 1 =5...15I 0 After the short pulse is completed at the output of the driven multi-frequency oscillator 710, the third transistor 710 is turned off and the third resistor 760 is disconnected from the first terminal 127 of the controllable current generator 1120. Therefore, the current I0 flows through the controllable current generator 1120 during the remaining duration of the control pulse IN.

[0297] The surge suppression circuit 160 is used to prevent the input barrier of the transistor 350 of the switch 140 from being broken down, which would otherwise cause the transistor 350 and the entire LSC 100b to fail. At the leading edge of the control pulse IN, a voltage surge is generated on the first electrode of the transistor 350 and is transferred to the third electrode of the transistor 350 of the switch 140 through the cross capacitance of the transistor, thereby causing a breakdown.

[0298] The working principle of the surge suppression circuit 160 is as follows.

[0299] The control pulse IN is from the control input terminal 102 of the LSC 100b to the second (control) input terminal 165 connected to the second electrode of the transistor 460, and turns on the transistor. The anode of the Zener diode 430 is connected to the third electrode of the transistor 350 of the switch 140 through the second terminal 169 of the surge suppression circuit 160 and the first terminal 147 of the switch 140, and the potential of the third electrode of the transistor 350 is equal to the voltage of the anode of the Zener diode 430. This voltage includes the voltage on the open transistor 460 and the stable voltage of the Zener diode 430, which is equivalent to several volts. The voltage on the second (control) electrode of the transistor 350 is equal to the potential Vcc of the low voltage power supply 5 on the low voltage power supply input terminal 143 of the switch 140. The potential difference between the second (control) electrode of the transistor 350 and the anode of the Zener diode 430 is very small, so the input barrier of the transistor 350 is unlikely to be broken down.

[0300] When the control pulse IN ends, the transistor 460 is closed, disconnecting the Zener diode 460 from the first terminal 167 of the surge suppression circuit 160, thereby preventing the Zener diode 460 from failing due to the potential Vcc of the low-voltage power supply 5 entering the anode of the Zener diode 430 from the low-voltage power supply input terminal 143 of the switch 140 through the short-circuit transistor 340.

[0301] Control pulse transmission channel 150 (see Figure 8 ) works as follows.

[0302] During the control pulse IN and when there is no interference (case 1), a pulse with a positive polarity relative to the voltage Vs at the terminal 106 of the low-voltage switch 100b is generated at the output terminal 159 of the control pulse transmission channel 150 and passes through the first input terminal 171 of the interference suppression circuit 170.

[0303] The pulse is generated as follows: when the control pulse IN appears at the control input terminal 102 of the LSC 100b and is transmitted to the second control terminal 145 of the switch 140, the latter is closed, thereby forming a current loop, and the current flows from the power input terminal 153 of the control pulse transmission channel 150 to the first terminal 127 of the controllable current generator 1120.

[0304] The current flows in the control pulse transmission channel 150 along the following loop: power supply input terminal 153 −third resistor 803 −second transistor 880 −first transistor 870 −first resistor 801 −input terminal 151 .

[0305] When the control pulse IN appears, the first transistor 870 is disconnected under the voltage of the DC voltage source 8030, and acts as a buffer stage to ensure that the circuit has sufficient operating speed.

[0306] The pair of transistors, the second transistor 880 and the third transistor 890, form a current mirror, so when current flows through the second transistor 880, current also flows through the third transistor 890. The value of this current is determined by the nominal ratio of the third resistor 803 and the fourth resistor 804. This current generates a voltage drop across the resistor 802, which is transmitted to the terminal 159 as an output pulse of the control pulse transmission channel 150, and the amplitude of the pulse exceeds the specified value of the potential Vs of the terminal 157.

[0307] If a high-intensity pulse interference appears on the terminal 157 of the control pulse transmission channel 150 during the existence of the control pulse IN (case 2), a surge current appears in the circuit of the power supply input terminal 153-the third resistor 803-the second transistor 880-the first transistor 870-the first resistor 801-the input terminal 151 of the control pulse transmission channel 150. At the same time, due to the effect of the current mirror, the pulse interference current also flows through the fourth resistor 804 and the third transistor 890, and generates an additional voltage drop on the second resistor 802. This voltage drop is added to the output pulse voltage of the control pulse transmission channel 150, and is transmitted to the output terminal 159 as an output signal containing the sum of the control pulse and the high-intensity pulse interference.

[0308] When there is no control pulse IN at the control input terminal 102 of the LSC 100b (case 3), the switch 140 will cut off the current loop between the power input terminal 153 and the input terminal 151 of the control pulse transmission channel 150. Similarly, the current will not flow through the fourth resistor 804-the third transistor 890-the second resistor 802, and the control pulse transmission channel 150 will not output a pulse.

[0309] If a high-intensity pulse interference occurs at the terminal 157 of the control pulse transmission channel 150 in the absence of a control pulse (Case 4), a surge current occurs in the circuit of the power supply input terminal 153-the third resistor 803-the second transistor 880-the first transistor 870-the first resistor 801-the input terminal 151 of the control pulse transmission channel 150. In addition, due to the effect of the current mirror, the pulse interference current also flows through the fourth resistor 804 and the third transistor 890, generating an additional voltage drop on the second resistor 802.

[0310] Therefore, during the control pulse IN, the output terminal 159 of the control pulse transmission channel 150 always outputs the control pulse (case 1). If a high-intensity pulse interference occurs (case 2), an interference pulse is added to the output terminal 159. When there is no control pulse IN, the output terminal 159 of the control pulse transmission channel 150 does not output the control pulse (case 3). However, when a high-intensity pulse interference occurs, an interference pulse appears at the output terminal 159 (case 4).

[0311] The working principle of the interference transmission channel 130 is similar to that of the control pulse transmission channel 150, but has the following special features:

[0312] 1) The control pulse does not enter the disturbing transmission channel 130, but it has a fourth transistor 9010 similar to the transistor 350 of the switch 140 (permanently closed due to the connection of the second (control) electrode and the third electrode).

[0313] Therefore, the circuit parameters in the interference transmission circuit 130: power input terminal 133-third resistor 903-second transistor 980-first transistor 970-first resistor 901-fourth transistor 9010 are similar to the corresponding circuit in the control pulse transmission channel 150 (and taking into account the transistor 350), except that no current flows through the circuit when there is a control pulse or no control pulse. No current flows through the following circuits respectively: power input terminal 133-fourth resistor 904-third transistor 990-second resistor 902-terminal 137 of the interference transmission channel 130. Therefore, when the control pulse IN exists or does not exist, the output pulse of the interference transmission channel 130 will not appear on the output terminal 139.

[0314] 2) When high-intensity pulse interference occurs at the terminal 137 of the interference signal transmission channel 130, the working principle of the channel 130 is similar to that of the control pulse transmission channel 150. When high-intensity pulse interference occurs, interference pulses always appear at the output terminal 139 of the interference signal transmission channel 130.

[0315] Therefore, there is no control pulse at the output end 139 of the interference transmission channel 130 at all times, and the interference pulse will only appear when a high-intensity pulse interference appears at the terminal 137.

[0316] Since the working principles of the control pulse transmission channel 150 and the interference transmission channel 130 are similar (taking into account the transistor 350 ), the interference pulses at the input terminals 171 and 175 of the interference suppression circuit 170 a have a high degree of similarity.

[0317] From the output terminal 159 of the control pulse transmission channel 150, the control pulse is output in the first case, or the control pulse and the interference pulse are output in the second case, and enter the first input terminal 171 of the interference suppression circuit 170a, which is connected to the third electrode of the transistor 570.

[0318] In Case 2 and Case 4, the interference pulse enters the second input terminal 175 of the interference suppression circuit 170a from the output terminal 139 of the interference transmission channel 130.

[0319] When a control pulse and a high-intensity pulse interference appear simultaneously at input terminals 171 and 175 (located at the third electrode and the second (control) electrode of transistor 570, respectively), the pulse interference is subtracted at these input terminals, and a positive differential signal of a set amplitude appears on resistor 510 of the interference suppression circuit 170a, which is connected to the first electrode 577 of transistor 570, and the differential signal passes through the output terminal 179 of the interference suppression circuit 170a.

[0320] If high-intensity pulse interference occurs in the absence of a control pulse, the voltages on the third electrode and the second electrode (i.e., the control electrode) of transistor 570 are equal, forming a zero differential signal on the resistor 510 connected to the first electrode 577 of transistor 570 and transmitted to the output terminal 179 of the interference suppression circuit 170a.

[0321] Therefore, if there is a control pulse at the input terminal 171 of the interference suppression circuit 170a (case 1 or 2), a differential signal as a positive pulse will be formed at its output terminal 179 regardless of whether there is high-intensity pulse interference; and if there is no control pulse at the input terminal 171 of the interference suppression circuit 170a (case 3 or 4), a zero differential signal will be formed at its output terminal 179 regardless of whether there is high-intensity pulse interference.

[0322] The differential signal enters the input terminal 181 of the output stage 180 composed of the Schmitt trigger 650 from the output terminal 179 of the interference suppression circuit 170a, and the analog input signal is converted into a digital output signal. From the output terminal 189 of the output stage 180, the digital signal (representing the pulse for controlling the upper transistor of the power switch) is output to the output terminal 105 of the required LSC, which has a sharp enough edge to turn on the upper transistor 7a of the power switch (such as Fig.10b shown, not part of the LSC).

[0323] In this way, the device claimed according to the second embodiment can simultaneously compensate for high-intensity pulse interference with a high rise rate (because the control pulse and interference passing through the same transmission channels 150 and 130 are respectively subtracted), and moderate power consumption in the normal operating mode (because the current flowing through the controllable current generator 1120, the switch 140 and the control pulse transmission channel 150 can be set at an extremely low level (for example, very few milliamperes)), thereby achieving the claimed technical results. In addition, according to the second embodiment, since the current rising time flowing through the controllable current generator 1120, the switch 140 and the control pulse transmission channel 150 at the beginning of the control pulse IN is short, the operating speed of the LSC is improved.

[0324] It will be apparent to those skilled in the art that the various elements of the desired LSC may be implemented.

[0325] For example, in the DC voltage sources 8030 (9030) in the channels 150 and 130 that transmit the control pulse and the interference, respectively (see Figure 8 and Fig. 9 ) can be achieved by connecting the terminal 104 of the device to a voltage divider of the floating low voltage supply 8 (see Figure 2a , 2b), either as a series connection of a resistor and a Zener diode, or in any other way ensuring that the required voltage is generated.

[0326] The current generator 120 and the controllable current generator 1120 can not only Figure 7a , b, can also be implemented in other known ways, for example, the RJWidlar circuit disclosed in U.S. Patent 3,320,439 issued on May 16, 1967.

[0327] Figure 2a , 2b The device shown can be implemented using standard electronic components such as diodes, transistors and resistors or integrated circuits (ICs) (including custom designed ICs). Therefore, the current generator 120 can use an n-channel field effect transistor with a maximum drain-source voltage of 20V, a drain current of not less than 20mA, and a pulse current of not less than 0.5A, such as DMN26DOUT.

[0328] Transistor 355 and 9010 (such as Figure 3 , 9 The maximum drain-source voltage of the transistor (as shown) should not be less than 600 V, and the drain-source capacitance should not exceed 5 pF at a voltage of 500 V. In this case, transistor BSS225 can be used.

[0329] Bipolar transistors can be used to replace the field effect transistors disclosed in the specification and shown in the figures. It particularly relates to transistor pairs 520-530, 730-740 and 880-890 used for current generators 120 and 1120, control pulse transmission channel 150 and current mirrors in interference transmission channel 130.

[0330] The interference suppression circuit 170 may use a comparator such as LT1719. Figure 6 The output stage 180 shown can be implemented using a microchip UCC27511DBV, which has a supply voltage of 4.5...18V, an output current of 4A, an input current of 8A, and an on / off delay of 13ns, or a microchip SN74LVC1G1, which has a supply voltage of 1.65...5.5V, an output / input current of 24mA, and an on / off delay of 1ns.

[0331] Control pulse transmission channel 150 ( Figure 8 ) and interference transmission channel 130( Fig. 9)'s resistors 803 (903) and 804 (904) may have nominal values ​​of 100...200 ohms and 200...300 ohms, respectively.

[0332] Other elements of the LSC 100 may be implemented in any manner known in the art to achieve the claimed technical effects.

[0333] For example, the LSC claimed in the present invention can be made into a microchip, a micromodule or a microcircuit board, preferably a microchip, which can minimize space and reduce manufacturing costs.

[0334] Furthermore, the claimed LSC may also be part of other structures or other microchips, microcomponents or microboards. Unless expressly stated to the contrary, portions of certain elements mentioned in the present disclosure may be different from, partially overlap with, or completely overlap with portions of other elements. Furthermore, portions of certain elements may be placed in different portions of other elements unless expressly stated to the contrary.

[0335] Experimental Results

[0336] In order to verify the feasibility of the claimed technical results, a second embodiment of the LSC for controlling the power switch was scaled and the following results were obtained:

[0337] The interference rise rate dV / dt shall not be less than 100V / ns.

[0338] Power consumption - does not exceed 600mW when the control frequency is 100kHz and the duty cycle is 2.

[0339] The high voltage power supply is not less than 500V.

[0340] The switching delay times are 130 / 180ns respectively.

[0341] As can be seen from the above description and the accompanying drawings, the technical achievement achieved by the present invention is to provide an LSC with enhanced anti-interference capability and very small power dissipation of the upper transistor of the power switch under high voltage power supply.

[0342] However, the present invention is not limited to the above. The present invention is described according to the practical application of its various embodiments. It should be understood that the present invention is not limited to the disclosed embodiments, but rather, the present invention is intended to be used for various modifications and equivalent implementations corresponding to the suggestions and spirit of the following claims.

[0343] Therefore, the description and drawings are merely illustrative and do not limit the possibilities of implementing the present invention.

[0344] The proposed technology is defined by the following claims.

Claims

1. A level conversion circuit (100a) for controlling a power switch, the circuit comprising a current generator (120) and a switch (140), wherein a second terminal (129) of the current generator (120) is connected to a first terminal (147) of the switch (140), and a second control terminal (145) of the switch (140) is connected to an input terminal (102) of the level conversion circuit (100a), characterized in that: The level conversion circuit (100a) further comprises an interference transmission channel (130), a control pulse transmission channel (150), and an interference suppression circuit (170) for generating an output signal of the level conversion circuit (100a) for controlling a power switch; a third end (149) of the switch (140) is connected to an input end (151) of the control pulse transmission channel (150); a first input end (171) of the interference suppression circuit (170) is connected to an output end (159) of the control pulse transmission channel (150); and a second input end (175) of the interference suppression circuit (170) is connected to an output end (139) of the interference transmission channel (130).

2. The level conversion circuit (100a) according to claim 1, characterized in that: The control pulse transmission channel (150) comprises a first transistor (870), a second transistor (880) forming a current mirror with a third transistor (890), a low voltage power supply (8030), a first resistor (801), a second resistor (802), a third resistor (803), and a fourth resistor (804), wherein the input end (151) of the control pulse transmission channel (150) is connected to the first resistor (801), the first resistor (801) is sequentially connected in series with the first transistor (890) and the fourth resistor (804), wherein the input end (151) of the control pulse transmission channel (150) is connected to the first resistor (801), the first resistor (801) is sequentially connected in series with the first transistor (870), the second transistor (880) and the third resistor (803), the third resistor (803) is sequentially connected in series with the control pulse transmission channel (150) ) and the terminal (157) of the control pulse transmission channel (150). A second resistor (802) is connected to the power input terminal (153) of the control pulse transmission channel (150), and is connected in series with a third transistor (890) and a fourth resistor (804) which are also connected to the power input terminal (153) of the control pulse transmission channel (150). Also connected to the terminal (157) of the control pulse transmission channel (150) is the negative electrode of the low voltage power supply (8030), whose positive electrode is connected to the second control electrodes of the second and first transistors (870), while the second control electrodes of the second transistor (880) and the third transistor (890) are connected to each other and to the first electrode of the first transistor (870) and the third electrode of the second transistor (880). The connection point between the first electrode of the third transistor (890) and the second resistor (802) is connected to the output terminal (159) of the control pulse transmission channel (150).

3. The level conversion circuit (100a) according to claim 1, characterized in that: The interference transmission channel (130) comprises a first transistor (970), a second transistor (980) forming a current mirror with a third transistor (990), a fourth transistor (9010), a low voltage power supply (9030), a first resistor (901), a second resistor (902), a third resistor (903) and a fourth resistor (904), a low voltage power supply input terminal (135) of the interference transmission channel (130) connected in series with the fourth transistor (9010), a first resistor (901), a first transistor (970), a second transistor (980) and a third resistor (903) connected in series with a high voltage power supply input terminal (133) of the interference transmission channel (130), a terminal (137) of the interference transmission channel (130) connected in series with the second resistor (902), and a third transistor (904). 90) and a fourth resistor (904), the latter is also connected to the high voltage power supply input terminal (133) of the interference transmission channel (130), the terminal (137) of the interference transmission channel (130) is also connected to the negative electrode of the low voltage power supply (9030), its positive electrode is connected to the second control electrode of the first transistor (970), the second control, the second control electrode of the second transistor (980) and the second control electrode of the third transistor (990) are mutually connected, and are connected to the first electrode of the first transistor (970) and the third electrode of the second transistor (980), the connection point between the first electrode of the third transistor (980) and the second resistor (902) is connected to the output terminal (139) of the interference transmission channel (130), and the second control electrode of the fourth transistor (9010) is connected to its third electrode.

4. The level shift circuit (100a) according to claim 1, characterized in that The interference suppression circuit (170) includes a transistor (570) and a resistor (510), wherein a third electrode (571) of the transistor (570) is connected to a first input terminal (171) of the interference suppression circuit (170), a second control electrode (575) of the transistor (570) is connected to a second input terminal (175) of the interference suppression circuit (170), a first electrode (577) of the transistor (570) is connected to the second input terminal (175) of the interference suppression circuit (170), and a resistor (510) is connected to the first control electrode (575) of the transistor (570). The second control electrode (575) of (570) is connected to the third input terminal (171) of the interference suppression circuit (170), the second control electrode (575) of the transistor (570) is connected to the second input terminal (175) of the interference suppression circuit (170), the first electrode (577) of the transistor (570) is connected to the output terminal (179) of the interference suppression circuit (170), and the resistor (510) is connected between the output terminal (179) and the terminal (177) of the interference suppression circuit (170).

5. The level conversion circuit (100a) according to claim 1, characterized in that: The interference suppression circuit (170) comprises a first transistor (570), a second transistor (520), a third transistor (530) and a resistor (510), wherein a first input terminal (171) of the interference suppression circuit (170) is connected to a third electrode (571) of the first transistor (570), a second input terminal (175) of the interference suppression circuit (170) is connected to a second control electrode (575) of the first transistor (570), a first electrode (577) of the first transistor (570) is connected to a connection point between a first electrode (527) of the second transistor (520) and the second control electrode (525), The second control electrode (525) of the second transistor (520) is connected to the second control electrode (535) of the third transistor (530); the third electrode (521) of the second transistor (520) is connected to the third electrode (531) of the third transistor (530) and is connected to the power supply input terminal (173) of the interference suppression circuit (170); the output terminal (179) of the interference suppression circuit (170) is connected to the first electrode (537) of the third transistor (530) and the first terminal (511) of the resistor (510); and the second terminal (513) thereof is connected to the terminal (177) of the interference suppression circuit (170).

6. The level conversion circuit (100a) according to claim 1, characterized in that: It comprises an output stage (180), whose input terminal (181) is connected to the output terminal (179) of the interference suppression circuit (170), and whose output terminal (189) is the output terminal of the level conversion circuit (100a).

7. The level conversion circuit (100a) according to claim 6, characterized in that: The output stage (180) includes a Schmitt trigger (650), an input terminal (181) of the output stage is connected to an input terminal (651) of the Schmitt trigger (650), an output terminal (655) of the Schmitt trigger (650) is connected to an output terminal (189) of the output stage (180), a power input terminal (652) of the Schmitt trigger (650) is connected to a power input terminal (183) of the output stage (180), and a terminal (654) of the Schmitt trigger (650) is connected to a terminal (187) of the output stage (180) for connecting a common wire.

8. The level conversion circuit (100a) according to claim 1, characterized in that: The current generator (120) comprises a first transistor (730) and a second transistor (740), wherein a first electrode (733) of the first transistor (730) and a connection point between a second control electrode (735) of the first transistor (730) and a second control electrode (745) are connected to a control input terminal (126) of the current generator (120), a first electrode (743) of the second transistor (740) is connected to the control input terminal (126) of the current generator (120), an electrode (745) of the second transistor (740) is connected to the control input terminal (126) of the current generator (120), a first electrode (743) of the second transistor (740) is connected to a second terminal (129) of the current generator (120), and a third electrode (737) of the first transistor (730) and a third electrode (747) of the second transistor (740) are connected to each other and to the first terminal (127) of the current generator (120).

9. The level conversion circuit (100a) according to claim 1, characterized in that: The switch (140) includes a first transistor (340), a second transistor (350) and a resistor (360), wherein a first terminal (365) of the resistor (360) is connected to a low voltage power supply input terminal (143) of the switch (140), a second control electrode (345) of the first transistor (340) is connected to a second control terminal (145) of the switch (140), a second control electrode (355) of the second transistor (350) is connected to a second terminal (367) of the resistor (360) and a first terminal (368) of the first transistor The three electrodes (347) and the second control electrode (355) of the second transistor (350) are connected to the second terminal (367) of the resistor (360) and the third electrode (347) of the first transistor (340), the first electrode (343) of the first transistor (340) and the third electrode (357) of the second transistor (350) are connected to the first terminal (147) of the switch (140), and the first electrode (353) of the second transistor (350) is connected to the third terminal (149) of the switch (140).

10. The level conversion circuit (100a) according to claim 1, characterized in that: It also includes a surge suppression circuit (160) connected in parallel with the current generator (120), the circuit including a transistor (460) and a Zener diode (430), the second control electrode (465) of the transistor (460) being connected to the second control input terminal (165) of the surge suppression circuit (160), the anode (432) of the Zener diode (430) being connected to the first electrode (463) of the transistor (460), the cathode (435) of the transistor (460) being connected to the second control input terminal (165) of the surge suppression circuit (160), the anode (432) of the Zener diode (430) being connected to the first electrode (463) of the transistor (460), the cathode (435) of the Zener diode (430) being connected to the first terminal (169) of the surge suppression circuit (160), and the third electrode (467) of the transistor (460) being connected to the second terminal (167) of the surge suppression circuit (160).

11. A level conversion circuit (100b) for controlling a power switch, the circuit comprising a switch (140), wherein a second control terminal of the switch (140) is connected to an input terminal (102) of the level conversion circuit (100b), wherein: The level shifting circuit (100b) further comprises a controllable current generator (1120), a control pulse transmission channel (150), an interference transmission channel (130) and an interference suppression circuit (170), which generates an output signal of the level shifting circuit (100b) for controlling a power switch, wherein a second terminal 129 of the controllable current generator 1120 is connected to a first terminal (147) of a switch 140, a third terminal (149) of the switch 140 is connected to an input terminal (151) of the control pulse transmission channel (150), a first input terminal (171) of the interference suppression circuit (170) is connected to an output terminal (159) of the control pulse transmission channel (150), a second input terminal (175) of the interference suppression circuit (170) is connected to an output terminal (139) of the interference transmission channel (130), and a pulse input terminal (1125) of the controllable current generator (1120) is connected to an input terminal (102) of the level shifting circuit (100b).

12. The level conversion circuit (100b) according to claim 11, characterized in that: The control pulse transmission channel (150) comprises a first transistor (870), a second transistor (880) forming a current mirror with a third transistor (890), a low voltage power supply (8030), a first resistor (801), a second resistor (802), a third resistor (803), and a fourth resistor (804), wherein an input terminal (151) of the control pulse transmission channel (150) is connected to the first resistor (801), the first resistor (801) is connected in series with the first transistor (870), the second transistor (880), and the third resistor (803) in sequence, the third resistor (803) is connected to a power supply input terminal (153) of the control pulse transmission channel (150), and a second resistor (804) is connected to a terminal (157) of the control pulse transmission channel (150). A resistor (802) is connected in series with a third transistor (890) and a fourth resistor (804) which are also connected to the power input terminal (153) of the control pulse transmission channel (150). Also connected to the terminal (157) of the control pulse transmission channel (150) is the negative electrode of the low voltage power supply (8030). Its positive electrode is connected to the second control electrodes of the second and first transistors (870). The second control electrodes of the second transistor (880) and the third transistor (890) are connected to each other and to the first electrode of the first transistor (870) and the third electrode of the second transistor (880). The connection point between the first electrode of the third transistor (890) and the second resistor (802) is connected to the output terminal (159) of the control pulse transmission channel (150).

13. The level conversion circuit (100b) according to claim 11, characterized in that: The interference transmission channel (130) comprises a first transistor (970), a second transistor (980) forming a current mirror with a third transistor (990), a fourth transistor (9010), a low voltage power supply (9030), a first resistor (901), a second resistor (902), a third resistor (903) and a fourth resistor (904), a low voltage power supply input terminal (135) of the interference transmission channel (130) connected in series with the fourth transistor (9010), a first resistor (901), a first transistor (970), a second transistor (980) and a third resistor (903) connected in series with a high voltage power supply input terminal (133) of the interference transmission channel (130), a terminal (137) of the interference transmission channel (130) connected in series with the second resistor (902), and a third transistor (904). 90) and a fourth resistor (904), the latter is also connected to the high voltage power supply input terminal (133) of the interference transmission channel (130), the terminal (137) of the interference transmission channel (130) is also connected to the negative electrode of the low voltage power supply (9030), its positive electrode is connected to the second control electrode of the first transistor (970), the second control, the second control electrode of the second transistor (980) and the second control electrode of the third transistor (990) are mutually connected, and are connected to the first electrode of the first transistor (970) and the third electrode of the second transistor (980), the connection point between the first electrode of the third transistor (980) and the second resistor (902) is connected to the output terminal (139) of the interference transmission channel (130), and the second control electrode of the fourth transistor (9010) is connected to its third electrode.

14. The level conversion circuit (100b) according to claim 11, characterized in that: The interference suppression circuit (170) includes a transistor (570) and a resistor (510), wherein a third electrode (571) of the transistor (570) is connected to a first input terminal (171) of the interference suppression circuit (170), a second control electrode (575) of the transistor (570) is connected to a second input terminal (175) of the interference suppression circuit (170), a first electrode (577) of the transistor (570) is connected to the second input terminal (175) of the interference suppression circuit (170), and a resistor (510) is connected to the first control electrode (575) of the transistor (570). The second control electrode (575) of (570) is connected to the third input terminal (171) of the interference suppression circuit (170), the second control electrode (575) of the transistor (570) is connected to the second input terminal (175) of the interference suppression circuit (170), the first electrode (577) of the transistor (570) is connected to the output terminal (179) of the interference suppression circuit (170), and the resistor (510) is connected between the output terminal (179) and the terminal (177) of the interference suppression circuit (170).

15. The level conversion circuit (100b) according to claim 11, characterized in that: The interference suppression circuit (170) comprises a first transistor (570), a second transistor (520), a third transistor (530) and a resistor (510), wherein a first input terminal (171) of the interference suppression circuit (170) is connected to a third electrode (571) of the first transistor (570), a second input terminal (175) of the interference suppression circuit (170) is connected to a second control electrode (575) of the first transistor (570), a first electrode (577) of the first transistor (570) is connected to a connection point between a first electrode (527) of the second transistor (520) and the second control electrode (525), and a second transistor (530) is connected to a third electrode (571) of the first transistor (570). The second control electrode (525) of the transistor (520) is connected to the second control electrode (535) of the third transistor (530); the third electrode (521) of the second transistor (520) and the third electrode (531) of the third transistor (530) are connected to each other and to the power supply input terminal (173) of the interference suppression circuit (170); the output terminal (179) of the interference suppression circuit (170) is connected to the first electrode (537) of the third transistor (530) and the first terminal (511) of the resistor (510); and the second terminal (513) thereof is connected to the terminal (177) of the interference suppression circuit (170).

16. The level shift circuit (100b) according to claim 11, characterized in that: It comprises an output stage (180) whose input terminal (181) is connected to the output terminal (179) of the interference suppression circuit (170) and whose output terminal (189) is the output terminal of the level shifting circuit (100b).

17. The level conversion circuit (100b) according to claim 16, characterized in that: The output stage (180) includes a Schmitt trigger (650), an input terminal (181) of the output stage is connected to an input terminal (651) of the Schmitt trigger (650), an output terminal (655) of the Schmitt trigger (650) is connected to an output terminal (189) of the output stage (180), a power input terminal (652) of the Schmitt trigger (650) is connected to a power input terminal (183) of the output stage (180), and a terminal (654) of the Schmitt trigger (650) is connected to a terminal (187) of the output stage (180) for connecting a common wire.

18. The level shift circuit (100b) according to claim 11, characterized in that: The controllable current generator (1120) includes a first transistor (730), a second transistor (740), a third transistor (720), a driving type multi-frequency device (710), a first resistor (750), a second resistor (770) and a third resistor (760), a connection point between a first electrode (733) of the first transistor (730) and a second transistor (740), the first resistor (750), the second resistor (770) and the third resistor (760), a first electrode (733) of the first transistor (730) and a connection point between a second control electrode (735) and a second control electrode (745) of the first transistor (730), the control electrode (745) of the second transistor (740) is connected to a control input terminal (126) of the controllable current generator (1120), a first electrode (743) of the second transistor (740) is connected to a second terminal (129) of the controllable current generator (1120), and the first transistor The third electrode (737) of the transistor (730) is connected to the first terminal (127) of the controllable current generator (1120) via the first resistor (750), the third electrode (747) of the second transistor (740) is connected to the first terminal (127) via the second resistor (770), the terminal (763) of the third resistor (760) is connected to a common point between the third electrode of the second transistor (740) and the second resistor (770), and the terminal (761) of the third resistor (760) is connected to the first terminal (127) of the controllable current generator (1120) via the first resistor (750). A first electrode (723) connected to a third transistor (720), a second control electrode (725) of the third transistor (720) is connected to an output terminal (719) of a driven multi-frequency oscillator (710), a third electrode (727) of the third transistor (720) is connected to a first terminal (127) of a controllable current generator (1120), and an input terminal (711) of the driven multi-frequency oscillator (710) is connected to a pulse input terminal (1125) of the controllable current generator (1120).

19. The level conversion circuit (100b) according to claim 11, characterized in that: The switch (140) includes a first transistor (340), a second transistor (350) and a resistor (360), wherein a first terminal (365) of the resistor (360) is connected to a low voltage power supply input terminal (143) of the switch (140), a second control electrode (345) of the first transistor (340) is connected to a second control terminal (145) of the switch (140), a second control electrode (355) of the second transistor (350) is connected to a second terminal (367) of the resistor (360) and a first terminal (368) of the first transistor The three electrodes (347) and the second control electrode (355) of the second transistor (350) are connected to the second terminal (367) of the resistor (360) and the third electrode (347) of the first transistor (340), the first electrode (343) of the first transistor (340) and the third electrode (357) of the second transistor (350) are connected to the first terminal (147) of the switch (140), and the first electrode (353) of the second transistor (350) is connected to the third terminal (149) of the switch (140).

20. The level conversion circuit (100b) according to claim 11, characterized in that: It also includes a surge suppression circuit (160) connected in parallel with the controllable current generator (1120), the circuit including a transistor (460) and a Zener diode (430), the second control electrode (465) of the transistor (460) being connected to the second control input terminal (165) of the surge suppression circuit (160), the anode (432) of the Zener diode (430) being connected to the first electrode (463) of the transistor (460), the cathode (435) of the Zener diode (430) being connected to the first terminal (169) of the surge suppression circuit (160), and the third electrode (467) of the transistor (460) being connected to the second terminal (167) of the surge suppression circuit (160).

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