Photodetector, method of manufacturing same, and electronic apparatus

Abstract

Provided is a photodetector capable of preventing deterioration in conductivity of wiring between semiconductor substrates that are bonded. The light detector includes a first semiconductor substrate including a first semiconductor layer provided with a photoelectric conversion element and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, a second semiconductor substrate including a second wiring layer stacked on a surface of the first semiconductor layer opposite to the light incident surface, and a third semiconductor substrate including a second wiring layer stacked on a surface of the second semiconductor layer opposite to the light incident surface, and a first conductor extending in a thickness direction. The second semiconductor substrate includes a second semiconductor layer, a second wiring layer stacked on one surface of the second semiconductor layer, and a third wiring layer stacked on the other surface of the second semiconductor layer, and the third semiconductor substrate includes a third semiconductor layer and a fourth wiring layer stacked on the third semiconductor layer, the first wiring layer and the second wiring layer are bonded, a bonding surface between the first wiring layer and the second wiring layer is a first bonding surface, the third wiring layer and the fourth wiring layer are bonded, a bonding surface between the third wiring layer and the fourth wiring layer is a second bonding surface, and the first conductor penetrates through the first bonding surface and is integrally arranged without a joint.

Description

Technical Field

[0001] The present technology (technology according to the present disclosure) relates to a photodetector, a method of manufacturing the photodetector, and an electronic device, and particularly to a photodetector in which a plurality of semiconductor substrates are bonded to each other, a method of manufacturing the photodetector, and an electronic device. Background Art

[0002] Hitherto, a known photodetector has a structure in which a plurality of semiconductor substrates are bonded to each other. For example, Patent Document 1 discloses a semiconductor device obtained by bonding a first semiconductor element to a second semiconductor element at a bonding surface. In addition, by bonding a pair of conductor portions at the bonding surface, wiring on the first semiconductor element side is connected to wiring on the second semiconductor element side. Citation List Patent Literature

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-65016 Summary of the invention Technical issues

[0004] As pixels become smaller, it is necessary to reduce the size of the above-mentioned conductor portion.

[0005] The present technology aims to provide a photodetector capable of preventing deterioration in wiring conductivity between bonded semiconductor substrates, a method for manufacturing the photodetector, and an electronic device.

Problem solving method

[0006] According to one aspect of the present technology, a photodetector includes a first semiconductor substrate, a second semiconductor substrate, a third semiconductor substrate and a first conductor extending in a thickness direction, wherein the first semiconductor substrate includes a first semiconductor layer provided with a photoelectric conversion element, and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, the second semiconductor substrate includes a second semiconductor layer, a second wiring layer stacked on one surface of the second semiconductor layer, and a third wiring layer stacked on another surface of the second semiconductor layer, the third semiconductor substrate includes a third semiconductor layer, and a fourth wiring layer stacked on the third semiconductor layer, the first wiring layer is bonded to the second wiring layer, and a bonding surface between the first wiring layer and the second wiring layer is a first bonding surface, the third wiring layer is bonded to the fourth wiring layer, and a bonding surface between the third wiring layer and the fourth wiring layer is a second bonding surface, and the first conductor passes through the first bonding surface and is integrally arranged without a joint.

[0007] A method for manufacturing a photodetector according to one aspect of the present technology includes: preparing a first semiconductor substrate including a first semiconductor layer provided with a photoelectric conversion element and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, and a second semiconductor substrate including a second semiconductor layer and a second wiring layer stacked on one surface of the second semiconductor layer, overlapping and joining the first wiring layer and the second wiring layer, forming a hole that penetrates the second semiconductor layer in a thickness direction and penetrates a first joining surface that serves as a joining surface between the first wiring layer and the second wiring layer from the other surface side of the second semiconductor layer, and burying a conductive material in the hole to thereby form a first conductor.

[0008] An electronic device according to an aspect of the present technology includes the above-mentioned photodetector and an optical system configured to form an image of image light from an object on the above-mentioned photodetector. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a chip layout diagram showing one configuration example of the photodetector according to the first embodiment of the present technology. Figure 2 is a block diagram showing one configuration example of a photodetector according to the first embodiment of the present technology. Figure 3 is an equivalent circuit diagram of a pixel of the photodetector according to the first embodiment of the present technology. Figure 4A is a longitudinal sectional view showing a sectional structure of a pixel of a photodetector according to the first embodiment of the present technology. Figure 4B Yes Figure 4A A longitudinal cross-sectional view showing an enlarged view of a main part of the Figure 5A : is a transparent plan view showing the arrangement relationship among the first conductor, the charge accumulation region, and the gate electrode of the transistor provided in the first semiconductor layer in the photodetector according to the first embodiment of the present technology. Figure 5B : is a transparent plan view showing an arrangement relationship between a first conductor in a photodetector according to a first embodiment of the present technology and a connection pad of a shield wiring at a first joint surface. Figure 5C : is a transparent plan view showing an arrangement relationship among a first conductor in a photodetector according to a first embodiment of the present technology, a gate electrode of a transistor provided in a second semiconductor layer, and a wiring configured to connect the first conductor to the gate electrode. Figure 5D : is a transparent plan view showing the arrangement relationship between the first conductor and the insulating film on the fourth surface side of the second semiconductor layer in the photodetector according to the first embodiment of the present technology. Fig. 6A1 is a process cross-sectional view showing a method of manufacturing the photodetector according to the first embodiment of the present technology. Figure 6B yes Fig. 6A A cross-sectional view of the process afterwards. Figure 6C yes Figure 6B A cross-sectional view of the process afterwards. Fig.6D yes Figure 6C A cross-sectional view of the process afterwards. Fig. 6E yes Fig.6D A cross-sectional view of the process afterwards. Fig. 6F yes Fig. 6E A cross-sectional view of the process afterwards. Figure 7 is a longitudinal cross-sectional view showing a cross-sectional structure of a part of a pixel of a photodetector including a first conductor having a configuration similar to that of a shield wiring. Figure 8 It is a transparent plan view showing the arrangement relationship among a first conductor in a photodetector according to Modification 1 of the first embodiment of the present technology, a gate electrode of a transistor provided in a second semiconductor layer, and a wiring configured to connect the first conductor to the gate electrode. Fig. 9A : is a longitudinal cross-sectional view showing a cross-sectional structure of a pixel of a photodetector according to Modification 2 of the first embodiment of the present technology. Fig. 9B It is a transparent plan view showing the arrangement relationship among a first conductor in a photodetector according to Modification 2 of the first embodiment of the present technology, a gate electrode of a transistor provided in a second semiconductor layer, and a wiring configured to connect the first conductor to the gate electrode. Fig.10 It is a transparent plan view showing the arrangement relationship among a first conductor in a photodetector according to Modification 3 of the first embodiment of the present technology, a gate electrode of a transistor provided in a second semiconductor layer, and a wiring configured to connect the first conductor to the gate electrode. Fig.11A : is a longitudinal cross-sectional view showing a cross-sectional structure of a pixel of a photodetector according to Modification 4 of the first embodiment of the present technology. Fig. 11B It is a transparent plan view showing an arrangement relationship between a first conductor in a photodetector according to Modification 4 of the first embodiment of the present technology and a gate electrode of a transistor provided in a second semiconductor layer. Fig.12 It is a transparent plan view of the arrangement relationship between the first conductor in the photodetector according to the modification example 5 of the first embodiment of the present technology and the gate electrode of the transistor provided in the second semiconductor layer. Fig.13 is a longitudinal sectional view showing, in an enlarged manner, a part of the sectional structure of a pixel of a photodetector according to a second embodiment of the present technology. Fig.14 It is a longitudinal cross-sectional view showing, in an enlarged manner, a part of the cross-sectional structure of a pixel of a photodetector according to Modification 1 of the second embodiment of the present technology. Fig.15 It is a longitudinal cross-sectional view showing, in an enlarged manner, a part of the cross-sectional structure of a pixel of a photodetector according to Modification 2 of the second embodiment of the present technology. Fig.16 is a longitudinal sectional view showing a sectional structure of a pixel of a photodetector according to a third embodiment of the present technology. Fig.17 : is a process cross-sectional view showing a method of manufacturing a photodetector according to a third embodiment of the present technology. Fig.18 is a block diagram showing a schematic configuration example of an electronic device. Fig.19 is a block diagram showing a schematic configuration example of a vehicle control system. Fig. 20 It is a diagram for assisting in explaining an example of the installation positions of the vehicle exterior information detection unit and the imaging unit. Fig.21 is a diagram showing a schematic configuration example of an endoscopic surgery system. Fig. 22 is a block diagram showing an example of the functional configuration of a camera head and a camera control unit (CCU). DETAILED DESCRIPTION

[0010] Now, the preferred mode for carrying out the present technology is described with reference to the drawings. Note that the embodiments described below represent examples of representative embodiments of the present technology, and the scope of the present technology should not be narrowly interpreted by these embodiments.

[0011] In the description of the drawings referred to below, the same or similar parts are represented by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and therefore, the relationship between the thickness and the plane size, the ratio of the thickness of each layer, etc. are different from the actual. Therefore, the specific thickness and size should be determined in consideration of the following description. In addition, there are of course partial differences in the dimensional relationship and ratio of the drawings. In addition, since drawings suitable for explaining the present technology are used, there are differences in the construction between the drawings in some cases.

[0012] In addition, the embodiments described below are examples of devices or methods for implementing the technical ideas of the present technology, and in the technical ideas of the present technology, the materials, shapes, structures, and arrangements of the components are not specific to the contents described below. The technical ideas of the present technology can be modified in various ways within the technical scope defined by the claims in the claims. In addition, the definitions of directions such as up and down in the following description are only made for the convenience of explanation and are not intended to limit the technical ideas of the present disclosure. For example, if an object is rotated 90º and observed, up and down are interpreted as left and right, and if the object is rotated 180º and observed, up and down are interpreted as upside down, which is a matter of course.

[0013] The description is given in the following order. 1. First Embodiment 2. Second Embodiment 3. Third embodiment 4. Fourth embodiment Application examples on electronic devices Application examples on mobile objects Application examples in endoscopic surgery systems

[0014] [First embodiment] In the present embodiment, an example in which the present technology is applied to a photodetector (back side illumination type CMOS (Complementary Metal Oxide Semiconductor) image sensor) is described.

[0015] <<Overall Structure of Photodetector>> First, the overall structure of the photodetector 1 is described. Figure 1 As shown, the photodetector 1 according to the first embodiment of the present technology mainly includes a semiconductor chip 2 having a rectangular two-dimensional planar shape in a plan view. That is, the photodetector 1 is mounted in the semiconductor chip 2. Fig.18 As shown, the photodetector 1 captures image light (incident light 106) from an object through an optical system (optical lens) 102, converts the amount of incident light 106 (whose image is formed on an image capturing surface) into an electrical signal for each pixel, and outputs the electrical signal as a pixel signal.

[0016] like Figure 1 As shown in FIG. 1 , in a two-dimensional plane including the X direction and the Y direction intersecting each other, the semiconductor chip 2 on which the photodetector 1 is mounted includes a rectangular pixel region 2A disposed at the center portion and a peripheral region 2B disposed around the pixel region 2A outside the pixel region 2A. The pixel region 2A is for receiving Fig.18The optical system 102 shown in FIG. 2A is a light receiving surface of light gathered by the optical system 102. In addition, in the pixel area 2A, a plurality of pixels 3 are arranged in a matrix form in a two-dimensional plane including an X direction and a Y direction. In other words, the pixels 3 are repeatedly arranged in the two-dimensional plane along the X direction and the Y direction that intersect each other. Note that in the present embodiment, as an example, the X direction is orthogonal to the Y direction. In addition, the direction orthogonal to both the X direction and the Y direction is the Z direction (thickness direction or stacking direction). In addition, the direction perpendicular to the Z direction is the horizontal direction.

[0017] like Figure 1 As shown, a plurality of bonding pads 14 are arranged in the peripheral region 2B. For example, the plurality of bonding pads 14 are arranged along each of the four sides of the semiconductor chip 2 in a two-dimensional plane. Each of the plurality of bonding pads 14 is an input / output terminal used when the semiconductor chip 2 is electrically connected to an external device.

[0018] <Logic Circuit> like Figure 2 As shown, the semiconductor chip 2 includes a logic circuit 13. The logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, a control circuit 8, etc. The logic circuit 13 includes a CMOS (Complementary MOS) circuit, which includes, for example, an n-channel conductive type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and a p-channel conductive type MOSFET as field effect transistors.

[0019] The vertical drive circuit 4 includes, for example, a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive line 10, supplies a pulse for driving the pixel 3 to the selected pixel drive line 10, and drives each pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each pixel 3 in the pixel area 2A row by row in the vertical direction, and supplies a pixel signal from the pixel 3 based on a signal charge generated by a photoelectric conversion element of each pixel 3 according to the amount of received light to the column signal processing circuit 5 through the vertical signal line 11.

[0020] For example, the column signal processing circuit 5 is provided for each column of the pixels 3, and performs signal processing such as noise elimination on the signals output by the pixels 3 in one row for each pixel column. For example, the column signal processing circuit 5 performs signal processing such as CDS (correlated double sampling) and AD (analog-to-digital) conversion to eliminate pixel-specific fixed pattern noise. A horizontal selection switch (not shown) is connected between the output stage of the column signal processing circuit 5 and the horizontal signal line 12.

[0021] The horizontal drive circuit 6 includes, for example, a shift register, and sequentially selects each column signal processing circuit 5 by sequentially outputting horizontal scanning pulses to the column signal processing circuit 5 , and causes each column signal processing circuit 5 to output a pixel signal after signal processing to the horizontal signal line 12 .

[0022] The output circuit 7 processes and outputs pixel signals sequentially supplied from the column signal processing circuits 5 through the horizontal signal line 12. The signal processing may use buffering, black level adjustment, column difference correction, or various types of digital signal processing, for example.

[0023] Based on the vertical synchronization signal, the horizontal synchronization signal, and the main clock signal, the control circuit 8 generates a clock signal and a control signal as an operation reference of the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. Then, the control circuit 8 outputs the generated clock signal and control signal to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0024] <Pixels> Figure 3 is an equivalent circuit diagram showing one configuration example of the pixel 3. Figure 3 In the example of , a plurality of pixels 3 share a single charge accumulation region (floating diffusion) FD and a readout circuit 15. More specifically, four pixels 3 share a single charge accumulation region FD and a readout circuit 15. The pixel 3 includes a photoelectric conversion element PD and a transfer transistor TR configured to transfer a signal charge generated by the photoelectric conversion element PD through photoelectric conversion to the charge accumulation region FD. The readout circuit 15 is connected to the subsequent stage of the charge accumulation region FD.

[0025] The photoelectric conversion element PD generates a signal charge corresponding to the amount of received light. In addition, the photoelectric conversion element PD temporarily accumulates (holds) the generated signal charge. The cathode side of the photoelectric conversion element PD is electrically connected to the source region of the transfer transistor TR, and the anode side thereof is electrically connected to a reference potential line (e.g., ground). For example, a photodiode is used as the photoelectric conversion element PD.

[0026] The drain region of the transfer transistor TR is electrically connected to the charge accumulation region FD. The gate electrode of the transfer transistor TR is electrically connected to a transfer transistor drive line among the pixel drive lines 10 (see Figure 2 ).

[0027] The charge accumulation region FD temporarily accumulates or holds the signal charge transferred from the photoelectric conversion element PD through the transfer transistor TR.

[0028] The readout circuit 15 reads out the signal charge accumulated in the charge accumulation region FD and outputs a pixel signal based on the signal charge. The readout circuit 15 includes, but is not limited to, for example, an amplifier transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors. These transistors (AMP, SEL, and RST) include MOSFETs, which include, for example, a gate insulating film including a silicon oxide film (SiO2 film), a gate electrode, and a pair of main electrode regions used as a source region and a drain region. In addition, these transistors can be MISFETs (metal insulator semiconductor FETs), which include a gate insulating film including a silicon nitride film (Si3N4 film) or a stacked film including a silicon nitride film and a silicon oxide film.

[0029] The source region of the amplifier transistor AMP is electrically connected to the drain region of the selection transistor SEL, and its drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor. In addition, the gate electrode of the amplifier transistor AMP is electrically connected to the charge accumulation region FD and the source region of the reset transistor RST.

[0030] The source region of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain thereof is electrically connected to the source region of the amplifier transistor AMP. In addition, the gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line among the pixel drive lines 10 (see Figure 2 ).

[0031] The source region of the reset transistor RST is electrically connected to the charge accumulation region FD and the gate electrode of the amplifier transistor AMP, and the drain region thereof is electrically connected to the power supply line Vdd and the drain region of the amplifier transistor AMP. The gate electrode of the reset transistor RST is electrically connected to a reset transistor drive line among the pixel drive lines 10 (see Figure 2 ).

[0032] <<Detailed Structure of Photodetector>> use Figure 4A , Figure 4B and FIG. 5A to FIG. 5D The specific configuration of the photodetector 1 will be described. Note that in some drawings, illustration of the barrier metal layer may be omitted.

[0033] <Stacked Structure of Photodetectors> like Figure 4AAs shown, the photodetector 1 (semiconductor chip 2) has a stacked structure in which, for example, a first semiconductor substrate A1, a second semiconductor substrate A2, and a third semiconductor substrate A3 are sequentially stacked, and the stacked structure includes a first conductor 90 and a shield wiring 91 extending in the thickness direction. The first semiconductor substrate A1 includes a first semiconductor layer 20 provided with a photoelectric conversion element PD, and a first wiring layer 30 stacked on a surface (first surface S1) of the first semiconductor layer 20 opposite to the light incident surface (second surface S2). The second semiconductor substrate A2 includes a second semiconductor layer 50, a second wiring layer 40 stacked on one surface (third surface S3) of the second semiconductor layer 50, and a third wiring layer 60 stacked on the other surface (fourth surface S4) of the second semiconductor layer 50. In addition, the third semiconductor substrate A3 includes a third semiconductor layer 80, and a fourth wiring layer 70 stacked on a fifth surface S5 of the third semiconductor layer 80.

[0034] In addition, the first wiring layer 30 is bonded to the second wiring layer 40, and the bonding surface between the first wiring layer 30 and the second wiring layer 40 is a first bonding surface B1. The third wiring layer 60 is bonded to the fourth wiring layer 70, and the bonding surface between the third wiring layer 60 and the fourth wiring layer 70 is a second bonding surface B2. In addition, the photodetector 1 (semiconductor chip 2) includes a light incident surface side stacked body located on the second surface S2 side. The light incident surface side stacked body has, but is not limited to, a stacked structure in which, for example, a flattening film PF, a color filter CF, and a microlens (on-chip lens) ML are stacked in sequence from the second surface S2 side.

[0035] <First Semiconductor Layer> The first semiconductor layer 20 includes a semiconductor substrate. The first semiconductor layer 20 includes, but is not limited to, for example, a single crystal silicon substrate, and one surface thereof is a first surface S1, and the other surface is a second surface S2. Note that the second surface S2 may also be referred to as a light incident surface or a back surface, and the first surface S1 may also be referred to as an element forming surface or a main surface. In a portion of the first semiconductor layer 20 corresponding to the pixel region 2A, a plurality of photoelectric conversion regions 20a arranged in row and column directions are provided. The photoelectric conversion region 20a is provided for each pixel 3. For example, Figure 4A As shown, in the portion of the first semiconductor layer 20 corresponding to the pixel region 2A, an island-shaped photoelectric conversion region 20a separated by a separation region 20b is provided for each pixel 3. In addition, the separation region 20b is, for example, but not limited to, an impurity separation structure formed by injecting impurities into the first semiconductor layer 20. For each photoelectric conversion region 20a, the photoelectric conversion region 20a includes a semiconductor region 21 of a first conductivity type (e.g., p-type) and semiconductor regions 22 and 23 of a second conductivity type (e.g., n-type). In addition, Figure 3The photoelectric conversion element PD shown is formed in the photoelectric conversion region 20a. At least a portion of the photoelectric conversion region 20a performs photoelectric conversion on incident light and generates signal charges. Figure 4A As shown, the photoelectric conversion region 20a is provided with, for example, a transistor T1. The transistor T1 is provided at a position closer to the first surface S1 of the first semiconductor layer 20. The transistor T1 is, for example, Figure 3 The transfer transistor TR is shown. In addition, Figure 4A The semiconductor region 23 shown corresponds to Figure 3 The semiconductor region 23 is sometimes referred to as the charge accumulation region FD below. The semiconductor region 23 is provided at a position closer to the first surface S1 of the first semiconductor layer 20. Note that the number of pixels 3 is not limited to Figure 4A The number of

[0036] <First Wiring Layer> One surface of the first wiring layer 30 is in contact with the first semiconductor layer 20, and the other surface is in contact with the second wiring layer 40. The first wiring layer 30 includes, but is not limited to, for example, an insulating film 31, a wiring 32, a first connection pad 33, and a vertical interconnection (contact portion) 34. In addition, the first wiring layer 30 is provided with a gate electrode G1 of the transistor T1. The wiring 32 and the first connection pad 33 are stacked through the insulating film 31 in the thickness direction. In addition, the wiring 32 and the first connection pad 33 can be formed, for example, by a damascene method, and can be formed integrally with the vertical interconnection (via) by a damascene method. The wiring 32 is a wiring arranged in the first wiring layer 30, and more specifically, a horizontal wiring extending mainly in the horizontal direction among the thickness direction and the horizontal direction. The first connection pad 33 is a wiring arranged in the first wiring layer 30. The first connection pad 33 faces the surface of the first wiring layer 30 located on the second wiring layer 40 side, and is bonded to the second connection pad 43 described later. The first connection pad 33 is bonded to the second connection pad 43, thereby electrically connecting the wiring on the first wiring layer 30 side to the wiring on the second wiring layer 40 side. The vertical interconnection 34 is a wiring arranged in the first wiring layer 30, more specifically, a vertical wiring extending mainly in the thickness direction among the thickness direction and the horizontal direction. The vertical interconnection 34 connects between elements located at different positions in the thickness direction. In addition, one end of the vertical interconnection 34 can be connected to the wiring 32, and the other end thereof can be connected to the first semiconductor layer 20 or an electrode arranged near the first surface S1, such as the gate electrode G1.

[0037] <Second Wiring Layer> One surface of the second wiring layer 40 is in contact with the first wiring layer 30, and the other surface is in contact with the second semiconductor layer 50. The second wiring layer 40 includes, but is not limited to, for example, an insulating film 41, a wiring 42, a second connection pad 43, and a vertical interconnection (contact portion) 44. In addition, the second wiring layer 40 is provided with a gate electrode G2 of the transistor T2 described later. The wiring 42 and the second connection pad 43 are stacked through the insulating film 41 in the thickness direction. In addition, the wiring 42 and the second connection pad 43 can be formed, for example, by a damascene method, and can be formed integrally with the vertical interconnection by a damascene method. The wiring 42 is a wiring arranged in the second wiring layer 40, more specifically, a horizontal wiring extending mainly in the horizontal direction among the thickness direction and the horizontal direction. The second connection pad 43 is a wiring arranged in the second wiring layer 40. The second connection pad 43 faces the surface of the second wiring layer 40 located on the first wiring layer 30 side, and is bonded to the above-mentioned first connection pad 33. The vertical interconnection 44 is a wiring arranged in the second wiring layer 40, more specifically, a vertical wiring extending mainly in the thickness direction among the thickness direction and the horizontal direction. The vertical interconnect 44 connects between elements at different positions in the thickness direction. In addition, one end of the vertical interconnect 44 can be connected to the wiring 42, and the other end thereof can be connected to the second semiconductor layer 50 or an electrode disposed near the third surface S3 of the second semiconductor layer 50, such as the gate electrode G2.

[0038] <Second Semiconductor Layer> The second semiconductor layer 50 includes a semiconductor substrate. The second semiconductor layer 50 includes, but is not limited to, for example, a single crystal silicon substrate, and one surface thereof serves as a third surface S3, and the other surface serves as a fourth surface S4. In addition, the third surface S3 of the second semiconductor layer 50 faces the first semiconductor layer 20. Note that the third surface S3 may also be referred to as an element forming surface or a main surface, and the fourth surface S4 may also be referred to as a back surface. Figure 4A As shown, the second semiconductor layer 50 is provided with a transistor T2. More specifically, the transistor T2 is provided at a position closer to the third surface S3 of the second semiconductor layer 50. The transistor T2 includes, for example, Figure 3 1 and 1 . Note that among the transistors T2, the transistor T2 corresponding to the amplifier transistor AMP is sometimes referred to as a transistor T2A to distinguish it from the other transistors T2. In the case where the transistor T2A is not distinguished from the other transistors T2, the transistor T2A is simply referred to as the transistor T2. In addition, among the gate electrodes G2, the gate electrode of the transistor T2A is sometimes referred to as the gate electrode G2A to distinguish it from the other gate electrodes G2. In the case where the gate electrode G2A is not distinguished from the gate electrode G2, the gate electrode G2A is simply referred to as the gate electrode G2.

[0039] <Third Wiring Layer> One surface of the third wiring layer 60 is in contact with the second semiconductor layer 50, and the other surface is in contact with the fourth wiring layer 70. The third wiring layer 60 includes, but is not limited to, for example, an insulating film 61, a wiring 62, a third connection pad 63, and a vertical interconnection (contact portion) not shown. The wiring 62 and the third connection pad 63 are stacked through the insulating film 61 in the thickness direction. In addition, the wiring 62 and the third connection pad 63 can be formed, for example, by a damascene method, and can be formed integrally with the vertical interconnection by a damascene method. The wiring 62 is a wiring arranged in the third wiring layer 60, and more specifically, a horizontal wiring extending mainly in the horizontal direction among the thickness direction and the horizontal direction. The third connection pad 63 is a wiring arranged in the third wiring layer 60. The third connection pad 63 faces the surface of the third wiring layer 60 located on the fourth wiring layer 70 side, and is bonded to the fourth connection pad 73 described later. The third connection pad 63 is bonded to the fourth connection pad 73, thereby electrically connecting the wiring on the third wiring layer 60 side to the wiring on the fourth wiring layer 70 side. The vertical interconnection portion not shown in the figure is a wiring provided in the third wiring layer 60, more specifically, a vertical wiring extending mainly in the thickness direction among the thickness direction and the horizontal direction. In addition, the vertical interconnection portion connects elements located at different positions in the thickness direction to each other. In addition, the wiring of the third wiring layer 60 and the wiring of the second wiring layer 40 can be electrically connected by a through conductor not shown in the figure. The through conductor is a conductor that penetrates the second semiconductor layer 50. One end of the through conductor is electrically connected to the wiring of the third wiring layer 60, and the other end thereof is electrically connected to the wiring of the second wiring layer 40.

[0040] <Fourth Wiring Layer> One surface of the fourth wiring layer 70 is in contact with the third wiring layer 60, and the other surface is in contact with the third semiconductor layer 80. The fourth wiring layer 70 includes, but is not limited to, for example, an insulating film 71, a wiring 72, a fourth connection pad 73, and a vertical interconnection (contact portion) 74. In addition, the fourth wiring layer 70 is provided with a gate electrode G3 of the transistor T3 described later. The wiring 72 and the fourth connection pad 73 are stacked through the insulating film 71 in the thickness direction. In addition, the wiring 72 and the fourth connection pad 73 can be formed, for example, by a damascene method, and can be formed integrally with the vertical interconnection by a damascene method. The wiring 72 is a wiring arranged in the fourth wiring layer 70, and more specifically, a horizontal wiring extending mainly in the horizontal direction among the thickness direction and the horizontal direction. The fourth connection pad 73 is a wiring arranged in the fourth wiring layer 70. The fourth connection pad 73 faces the surface of the fourth wiring layer 70 located on the third wiring layer 60 side, and is bonded to the above-mentioned third connection pad 63. The vertical interconnection 74 is a wiring arranged in the fourth wiring layer 70, more specifically a vertical wiring extending mainly in the thickness direction among the thickness direction and the horizontal direction. The vertical interconnection 74 connects the elements located at different positions in the thickness direction to each other. In addition, one end of the vertical interconnection 74 can be connected to the wiring 72, and the other end thereof can be connected to the third semiconductor layer 80 or an electrode arranged near the fifth surface S5 of the third semiconductor layer 80, such as the gate electrode G3.

[0041] <Third Semiconductor Layer> The third semiconductor layer 80 includes a semiconductor substrate. The third semiconductor layer 80 includes, but is not limited to, for example, a single crystal silicon substrate, and has a surface located on the fourth wiring layer 70 side as a fifth surface S5. Note that the fifth surface S5 may also be referred to as an element forming surface or a main surface. The third semiconductor layer 80 is provided with a transistor T3. The transistor T3 includes, for example, a transistor forming the logic circuit 13.

[0042] <Shielded wiring> The shielding wiring 91 is arranged across the first wiring layer 30 and the second wiring layer 40. The shielding wiring 91 extends mainly in the thickness direction, and its potential is fixed to a reference potential. More specifically, the shielding wiring 91 has an end closer to the second semiconductor layer 50, which is connected to a region having a reference potential in the second semiconductor layer 50, and the shielding wiring 91 has an end closer to the first semiconductor layer 20, which is connected to a region having a reference potential in the first semiconductor layer 20. In addition, the shielding wiring 91 is arranged between one of the first conductors 90 and another of the first conductors 90 in a plan view. Since the first conductor 90 is a path for signal charges to flow from the charge accumulation region FD to the gate electrode G2A of the transistor T2A, the first conductor 90 may interfere with other adjacent first conductors 90. Shielding wiring is provided to prevent such interference. For example, a plurality of shielding wirings may be provided in a manner to surround the first conductor 90 in a plan view. In Figure 5B In the illustrated example, the shield wiring 91 is provided on three sides of the first conductor 90 in plan view.

[0043] like Figure 4B As shown, the shield wiring 91 has a first portion 91a extending in the first wiring layer 30 and a second portion 91b extending in the second wiring layer 40. The first portion 91a includes a multilayer wiring (wiring 32, a first connection pad 33, and a vertical interconnection 34) disposed in the first wiring layer 30 and connected in the thickness direction. The second portion 91b includes a multilayer wiring (wiring 42, a second connection pad 43, and a vertical interconnection 44) disposed in the second wiring layer 40 and connected in the thickness direction. In addition, the first connection pad 33 of the first portion 91a is bonded to the second connection pad 43 of the second portion 91b at the first bonding surface B1, so that the first portion 91a is bonded to the second portion 91b.

[0044] <First Conductor> The first conductor 90 is disposed Figure 1The first conductor 90 is a vertical wiring extending in the thickness direction of the first wiring layer 30 and the second wiring layer 40 and penetrating the first joint surface B1. In addition, the first conductor 90 penetrates the first joint surface B1 in the thickness direction and is integrally arranged without a joint in the extension direction. The first conductor 90 connects two elements arranged at different heights in the thickness direction between the first semiconductor layer 20 and the second semiconductor layer 50. For example, the first conductor 90 connects the first semiconductor layer 20 to the wiring 42. More specifically, the first conductor 90 connects the charge accumulation region FD to the wiring 42. More specifically, one end of the first conductor 90 (i.e., the end located on the side of the first wiring layer 30) is connected to the charge accumulation region FD. In addition, in the second wiring layer 40, the connection portion of the first conductor 90 (the portion closer to the second semiconductor layer 50) is connected to the wiring 42. Note that the wiring connected to the first conductor 90 among the wirings 42 is referred to as wiring 42A to distinguish it from other wirings 42. In the case where the wiring 42A is not distinguished from other wirings 42, the wiring 42A is simply referred to as the wiring 42. In the second wiring layer 40, the first conductor 90 may be configured to be connected only to the single wiring 42A. Figure 4B and Figure 5C As shown, the wiring 42A is connected to the gate electrode G2A through the vertical interconnect 44. The vertical interconnect configured to connect the wiring 42A to the gate electrode G2A is sometimes referred to as the vertical interconnect 44A to distinguish it from the other vertical interconnects 44. Note that the vertical interconnect 44A is simply referred to as the vertical interconnect 44 without distinguishing the vertical interconnect 44A from the vertical interconnect 44. The connecting portion of the first conductor 90 is electrically connected to the gate electrode G2A through the wiring 42A and the vertical interconnect 44A. That is, the first conductor 90 is directly connected to the charge accumulation region FD at one end, and is indirectly connected to the gate electrode G2A at the connecting portion. The first conductor 90 indirectly connects the charge accumulation region FD and the gate electrode G2A to each other.

[0045] like Figure 5A As shown in FIG. 1 , in a plan view, the first conductor 90 is disposed at a position overlapping with the charge accumulation region FD. Figure 4B and Figure 5C As shown in FIG. 1 , the first conductor 90 penetrates the wiring 42A in the thickness direction. Figure 5C As shown, the connection portion of the first conductor 90 is connected to the inner peripheral surface of the through hole 42h provided in the wiring 42A. Figure 4B As shown, the first conductor 90 penetrating the wiring 42A further penetrates the second semiconductor layer 50 in the thickness direction. In addition, the other end of the first conductor 90 opposite to the one end extends into the insulating film 61 of the third wiring layer 60. Figure 4B and Figure 5D As shown, the insulating film m2 is provided between the peripheral surface of the first conductor 90 and the second semiconductor layer 50 to insulate between the first conductor 90 and the second semiconductor layer 50. Figure 4B As shown, the other end of the first conductor 90 is not connected to any wiring.

[0046] like Figure 4B As shown, unlike the shield wiring 91, the first conductor 90 is continuous and has no joints at the first joint surface B1, and is integrally provided across the first joint surface B1 in the extending direction. Figure 5B As shown, although the shield wiring 91 includes the first connection pad 33 and the second connection pad 43 at the first joint surface B1, and the first part 91a is connected to the second part 91b through the first connection pad 33 and the second connection pad 43, the first conductor 90 does not have any connection pad at the first joint surface B1, and is not configured to allow a plurality of components to be connected through the connection pad. Fig. 6E As shown, the first conductor 90 includes a barrier metal layer BM on its outer peripheral surface. In addition, the barrier metal layer BM is continuous across the first bonding surface B1.

[0047] <Light-incident-side stack> The planarization film PF includes a known insulating material or a known resin material, and may include, but is not limited to, for example, silicon oxide. The color filter CF is provided for each pixel 3, and separates light incident on the photoelectric conversion region 20a by color. The color filter CF includes, for example, a resin material. The microlens ML is provided for each pixel 3, and includes, for example, a resin material.

[0048] <Material for Forming Insulating Film> Figure 4A The insulating films 31, 41, 61 and 71 shown contain known insulating materials and include, but are not limited to, for example, a silicon oxide layer (SiO2). In addition, as an insulating film for insulating between the second semiconductor layer 50 and the first conductor 90, although not limited thereto, for example, a silicon oxide film, a silicon nitride (Si3N4) film, or a silicon oxynitride (SiON) film or the like can be used.

[0049] <Material for forming vertical wiring> Vertical interconnects such as the vertical interconnects 34, 44, and 74 (including vertical interconnects not shown) and vertical wirings such as the first conductor 90 include known conductive materials. As materials forming the vertical interconnects and the first conductor 90, for example, tungsten (W), copper (Cu), aluminum (Al), silicon (Si), and the like can be given. In the present embodiment, an example of forming the vertical interconnects and the first conductor 90 using tungsten is described.

[0050] <Materials for forming horizontal wiring and connection pads> As materials forming horizontal wirings such as wirings 32, 42, 62, and 72 and connection pads from the first connection pad 33 to the fourth connection pad 73, for example, copper (Cu) and aluminum (Al) can be given. In this embodiment, an example of forming horizontal wirings and connection pads using copper is described.

[0051] <Material for forming barrier metal layer> The first conductor 90, the vertical wiring, the horizontal wiring, and various other wirings may include, for example, a barrier metal layer BM on their outer peripheral surfaces. As a material forming the barrier metal layer, for example, a high melting point metal such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN) may be given.

[0052] 《Method for manufacturing light detector》 Now, refer to 6A to 6F , a method for manufacturing the optical detector 1 is described. Note that in this embodiment, an example of a manufacturing method in which wafers are bonded together is described, but the present technology is not limited thereto. First, as Fig. 6A As shown, a wafer W1 and a wafer W2 are prepared. Each of the wafers W1 and W2 has a plurality of chip regions arranged in a matrix form in a plan view, and the spaces between the chip regions are separated by scribe lines. In addition, an integrated circuit of the photodetector 1 is formed for each chip region. 6A to 6F , only a portion of the pixel region 2A of one chip region is shown.

[0053] The wafer W1 includes a first semiconductor layer 20W in which a transistor T1, a photoelectric conversion element PD, a charge accumulation region FD, etc. are formed, and a first wiring layer 30 stacked on a surface (first surface S1) opposite to the light incident surface of the first semiconductor layer 20W. The wafer W2 includes a second semiconductor layer 50W in which a transistor T2 (including a transistor T2A) is formed, and a second wiring layer 40 stacked on a third surface S3 of the second semiconductor layer 50W. Then, by overlapping and bonding the wiring layers, the prepared wafers W1 and W2 are bonded together. More specifically, the surface of the first wiring layer 30 opposite to the surface located on the first semiconductor layer 20W side is bonded to the surface of the second wiring layer 40 opposite to the surface located on the second semiconductor layer 50W side, thereby bonding the wafer W1 and the wafer W2 together. In other words, the wafer W1 is bonded to the wafer W2 so that the first surface S1 is opposite to the third surface S3. Furthermore, by this bonding, the first connection pad 33 of the first wiring layer 30 is bonded to the second connection pad 43 of the second wiring layer 40 , and the first portion 91 a and the second portion 91 b of the shield wiring 91 are thereby bonded.

[0054] Next, if Figure 6B As shown, the second semiconductor layer 50W is thinned by grinding the surface opposite to the third surface S3 of the second semiconductor layer 50W, thereby leaving a portion that becomes the second semiconductor layer 50. Thereafter, a hole 90h is formed from the other surface (fourth surface S4) side of the second semiconductor layer 50, the hole penetrating the second semiconductor layer 50 in the thickness direction and penetrating the first bonding surface B1 (i.e., the bonding surface between the first wiring layer 30 and the second wiring layer 40). Now, a method of forming the hole 90h is described.

[0055] First, if Figure 6C As shown, an insulating film m1 is stacked on the fourth surface S4 by a known film forming technique. Then, for example, by known photolithography and etching techniques, a through hole 50h is formed that penetrates the insulating film m1 and the second semiconductor layer 50. Note that when etching the second semiconductor layer 50, the insulating film m1 provided with an opening can be used as a hard mask. Note that in the plan view, the through hole 50h is set at the position where the first conductor 90 is to be set. Then, an insulating film m2 is stacked by a known film forming technique to cover the exposed surface of the insulating film m1 and the inner peripheral surface and bottom surface of the through hole 50h. The insulating film m2 serves as an insulating film configured to insulate between the first conductor 90 and the second semiconductor layer 50. The insulating film m1 can be, for example, an insulating film made of silicon oxide, silicon nitride (Si3N4), silicon oxynitride (SiON), etc. Similarly, the insulating film m2 can be, for example, an insulating film made of silicon oxide, silicon nitride (Si3N4), silicon nitride oxide (SiON), etc. Thereafter, as Fig.6D As shown, a hole 90h is formed from the bottom of the through hole 50h toward the first semiconductor layer 20W in the thickness direction by a known etching technique. The hole 90h is set to a depth reaching the first semiconductor layer 20W, more specifically, to a depth reaching the charge accumulation region FD. Thus, a hole 90h having a depth reaching the charge accumulation region FD from the exposed surface of the insulating film m1 is formed.

[0056] Next, a conductive material is embedded in the formed hole 90h, thereby forming the first conductor 90. For example, first, Fig. 6E As shown, a barrier metal layer BM is stacked by a known film forming technique to cover the exposed surface in the hole 90h, and thereafter, the hole 90h is filled with tungsten. Then, unnecessary portions of the metal barrier layer BM and tungsten are removed by grinding, thereby flattening the exposed surface. Thus, the first conductor 90 can be formed without adding or joining a plurality of components. Then, as shown in FIG. Fig. 6F As shown, the formation of the third wiring layer 60 is almost completed on the fourth surface S4 side of the second semiconductor layer 50 .

[0057] Thereafter, although not shown, a third wafer prepared separately is bonded to the exposed surface of the third wiring layer 60. The third wafer has a plurality of chip regions arranged in a matrix form in a plan view, and the spaces between the chip regions are separated by scribe regions. In addition, an integrated circuit of the photodetector 1 is formed for each chip region. The third wafer includes a third semiconductor layer 80 and a fourth wiring layer 70 stacked on a fifth surface S5 of the third semiconductor layer 80, and the exposed surface of the third wiring layer 60 is bonded to the exposed surface of the fourth wiring layer 70. Then, the first semiconductor layer 20W is thinned by grinding the surface of the first semiconductor layer 20W opposite to the first surface S1, thereby retaining a portion that becomes the first semiconductor layer 20. Thereafter, a planarization film PF, a color filter CF, a microlens ML, etc. are formed, and the photodetector 1 is almost completed. Then, the photodetector 1 set for each chip region is singulated to obtain a semiconductor chip 2.

[0058] 《Main Effects of the First Embodiment》 Now, the main effects of the first embodiment will be described, but before that, Figure 7 1, a photodetector including a first conductor 90A instead of the first conductor 90 is described. The first conductor 90A has a configuration similar to the shield wiring 91. More specifically, the first conductor 90A has a first portion 90a provided in the first wiring layer 30 and a second portion 90b provided in the second wiring layer 40. The first portion 90a includes a multilayer wiring provided in the first wiring layer 30 and connected in the thickness direction. The second portion 90b includes a multilayer wiring provided in the second wiring layer 40 and connected in the thickness direction. In addition, the first connection pad 33 of the first portion 90a is bonded to the second connection pad 43 of the second portion 90b, so that the first portion 90a is bonded to the second portion 90b.

[0059] In this way, in the case where the first portion 90a and the second portion 90b of the first conductor 90A are joined by a pair of connection pads, the joining between the connection pads must be sufficient to prevent the conductivity between the first portion 90a and the second portion 90b from being deteriorated. In addition, in order to prevent an increase in parasitic capacitance, it is desirable to ensure a sufficient distance between the connection pads of the first conductor 90A and other wirings in the thickness direction and the horizontal direction.

[0060] At the same time, it is expected that the pixel 3 will be miniaturized. When the pixel 3 and the photoelectric conversion region 20a are miniaturized, it is expected to reduce the size of various components in the plan view. For example, it is expected to reduce the thickness of the wiring, the diameter of the vertical interconnection portion, and the horizontal size of the connection pad. However, when the size of the connection pad in the plan view is reduced, the thermal expansion amount of the metal forming the connection pad will be reduced, which may make it difficult to prevent the connection conductivity between the connection pads from deteriorating. In view of this, in some cases, the size of the connection pad in the thickness direction will increase to prevent the thermal expansion amount of the connection pad from being reduced. However, when the size of the connection pad in the thickness direction increases, the distance between adjacent wirings in the thickness direction will decrease, resulting in a potential increase in parasitic capacitance. In addition, when the parasitic capacitance increases, it may affect pixel performance, more specifically, conversion efficiency.

[0061] In contrast, the photodetector 1 according to the first embodiment of the present technology includes a first semiconductor substrate A1, a second semiconductor substrate A2, a third semiconductor substrate A3 and a first conductor 90 extending in the thickness direction, wherein the first semiconductor substrate A1 includes a first semiconductor layer 20 provided with a photoelectric conversion element, and a first wiring layer 30 stacked on the surface of the first semiconductor layer 20 opposite to the light incident surface S2, the second semiconductor substrate A2 includes a second semiconductor layer 50, a second wiring layer 40 stacked on one surface of the second semiconductor layer 50, and a third wiring layer 60 stacked on the other surface of the second semiconductor layer 50, the third semiconductor substrate A3 includes a third semiconductor layer 80, and a fourth wiring layer 70 stacked on the third semiconductor layer 80, the first wiring layer 30 is bonded to the second wiring layer 40, and the bonding surface between the first wiring layer 30 and the second wiring layer 40 is the first bonding surface B1, the third wiring layer 60 is bonded to the fourth wiring layer 70, and the bonding surface between the third wiring layer 60 and the fourth wiring layer 70 is the second bonding surface, and the first conductor 90 passes through the first bonding surface B1 and is integrally arranged without a joint.

[0062] In this way, since the first conductor 90 passes through the first joint surface B1 and is integrally provided without a joint, the first conductor 90 does not need to include a connection pad at the first joint surface B1. In addition, since the first conductor 90 is continuous when crossing the first joint surface B1, the conductivity between the wiring on the first semiconductor substrate A1 side and the wiring on the second semiconductor substrate A2 side can be prevented from being deteriorated. Therefore, the reliability can be prevented from being reduced. In addition, since the first conductor 90 is configured not to include a connection pad at the first joint surface B1, the distance between the first conductor 90 and other wirings can be prevented from becoming too small in the thickness direction and the horizontal direction. Therefore, the increase of parasitic capacitance can be prevented, and the deterioration of pixel performance, more specifically, the deterioration of conversion efficiency can be prevented.

[0063] In addition, in the photodetector 1 according to the first embodiment of the present technology, the first conductor 90 includes a barrier metal layer BM on its outer peripheral surface, and the barrier metal layer BM is continuous when crossing the first joint surface B1. In this way, the first conductor 90 is not misaligned in the horizontal direction when crossing the first joint surface B1, and therefore, the conductivity of the first conductor 90 at the first joint surface B1 can be prevented from being deteriorated.

[0064] In addition, according to the first embodiment of the present technology, the photodetector 1 also includes a shielding wiring 91, which is arranged between one of the first conductors 90 and the other of the first conductors 90 in a plan view, extends in the thickness direction of the photodetector 1, and has a potential fixed to the reference potential, wherein the shielding wiring 91 has a first portion 91a extending in the first wiring layer 30 and a second portion 91b extending in the second wiring layer 40, the first portion 91a and the second portion 91b are connected by a pair of connecting pads (a first connecting pad 33 and a second connecting pad 43) at the first joint surface B1, and the first conductor 90 directly or indirectly connects the charge accumulation region FD set in the first semiconductor layer 20 to the gate electrode G2A of the transistor T2A which is an amplifying transistor set in the second semiconductor layer 50.

[0065] In this way, among the first conductor 90 and the shield wiring 91, the first conductor 90 through which the signal charge flows is integrally arranged across the first joint surface B1 in the extension direction and has no joint at the first joint surface B1. Therefore, since the first conductor 90 does not have a connection pad that is susceptible to pixel miniaturization, the conductivity between the charge accumulation region FD and the gate electrode G2A of the transistor T2A as the amplifying transistor can be prevented from being deteriorated. Therefore, the reliability can be prevented from being reduced. In addition, since the first conductor 90 originally does not have a connection pad, the increase of parasitic capacitance can be prevented, and the influence of parasitic capacitance on pixel performance (more specifically, conversion efficiency) can be prevented from increasing.

[0066] Furthermore, since the first conductor 90 is configured without a connection pad, the area occupied by the first conductor 90 at the first joint surface B1 in a plan view can be reduced. Furthermore, as the area occupied by the first conductor 90 in a plan view is reduced, on the contrary, Figure 5B As shown in the figure, the area occupied by the first connection pad 33 and the second connection pad 43 of the shield wiring 91 can be increased. Therefore, it is possible to prevent the bonding between the first connection pad 33 and the second connection pad 43 of the shield wiring 91 from being deteriorated, and to prevent the conductivity between the first part 90a and the second part 90b from being deteriorated. In addition, even in the case of miniaturization of the pixel 3, the conductivity of the first conductor 90 as a signal line and the shield wiring 91 for preventing noise can be provided at the same time.

[0067] In addition, the manufacturing method of the photodetector 1 according to the first embodiment of the present technology includes: preparing a first semiconductor substrate A1 including a first semiconductor layer 20 provided with a photoelectric conversion element PD, and a first wiring layer 30 stacked on a surface opposite to the light incident surface of the first semiconductor layer 20, and a second semiconductor substrate A2 including a second semiconductor layer 50, and a second wiring layer 40 stacked on one surface of the second semiconductor layer 50; overlapping and joining the first wiring layer 30 and the second wiring layer 40; forming a hole 90h that penetrates the second semiconductor layer 50 in the thickness direction and penetrates the first joint surface B1 (i.e., the joint surface between the first wiring layer 30 and the second wiring layer 40) from the other surface side of the second semiconductor layer 50; and forming a first conductor 90 by burying a conductive material in the hole 90h. In this way, since the first conductor 90 is formed after the first wiring layer 30 and the second wiring layer 40 are joined together, the first conductor 90 that is integrally provided in the extension direction across the first joint surface B1 can be formed without providing a pair of connection pads on the first conductor 90. Therefore, the conductivity of the first conductor 90 at the first joint surface B1 can be prevented from being deteriorated. In addition, since the first conductor 90 is configured not to include a connection pad at the first joint surface B1, the distance between the first conductor 90 and other wirings can be prevented from becoming too small in the thickness direction and the horizontal direction. Therefore, an increase in parasitic capacitance can be prevented.

[0068] <<Modification of the First Embodiment>> Modifications of the first embodiment will now be described.

[0069] <Modification 1> In the photodetector 1 according to the first embodiment, as Figure 5C As shown in FIG. 1 , the bonding surface between the first conductor 90 and the wiring 42A surrounds the entire circumference of the first conductor 90, but the present technology is not limited thereto. In the photodetector 1 according to the modification 1 of the first embodiment, as shown in FIG. Figure 8 As shown, the bonding surface between the first conductor 90 and the wiring 42A may extend only in a part of the circumferential direction of the first conductor 90. It is sufficient that the first conductor 90 is in contact with at least a part of the wiring 42A.

[0070] Even if the photodetector 1 according to Modification 1 of the first embodiment is employed, effects similar to those of the photodetector 1 according to the above-described first embodiment can be obtained.

[0071] <Modification 2> In the photodetector 1 according to the first embodiment, as Figure 4A and Figure 5CAs shown, the first conductor 90 is electrically connected to the gate electrode G2A through the wiring 42A and the vertical interconnect 44A at the connection portion, but the present technology is not limited thereto. Fig. 9A and Fig. 9B As shown in FIG. 1 , the connection portion of the first conductor 90 is connected to the wiring 42A, and the wiring 42A is directly connected to the gate electrode G2A without passing through the vertical interconnect 44. That is, the connection portion of the first conductor 90 is indirectly connected to the gate electrode G2A through the wiring 42A. In this modification, as a material forming the wiring 42A, tungsten (W), aluminum (Al), titanium (Ti), and the like can be given.

[0072] Even if the photodetector 1 according to the modification 2 of the first embodiment is employed, effects similar to those of the photodetector 1 according to the above-described first embodiment can be obtained.

[0073] <Variation 3> In the photodetector 1 according to the modification 2 of the first embodiment, as Fig. 9B As shown in FIG. 1 , the bonding surface between the first conductor 90 and the wiring 42A surrounds the entire circumference of the first conductor 90, but the present technology is not limited thereto. In the photodetector 1 according to the modification example 3 of the first embodiment, as shown in FIG. Fig.10 As shown, the bonding surface between the first conductor 90 and the wiring 42A may extend only in a part of the circumferential direction of the first conductor 90. It is sufficient that the first conductor 90 is in contact with at least a part of the wiring 42A.

[0074] Even if the photodetector 1 according to the modification 3 of the first embodiment is employed, effects similar to those of the photodetector 1 according to the modification 2 of the above-described first embodiment can be obtained.

[0075] <Variation 4> In the photodetector 1 according to the first embodiment, as Figure 4A and Figure 5C As shown, the first conductor 90 is electrically connected to the gate electrode G2A through the wiring 42A and the vertical interconnect 44A at the connection portion, but the present technology is not limited thereto. Fig.11A and Fig. 11B As shown, the connection portion of the first conductor 90 is directly connected to the gate electrode G2A. Fig. 11B As shown, the gate electrode G2A is arranged to extend toward the first conductor 90 in the X direction. In addition, the first conductor 90 penetrates the extended portion of the gate electrode G2A, and the connecting portion is connected to the gate electrode G2A. The extended portion of the gate electrode G2A is arranged not to overlap with the active area of ​​the transistor T2A. In addition, the connecting portion of the first conductor 90 is connected to the inner peripheral surface of the through hole G2Ah provided in the gate electrode G2A. In addition, as shown in FIG. Fig.11AAs shown, the first conductor 90 penetrates the gate electrode G2A and further penetrates a region where no active region is provided in the second semiconductor layer 50. With the configuration of this modification, the first conductor 90 directly connects the charge storage region FD to the gate electrode G2A.

[0076] Even if the photodetector 1 according to the modification 4 of the first embodiment is employed, effects similar to those of the photodetector 1 according to the above-described first embodiment can be obtained.

[0077] <Variation 5> In the photodetector 1 according to the modification 4 of the first embodiment, as Fig. 11B As shown in FIG. 1 , the bonding surface between the first conductor 90 and the gate electrode G2A surrounds the entire circumference of the first conductor 90, but the present technology is not limited thereto. In the photodetector 1 according to the modification 5 of the first embodiment, as shown in FIG. Fig.12 As shown, the junction surface between the first conductor 90 and the gate electrode G2A may extend only in a partial circumferential direction of the first conductor 90. It is sufficient as long as the first conductor 90 is in contact with at least a portion of the gate electrode G2A.

[0078] Even if the photodetector 1 according to the modification 5 of the first embodiment is employed, effects similar to those of the photodetector 1 according to the modification 4 of the above-described first embodiment can be obtained.

[0079] <Variation 6> In the above-mentioned first embodiment, the shield wiring 91 is connected to the region with the reference potential in the second semiconductor layer 50 and the region with the reference potential in the first semiconductor layer 20, but the present technology is not limited thereto. In the photodetector 1 according to the modification 6 of the first embodiment of the present technology, although not shown, the shield wiring 91 may be fixed only to the second semiconductor layer 50 among the second semiconductor layer 50 and the first semiconductor layer 20 in terms of potential. When the bonding between the first connection pad 33 and the second connection pad 43 of the shield wiring 91 is sufficient, sufficient conductivity can be obtained between the first part 90a and the second part 90b. Therefore, even if the shield wiring 91 is fixed only to the second semiconductor layer 50 in terms of potential, the potential of the entire shield wiring 91 can be set to the reference potential.

[0080] Even if the photodetector 1 according to the modification 6 of the first embodiment is employed, effects similar to those of the photodetector 1 according to the above-described first embodiment can be obtained.

[0081] <Variation 7> In the above-mentioned first embodiment, the first conductor 90 connects the charge accumulation region FD to the gate electrode of the transistor T2A (amplification transistor AMP), but the present technology is not limited to this. In the modification 7 of the first embodiment, the first conductor 90 can connect other elements to each other. For example, even in the case where the readout circuit 15 is formed on the first semiconductor substrate A1 and the logic circuit 13 is formed on the second semiconductor substrate A2, the first conductor 90 can be used to connect the elements provided in the first semiconductor layer 20 to the elements provided in the second semiconductor layer 50. In this way, the elements connected by the first conductor 90 are not limited.

[0082] Even if the photodetector 1 according to the modification 7 of the first embodiment is employed, effects similar to those of the photodetector 1 according to the above-described first embodiment can be obtained.

[0083] [Second embodiment] The following explains Fig.13 The second embodiment of the present technology is shown. The photodetector 1 according to this second embodiment is different from the photodetector 1 according to the above-described first embodiment in that one end of the first conductor 90 is indirectly connected to the charge accumulation region FD, and the remaining configuration of the photodetector 1 is substantially similar to that of the photodetector 1 of the above-described first embodiment. Note that components that have already been described are denoted by the same reference numerals, and descriptions thereof are omitted. Note that in Fig.13 And in the subsequent figures, omitted Figure 4A Illustration of some of the components shown (e.g., gate insulating film).

[0084] like Fig.13 As shown, one end of the first conductor 90 is connected to the wiring 32 provided in the first wiring layer 30. In addition, the wiring 32 and the charge accumulation region FD are connected through the vertical interconnection 34. That is, one end of the first conductor 90 and the charge accumulation region FD are indirectly connected through the wiring 32 and the vertical interconnection 34.

[0085] Even with the photodetector 1 according to the second embodiment, it is possible to obtain effects similar to those of the photodetector 1 according to the above-described first embodiment.

[0086] <<Variation of the Second Embodiment>> Modifications of the second embodiment will now be described.

[0087] <Modification 1> In the photodetector 1 according to the second embodiment, one end of the first conductor 90 and the charge accumulation region FD are indirectly connected through the wiring 32 and the vertical interconnection 34, but the present technology is not limited thereto. Fig.14As shown, one end of the first conductor 90 and the charge accumulation region FD can be indirectly connected through the electrode E. In this modification, the separation region 20b has a groove structure. More specifically, the separation region 20b has a groove structure obtained by forming a groove in the first semiconductor layer 20 along the thickness direction and burying polysilicon in the formed groove through an insulating film not shown. In addition, the separation region 20b has a shallow trench structure STI obtained by burying an insulating film in the groove at its end on the first surface S1 side. The charge accumulation region FD is set for each pixel 3, and adjacent charge accumulation regions FD are separated by the separation region 20b. The electrode E is set on the first surface S1 and is connected to all four charge accumulation regions FD adjacent to each other.

[0088] Even if the photodetector 1 according to Modification 1 of the second embodiment is employed, effects similar to those of the photodetector 1 according to the above-described second embodiment can be obtained.

[0089] <Modification 2> In the photodetector 1 according to the modification 2 of the second embodiment, the configuration of the electrode E is different from that of the electrode E of the modification 1. In this modification, Fig.15 As shown, the electrode E is configured to be partially buried in the first semiconductor layer 20 .

[0090] Even if the photodetector 1 according to the modification 2 of the second embodiment is employed, effects similar to those of the photodetector 1 according to the above-described second embodiment can be obtained.

[0091] [Third embodiment] The following explains Fig.16 The third embodiment of the present technology is shown. The photodetector 1 according to the third embodiment is different from the photodetector 1 according to the above-described first embodiment in that the other end portion of the first conductor 90 is provided in the second wiring layer 40, and the remaining configuration of the photodetector 1 is substantially similar to that of the photodetector 1 of the above-described first embodiment. Note that components that have already been described are denoted by the same reference numerals, and description thereof is omitted.

[0092] like Fig.16 As shown, one end of the first conductor 90 is located in the first wiring layer 30, and the other end is located in the second wiring layer 40. In addition, in a plan view, a through hole 50h filled with an insulating film is provided at a position of the second semiconductor layer 50 overlapping with the first conductor 90. Such a first conductor 90 is formed by removing a portion of the first conductor 90 during the manufacturing process. For example, Fig. 6E Starting from the state shown in FIG. 1 , a portion of the first conductor 90 is etched from the other end side by a known etching technique. More specifically, as shown in FIG. Fig.17As shown, the portion of the first conductor 90 located in the through hole 50h of the second semiconductor layer 50 is removed from the other end side. More preferably, the first conductor 90 is etched until the other end of the first conductor 90 is located in the second wiring layer 40. Thereafter, the hole formed by etching is filled with an insulating film, and the manufacturing method described in the first embodiment is continued.

[0093] Even if the photodetector 1 according to the third embodiment is employed, effects similar to those of the photodetector 1 according to the above-described first embodiment can be obtained.

[0094] Furthermore, in the photodetector 1 according to the third embodiment, since the first conductor 90 is not located in the through hole 50h of the second semiconductor layer 50, it is possible to prevent parasitic capacitance from occurring between the first conductor 90 and the second semiconductor layer 50. Therefore, an increase in parasitic capacitance occurring in the first conductor 90 can be further prevented.

[0095] Note that the configuration of the photodetector 1 according to the third embodiment may be combined with the configurations described in the respective modifications of the above-described first embodiment and the configurations described in the above-described second embodiment and its modifications.

[0096] [Fourth embodiment] <1. Application examples on electronic devices> Next, explain Fig.18 The electronic device 100 shown in FIG. 1 includes a solid-state image capturing device 101, an optical lens 102, a shutter device 103, a drive circuit 104, and a signal processing circuit 105. The electronic device 100 is, but not limited to, an electronic device such as a camera. In addition, the electronic device 100 includes the above-mentioned photodetector 1 as the solid-state image capturing device 101.

[0097] The optical lens (optical system) 102 forms an image of the image light (incident light 106) from the object on the image capturing surface of the solid-state image capturing device 101. Therefore, the signal charge is accumulated in the solid-state image capturing device 101 for a certain period of time. The shutter device 103 controls the illumination period and the light shielding period of the solid-state image capturing device 101. The drive circuit 104 provides a drive signal for controlling the transmission operation of the solid-state image capturing device 101 and the shutter operation of the shutter device 103. The signal is transmitted from the solid-state image capturing device 101 by the drive signal (timing signal) provided from the drive circuit 104. The signal processing circuit 105 performs various types of signal processing on the signal (pixel signal) output from the solid-state image capturing device 101. The video signal after the signal processing is stored in a storage medium such as a memory or output to a monitor.

[0098] With this configuration, the conductivity of the wiring across the first joint surface B1 can be prevented from being deteriorated, thereby preventing the reliability from being reduced. In addition, with this configuration, the increase of the parasitic capacitance in the solid-state image capture device 101 can be prevented, thereby improving the image quality of the video signal.

[0099] Note that the electronic device 100 is not limited to a camera, and may be other electronic devices. For example, the electronic device 100 may be an image capturing device such as a camera module of a mobile device such as a mobile phone.

[0100] In addition, the solid-state image capturing device 101 of the electronic device 100 may include a light detector 1 according to any one of the first to third embodiments and their variants, or a light detector 1 according to a combination of at least two of the first to third embodiments and their variants.

[0101] <2. Application examples on mobile objects> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body, such as a car, an electric car, a hybrid electric car, a motorcycle, a bicycle, a personal mobility device, an airplane, a drone, a ship, or a robot.

[0102] Fig.19 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0103] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.19 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside information detection unit 12030, an inside information detection unit 12040, and an integrated control unit 12050. In addition, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown as a functional configuration of the integrated control unit 12050.

[0104] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force, etc.

[0105] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for the following devices: a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal, or a fog light. In this case, a radio wave or a signal of various switches transmitted from a portable device as a key substitute may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, or the lights of the vehicle.

[0106] The vehicle exterior information detection unit 12030 detects external information about the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to image the exterior of the vehicle and receive the captured image. Based on the received image, the vehicle exterior information detection unit 12030 may perform processing for detecting objects such as people, vehicles, obstacles, signs, or characters on the road surface, or processing for detecting their distances.

[0107] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0108] The in-vehicle information detection unit 12040 detects interior information about the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting a driver state. The driver state detection unit 12041 includes, for example, a camera for imaging the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0109] The microcomputer 12051 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the information about the inside and outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the driving system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions intended to implement an advanced driver assistance system (ADAS), such as collision avoidance or shock absorption of the vehicle, following driving based on vehicle spacing, speed maintenance driving, vehicle collision warning, or vehicle lane departure warning.

[0110] In addition, based on the environmental information about the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 can perform coordinated control for automatic driving by controlling the driving force generating device, steering mechanism or braking device, etc., which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0111] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12030 based on the external information about the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control intended for preventing glare by, for example, controlling the headlights to change from high beam to low beam according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0112] The sound / image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the vehicle occupants or the outside of the vehicle of information. Fig.19 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. The display portion 12062 may include, for example, at least one of an in-vehicle display and a head-up display.

[0113] Fig. 20 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0114] exist Fig. 20 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0115] The imaging units 12101, 12102, 12103, 12104 and 12105 are, for example, disposed at locations such as the front nose, rearview mirror, rear bumper, rear door and upper portion of the windshield inside the vehicle 12100. The imaging unit 12101 disposed at the front nose and the imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 disposed at the rearview mirror mainly acquire images on both sides of the vehicle 12100. The imaging unit 12104 disposed at the rear bumper or rear door mainly acquires images behind the vehicle 12100. The imaging unit 12105 disposed at the upper portion of the windshield inside the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signal lights, traffic signs or lanes, etc.

[0116] Notice, Fig. 20 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. The imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirror. The imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 is obtained by superimposing the image data imaged by the imaging units 12101 to 12104.

[0117] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0118] For example, the microcomputer 12051 can determine the distance of each three-dimensional object within the imaging ranges 12111 to 12114 and the time change of the distance (relative speed with respect to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, and extract the nearest three-dimensional object as the preceding vehicle, which is particularly present on the travel path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / h) in substantially the same direction as the vehicle 12100. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Therefore, it is possible to perform coordinated control for automatic driving so that the vehicle can travel automatically without relying on the operation of the driver, etc.

[0119] For example, the microcomputer 12051 can classify the three-dimensional object data of the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually identified by the driver of the vehicle 12100 and obstacles that are difficult to be visually identified by the driver of the vehicle 12100. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver through the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering through the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0120] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the captured images of the imaging units 12101 to 12104. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the captured images of the imaging units 12101 to 12104 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 12051 determines that there is a pedestrian in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 12052 may control the display unit 12062 so as to display an icon or the like indicating a pedestrian at a desired position.

[0121] The above describes an example of a vehicle control system to which the technology according to the present disclosure can be applied. For example, the technology according to the present disclosure can be applied to the imaging unit 12031 in the above-mentioned structure. Specifically, the above-mentioned light detector 1 can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the imaging unit 12031, the conductivity of the wiring across the first joint surface B1 can be prevented from being deteriorated, thereby preventing the reliability from being reduced. In addition, since the increase of parasitic capacitance can be prevented, a clearer captured image can be obtained, thereby reducing driver fatigue.

[0122] <3. Application examples in endoscopic surgery systems> The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be applied to an endoscopic surgery system.

[0123] Fig.21 is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology according to the present disclosure (the present technology) can be applied.

[0124] exist Fig.21 , a state is shown in which a surgical operator (doctor) 11131 is using an endoscopic surgical system 11000 to perform surgery on a patient 11132 on a bed 11133. As shown in the figure, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical tools 11110 such as a pneumoperitoneum tube 11111 and an energy device 11112, a support arm device 11120 for supporting the endoscope 11100 thereon, and a cart 11200 on which various endoscopic surgical devices are mounted.

[0125] The endoscope 11100 includes a lens barrel 11101 and a camera head 11102 connected to the proximal end of the lens barrel 11101, and a region of the lens barrel 11101 having a predetermined length starting from the distal end thereof is inserted into a body cavity of a patient 11132. In the illustrated example, the endoscope 11100 is shown as including a rigid endoscope including the rigid lens barrel 11101. However, the endoscope 11100 may also be a flexible endoscope including the flexible lens barrel 11101.

[0126] The lens barrel 11101 has an opening at its distal end, and the objective lens is fitted into the opening. The light source device 11203 is connected to the endoscope 11100, so that the light generated by the light source device 11203 is introduced into the distal end of the lens barrel 11101 through the light guide extending inside the lens barrel 11101, and irradiated toward the observation target in the body cavity of the patient 11132 through the objective lens. It should be noted that the endoscope 11100 can be a forward-looking endoscope, or can be an oblique-looking endoscope or a side-looking endoscope.

[0127] An optical system and an image capturing element are provided inside the camera 11102, so that the reflected light (observation light) from the observation target is focused on the image capturing element through the optical system. The observation light is photoelectrically converted by the image capturing element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The image signal is transmitted to the CCU 11201 as raw data.

[0128] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 11100 and the display device 11202. In addition, the CCU 11201 receives an image signal from the camera 11102, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0129] Under the control of the CCU 11201 , the display device 11202 displays an image thereon based on the image signal on which the CCU 11201 has performed image processing.

[0130] The light source device 11203 includes, for example, a light source such as a light emitting diode (LED), and provides illumination light to the endoscope 11100 when imaging a surgical area.

[0131] The input device 11204 is an input interface of the endoscopic surgery system 11000. The user can input various types of information or instructions in the endoscopic surgery system 11000 through the input device 11204. For example, the user can input instructions for changing the image capturing conditions (type of irradiation light, magnification factor, focal length, etc.) of the endoscope 11100.

[0132] The treatment tool control device 11205 controls the drive of the energy device 11112 for burning tissue, cutting tissue, sealing blood vessels, etc. The pneumoperitoneum device 11206 feeds gas into the body cavity of the patient 11132 through the pneumoperitoneum tube 11111 to expand the body cavity, thereby ensuring the field of view of the endoscope 11100 and ensuring the working space for the treatment operation. The recorder 11207 is a device capable of recording various information related to the operation. The printer 11208 is a device capable of recording various information related to the operation. - A device capable of printing various information related to surgery in various forms such as text, images and charts.

[0133] It should be noted that, for example, the light source device 11203 that provides irradiation light to the endoscope 11100 when imaging the surgical area may include a white light source, such as an LED, a laser light source, or a combination thereof. In the case where the white light source includes a combination of red, green, and blue (RGB) laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the white balance of the captured image can be adjusted by the light source device 11203. In addition, in this case, if the laser beam from the RGB laser light source is irradiated to the observation target in a time-division manner and the drive of the image capturing element of the camera 11102 is controlled in synchronization with the emission timing, images corresponding to RGB respectively can be captured in a time-division manner. According to this method, a color image can be acquired even if a color filter is not provided for the image capturing element.

[0134] In addition, the light source device 11203 can be controlled so that the intensity of the output light is changed at each predetermined time. By controlling the drive of the image capturing element of the camera 11102 in synchronization with the timing of the change in light intensity so as to acquire images in a time-division manner and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be generated.

[0135] In addition, the light source device 11203 can be configured to provide light having a predetermined wavelength region domain prepared for specific light observation. In specific light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue to irradiate light having a narrower band than the irradiation light (i.e., white light) during normal observation, imaging (narrow-band imaging) for predetermined tissues such as blood vessels in the surface part of the mucosal layer with high contrast is performed. Alternatively, in specific light observation, fluorescence observation for obtaining an image based on fluorescence generated by irradiation of excitation light can be performed. In fluorescence observation, observation of fluorescence from body tissue (autofluorescence observation) can be performed by irradiating body tissue, or a fluorescent image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to provide narrow-band light and / or excitation light suitable for specific light observation as described above.

[0136] Fig. 22 It is shown Fig.21 A block diagram of an example of the functional configuration of the camera 11102 and the CCU 11201 shown.

[0137] The camera 11102 includes a lens unit 11401, an image capturing unit 11402, a driving unit 11403, a communication unit 11404, and a camera control unit 11405. The CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. The camera 11102 and the CCU 11201 are connected via a transmission cable 11400 to communicate with each other.

[0138] The lens unit 11401 is an optical system provided at a position connected to the lens barrel 11101. Observation light acquired from the distal end of the lens barrel 11101 is guided to the camera head 11102 and introduced into the lens unit 11401. The lens unit 11401 includes a combination of a plurality of lenses including a zoom lens and a focus lens.

[0139] The number of image capturing elements included in the image capturing unit 11402 may be one (single-board type) or multiple (multi-board type). In the case where the image capturing unit 11402 is configured as a multi-board type, for example, image signals corresponding to R, G, and B, respectively, are generated by the image capturing elements, and a color image can be obtained by synthesizing these image signals. The image capturing unit 11402 may also be configured to have a pair of image capturing elements for acquiring a right-eye image signal and a left-eye image signal for three-dimensional (3D) display. If a 3D display is performed, the surgical operator 11131 is able to more accurately perceive the depth of body tissue at the surgical site. It should be noted that in the case where the image capturing unit 11402 is configured as a multi-board type, a plurality of systems of lens units 11401 may be arranged in a manner corresponding to the respective image capturing elements.

[0140] In addition, the image capturing unit 11402 may not necessarily be disposed in the camera head 11102. For example, the image capturing unit 11402 may be disposed immediately after the objective lens inside the lens barrel 11101.

[0141] The driving unit 11403 includes an actuator, and under the control of the camera control unit 11405, the driving unit 11403 moves the zoom lens and the focus lens of the lens unit 11401 by a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the image capturing unit 11402 can be appropriately adjusted.

[0142] The communication unit 11404 includes a communication device for transmitting / receiving various information to / from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the image capturing unit 11402 to the CCU 11201 through the transmission cable 11400 as raw data.

[0143] In addition, the communication unit 11404 receives a control signal for controlling the driving of the camera 11102 from the CCU 11201, and provides the control signal to the camera control unit 11405. For example, the control signal includes information related to imaging conditions, such as information for specifying a frame rate for capturing an image and information for specifying an exposure value when capturing an image and / or information for specifying a magnification and a focus of a captured image.

[0144] It should be noted that image capturing conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user or automatically set based on the acquired image signal by the control unit 11413 of the CCU 11201. In the latter case, an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function are combined in the endoscope 11100.

[0145] The camera control unit 11405 controls the driving of the camera 11102 based on a control signal received from the CCU 11201 through the communication unit 11404 .

[0146] The communication unit 11411 includes a communication device for transmitting / receiving various types of information to / from the camera 11102. The communication unit 11411 receives an image signal transmitted from the camera 11102 through the transmission cable 11400.

[0147] In addition, the communication unit 11411 transmits a control signal for controlling the driving of the camera 11102 to the camera 11102. The image signal and the control signal may be transmitted through electrical communication, optical communication, or the like.

[0148] The image processing unit 11412 performs various image processing on the image signal transmitted from the camera 11102 in the form of raw data.

[0149] The control unit 11413 performs various types of control related to image capture of the operation area, etc. performed by the endoscope 11100 and display of captured images obtained by the image capture of the operation area, etc. For example, the control unit 11413 generates a control signal for controlling the driving of the camera head 11102.

[0150] In addition, the control unit 11413 controls the display device 11202 to display a captured image depicting the surgical area, etc., based on the image signal that has been image-processed by the image processing unit 11412. At this time, the control unit 11413 can identify various objects in the captured image by using various image recognition technologies. For example, the control unit 11413 can identify surgical tools such as forceps, specific living parts, bleeding, fog when using the energy device 11112, etc. by detecting the shape, color, etc. of the edge of the object included in the captured image. When the control unit 11413 controls the display device 11202 to display the captured image, the control unit 11413 can display various surgical auxiliary information in a manner superimposed with the image of the surgical area by using the recognition result. By displaying and presenting the surgical auxiliary information to the surgical operator 11131 in a superimposed manner, the burden on the surgical operator 11131 can be reduced, or the surgeon 11131 can be enabled to perform surgery more reliably.

[0151] The transmission cable 11400 connecting the camera head 11102 and the CCU 11201 to each other is an electric signal cable for electric signal communication, an optical fiber for optical communication, or a composite cable for both electric communication and optical communication.

[0152] Here, in the example shown, although communication is performed by wired communication using the transmission cable 11400, communication between the camera 11102 and the CCU 11201 may be performed by wireless communication.

[0153] The above describes an example of an endoscopic surgical system to which the technology according to the present disclosure can be applied. For example, the technology according to the present disclosure can be applied to the image capturing unit 11402 of the camera 11102 in the above-mentioned structure. Specifically, the above-mentioned light detector 1 can be applied to the image capturing unit 11402. By applying the technology according to the present disclosure to the image capturing unit 11402, the conductivity of the wiring across the first joint surface B1 can be prevented from being deteriorated, thereby preventing the reliability from being reduced. In addition, since the parasitic capacitance can be prevented from increasing, a clearer image of the surgical site can be obtained, allowing the surgeon to reliably confirm the surgical site.

[0154] Note that an endoscopic surgery system is used as an example for description here. However, the technology disclosed herein can also be applied to other systems, such as a microscope surgery system.

[0155] [Other embodiments] As described above, the present technology has been described through the first to fourth embodiments, but it should be understood that the present technology is not limited to the statements and drawings included in the present disclosure. Various alternative embodiments, examples, and operation techniques can be clearly understood by those skilled in the art from the present disclosure.

[0156] For example, the technical concepts described in the first to fourth embodiments may be combined with each other. Various combinations are possible according to the technical concepts.

[0157] In addition, the present technology can be applied to a wide range of photodetectors, including not only solid-state image capturing devices used as image sensors as described above, but also ranging sensors for measuring distances, also known as ToF (time of flight) sensors, etc. The ranging sensor emits irradiation light to an object, detects reflected light of the irradiation light reflected by the surface of the object, and calculates the distance to the object based on the flight time from the emission of the irradiation light to the reception of the reflected light. As the structure of the ranging sensor, a structure including the above-mentioned first conductor 90 and shield wiring 91 can be adopted.

[0158] Furthermore, for example, the materials forming the above-mentioned components may contain additives or impurities.

[0159] In this manner, the present technology of course includes various embodiments and the like which are not described here. Therefore, the technical scope of the present technology is defined only by the matters for defining the present invention described in the claims supported by the above description.

[0160] Furthermore, the effects described herein are merely exemplary and not restrictive, and other effects are possible.

[0161] Note that the present technology may also have the following configurations. (1) A light detector comprising: a first semiconductor substrate; a second semiconductor substrate; a third semiconductor substrate; and A first conductor extending in a thickness direction, wherein The first semiconductor substrate includes: a first semiconductor layer provided with a photoelectric conversion element, and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, The second semiconductor substrate includes: a second semiconductor layer, a second wiring layer stacked on one surface of the second semiconductor layer, and a third wiring layer stacked on the other surface of the second semiconductor layer, The third semiconductor substrate includes: a third semiconductor layer, and a fourth wiring layer stacked on the third semiconductor layer. The first wiring layer is bonded to the second wiring layer, The bonding surface between the first wiring layer and the second wiring layer is a first bonding surface, The third wiring layer is bonded to the fourth wiring layer, A bonding surface between the third wiring layer and the fourth wiring layer is a second bonding surface, and The first conductor passes through the first joint surface and is integrally arranged without a joint. (2) The photodetector according to (1), wherein: The first conductor penetrates the second semiconductor layer. (3) The photodetector according to (1), wherein One end portion of the first conductor is located in the first wiring layer, and the other end portion is located in the second wiring layer. (4) The photodetector according to any one of (1) to (3), wherein The first conductor includes a barrier metal layer on its outer peripheral surface, and The barrier metal layer is continuous across the first bonding surface. (5) The photodetector according to any one of (1) to (4), further comprising: a shield wiring disposed between one of the first conductors and the other of the first conductors, extending in the thickness direction, and having a potential fixed to a reference potential, wherein The shield wiring has a first portion extending in the first wiring layer and a second portion extending in the second wiring layer. The first portion and the second portion are connected at the first joint surface via a pair of connection pads, and The first conductor directly or indirectly connects a charge accumulation region provided in the first semiconductor layer and a gate electrode of an amplifying transistor provided in the second semiconductor layer. (6) A method for manufacturing a light detector, comprising: preparing a first semiconductor substrate and a second semiconductor substrate, the first semiconductor substrate including a first semiconductor layer provided with a photoelectric conversion element and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, and the second semiconductor substrate including a second semiconductor layer and a second wiring layer stacked on one surface of the second semiconductor layer; Overlapping and bonding the first wiring layer and the second wiring layer; forming a hole from the other surface side of the second semiconductor layer, the hole penetrating the second semiconductor layer in the thickness direction and penetrating a first joint surface that is a joint surface between the first wiring layer and the second wiring layer; and A conductive material is buried in the hole to thereby form a first conductor. (7) An electronic device comprising: a light detector; and an optical system configured to form an image of image light from an object on the light detector, wherein The light detector comprises: a first semiconductor substrate; a second semiconductor substrate; a third semiconductor substrate; and A first conductor extending in a thickness direction, wherein The first semiconductor substrate includes: a first semiconductor layer provided with a photoelectric conversion element, and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, The second semiconductor substrate includes: a second semiconductor layer, a second wiring layer stacked on one surface of the second semiconductor layer, and a third wiring layer stacked on the other surface of the second semiconductor layer, The third semiconductor substrate includes: a third semiconductor layer, and a fourth wiring layer stacked on the third semiconductor layer. The first wiring layer is bonded to the second wiring layer, The bonding surface between the first wiring layer and the second wiring layer is a first bonding surface, The third wiring layer is bonded to the fourth wiring layer, A bonding surface between the third wiring layer and the fourth wiring layer is a second bonding surface, and The first conductor passes through the first joint surface and is integrally arranged without a joint.

[0162] The scope of the present technology is not limited to the exemplary embodiments depicted and described, but also includes all embodiments that produce the same effects as the effects that the present technology is intended to achieve. In addition, the scope of the present technology is not limited to the combination of inventive features defined in the claims, but can be defined by any combination of specific features in all the various disclosed features. Reference numerals list

[0163] 1: Light detector 20: First semiconductor layer 30: First wiring layer 32, 42, 42A, 62, 72: Wiring 40: Second wiring layer 50: Second semiconductor layer 60: The third wiring layer 70: Fourth wiring layer 80: The third semiconductor layer 90: First conductor 90h: Hole 91 shielded wiring 91a: Part I 91b: Part 2 100: Electronic devices 102: Optical system A1: First semiconductor substrate A2: Second semiconductor substrate A3: The third semiconductor substrate B1: First joint surface B2: Second joint surface BM: Barrier Metal Layer FD: Charge accumulation region G1, G2, G2A, G3: Gate electrodes PD: Photoelectric conversion device T1: Transistor T2: Transistor T2A: Transistor (amplifier transistor) T3: Transistor.

Claims

1. A light detector comprising: a first semiconductor substrate; a second semiconductor substrate; a third semiconductor substrate; as well as A first conductor extending in a thickness direction, wherein The first semiconductor substrate includes: a first semiconductor layer provided with a photoelectric conversion element, and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, The second semiconductor substrate includes: a second semiconductor layer, a second wiring layer stacked on one surface of the second semiconductor layer, and a third wiring layer stacked on the other surface of the second semiconductor layer, The third semiconductor substrate includes: a third semiconductor layer, and a fourth wiring layer stacked on the third semiconductor layer. The first wiring layer is bonded to the second wiring layer, The bonding surface between the first wiring layer and the second wiring layer is a first bonding surface, The third wiring layer is bonded to the fourth wiring layer, A bonding surface between the third wiring layer and the fourth wiring layer is a second bonding surface, and The first conductor passes through the first joint surface and is integrally arranged without a joint.

2. The optical detector according to claim 1, wherein The first conductor penetrates the second semiconductor layer.

3. The light detector according to claim 1, wherein One end portion of the first conductor is located in the first wiring layer, and the other end portion is located in the second wiring layer.

4. The light detector according to claim 1, wherein The first conductor includes a barrier metal layer on its outer peripheral surface, and The barrier metal layer is continuous across the first bonding surface.

5. The light detector according to claim 1, further comprising: a shield wiring disposed between one of the first conductors and the other of the first conductors, extending in the thickness direction, and having a potential fixed to a reference potential, wherein The shield wiring has a first portion extending in the first wiring layer and a second portion extending in the second wiring layer. The first portion and the second portion are connected at the first joint surface via a pair of connection pads, and The first conductor directly or indirectly connects a charge accumulation region provided in the first semiconductor layer and a gate electrode of an amplifying transistor provided in the second semiconductor layer.

6. A method for manufacturing a light detector, comprising: preparing a first semiconductor substrate and a second semiconductor substrate, the first semiconductor substrate including a first semiconductor layer provided with a photoelectric conversion element and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, and the second semiconductor substrate including a second semiconductor layer and a second wiring layer stacked on one surface of the second semiconductor layer; Overlapping and bonding the first wiring layer and the second wiring layer; forming a hole from the other surface side of the second semiconductor layer, the hole penetrating the second semiconductor layer in the thickness direction and penetrating a first bonding surface, the first bonding surface being a bonding surface between the first wiring layer and the second wiring layer; as well as A conductive material is buried in the hole to thereby form a first conductor.

7. An electronic device, comprising: Light detector; as well as an optical system configured to form an image of image light from an object on the light detector, wherein The light detector comprises: a first semiconductor substrate; a second semiconductor substrate; a third semiconductor substrate; and A first conductor extending in a thickness direction, wherein The first semiconductor substrate includes: a first semiconductor layer provided with a photoelectric conversion element, and a first wiring layer stacked on a surface of the first semiconductor layer opposite to a light incident surface, The second semiconductor substrate includes: a second semiconductor layer, a second wiring layer stacked on one surface of the second semiconductor layer, and a third wiring layer stacked on the other surface of the second semiconductor layer, The third semiconductor substrate includes: a third semiconductor layer, and a fourth wiring layer stacked on the third semiconductor layer. The first wiring layer is bonded to the second wiring layer, The bonding surface between the first wiring layer and the second wiring layer is a first bonding surface, The third wiring layer is bonded to the fourth wiring layer, A bonding surface between the third wiring layer and the fourth wiring layer is a second bonding surface, and The first conductor passes through the first joint surface and is integrally arranged without a joint.

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