Chip wiring planning method and device

Abstract

The invention provides a chip wiring planning method and device, and the method comprises the steps: obtaining the layout planning information of a chip, the layout planning information comprises the layout positions of a plurality of hardware modules in the chip, and a plurality of interconnection relationships for connecting the plurality of hardware modules or between the hardware modules and chip pins; determining at least two interconnection relationships from the plurality of interconnection relationships, wherein the feed-through information of the at least two interconnection relationships is the same; determining a first wiring planning path according to the feed-through information of the at least two interconnection relations; and according to the first wiring planning path, generating at least two planning wirings. According to the scheme of the embodiment of the invention, the method has the characteristics of manual planning and automatic algorithm, enables the wiring in the chip to be controllable, and greatly improves the working efficiency of chip design.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of chip design, and more particularly, to a method and apparatus for chip wiring planning. Background Art

[0002] In the chip design process, the floorplan of the chip is one of the most critical steps in the design process. The floorplan of the chip mainly includes module size and placement, memory / IP core placement, port placement, etc. In addition, it is necessary to plan the routing paths between pins and between ports (a set of pins).

[0003] However, due to the huge number of routing paths between ports and between pins and the influence of various constraints on the planned routing paths (such as the routing paths passing through blockages), the current manual planning is extremely inefficient and takes a large amount of design time. Moreover, due to the wide range of business scenarios of the chip, different placement methods of circuit modules in different business scenarios, and different routing constraints, it is necessary to manually intervene in the design process of the routing paths. Therefore, it is difficult to abstract general automatic routing rules suitable for each business scenario. Furthermore, the routing planning step becomes one of the most time-consuming process nodes in the entire chip design process. Summary of the Invention

[0004] The present application provides a method and apparatus for chip wiring planning. By forming a batch routing planning group for all interconnection relationships with the same feedthrough information, the corresponding planned feedthrough paths are determined based on the planning group. This method can not only avoid the inefficient work of traditional manual planning that can only plan one interconnection relationship at a time, but also avoid the routing uncertainty brought by automatic routing and the inappropriateness that automatic routing rules cannot be abstracted in some scenarios, as well as avoid the algorithm instability caused by the need to continuously adapt to new projects, new scenarios, new processes, etc. in automatic routing.

[0005] In a first aspect, a method for chip wiring planning is provided, including: obtaining layout planning information of a chip, where the layout planning information includes layout positions of multiple hardware modules in the chip and multiple interconnection relationships connecting between the multiple hardware modules or between a hardware module and a chip pin, and each interconnection relationship in the multiple interconnection relationships is used to indicate a connection relationship between pins at both ends of the interconnection relationship; determining at least two interconnection relationships from the multiple interconnection relationships, where feedthrough information of the at least two interconnection relationships is the same, and the feedthrough information is used to indicate at least one hardware module that the planned wiring between pins at both ends of the interconnection relationship needs to pass through; determining a first wiring planning path according to the at least two interconnection relationships, where the first wiring planning path is used to indicate a path when the planned wiring between pins at both ends of the at least two interconnection relationships passes through a hardware module; generating at least two planned wirings according to the first wiring planning path, where the at least two planned wirings correspond to the at least two interconnection relationships one by one, and each planned wiring in the at least two planned wirings is used to connect pins at both ends of the corresponding interconnection relationship.

[0006] Among them, the layout planning (floorplan) information of the chip may include layout positions of multiple hardware modules in the chip. For example, in a certain planar area, the size and shape of the chip are planned and defined, and the sizes and positions of various modules, hard cores (such as memories and other IP cores), IO interfaces, etc. within the chip are defined, and some special areas are defined, such as areas of blockages, areas of power / ground planes, etc. It may also include the above-mentioned interconnection relationships connecting between the multiple hardware modules or between a hardware module and a chip pin, such as fly lines used to indicate connection relationships of pins or ports between hardware modules or between a hardware module and a chip.

[0007] It should be understood that the above-mentioned feedthrough information refers to the hardware module that the planned wiring between pins at both ends of the interconnection relationship passes through. Or rather, when the planned wiring between pins at both ends of the interconnection relationship penetrates at least one hardware module, there is feedthrough information for the interconnection relationship, that is, at least one penetrated hardware module. And the first wiring planning path is the planned routing path or routing direction, and the planned wiring is the actual wiring planned inside the chip.

[0008] In the solution of the embodiment of the present application, multiple interconnection relationships with the same feedthrough information are grouped into the same planning group, and a first routing planning path is planned. Finally, based on the first routing planning path, the planned routing corresponding to the same planning group is generated in batches. This method can not only avoid the inefficient work of traditional manual planning that can only plan one signal group at a time, but also avoid the routing uncertainty brought by automatic routing and the inappropriateness that some scenarios cannot abstract automatic routing rules, as well as avoid the algorithm instability caused by the need for continuous adaptation to new projects, new scenarios, new processes, etc. in automatic routing.

[0009] In combination with the first aspect, in some implementation manners of the first aspect, determining at least two interconnection relationships with the same feedthrough information from the multiple interconnection relationships includes: providing the multiple interconnection relationships through a visual interface; obtaining the at least two interconnection relationships with the same feedthrough information selected by the user from the multiple interconnection relationships.

[0010] In combination with the first aspect, in some implementation manners of the first aspect, determining the first routing planning path according to the at least two interconnection relationships includes: obtaining one or more turning points selected by the user from the layout planning information presented on the visual interface, and the one or more turning points are located on some hardware modules in the layout planning information; generating the first routing planning path according to the one or more turning points, and the first routing planning path passes through the one or more turning points.

[0011] In combination with the first aspect, in some implementation manners of the first aspect, generating the first routing planning path includes: generating a second routing planning path, and the second routing planning path passes through the one or more turning points; obtaining the adjustment of the second routing planning path by the user on the visual interface to obtain the first routing planning path.

[0012] In the solution of the embodiment of the present application, the solution of the present application combines the characteristics of manual planning and automatic algorithms. For example, the above-mentioned manual selection of the planning group or the above-mentioned at least two interconnection relationships with the same feedthrough information, and the above-mentioned determination of the first routing planning path through the turning points or the manual adjustment of the direction of the first routing planning path make the routing in the chip controllable, thereby greatly improving the efficiency of chip design work.

[0013] In combination with the first aspect, in some implementation manners of the first aspect, each interconnection relationship in the multiple interconnection relationships is further used to indicate the signal transmission direction between the pins at both ends of the interconnection relationship, and the signal transmission directions indicated by the at least two interconnection relationships are the same.

[0014] In combination with the first aspect, in some implementation manners of the first aspect, the method further includes: determining the line width occupied by the first routing planning path according to the sum of the bit widths of the pins connected by the at least two interconnection relationships.

[0015] In combination with the first aspect, in some implementations of the first aspect, the hardware modules at both ends of the interconnection relationship are the starting module and the terminating module, and the at least two interconnection relationships include a first interconnection relationship and a second interconnection relationship in which the starting module and / or the terminating module are different.

[0016] In the solution of the embodiment of the present application, the grouping selection of the planning group of the interconnection relationship is not restricted by the difference of the starting module, not restricted by the difference of the terminating module, and not restricted by the number and type of signals in the pins either. Only the feedthrough information needs to be considered whether it is the same.

[0017] In combination with the first aspect, in some implementations of the first aspect, generating at least two planned wirings according to the first wiring planning path includes: generating at least two intermediate planned wirings along the direction of the first wiring planning path according to the first wiring planning path, and the at least two intermediate planned wirings correspond to the at least two interconnection relationships one by one; generating start-end wirings connecting the two end pins of each intermediate planned wiring and the corresponding interconnection relationship among the at least two intermediate planned wirings, so as to obtain the at least two planned wirings.

[0018] In the solution of the embodiment of the present application, the function of batch connection is completed by automatically completing the start-end wirings of the traces, which greatly improves the work efficiency.

[0019] In a second aspect, there is provided an apparatus for chip wiring planning, including: an obtaining module, configured to: obtain layout planning information of a chip, where the layout planning information includes layout positions of a plurality of hardware modules in the chip and a plurality of interconnection relationships connecting between the plurality of hardware modules or between a hardware module and a chip pin, and each interconnection relationship in the plurality of interconnection relationships is used to indicate a connection relationship between two end pins of the interconnection relationship; a processing module, configured to: determine at least two interconnection relationships from the plurality of interconnection relationships, where the feedthrough information of the at least two interconnection relationships is the same, and the feedthrough information is used to indicate at least one hardware module that a planned wiring between two end pins of the interconnection relationship needs to pass through; determine a first wiring planning path according to the at least two interconnection relationships, where the first wiring planning path is used to indicate a path when a planned wiring between two end pins of the at least two interconnection relationships passes through a hardware module; a generating module, configured to: generate at least two planned wirings according to the first wiring planning path, the at least two planned wirings correspond to the at least two interconnection relationships one by one, and each planned wiring in the at least two planned wirings is used to connect two end pins of the corresponding interconnection relationship.

[0020] In combination with the second aspect, in a possible implementation manner of the second aspect, the processing module is specifically configured to: provide the multiple interconnection relationships through a visual interface; obtain at least two interconnection relationships in which the feedthrough information selected by the user is the same among the multiple interconnection relationships.

[0021] In combination with the second aspect, in a possible implementation manner of the second aspect, the processing module is specifically configured to: obtain one or more turning points selected by the user from the layout planning information presented on the visual interface, where the one or more turning points are located on some hardware modules in the layout planning information; generate the first wiring planning path according to the one or more turning points, and the first wiring planning path passes through the one or more turning points.

[0022] In combination with the second aspect, in a possible implementation manner of the second aspect, the generating module is specifically configured to: generate a second wiring planning path, and the second wiring planning path passes through the one or more turning points; obtain the adjustment of the second wiring planning path by the user on the visual interface to obtain the first wiring planning path.

[0023] In combination with the second aspect, in a possible implementation manner of the second aspect, each interconnection relationship in the multiple interconnection relationships is further used to indicate the signal transmission direction between the pins at both ends of the interconnection relationship, and the signal transmission directions indicated by the at least two interconnection relationships are the same.

[0024] In combination with the second aspect, in a possible implementation manner of the second aspect, the processing module is further configured to: determine the line width occupied by the first wiring planning path according to the sum of the bit widths of the pins connected by the at least two interconnection relationships.

[0025] In combination with the second aspect, in a possible implementation manner of the second aspect, the hardware modules at both ends of the interconnection relationship are a starting module and a terminating module, and the at least two interconnection relationships include a first interconnection relationship and a second interconnection relationship in which the starting module and / or the terminating module are different.

[0026] In combination with the second aspect, in a possible implementation manner of the second aspect, the generating module is specifically configured to: generate at least two intermediate planned wirings along the direction of the first wiring planning path according to the first wiring planning path, and the at least two intermediate planned wirings correspond to the at least two interconnection relationships one by one; generate start-end wirings connecting the two ends of the pins of each intermediate planned wiring in the at least two intermediate planned wirings and the corresponding interconnection relationship to obtain the at least two planned wirings.

[0027] In a third aspect, an embodiment of the present application provides a computer-readable storage medium storing program code, and when the computer storage medium runs on a computer, it causes the computer to execute the first aspect or any possible implementation manner of the first aspect.

[0028] Fourthly, an embodiment of the present application provides a computer program product, which includes computer program code. When the computer program code runs on a computer, the computer is caused to execute the first aspect or any possible implementation manner of the first aspect.

[0029] Fifthly, an embodiment of the present application provides a computer device, which includes a processor. The processor is used to be coupled with a memory, read and execute instructions and / or program code in the memory, so as to execute the first aspect or any possible implementation manner of the first aspect.

[0030] Sixthly, an embodiment of the present application provides a chip system, which includes a logic circuit. The logic circuit is used to be coupled with an input / output interface and transmit data through the input / output interface, so as to execute the first aspect or any possible implementation manner of the first aspect. Description of the Drawings

[0031] Figure 1 It is a schematic diagram of a chip layout planning provided by an embodiment of the present application.

[0032] Figure 2 It is a schematic diagram of a chip planning and routing provided by an embodiment of the present application.

[0033] Figure 3 It is a schematic flowchart of a method for chip routing planning provided by an embodiment of the present application.

[0034] Figure 4 It is a schematic diagram of feedthrough information of an interconnection relationship provided by an embodiment of the present application.

[0035] Figure 5 It is a schematic diagram of a selected interconnection relationship provided by an embodiment of the present application.

[0036] Figure 6 It is a schematic diagram of determining a first routing planning path provided by an embodiment of the present application.

[0037] Figure 7 It is another schematic diagram of determining a first routing planning path provided by an embodiment of the present application.

[0038] Figure 8 It is a schematic diagram of generating a planned routing provided by an embodiment of the present application.

[0039] Figure 9 It is another schematic diagram of generating a planned routing provided by an embodiment of the present application.

[0040] Figure 10It is a schematic structural block diagram of a chip wiring planning device provided by an embodiment of the present application.

[0041] Figure 11 It is a schematic diagram of the hardware structure of a chip wiring planning device provided by an embodiment of the present application. Detailed implementation manners

[0042] Next, the technical solutions in the present application will be described with reference to the accompanying drawings.

[0043] In the design and implementation process of digital integrated circuits (ICs), floorplanning is the initial step and one of the most critical steps. Floorplan mainly represents the graphical representation of circuit functional modules in a tentative layout in integrated circuit design. The floorplan of a chip can include defining the size and shape of the chip, as well as defining the size and position of various modules, hard cores (such as memories and other intellectual property cores), IO interfaces, etc. within the chip, and defining some special areas, such as the areas of blockages and power / ground planes. The rationality of the floorplan is directly related to the timing convergence, smooth wiring, power stability, and yield rate of the chip. For example, a reasonable floorplan can accelerate the signoff of timing verification, design rule check (DRC), and layout versus schematic (LVS) Figure 1 signoff.

[0044] Next, with reference to Figure 1 introduce the graphical representation of the floorplan, Figure 1 shows a schematic diagram of the floorplan of the chip layout planning. After the size and shape of the chip are defined, it is necessary to define the size, position, and placement method of hardware modules such as macro modules and hard cores within the chip. As Figure 1 shown in (a) of Figure 1 the rectangles in the chip are the hardware modules defined in the chip, or rather, the size and position of the hardware modules in the chip that have been defined, while

[0045] Exemplarily, Figure 1The hardware modules in (a) include Module #1 to Module #10. The hardware modules can be macro cells such as flip - flops, arithmetic logic units, hardware registers, or the above - mentioned memory / IP cores. These hardware modules can also include smaller modules or units inside. Users, or chip designers, can place Module #1 to Module #10 according to the types, areas, interconnect line lengths, etc. of different hardware modules.

[0046] For example, Figure 1 Module #5 in the middle area shown in (a) can be the basic logic operation unit that constitutes the entire chip. Module #1 to Module #3 can be memory cells placed along the edge. For memory cells, there are data ports and memory ports, and some testability circuits are required around them. This makes the leads of these memory cells numerous and the power consumption huge. Therefore, as Figure 1 shown in (a), placing these memory cells along the edge of the chip not only facilitates the power supply of these cells but also prevents too many pins from affecting the wiring of other cells.

[0047] For another example, for a macro cell with a large area such as Figure 1 Module #4 in, it not only needs to exchange data with other macro cells or standard cells inside the chip but also needs to communicate with devices outside the chip through input / output pins (IO pads). Therefore, these macro cells with a large area can be placed near the corresponding IO pads or IO corners, which is beneficial to reducing the interconnect line length, reducing the on - line delay, and saving wiring resources.

[0048] For another example, the placement of modules can also be determined according to the connection relationship of pins, ports, and the position of the interconnect module. As Figure 1 shown, if Hardware Module #10 is a memory module and Hardware Module #9 needs to exchange data with Hardware Module #10, or there is an interconnect relationship between Hardware Module #9 and Hardware Module #10 as shown by the arrow in the figure. Then the placement of Hardware Module #9 is such that the pin or port direction needs to face Hardware Module #10. For another example, if there is an interconnect relationship between Hardware Module #2 and Hardware Module #3, then the pin or port directions of Hardware Module #2 and Hardware Module #3 need to be set opposite to each other to save wiring resources. Generally speaking, during the floorplan design process, the placement of different modules can be determined according to the logical connection relationship between different modules.

[0049] Optionally, Figure 1There can be a certain gap between the shown hardware modules to provide wiring resources. In particular, a relatively large gap can be left at the boundaries of hardware modules with more ports. In some other embodiments of the present application, in order to save space for placing more hardware modules, the boundaries between hardware modules can also be adjacent without gaps, such as hardware module #6 and hardware module #7 shown in the figure. During the design process of the floorplan, the size of the gap can also be determined according to the logical connection relationships between different modules.

[0050] Exemplarily, the floorplan of the chip can also include the interconnection relationships between the above different hardware modules or between the hardware modules and the chip. For example, the interconnection relationships can be represented by fly lines or listed in a table. As Figure 1 shown in (a) therein, the interconnection relationships between different hardware modules are represented by connection lines or fly lines containing arrows, which are used to indicate that there is a signal transmission relationship between two hardware modules. As Figure 1 shown in (b) therein, the interconnection relationships between different hardware modules can be used to indicate the logical connection relationships between the pins or ports of the hardware modules, and the interconnection relationships between the hardware modules and the chip can be used to indicate the logical connection relationships between the pins or ports of the hardware modules and the IO pads of the chip. For example, pin a1 of module #9 and pin b1 of module #10, and pin a2 of module #9 and pin b2 of module #10 have logical connection relationships. Therefore, as Figure 1 shown in (b) therein, module #9 can be connected to module #10 by two fly lines. For another example, pin a3 of module #9 is also connected to port c1 of the chip. Therefore, as Figure 1 shown in (b) therein, module #9 can be connected to the IO pad of the chip by one fly line.

[0051] Specifically, Figure 1 the direction of the fly lines in (b) can be used to indicate the signal transmission direction between the pins or ports at both ends of the interconnection relationship. For example, the direction of the fly line from pin a1 to pin b1 can be used to indicate that the signal transmission direction is from pin a1 to pin b1.

[0052] It should be understood that in the above cases, each interconnection relationship can be regarded as a signal group, and multiple pins at both ends of the signal group can be classified into pin groups with the same function (pingroup). In other words, each interconnection relationship corresponds to a signal group or a pin group, which is used to indicate the signal transmission relationship between the pins in the same pin group.

[0053] After determining the floorplan of the chip, it is necessary to determine the planned wiring inside the chip according to the interconnection relationships in the floorplan. Figure 2shows the form of planned wiring in the embodiments of the present application. As Figure 2 shown in (a) of Figure 2 , when two hardware modules are adjacent and their pins are placed opposite to each other, the routing method of the planned wiring can be to directly pass through the gap between the hardware modules to connect the pins of the two hardware modules; when there are other hardware modules or blockages between two hardware modules with an interconnection relationship, the routing method of the planned wiring can be to bypass the intermediate blocked hardware module as shown in Figure 2 (b) of Figure 2 , or it can be the planned wiring passing through the intermediate blocked hardware module as shown in Figure 2 (c) of Figure 2 , and the behavior of the planned wiring passing through the hardware module can also be referred to as feedthrough.

[0054] At present, the methods for determining the planned wiring inside the chip have many limitations. For example, due to the wide range of business scenarios of the chip, the placement methods and routing constraints of circuit modules in different business scenarios are different. The penetration routes of the wiring in the chip are very long, and the channels and resources for routing are limited. It is necessary to manually intervene in the design process of the routing path, so it is difficult to abstract general automatic routing rules suitable for each business scenario. Moreover, due to the huge number of routing lines between ports and pins, the long routing distance, and the fact that the planned routing path is affected by various constraints (such as the routing path passing through blockages), the current manual planning is extremely inefficient and takes up a large amount of design time. Furthermore, it makes the routing planning step one of the most time-consuming process nodes in the entire chip design process.

[0055] To solve the above technical problems, the present application proposes a chip wiring planning method 300, as shown in the schematic flowchart of Figure 3 . The method 300 includes steps 310 to 340. The method 300 forms a batch routing planning group by combining all interconnection relationships with the same feedthrough information, and determines the corresponding planned feedthrough path based on this planning group. The method 300 can not only avoid the inefficient work of traditional manual planning that can only plan one interconnection relationship at a time, but also avoid the routing uncertainty brought by automatic routing and the inappropriateness of not being able to abstract automatic routing rules in some scenarios, as well as avoid the algorithm instability caused by the need for continuous adaptation to new projects, new scenarios, new processes, etc. in automatic routing.

[0056] Step 310: Obtain the layout planning information of the chip.

[0057] According to the above introduction of the floorplan, the layout planning information in step 310 may include the layout positions of multiple hardware modules in the chip and multiple interconnection relationships connecting between the multiple hardware modules or between a hardware module and the chip. Each of the multiple interconnection relationships is used to indicate the connection relationship between the pins at both ends of the interconnection relationship.

[0058] Optionally, the obtaining manner of step 310 may be that an electronic design automation (EDA) software or device executing method 300 obtains an input file, and the input file may be a floorplan file that has been designed by a user or a designer. Optionally, if method 300 is executed by EDA software, the layout planning information in step 310 may also be obtained by a user or a designer performing an online layout planning for the chip in the EDA software.

[0059] Step 320: Determine at least two interconnection relationships from the multiple interconnection relationships, and the feedthrough information of the at least two interconnection relationships is the same.

[0060] It should be understood that the feedthrough information in step 320 is used to indicate at least one hardware module that the planned wiring between the hardware modules at both ends of the interconnection relationship needs to pass through. Or rather, the feedthrough information is the hardware module that the planned wiring determined by the interconnection relationship needs to pass through. For example, Figure 2 hardware module C shown in (c) in. If the planned wiring between the hardware modules at both ends of the interconnection relationship does not pass through any hardware module, then this interconnection relationship can be regarded as having no feedthrough information.

[0061] Figure 4 shows a schematic diagram of the feedthrough information of the interconnection relationship. As Figure 4 shown, there are interconnection relationships between hardware module A and hardware modules D and F, and between hardware modules B and E and hardware module H. Among them, according to the hardware modules passed by the interconnection relationships shown in the figure, the feedthrough information of the interconnection relationship between hardware module A and hardware module D includes hardware modules B and C, and the feedthrough information of the interconnection relationship between hardware module A and hardware module F includes hardware modules B and C. Therefore, the hardware modules that the planned wiring between the hardware modules at both ends of the above two interconnection relationships needs to pass through are the same, both being hardware modules B and C. Furthermore, the feedthrough information of the above two interconnection relationships is the same. Similarly, the feedthrough information of the interconnection relationship between hardware module B and hardware module H includes hardware module F, and the feedthrough information of the interconnection relationship between hardware module E and hardware module H includes hardware module F. Furthermore, the feedthrough information of these two interconnection relationships is the same.

[0062] It should be understood that Figure 4 is only an example of the feedthrough information. In the embodiments of the present application, Figure 4The interconnection relationships therein can also be straight lines without turns, or straight lines including arrows for indicating the signal transmission direction, and users or designers can determine, based on experience or the actual routing resources inside the chip, that the planned routing between the hardware module A and the hardware module F as shown in Figure 4 needs to pass through the hardware modules B and C.

[0063] It can be obtained therefrom that, in the embodiments of the present application, at least two interconnection relationships with the same feedthrough information are not restricted by the starting module and the ending module, nor by the number and types of signals of the pins and ports, and only consider whether the hardware modules passed through by the feedthrough paths are the same. The following embodiments do not elaborate on the design and planning of the routing for the interconnection relationships with exactly the same starting module and ending module.

[0064] It should be noted that the feedthrough information of at least two interconnection relationships in step 320 needs to be exactly the same. For example, if Figure 4 the feedthrough information of the interconnection relationship between the hardware module F and the hardware module C as shown includes the hardware module E, although the feedthrough information of the interconnection relationship between the hardware module A and the hardware module C includes the hardware modules F and E, covering the feedthrough information of the interconnection relationship between the hardware module F and the hardware module C, the feedthrough information of these two interconnection relationships is not the same.

[0065] Optionally, the feedthrough information can be determined through the input file received by the EDA software. For example, the input file includes the feedthrough information existing in all or part of the interconnection relationships in the layout planning information. It can also be that users or designers select at least two interconnection relationships with the same feedthrough information in the visual interface presented by the EDA software according to their own experience. The following embodiments will introduce this process in detail and will not elaborate here.

[0066] Step 330: Determine the first routing planning path according to the feedthrough information of the at least two interconnection relationships.

[0067] Specifically, the first routing planning path is used to indicate the path when the planned routing between the two end hardware modules of at least two interconnection relationships in step 320 passes through the hardware modules. It should be understood that this first routing planning path is only the planned path information and does not include the planning of the actual routing.

[0068] Optionally, step 330 can be implemented through an automatic planning algorithm. For example, the automatic planning algorithm can automatically determine, according to Figure 4 the feedthrough information of the interconnection relationship between the hardware module A and the hardware module C as shown, that the first routing planning path is from the hardware module B to the hardware module C, and determine the shortest path among them as the first routing planning path. The automatic planning algorithm can be any path planning algorithm at the present stage, and the present application does not limit this.

[0069] Optionally, step 330 may be to select one or more turning points by a user or a designer in the visual interface presented by the EDA software, where the visual interface presents layout planning information, and these turning points are located on some of the hardware modules presented in the layout planning information. These hardware modules may be the hardware modules indicated by the feedthrough information of at least two of the above-mentioned interconnection relationships. In some other embodiments of the present application, these hardware modules may also be different from the hardware modules indicated by the feedthrough information of at least two of the above-mentioned interconnection relationships. For example, the user or the designer may, according to the actual application scenario of the chip, adjust the position where the turning point is located through the above-mentioned visual interface, or move the turning point from one hardware module to another hardware module. The following embodiments will introduce the specific process in detail and will not be elaborated here. The above-mentioned first wiring planning path may be formed along the order of the turning points, or in other words, the above-mentioned first wiring planning path is generated by passing through the turning points one by one.

[0070] In an embodiment of the present application, the width of the first wiring planning path, or in other words, the line width occupied, may be determined according to the bit widths of at least two of the interconnection relationships in step 320. For example, if the at least two interconnection relationships are the interconnection relationships between N groups of pin groups, then the sum of the bit widths of the N groups of pin groups is the width of the first wiring planning path, or in other words, the line width occupied.

[0071] Step 340: Generate at least two planned wirings according to the first wiring planning path.

[0072] Specifically, the at least two planned wirings correspond one-to-one to the at least two interconnection relationships in step 320, and each of the at least two planned wirings is used to connect the pins of the hardware modules at both ends of the corresponding interconnection relationship.

[0073] In an embodiment of the present application, the intermediate planned wiring may be determined in advance through the first wiring planning path. The intermediate planned wiring corresponds one-to-one to the at least two interconnection relationships and is located in the feedthrough hardware module. Finally, the start and end connection lines between the intermediate planned wiring and the hardware modules at both ends of the interconnection relationship are determined to obtain the complete planned wiring. In some other embodiments of the present application, the user or the designer may also adjust the routing of the planned wiring in the visual interface of the EDA software, such as changing the hardware module through which the planned wiring passes or changing the routing of the planned wiring. The following embodiments will introduce this part in detail and will not be elaborated here.

[0074] The following will be combined with Figures 5 to 9 , taking the visual interface of the EDA software as an example, to introduce specific embodiments of the chip wiring planning method 300.

[0075] Based on Figure 4 the layout planning information and feedthrough information shown,Figure 5 A schematic diagram showing the determination of at least two interconnection relationships in step 320 is presented. Among them, Figure 5 the dashed circles in it can be the interconnection relationships repeatedly selected by the user or designer in the visualization interface. For example, from the above, the feedthrough information of the interconnection relationship between hardware module A and hardware module D and the interconnection relationship between hardware module A and hardware module F is the same, both passing through hardware modules B and C. Then, the user or designer can select the above two interconnection relationships through Figure 5 the dashed circles shown. The two selected interconnection relationships can be regarded as the same planning group. Similarly, the user or designer can select the interconnection relationship between hardware module B and hardware module D and the interconnection relationship between hardware module E and hardware module D (the feedthrough information is both hardware module F) through Figure 5 another dashed circle shown. These two interconnection relationships can be regarded as another planning group. In some other embodiments of the present application, when the interconnection relationship includes an arrow indicating the signal transmission direction, the signal transmission directions of the interconnection relationships in each planning group are the same, that is, the directions indicated by the arrows are the same. For example, Figure 5 the arrows of the interconnection relationships selected by the right dashed circle all point to hardware module D.

[0076] In step 330, it is possible to determine Figure 5 the first wiring planning paths respectively corresponding to the two selected planning groups. Figure 6 And Figure 7 respectively show schematic diagrams of the first wiring planning paths. Among them, Figure 6 the first wiring planning path shown in it can be determined by an automatic planning algorithm, Figure 7 the first wiring planning path shown in it can be determined manually by the user or designer.

[0077] Exemplarily, as Figure 6 shown, since the feedthrough information of the two groups of interconnection relationships is hardware module B and hardware module C and hardware module F respectively, the automatic planning algorithm can automatically determine the shortest planning path of the feedthrough according to the pin positions at both ends of the connection relationship, the signal connection direction, etc., that is, Figure 6 the two rectangles filled with diagonal stripes shown, one of which passes through hardware modules B and C, and the other passes through hardware module F. Figure 6 The two first wiring planning paths in it correspond one by one to Figure 5 the two groups of planning groups shown.

[0078] Exemplarily, the first wiring planning path can also be determined according to the turning points selected by the user or designer. For example, since the planning path obtained by the automatic planning algorithm may not consider the possible blocking blocks encountered in the middle, or the positions of the pins at both ends of the interconnection relationship deviate, etc., it is necessary to manually intervene in the direction of the wiring planning path to ensure the accuracy of the wiring planning. As Figure 7 shown in (a) of Figure 7 , the user or designer can click one or more turning points in the layout planning plane presented in the visualization interface, and then the first wiring planning path is determined by passing through the above one or more turning points. For example, if a feedthrough cannot be formed on the left side of hardware modules B and C, or the positions of the pins to be connected are changed to the right side of hardware module A, it is necessary to replace the feedthrough path with the right side of hardware modules B and C. Therefore, the user or designer can click on the right side of hardware modules B and C to generate turning points, and then as Figure 7 shown in (b) of

[0079] , the first wiring planning path can be formed along the turning points, that is, the right side of hardware modules B and C. Finally, through multiple turns, it reaches the position of the pins to be connected. For another example, if there is a blocking block between hardware module E and hardware module F, which affects the direct connection wiring between hardware module E and hardware module F, then as

[0080] shown in (b) of Figure 6 and Figure 7 , the user or designer can click on the turning points so that the finally generated first wiring planning path bypasses the blocking block and then feeds through hardware module F. Figure 8

[0079] In some other embodiments of the present application, the turning points can also be located on hardware modules not included in the feedthrough information. For example, if the blocking block between hardware modules E and F has a large area, making it difficult to directly wire between hardware modules E and F, at this time, the user or designer can click the turning points on hardware module A and hardware module D, and finally change the feedthrough information corresponding to the interconnection relationship between hardware modules E and H to hardware modules A, B, C, and D, and the finally generated planned wiring passes through hardware modules A, B, C, and D.

[0080] After that, according to Figure 6 and Figure 7 the automatically or manually generated first wiring planning path shown, Figure 8

[0079] and Figure 9 show a schematic diagram of generating planned wiring according to the first wiring planning path in step 340. As Figure 8 shown, since the number of interconnection relationships in both groups of planning groups is two, two groups of planned wiring groups are generated according to the Figure 7 shown wiring planning path, and each group of planned wiring groups includes two planned wirings. As Figure 8 shown, the direction of the planned wiring is the same as that of the first wiring planning path.

[0081] As Figure 8As shown in (a) therein, the planned routing can be generated directly along the direction of the first routing planning path, or rather, the first routing planning path is replaced by multiple planned routings. Optionally, the planned routing can also be determined according to the first routing planning path and the actually connected hardware modules. For example, as shown in Figure 8 (b) therein, the planned routing between hardware modules A and F (i.e., the second planned routing from left to right) does not need to pass through the bottom end of hardware module C. Therefore, it can stop planning when reaching the position of the pin of hardware module F. Optionally, the user or designer can also adjust the obtained planned routing, such as changing the position, length, etc. of the planned routing to adapt to the pin positions of the hardware modules to be connected. Finally, multiple planned routings as shown in Figure 8 can be obtained.

[0082] It should be noted that Figure 8 the planned routing shown is only an intermediate planned routing, that is, this intermediate planned routing only passes through the hardware modules and is not connected to the starting module and the terminating module. Therefore, as shown in Figure 9 based on Figure 8 the intermediate planned routing therein, the start-end connections (such as the light-colored rectangular blocks) between the intermediate planned module and the start-end hardware modules are determined, or rather, according to the order of the planning groups or the preset allocation mechanism, the Figure 8 intermediate planned routing therein is connected to the hardware modules at both ends of the corresponding interconnection relationship, and the situation of crossing is avoided. Finally, the complete planned routings as shown in (a) and (b) in Figure 9 are generated.

[0083] In the technical solution of this application, multiple interconnection relationships with the same feedthrough information are grouped into the same planning group, and the first routing planning path is planned. Finally, the planned routings corresponding to the same planning group are generated in batches based on the first routing planning path. This method can not only avoid the low efficiency of traditional manual planning which can only plan one signal group at a time, but also avoid the routing uncertainty brought by automatic routing and the inadaptability that some scenarios cannot abstract automatic routing rules, as well as avoid the algorithm instability caused by the need to continuously adapt to new projects, new scenarios, new processes, etc. in automatic routing. The solution of this application combines the characteristics of manual planning and automatic algorithms, that is, the planning group can be manually selected, the planning path and the planned routing can be manually controlled, so that the routing in the chip is controllable, thereby greatly improving the efficiency of chip design work.

[0084] The following will describe the device of the embodiment of this application in combination with Figure 10 and Figure 11 . It should be understood that the device described below can execute the method of the foregoing embodiment of this application. To avoid unnecessary repetition, the following description of the device of the embodiment of this application appropriately omits the repeated description.

[0085] Figure 10 It is a schematic structural block diagram of a device for chip wiring planning provided according to an embodiment of the present application. As Figure 10 shown, the device 1000 for chip wiring planning includes an acquisition module 1001, a processing module 1002, and a generation module 1003.

[0086] The acquisition module 1001 is configured to: acquire layout planning information of the chip, where the layout planning information includes layout positions of multiple hardware modules in the chip and multiple interconnection relationships connecting the multiple hardware modules, and each interconnection relationship in the multiple interconnection relationships is used to indicate a connection relationship between pins of hardware modules at both ends of the interconnection relationship; the processing module 1002 is configured to: determine at least two interconnection relationships from the multiple interconnection relationships, where feedthrough information of the at least two interconnection relationships is the same, the feedthrough information is used to indicate at least one hardware module that the planned wiring between hardware modules at both ends of the interconnection relationship needs to pass through, and determine a first wiring planning path according to the feedthrough information of the at least two interconnection relationships, the first wiring planning path is used to indicate a path when the planned wiring between hardware modules at both ends of the at least two interconnection relationships passes through the hardware module; the generation module 1003 is configured to: generate at least two planned wirings according to the first wiring planning path, the at least two planned wirings correspond to the at least two interconnection relationships one by one, and each planned wiring in the at least two planned wirings connects pins of hardware modules at both ends of the corresponding interconnection relationship.

[0087] The device provided in the above embodiment and the method embodiment belong to the same concept. For the specific implementation process, refer to the method embodiment in the above text, which will not be elaborated here.

[0088] The modules in each example described in the embodiments of the present application can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but this implementation should not be considered to exceed the scope of the present application.

[0089] For example, during the implementation process, the acquisition module 1001, the processing module 1002, and the generation module 1003 can be completed through instructions or program codes in software form, such as being executed by a combination of hardware and software modules in a processor. The software module can be located in a mature storage medium in the art such as random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to implement the acquisition module 1001, the processing module 1002, and the generation module 1003.

[0090] It should be noted that: when the device provided in the above embodiment executes the above method, only the division of the above functional modules is used for illustration. In actual application, the above functions can be allocated to different functional modules according to needs, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For example, in device 1000, acquisition module 1001 can be used to execute any step in the above method, and processing module 1002 can be used to execute any step in the above method. The steps to be implemented by each unit can be specified according to needs, and all functions of the above device can be implemented by each unit respectively implementing different steps in the above method.

[0091] Figure 11 It is a schematic diagram of the hardware structure of a device for chip wiring planning provided by an embodiment of the present application. Figure 11 The shown device 1100 for chip wiring planning (the device 1100 may specifically be a computer device) includes a memory 1101, a processor 1102, a communication interface 1103, and a bus 1104. Among them, the memory 1101, the processor 1102, and the communication interface 1103 are communicatively connected to each other through the bus 1104.

[0092] The memory 1101 may be a read only memory (ROM), a static storage device, a dynamic storage device, or a random access memory (RAM). The memory 1101 may store a program. When the program stored in the memory 1101 is executed by the processor 1102, the processor 1102 is used to execute each step of the method of the embodiment of the present application. For example, the processor 1102 may execute method 300 described above.

[0093] The processor 1102 may adopt a general-purpose central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU), or one or more integrated circuits, and is used to execute relevant programs to implement the method of the method embodiment of the present application.

[0094] The processor 1102 may also be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the method of the present application may be completed by the integrated logic circuit in the hardware of the processor 1102 or instructions in software form.

[0095] The above-mentioned processor 1102 may also be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory 1101, and the processor 1102 reads the information in the memory 1101 and completes it in combination with its hardware. Figure 10 the functions required to be executed by the modules included in the device shown, or execute the method 300 of the method embodiment of the present application.

[0096] The communication interface 1103 uses a transceiver device such as, but not limited to, a transceiver to implement the communication between the device 1100 and other devices or communication networks.

[0097] The bus 1104 may include a path for transmitting information between the various components of the device 1100 (for example, the memory 1101, the processor 1102, and the communication interface 1103).

[0098] The embodiments of the present application also provide a computer device, which includes a processor for coupling with a memory, reading and executing instructions and / or program codes in the memory to execute the method described in any one of the above embodiments.

[0099] The embodiments of the present application also provide a chip system, which includes a logic circuit for coupling with an input / output interface and transmitting data through the input / output interface to execute the method described in any one of the above embodiments.

[0100] It should be noted that the processor in the embodiments of the present application may be an integrated circuit chip with signal processing capabilities. In the implementation process, the steps of the above method embodiments may be completed by the integrated logic circuit in the hardware of the processor or by instructions or program codes in software form. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the embodiments of the present application may be directly embodied as being executed and completed by the hardware decoding processor, or may be executed and completed by a combination of the hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, flash memory, read-only memory, programmable read-only memory, or electrically erasable programmable memory, register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method.

[0101] It can be understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchlink dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0102] The present application also provides a computer program product, which includes: computer program code, and when the computer program code runs on a computer, it causes the computer to execute the method of any one of the above embodiments.

[0103] The present application also provides a computer-readable medium storing program code which, when run on a computer, causes the computer to execute the method of any one of the above embodiments.

[0104] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0105] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0106] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings, direct couplings, or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of devices or units can be in electrical, mechanical, or other forms.

[0107] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions or program codes to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0108] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A chip wiring planning method, characterized in that: include: Acquire layout planning information of a chip, wherein the layout planning information includes layout positions of multiple hardware modules in the chip and multiple interconnection relationships between the multiple hardware modules or between the hardware modules and the chip pins, wherein each interconnection relationship among the multiple interconnection relationships is used to indicate a connection relationship between pins at both ends of the interconnection relationship; Determine at least two interconnection relationships from the multiple interconnection relationships, wherein the at least two interconnection relationships have the same feedthrough information, and the feedthrough information is used to indicate at least one hardware module that the planned wiring between the pins at both ends of the interconnection relationship needs to pass through; Determine a first wiring planning path according to the at least two interconnection relationships, wherein the first wiring planning path is used to indicate a path of the planned wiring between the pins at both ends of the at least two interconnection relationships when passing through the hardware module; At least two planned wirings are generated according to the first planned wiring path. The at least two planned wirings correspond to the at least two interconnection relationships in a one-to-one manner. Each of the at least two planned wirings is used to connect pins at both ends of the corresponding interconnection relationship.

2. The method according to claim 1, characterized in that Determining at least two interconnection relationships having the same feedthrough information from the plurality of interconnection relationships comprises: Providing the plurality of interconnected relationships through a visual interface; At least two interconnection relationships with the same feedthrough information selected by a user from among the multiple interconnection relationships are obtained.

3. The method according to claim 1 or 2, characterized in that: The step of determining a first wiring planning path according to the at least two interconnection relationships includes: Acquire one or more turning points selected by a user from the layout planning information presented on the visualization interface, wherein the one or more turning points are located on some hardware modules in the layout planning information; The first wiring planning path is generated according to the one or more turning points, and the first wiring planning path passes through the one or more turning points.

4. The method according to claim 3, characterized in that The generating the first wiring planning path comprises: generating a second wiring planning path, wherein the second wiring planning path passes through the one or more turning points; The adjustment of the second wiring planning path by the user on the visual interface is obtained to obtain the first wiring planning path.

5. The method according to any one of claims 1 to 4, characterized in that Each interconnection relationship among the plurality of interconnection relationships is further used to indicate a signal transmission direction between pins at both ends of the interconnection relationship, and the signal transmission directions indicated by the at least two interconnection relationships are the same.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The line width occupied by the first wiring planning path is determined according to the sum of the bit widths of the pins connected by the at least two interconnected relationships.

7. The method according to any one of claims 1 to 6, characterized in that The hardware modules at both ends of the interconnection relationship are a starting module and a terminating module, and the at least two interconnection relationships include a first interconnection relationship and a second interconnection relationship in which the starting modules and / or the terminating modules are different.

8. The method according to any one of claims 1 to 7, characterized in that The step of generating at least two planned wirings according to the first wiring planning path includes: According to the first planned wiring path, generating at least two intermediate planned wirings along the direction of the first planned wiring path, wherein the at least two intermediate planned wirings correspond one-to-one to the at least two interconnection relationships; Generate a start and end wiring for connecting each of the at least two intermediate planned wirings with the corresponding two end pins of the interconnection relationship to obtain the at least two planned wirings.

9. A device for chip wiring planning, characterized in that: include: An acquisition module is used to: acquire layout planning information of a chip, wherein the layout planning information includes layout positions of multiple hardware modules in the chip and multiple interconnection relationships between the multiple hardware modules or between the hardware modules and the chip pins, wherein each interconnection relationship among the multiple interconnection relationships is used to indicate a connection relationship between pins at both ends of the interconnection relationship; A processing module, used to: determine at least two interconnection relationships from the multiple interconnection relationships, the at least two interconnection relationships have the same feedthrough information, and the feedthrough information is used to indicate at least one hardware module that the planned wiring between the pins at both ends of the interconnection relationship needs to pass through; Determine a first wiring planning path according to the at least two interconnection relationships, wherein the first wiring planning path is used to indicate a path of the planned wiring between the pins at both ends of the at least two interconnection relationships when passing through the hardware module; A generation module is used to: generate at least two planned wirings according to the first wiring planning path, the at least two planned wirings correspond to the at least two interconnection relationships one by one, and each of the at least two planned wirings is used to connect the pins at both ends of the corresponding interconnection relationship.

10. The device according to claim 9, characterized in that The processing module is specifically used for: Providing the plurality of interconnected relationships through a visual interface; At least two interconnection relationships with the same feedthrough information selected by a user from among the multiple interconnection relationships are obtained.

11. The device according to claim 9 or 10, characterized in that The processing module is specifically used for: Acquire one or more turning points selected by a user from the layout planning information presented on the visualization interface, wherein the one or more turning points are located on some hardware modules in the layout planning information; The first wiring planning path is generated according to the one or more turning points, and the first wiring planning path passes through the one or more turning points.

12. The device according to claim 11, characterized in that The generation module is specifically used for: generating a second wiring planning path, wherein the second wiring planning path passes through the one or more turning points; The adjustment of the second wiring planning path by the user on the visual interface is obtained to obtain the first wiring planning path.

13. The device according to any one of claims 9 to 12, characterized in that Each interconnection relationship among the plurality of interconnection relationships is further used to indicate a signal transmission direction between pins at both ends of the interconnection relationship, and the signal transmission directions indicated by the at least two interconnection relationships are the same.

14. The device according to any one of claims 9 to 13, characterized in that The processing module is also used for: The line width occupied by the first wiring planning path is determined according to the sum of the bit widths of the pins connected by the at least two interconnected relationships.

15. The device according to any one of claims 9 to 14, characterized in that The hardware modules at both ends of the interconnection relationship are a starting module and a terminating module, and the at least two interconnection relationships include a first interconnection relationship and a second interconnection relationship in which the starting modules and / or the terminating modules are different.

16. The device according to any one of claims 9 to 15, characterized in that The generation module is specifically used for: According to the first planned wiring path, generating at least two intermediate planned wirings along the direction of the first planned wiring path, wherein the at least two intermediate planned wirings correspond one-to-one to the at least two interconnection relationships; Generate a start and end wiring for connecting each of the at least two intermediate planned wirings with the corresponding two end pins of the interconnection relationship to obtain the at least two planned wirings.

17. A computer readable medium, characterized in that The computer readable medium stores a program code, and when the computer program code is executed on a computer, the computer is caused to perform the method according to any one of claims 1 to 8.

18. A computer program product, characterized in that The computer program product comprises a computer program code, which, when executed on a computer, causes the computer to perform the method according to any one of claims 1 to 8.

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