Substrate structure and preparation method thereof

Abstract

The invention provides a substrate structure and a preparation method thereof. The method comprises the steps that a first through hole penetrates through a ceramic core plate; the core plate dielectric layer covers the surface of the ceramic core plate and fills the first through hole; second through holes are formed in the positions, corresponding to the first through holes, of the core board dielectric layer and penetrate through the core board dielectric layer, a patterned core board circuit layer, a layer-adding dielectric layer with layer-adding through holes and a layer-adding circuit layer are arranged on the surface of the core board dielectric layer, and the layer-adding circuit layer is electrically connected with the core board circuit layer through the layer-adding through holes. By using the ceramic core plate, the warping degree and the loss of the substrate are reduced, and the substrate is suitable for a substrate with a larger size; meanwhile, the surface of the ceramic core plate is wrapped by the core plate dielectric layer, so that ceramic is prevented from being easily broken due to insufficient toughness, and the product life is prolonged; in addition, the circuit layer is arranged after the ceramic core plate is wrapped by the core plate dielectric layer, so that the binding force between the ceramic core plate and the core plate circuit layer is improved, and the structural stability is improved; and finally, the ceramic core plate is prepared in cooperation with the 3D printing technology, and the preparation efficiency of the substrate is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a substrate structure and a preparation method thereof. Background Art

[0002] With the rapid development of electronic technology, the number of I / O (input / output) pins of chips is increasing continuously, and multi-chip packaging and heterogeneous integration applications are becoming more and more widespread. Higher requirements are imposed on the warpage deformation of packaging substrates. For traditional organic IC (integrated circuit) packaging substrates, since the core board is composed of polymers and glass fibers, the expansion and contraction deformation is large and the warpage is serious. Currently, it is solved by increasing the board thickness. However, if the board thickness is too large, it will cause an increase in the overall board thickness of the IC packaging substrate and a significant increase in weight, bringing inconvenience to production operations.

[0003] As a structural material, ceramics are widely used in aerospace, industrial manufacturing, biomedicine, etc. due to their high flexural strength, good creep properties, high hardness, and high temperature resistance. If ceramic materials can be used to make packaging substrates, their good properties can solve the problems existing in current packaging substrates. However, ceramics prepared by traditional methods generally have difficulties in processing and it is difficult to prepare products with complex shapes. Traditional ceramic preparation technologies cannot meet the requirements for preparing packaging substrates.

[0004] Therefore, there is an urgent need for a substrate preparation method and a substrate structure that can reduce the warpage of the substrate and are convenient to prepare.

[0005] It should be noted that the above introduction of the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a substrate structure and a preparation method thereof, which are used to solve the problems of large warpage of the substrate and great preparation difficulty in the prior art.

[0007] To achieve the above purpose, the present invention provides a preparation method of a substrate structure, and the preparation method includes:

[0008] Providing a ceramic core board, the ceramic core board includes a first surface and a second surface arranged oppositely, and a first through hole penetrating the ceramic core board is arranged on the first surface or the second surface of the ceramic core board;

[0009] Core board dielectric layers are arranged on the first surface and the second surface of the ceramic core board, and the core board dielectric layers cover the first surface and the second surface and fill the first through hole;

[0010] A second via hole is provided at a position within the core board dielectric layer and the first via hole. The second via hole penetrates the core board dielectric layer. The aperture of the second via hole is smaller than that of the first via hole, and the hole wall of the second via hole does not contact the hole wall of the first via hole.

[0011] A patterned core board circuit layer is provided on the surface of the core board dielectric layer, and the core board circuit layer fills the second via hole.

[0012] A patterned build-up dielectric layer is provided on the patterned core board circuit layer. The build-up dielectric layer includes build-up via holes that penetrate the build-up dielectric layer, and the build-up via holes expose a part of the core board circuit layer.

[0013] A patterned build-up circuit layer is provided on the patterned build-up dielectric layer, and the build-up circuit layer forms an effective electrical connection with a part of the core board circuit layer through the third via hole.

[0014] Optionally, the ceramic core board including the first via hole is prepared by a 3D printing method.

[0015] Optionally, the 3D printing method adopted includes a fused deposition modeling technique or a stereolithography 3D printing technique.

[0016] Optionally, the method for preparing the core board circuit layer includes:

[0017] A first seed layer is covered on the surface of the core board dielectric layer, and the first seed layer covers all the surfaces exposed by the core board dielectric layer.

[0018] A patterned first photosensitive layer is provided on the surface of the first seed layer.

[0019] A first conductive layer is filled in the gaps between the patterned first photosensitive layers, and the first conductive layer also fills the second via hole.

[0020] The first photosensitive layer and the first seed layer below the first photosensitive layer are removed, and the patterned first seed layer and the first conductive layer constitute the core board circuit layer.

[0021] Optionally, the method for preparing the build-up circuit layer includes:

[0022] A second seed layer is provided on the patterned build-up dielectric layer, and the second seed layer covers the surfaces exposed by the build-up dielectric layer and the surfaces exposed by the core board circuit layer.

[0023] A patterned second photosensitive layer is provided on the second seed layer.

[0024] Fill a second conductive layer in the gaps between the patterned second photosensitive layers, and the second conductive layer also fills the third through-hole;

[0025] Remove the second photosensitive layer and the second seed layer under the second photosensitive layer. The patterned second seed layer and the second conductive layer constitute the build-up circuit layer.

[0026] Optionally, the build-up circuit layer and the build-up dielectric layer constitute a substrate build-up layer, and multiple substrate build-up layers are provided.

[0027] Optionally, fill a solder mask layer in the gaps between the build-up circuit layers on the exposed surface of the substrate structure.

[0028] Optionally, provide a surface treatment layer on the surface of the build-up circuit layer exposed by the substrate structure.

[0029] The present invention also provides a substrate structure, which is obtained by using any of the above preparation methods. The substrate structure includes: a ceramic core board, a core board dielectric layer, a core board circuit layer, multiple substrate build-up layers, a solder mask layer, and a surface treatment layer;

[0030] The ceramic core board includes a first surface and a second surface arranged opposite to each other. A first through-hole is provided in the ceramic core board and penetrates from the first surface to the second surface;

[0031] The core board dielectric layer wraps all the exposed surfaces of the ceramic core board. A second through-hole penetrating the core board dielectric layer is provided at the position of the first through-hole in the core board dielectric layer. The aperture of the second through-hole is smaller than that of the first through-hole, and the hole wall of the second through-hole does not contact the hole wall of the first through-hole;

[0032] The patterned core board circuit layer is located on the surface of the core board dielectric layer and fills the second through-hole;

[0033] Each substrate build-up layer includes a patterned build-up dielectric layer and a build-up circuit layer. The build-up dielectric layer is provided with a build-up through-hole penetrating the build-up dielectric layer, and the build-up through-hole exposes a part of the core board circuit layer or the build-up circuit layer below; the build-up circuit layer is located on the build-up dielectric layer and fills the build-up through-hole to make an effective electrical connection with the exposed core board circuit layer or build-up circuit layer;

[0034] The solder mask layer is located in the gaps between the build-up circuit layers on the surface of the substrate structure, and the surface treatment layer is located on the surface of the build-up circuit layer on the surface of the substrate structure.

[0035] Optionally, the material of the ceramic core board is one or more arbitrary combinations of silicon carbonitride ceramics, silicon nitride ceramics, alumina ceramics, or aluminum nitride ceramics.

[0036] As described above, the substrate structure and its preparation method of the present invention have the following beneficial effects:

[0037] By using a ceramic core board, the present invention reduces the warpage and loss of the substrate and is applicable to larger-sized substrates;

[0038] By wrapping the surface of the ceramic core board with a core board dielectric layer, the present invention avoids the easy breakage of the ceramic due to insufficient toughness and improves the product life;

[0039] By arranging a circuit layer after wrapping the ceramic core board with a core board dielectric layer, the present invention improves the bonding force between the ceramic core board and the core board circuit layer and improves the structural stability;

[0040] The present invention prepares a ceramic core board in cooperation with 3D printing technology to improve the preparation efficiency of the substrate. Description of the Drawings

[0041] Figure 1 It shows a schematic structural diagram of providing a ceramic core board in step 1 of Embodiment 1 of the present invention.

[0042] Figure 2 It shows a schematic structural diagram of arranging a core board dielectric layer in step 2 of Embodiment 1 of the present invention.

[0043] Figure 3 It shows a schematic structural diagram of arranging a second through hole in step 3 of Embodiment 1 of the present invention.

[0044] Figure 4 It shows a schematic structural diagram of arranging a first seed layer in an optional example of step 4 of Embodiment 1 of the present invention.

[0045] Figure 5 It shows a schematic structural diagram of arranging a first photosensitive layer in an optional example of step 4 of Embodiment 1 of the present invention.

[0046] Figure 6 It shows a schematic structural diagram of arranging a first conductive layer in an optional example of step 4 of Embodiment 1 of the present invention.

[0047] Figure 7 It shows a schematic structural diagram of removing the first photosensitive layer in an optional example of step 4 of Embodiment 1 of the present invention.

[0048] Figure 8 It shows a schematic structural diagram of arranging an additional layer dielectric layer in step 5 of Embodiment 1 of the present invention.

[0049] Figure 9 It shows a schematic structural diagram of setting the second seed layer in an optional example of step 6 in Embodiment 1 of the present invention.

[0050] Figure 10 It shows a schematic structural diagram of setting the second photosensitive layer in an optional example of step 6 in Embodiment 1 of the present invention.

[0051] Figure 11 It shows a schematic structural diagram of setting the second conductive layer in an optional example of step 6 in Embodiment 1 of the present invention.

[0052] Figure 12 It shows a schematic structural diagram of removing the second photosensitive layer in an optional example of step 6 in Embodiment 1 of the present invention.

[0053] Figure 13 It shows a schematic structural diagram of setting a multi-layer substrate build-up in an optional example of step 6 in Embodiment 1 of the present invention.

[0054] Figure 14 It shows a schematic structural diagram of setting a solder mask layer and a surface treatment layer in an optional example of step 6 in Embodiment 1 of the present invention.

[0055] Figure 15 It shows a schematic structural diagram of the substrate structure in Embodiment 2 of the present invention.

[0056] Element number description

[0057] 1. Ceramic core board; 12. First through hole; 2. Core board dielectric layer; 21. Second through hole; 3. Core board circuit layer; 31. First seed layer; 32. First photosensitive layer; 33. First conductive layer; 4. Substrate build-up; 41. Build-up dielectric layer; 42. Third through hole; 43. Build-up circuit layer; 44. Second seed layer; 45. Second photosensitive layer; 46. Second conductive layer; 5. Solder mask layer; 6. Surface treatment layer. Detailed implementation manners

[0058] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] When detailing the embodiments of the present invention, for the convenience of description, the schematic diagrams showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples and should not limit the protection scope of the present invention herein. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0060] For ease of description, spatially relative terms such as "below", "beneath", "lower", "under", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings.

[0061] In the context of the present application, a structure in which a first feature is "above" a second feature may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0062] It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation may be arbitrarily changed, and the component layout type may also be more complex.

[0063] Embodiment 1:

[0064] The present invention provides a method for preparing a substrate structure, and the preparation method includes:

[0065] Step 1: Provide a ceramic core board, the ceramic core board includes a first surface and a second surface disposed opposite to each other, and a first through hole penetrating the ceramic core board is disposed on the first surface or the second surface of the ceramic core board;

[0066] Step 2: Dispose core board dielectric layers on the first surface and the second surface of the ceramic core board, and the core board dielectric layers cover the first surface and the second surface and fill the first through hole;

[0067] Step 3: Dispose a second through hole at a position in the core board dielectric layer and in the first through hole, the second through hole penetrates the core board dielectric layer, the aperture of the second through hole is smaller than the aperture of the first through hole, and the hole wall of the second through hole does not contact the hole wall of the first through hole;

[0068] Step 4: Dispose a patterned core board circuit layer on the surface of the core board dielectric layer, and the core board circuit layer fills the second through hole;

[0069] Step 5: Dispose a patterned build-up dielectric layer on the patterned core board circuit layer, the build-up dielectric layer includes a build-up through hole penetrating the build-up dielectric layer, and the build-up through hole exposes a part of the core board circuit layer;

[0070] Step 6: Provide a patterned build-up circuit layer on the patterned build-up dielectric layer. The build-up circuit layer forms an effective electrical connection with a part of the core board circuit layer through the third via hole.

[0071] The preparation method of the substrate structure of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the substrate structure protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0072] First, as Figure 1 shown, perform Step 1 to provide a ceramic core board 1. The ceramic core board 1 includes a first surface and a second surface arranged opposite to each other. A first via hole 12 penetrating the ceramic core board 1 is provided on the first surface or the second surface of the ceramic core board 1.

[0073] In one embodiment, the ceramic core board 1 including the first via hole 12 is prepared by a 3D printing method.

[0074] The present invention prepares a ceramic substrate by a 3D printing method, which can achieve higher-precision preparation, so that the obtained substrate can adapt to higher-density line alignment and meet the requirements of high-density and small-size substrates.

[0075] In one embodiment, the 3D printing method adopted includes a fused deposition modeling technique or a stereolithography 3D printing technique.

[0076] Preferably, the stereolithography 3D printing technique is used. It has a fast forming speed, high automation degree, can form any complex shape, high dimensional accuracy, excellent surface quality, can realize rapid forming of high-precision fine workpieces, and further improve the line density that the substrate can achieve.

[0077] Then, as Figure 2 shown, perform Step 2 to provide a core board dielectric layer 2 on the first surface and the second surface of the ceramic core board 1. The core board dielectric layer 2 covers the first surface and the second surface and fills the first via hole 12.

[0078] Next, as Figure 3 shown, perform Step 3 to provide a second via hole 21 at a position within the core board dielectric layer 2 and the first via hole 12. The second via hole 21 penetrates the core board dielectric layer 2. The aperture of the second via hole 21 is smaller than the aperture of the first via hole 12, and the hole wall of the second via hole 21 does not contact the hole wall of the first via hole 12.

[0079] In one embodiment, the second via hole 21 is formed by laser drilling with carbon dioxide or ultraviolet light.

[0080] In one embodiment, after the second through-hole 21 is formed, desmearing is performed.

[0081] Then, step 4 is carried out, and a patterned core board circuit layer 3 is formed on the surface of the core board dielectric layer 2, and the core board circuit layer 3 fills the second through-hole 21.

[0082] In one embodiment, the method for preparing the core board circuit layer 3 includes:

[0083] As Figure 4 shown, a first seed layer 4431 is covered on the surface of the core board dielectric layer 2, and the first seed layer 4431 covers all the exposed surfaces of the core board dielectric layer 2;

[0084] As Figure 5 shown, a patterned first photosensitive layer 32 is formed on the surface of the first seed layer 4431;

[0085] As Figure 6 shown, a first conductive layer 33 is filled in the gaps between the patterned first photosensitive layers 32, and the first conductive layer 33 also fills the second through-hole 21;

[0086] As Figure 7 shown, the first photosensitive layer 32 and the first seed layer 4431 under the first photosensitive layer 32 are removed, and the patterned first seed layer 4431 and the first conductive layer 33 constitute the core board circuit layer 3.

[0087] In one embodiment, the first seed layer 4431 is formed by a PTH (Plated Through Hole) process.

[0088] In one embodiment, the first seed layer 4431 is formed by electroless copper plating.

[0089] In one embodiment, the first seed layer 4431 under the first photosensitive layer 32 is removed by flash etching.

[0090] Next, as Figure 8 shown, step 5 is carried out, and a patterned build-up dielectric layer 41 is formed on the patterned core board circuit layer 3. The build-up dielectric layer 41 includes build-up through-holes penetrating the build-up dielectric layer 41, and the build-up through-holes expose part of the core board circuit layer 3.

[0091] Finally, step 6 is carried out, and a patterned build-up circuit layer 43 is formed on the patterned build-up dielectric layer 41. The build-up circuit layer 43 forms an effective electrical connection with part of the core board circuit layer 3 through the third through-hole 42.

[0092] In one embodiment, the method for fabricating the build-up wiring layer 43 includes:

[0093] As Figure 9 shown, a second seed layer is disposed on the patterned build-up dielectric layer 41, and the second seed layer covers the exposed surface of the build-up dielectric layer 41 and the exposed surface of the core board wiring layer 3;

[0094] As Figure 10 shown, a patterned second photosensitive layer 45 is disposed on the second seed layer;

[0095] As Figure 11 shown, a second conductive layer 46 is filled in the gaps between the patterned second photosensitive layers 45, and the second conductive layer 46 also fills the third via 42;

[0096] As Figure 12 shown, the second photosensitive layer 45 and the second seed layer under the second photosensitive layer 45 are removed, and the patterned second seed layer and the second conductive layer 46 constitute the build-up wiring layer 43.

[0097] In one embodiment, the second seed layer is disposed by a Plated Through Hole (PTH) process.

[0098] In one embodiment, the second seed layer is disposed by electroless copper plating.

[0099] In one embodiment, the second seed layer under the second photosensitive layer 45 is removed by a flash etching process.

[0100] In one embodiment, the third via 42 is formed by laser drilling with carbon dioxide or ultraviolet light.

[0101] In one embodiment, after the third via 42 in the build-up dielectric layer 41 is formed, desmear is performed.

[0102] By using ceramic as the core board material in the substrate, the present invention realizes a large-size packaging substrate with low warpage and low loss. The smaller warpage deformation enables the obtained substrate structure to have better coplanarity, thereby realizing better interconnect performance of the substrate. At the same time, by wrapping the core board dielectric layer 2 on the surface of the first via 12, a buffering and protecting effect on the ceramic core board 1 is achieved, solving the problem that the ceramic is fragile due to insufficient toughness, improving the reliability of the substrate structure, and extending the service life of the product. In addition, the higher adhesion of the core board dielectric layer 2 improves the bonding force between the ceramic core board 1 and the core board wiring layer 3, enhancing the structural stability of the substrate structure, so that the ceramic core board 1 can be widely used in the production line.

[0103] In one embodiment, as Figure 13 shown, the build-up wiring layer 43 and the build-up dielectric layer 41 form a substrate build-up 4, and multiple layers of the substrate build-up 4 are provided.

[0104] In one embodiment, each build-up wiring layer 43 is composed of a seed layer and a conductive layer, and the seed layer is in contact with the underlying structural layer.

[0105] In one embodiment, the material of the build-up dielectric layer 41 is all ABF (Ajinomoto Build-up Film).

[0106] In one embodiment, as Figure 14 shown, a solder mask layer 5 is filled in the gap between the build-up wiring layers 43 on the surface exposed by the substrate structure.

[0107] In one embodiment, the material of the solder mask layer 5 is solder mask ink.

[0108] In one embodiment, as Figure 14 shown, a surface treatment layer 6 is provided on the surface of the build-up wiring layer 43 exposed by the substrate structure.

[0109] Embodiment 2:

[0110] As Figure 15 shown, the present invention provides a substrate structure obtained by using any one of the preparation methods in the above Embodiment 1. The substrate structure includes: a ceramic core board 1, a core board dielectric layer 2, a core board wiring layer 3, multiple substrate build-ups 4, a solder mask layer 5, and a surface treatment layer 6;

[0111] The ceramic core board 1 includes a first surface and a second surface which are oppositely arranged, and a first through hole 12 is provided in the ceramic core board 1 and penetrates from the first surface to the second surface;

[0112] The core board dielectric layer 2 wraps all the surfaces exposed by the ceramic core board 1. A second through hole 21 penetrating the core board dielectric layer 2 is provided at the position of the second through hole 21 in the first through hole 12. The aperture of the second through hole 21 is smaller than the aperture of the first through hole 12, and the hole wall of the second through hole 21 does not contact the hole wall of the first through hole 12;

[0113] The patterned core board wiring layer 3 is located on the surface of the core board dielectric layer 2 and fills the second through hole 21;

[0114] Each substrate build-up layer 4 includes a patterned build-up dielectric layer 41 and a build-up circuit layer 43. The build-up dielectric layer 41 is provided with build-up vias penetrating through the build-up dielectric layer 41, and the build-up vias expose a part of the underlying core board circuit layer 3 or the build-up circuit layer 43; the build-up circuit layer 43 is located on the build-up dielectric layer 41 and fills the build-up vias to make effective electrical connection with the exposed core board circuit layer 3 or the build-up circuit layer 43;

[0115] The solder mask layer 5 is located in the gaps between the build-up circuit layers 43 on the surface of the substrate structure, and the surface treatment layer 6 is located on the surface of the build-up circuit layers 43 on the surface of the substrate structure.

[0116] In one embodiment, the material of the core board dielectric layer 2 and / or the build-up dielectric layer 41 is ABF (Ajinomoto Build-up Film).

[0117] In one embodiment, the material of the ceramic core board 1 is one or any combination of silicon oxycarbide ceramic, silicon nitride ceramic, alumina ceramic or aluminum nitride ceramic.

[0118] By adopting a lightweight ceramic material, the present invention can reduce the weight of the substrate structure, realize the lightweight of the product, and at the same time maintain other excellent properties of the ceramic core board 1 such as low warpage, high density and large size.

[0119] In summary, the substrate structure and its preparation method of the present invention can reduce the warpage and loss of the substrate by using a ceramic core board, and are applicable to larger-sized substrates; at the same time, by wrapping the surface of the ceramic core board with a core board dielectric layer, it is possible to avoid the ceramic being easily broken due to insufficient toughness and improve the product life; in addition, by arranging a circuit layer after wrapping the ceramic core board with a core board dielectric layer, the bonding force between the ceramic core board and the core board circuit layer is improved, and the structural stability is enhanced; finally, by preparing the ceramic core board in cooperation with 3D printing technology, the preparation efficiency of the substrate is improved.

[0120] Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0121] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a substrate structure, characterized in that: The preparation method comprises: Provide a ceramic core plate, the ceramic core plate comprising a first surface and a second surface arranged opposite to each other, and a first through hole penetrating the ceramic core plate is arranged on the first surface or the second surface of the ceramic core plate; Disposing a core plate dielectric layer on the first surface and the second surface of the ceramic core plate, wherein the core plate dielectric layer covers the first surface and the second surface and fills the first through hole; A second through hole is provided at a position between the core dielectric layer and the first through hole, the second through hole passes through the core dielectric layer, the aperture of the second through hole is smaller than the aperture of the first through hole, and the hole wall of the second through hole does not contact the hole wall of the first through hole; A patterned core board circuit layer is provided on the surface of the core board dielectric layer, and the core board circuit layer fills the second through hole; A patterned build-up dielectric layer is provided on the patterned core circuit layer, wherein the build-up dielectric layer includes a build-up through hole penetrating the build-up dielectric layer, and the build-up through hole exposes a portion of the core circuit layer; A patterned build-up circuit layer is disposed on the patterned build-up dielectric layer, and the build-up circuit layer forms an effective electrical connection with a portion of the core board circuit layer through the third through hole.

2. The method for preparing a substrate structure according to claim 1, characterized in that: The ceramic core plate including the first through hole is prepared by a 3D printing method.

3. The method for preparing a substrate structure according to claim 2, characterized in that: The 3D printing methods used include fused deposition modeling technology or light-stereolithography 3D printing technology.

4. The method for preparing a substrate structure according to claim 1, characterized in that: The method for preparing the core board circuit layer comprises: A first seed layer is covered on the surface of the core dielectric layer, wherein the first seed layer covers all exposed surfaces of the core dielectric layer; Disposing a patterned first photosensitive layer on the surface of the first seed layer; Filling the gaps between the patterned first photosensitive layers with a first conductive layer, wherein the first conductive layer also fills the second through hole; The first photosensitive layer and the first seed layer below the first photosensitive layer are removed, and the patterned first seed layer and the first conductive layer constitute the core board circuit layer.

5. The method for preparing a substrate structure according to claim 1, characterized in that: The method for preparing the build-up circuit layer comprises: Disposing a second seed layer on the patterned build-up dielectric layer, wherein the second seed layer covers the exposed surface of the build-up dielectric layer and the exposed surface of the core circuit layer; Disposing a patterned second photosensitive layer on the second seed layer; Filling the gaps between the patterned second photosensitive layers with a second conductive layer, wherein the second conductive layer also fills the third through hole; The second photosensitive layer and the second seed layer below the second photosensitive layer are removed, and the patterned second seed layer and the second conductive layer constitute the build-up circuit layer.

6. The method for preparing a substrate structure according to claim 5, characterized in that: The build-up circuit layer and the build-up dielectric layer constitute a substrate build-up layer, and multiple layers of the substrate build-up layers are provided.

7. The method for preparing a substrate structure according to claim 1, characterized in that: The gaps between the build-up circuit layers on the surface exposed by the substrate structure are filled with solder resist layers.

8. The method for preparing a substrate structure according to claim 1, characterized in that: A surface treatment layer is disposed on the surface of the build-up circuit layer exposed from the substrate structure.

9. A substrate structure, characterized in that: The substrate structure is obtained by the preparation method of the substrate structure according to any one of claims 1 to 8, and the substrate structure comprises: a ceramic core board, a core board dielectric layer, a core board circuit layer, a multi-layer substrate build-up layer, a solder resist layer, and a surface treatment layer; The ceramic core plate comprises a first surface and a second surface which are arranged opposite to each other, and a first through hole is arranged in the ceramic core plate and passes through from the first surface to the second surface; The core plate dielectric layer wraps all exposed surfaces of the ceramic core plate, and the core plate dielectric layer is provided with a second through hole penetrating the core plate dielectric layer at a position within the first through hole, the aperture of the second through hole is smaller than the aperture of the first through hole, and the hole wall of the second through hole does not contact the hole wall of the first through hole; The patterned core board circuit layer is located on the surface of the core board dielectric layer and filled in the second through hole; Each substrate build-up layer comprises a patterned build-up dielectric layer and a build-up circuit layer, wherein the build-up dielectric layer is provided with a build-up through hole penetrating the build-up dielectric layer, wherein the build-up through hole exposes a portion of the core circuit layer or the build-up circuit layer below; the build-up circuit layer is located on the build-up dielectric layer and filled in the build-up through hole, so as to be effectively electrically connected with the exposed core circuit layer or the build-up circuit layer; The solder resist layer is located in the gaps between the build-up circuit layers on the surface of the substrate structure, and the surface treatment layer is located on the surface of the build-up circuit layer on the surface of the substrate structure.

10. The substrate structure according to claim 9, characterized in that: The material of the ceramic core plate is one or any combination of silicon oxycarbide ceramics, silicon nitride ceramics, aluminum oxide ceramics or aluminum nitride ceramics.

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