Transistor component and method for producing transistor component

Abstract

The invention relates to a transistor component (100), in particular a trench-type power MISFET, having a substrate (10), preferably made of silicon carbide (SiC), silicon (Si) or gallium nitride (GaN), a source contact (1), a drain contact (2) and a trench structure (4) with a gate (3).

Description

Technical Field

[0001] The present invention relates to a transistor component, in particular a trench-type power MISFET, the source contact portion of which has a variable contact surface for optimizing the short-circuit capability. The trench-type power MISFET particularly includes at least two unit cells having different configurations of the source contact portion. The present invention also relates to a method for manufacturing a corresponding transistor component. Background Art

[0002] Power transistors such as power MISFETs (metal-insulator-semiconductor field effect transistors) are a special type of MISFET designed to handle high power in electronic circuits. For example, trench-type power MISFETs based particularly on silicon carbide (SiC) are one of the preferred solutions for electronic power switches for high-voltage applications in electric vehicles (such as inverters, chargers), etc. The trench structure can further reduce the on-resistance (RDS(on)) and improve the performance of the transistor. One of the requirements for such power MISFETs is to achieve a low on-resistance to minimize static power losses, while ensuring a low saturation current, which is necessary to reduce the energy consumption in short-circuit events.

[0003] The disadvantage of trench-type power MISFETs known in the prior art (see Figure 1 ) is that it is not possible to significantly reduce the saturation current without causing a huge loss of the specific resistance (RonA) in the on-state or without impairing other important MOSFET parameters. The saturation current is generally limited by the formed conductive channel and the JFET effect, which is generated by adjacent lateral space charge regions in the semiconductor structure, and these lateral space charge regions are formed at the transition between the lateral regions of the component.

[0004] One possible solution to reduce the saturation current is to increase the channel resistance, for example, by increasing the thickness of the channel structure insulator, or by increasing the doping level or thickness of the body region under the source region, or a combination of both. However, this will have an adverse effect on the specific resistance (RonA) in the on-state or cause other important MOSFET parameters to be impaired, such as raising the threshold voltage beyond the available range.

[0005] Another possible solution to reduce the saturation current is to increase the JFET effect such that the additional voltage drop in this region limits the increase in the channel voltage, thereby reducing the saturation current. This can be achieved by increasing the width of the lateral regions in the component, or by reducing the doping level of the region between the lateral regions, or by a combination of both. However, this will also cause an increase in the resistance of the region between the lateral regions, resulting in an undesirable increase in the specific resistance (RonA).

[0006] The object of the present invention is to solve the above-mentioned drawbacks and to provide an improved transistor component. Summary of the Invention

[0007] The present invention relates to a transistor component, in particular a trench-type power MISFET, which comprises a substrate, a source contact, a drain contact and a trench structure. The substrate is preferably made of silicon carbide (SiC), silicon (Si) or gallium nitride (GaN). The trench structure has a gate. The transistor component comprises a parallel circuit consisting of at least two unit cells, wherein the contact surface of the source contact with the continuous source region arranged thereunder for the second unit cell is constructed smaller compared to the case of the first unit cell.

[0008] The construction of the transistor component according to the invention has the following advantages: By the variable structuring of the source contact, in particular the local reduction of the metal contact surface in one of the adjacent unit cells, the series resistance of the region connected to the source contact (in particular the n+ source region) is increased, thereby reducing the saturation current, which reduces the adverse effect on the overall RdsOn. In particular, the effective voltage (VGS) between the gate and the source is reduced, resulting in a reduction of the saturation current.

[0009] In a preferred embodiment, in a top view, the contact surface of the source contact has a profile that varies above the source regions of the two unit cells. In this case, in a top view, the contact surface of the source contact can be at least partially constructed in a rectangular profile, a polygonal profile and / or a circular profile. In the prior art, the corresponding contact surface is usually constructed as a contact strip with a constant width, which extends substantially perpendicular to the plurality of unit cells arranged parallel to each other with respect to the semiconductor component. In contrast, the source contact has a contact surface with such a profile that a contact surface varying for the unit cell in contact is formed between the source metallization and the source region arranged thereunder.

[0010] In a preferred embodiment, the contact surface of the source contact has at least one contact surface reduction in the form of a local recess, which is constructed in at least one of the two unit cells. The contact surface reduction exists in the continuously applied metallization of the source contact in the form of a rectangular cutout, a polygonal cutout and / or a circular cutout. In a top view of the semiconductor component, the contact surface of the source contact can have two recesses, which are arranged directly opposite each other on both sides of the trench structure or at least partially offset relative to each other.

[0011] In a preferred embodiment, the source contact portion contacts only the source region of one unit cell, particularly the first unit cell, among the two unit cells, which is located below the source contact portion. Preferably, for the source region of one unit cell, particularly the second unit cell, among the two unit cells, there is no contact surface of the source contact portion disposed above the source region. In this case, no current flows in the surface direction through the source region of the second unit cell that is not connected to the source contact portion of the transistor member and reaches the source contact portion.

[0012] In a preferred embodiment, in a top view of the unit cell, the area of the contact surface between the source contact portion of the unit cell and the source region located below it is equal to or less than the area of the adjacent recess in the source contact portion.

[0013] Preferably, the two unit cells of the transistor member have the same structural configuration in other aspects except for the source contact portions with different configurations from each other.

[0014] In a preferred embodiment, the corresponding unit cell of the transistor member includes a highly doped n+ substrate, on which an n-doped drift region is disposed, and optionally a buffer region is disposed between them. Preferably, the buffer region has a higher n-doping degree than the drift region.

[0015] Preferably, the corresponding unit cell of the transistor member includes a trench structure or a trench, and the trench structure or the trench is filled with a thin dielectric layer. This may particularly include silicon oxide, hafnium oxide, alumina-nitride, or a combination of multiple insulating materials with different dielectric constants, or formed on silicon oxide, hafnium oxide, alumina-nitride, or a combination of multiple insulating materials with different dielectric constants. The dielectric layer may have different thicknesses at the bottom wall and side walls of the trench structure. The trench structure is filled with a highly conductive material, preferably n+-doped polysilicon, and forms a gate or a gate electrode connected to the metal gate contact portion.

[0016] Preferably, the corresponding unit cell of the transistor member includes laterally arranged deep p+-doped regions, which extend laterally from the top of the semiconductor structure and extend deeper into the drift region than the trench structure. Preferably, an n-doped intermediate region is disposed between the laterally p+-doped regions, and the n-doping degree of the intermediate region is higher than that of the drift region, so that the specific resistance of the member in the on state can be reduced.

[0017] Preferably, the corresponding unit cell of the transistor member includes a p-doped body region or layer and a source region disposed thereon. The body region or layer is located between the trench structure and the laterally deep p+-doped region, and the source region is connected to the source contact portion. The source contact portion forms a low-resistance contact with the source region and with the laterally deep p+-doped region.

[0018] In a preferred embodiment, the source region of the first unit cell is configured as an n+ doped region, and the body region or layer located thereunder is configured as a p+ doped region. Further preferably, the source region of the second unit cell is configured as an n+ doped region, and the body region or layer located thereunder is also configured as a p doped region.

[0019] Preferably, the source contact is configured as a continuous metallization that completely or partially contacts the lateral deep p+ doped regions and the source regions of the two unit cells.

[0020] The transistor component according to the present invention can be an n-channel MISFET as described above, or a p-channel MISFET. In the latter case, the corresponding n and p dopings are interchanged, and the sign of the voltage changes from positive to negative. For the device according to the present invention, this should be considered equally disclosed and claimed.

[0021] Preferably, the transistor component according to the present invention is suitable for a variety of power electronics applications, particularly for applications in industrial drives, regenerative power generation, automotive applications, train drives, and high-voltage rectifiers.

[0022] On the other hand, the present invention relates to a method for manufacturing the above-described transistor component, the method including a plurality of method steps for forming (in particular depositing) a layer sequence on a substrate. Regarding layer growth, layer structuring, and the possible effects and processing of the formed layers (in particular the grown layers), methods and techniques that are basically known in semiconductor technology can be used.

[0023] According to the present invention, the method includes the following steps: The source contact is constructed differently for two adjacent unit cells of the transistor component such that, compared to the case of the first unit cell, the contact surface of the source contact with the continuous source region arranged thereunder for the second unit cell is constructed to be smaller.

[0024] Preferably, the method includes a photolithography step using a structured mask, wherein the contact metallization serving as the source contact for the first unit cell is constructed differently from the adjacent second unit cell.

[0025] To avoid repetition, regarding other features of the method according to the present invention, reference should be made to the previously described features of the semiconductor component according to the present invention, which should be considered equally disclosed and claimed for the method according to the present invention, and vice versa.

[0026] Other advantages, features, and details of the present invention will be derived from the following description of the preferred embodiments of the present invention and from the drawings. Description of the Drawings

[0027] Figure 1Shows a cross-sectional view of a unit cell of a trench-type power MISFET according to the prior art;

[0028] Figure 2a Shows a top view of a trench-type power MISFET according to a first embodiment of the present invention;

[0029] Figure 2b Shows according to Figure 2a A side cross-sectional view of a first unit cell of the semiconductor component along section A;

[0030] Figure 2c Shows according to Figure 2a A side cross-sectional view of a second unit cell of the semiconductor component along section A';

[0031] Figure 3 a-d show schematic diagrams of manufacturing steps of a semiconductor component according to the present invention;

[0032] Figure 4 a-c show top views of trench-type power MISFETs according to further embodiments of the present invention. Detailed Description

[0033] The same elements or elements having the same functions in the drawings are provided with the same reference numerals.

[0034] Figure 1 Shows the structure of a semiconductor component known from the prior art, which forms a trench-type power MISFET 100'. For simplicity, only one unit cell is shown in the figure. The specific structure of the edge ends is not shown and can be implemented in different known ways.

[0035] The trench-type power MISFET 100' includes a highly doped n+ substrate 10, on which an n-doped drift region 12 is arranged. Optionally, a buffer region 11 is arranged between the substrate 10 and the drift region 12. In addition, the component further includes a known trench structure 4, which has a thin dielectric layer 5 and is filled with a highly conductive material 3 (usually n+ doped polysilicon). This forms a gate, which is connected to a metal gate contact (not shown) and is electrically isolated from the source metallization 1 by an insulating layer (not shown).

[0036] The trench-type power MISFET 100' further includes a laterally arranged deep p+ doped region 8, which extends deeper from the top of the semiconductor structure than the trench 4 and extends into the drift region 12. Preferably, n doped regions 9 are arranged between the p+ doped regions 8, and the n doping degree of the n doped regions is higher than the n doping degree in the drift region 12. The doping degree in the region 9 can be constant or different. Alternatively, the region 9 can also extend below the region 8. In addition, a p doped body region 6 and an n+ doped source region 7 located thereon are included, and they are arranged on both sides of the trench 4. The source contact or source metallization 1 forms a low-resistance contact with the source region 7 and with the p+ doped region 8. The body region 6 is indirectly connected to the source contact 1 via the lateral p+ doped region 8. The substrate 10 is connected to the drain contact 2, and the drain contact 2 forms a low-resistance contact with the n+ substrate 10.

[0037] Once a sufficiently high voltage is applied (e.g., 15 - 18V, i.e., higher than the threshold voltage which is usually 2 - 5V), an electron inversion layer or a conductive channel is formed at the interface between the p doped body region 6 and the gate dielectric 5 in the p doped body region 6. Thereby, a conductive path is generated between the n+ source region 7 and the drain, which is composed of the n doped regions 9, 12, 11, the n+ doped substrate 10, and the drain contact 2. When the drain potential is higher than the source potential, current starts to flow from the drain contact 2 through the regions 10, 11, 12, 9, the electric channel, and the source region 7 to the source contact 1.

[0038] When a positive voltage is applied between the drain contact 2 and the source contact 1 while short-circuiting the gate 3 electrode and the source 1 electrode, or alternatively, when the gate 3 has a negative voltage of several volts relative to the source in the cut-off state, a space charge region is formed at the PN junction between the p doped region 8 and the n doped region 9 and at the structures 3, 5, 9. As the drain potential increases, the space charge region extends downward to the regions 9 and the drift region 12 until finally reaching the n doped buffer region 11. The n doped buffer region 11 is designed to prevent the space charge region from penetrating the substrate 10. In the cut-off mode, the peak electric field is located at the bottom of the p+ doped region 8, which shields the trench 4, so as to ensure a low electric field strength in the gate dielectric 5 (usually lower than 3MV / cm for component reliability reasons). In the short-circuit case, a high forward voltage is generated between the drain and the source, and the electric channel is fully conductive, where the gate-source potential is higher than the threshold voltage (usually 2 - 5V, typically 15 - 18V), resulting in a very high saturation current flowing through the structure. Generally, the current is limited by the channel, but it also depends to a large extent on the distance between adjacent p doped regions 8, which means that as the voltage between the source and the drain increases, due to the JFET effect, a lateral space charge region is formed at the transition between the p doped region 8 and the n doped region 9.

[0039] Figures 2a to 2cShows a first preferred embodiment of a transistor component 100 according to the present invention, the transistor component comprising at least two adjacent unit cells 100a, 100b (see Figure 2b , 2c ). As Figure 2a shown, at least two unit cells 100a, 100b are configured as a parallel circuit. The transistor component may further comprise a plurality of unit cells 100a, 100b, wherein the unit cells 100a, 100b are preferably arranged alternately. The basic structure of two unit cells 100a, 100b corresponds to Figure 1 the known structure shown.

[0040] According to the present invention, the contact metal part 1 of the source electrode is structured such that, compared with the prior art shown in Figure 1 , it does not form a continuous contact band on the n+ region 7 in a top view, and in particular does not form a continuous contact band on the continuous source electrode regions 7 of at least two adjacent unit cells. This results in the current in the component region or source electrode region flowing laterally through the n+ region 7 to the contact metal part 1 with a reduced contact metal part 1 in terms of the contact surface, especially without a contact metal part 1 above, thereby increasing the source series resistance of the component.

[0041] The increase in the source electrode region voltage drop results in a decrease in the effective voltage VGS eff (VGS eff = VGS - V th ), thereby resulting in a decrease in the saturation current. Since the saturation current has a square relationship with VGS eff (ISC ∼ VGSeff 2 , see B. Jayant Baliga "Silicon Carbide Power Devices", World Scientific Publishing Co., 2005), the saturation current decreases significantly. Since the channel component of Rdson is only inversely proportional to VGS eff (Rdson,ch ∼ 1 / VGSeff, see B. Jayant Baliga "Silicon Carbide Power Devices", World Scientific Publishing Co., 2005), the damage to RonA is significantly reduced.

[0042] As Figure 2a shown, the source electrode contact parts 1 or source electrode metallization layers of at least two adjacent unit cells 100a, 100b are structured differently from each other such that at least in the second unit cell 100b, the contact surface 13 of the source electrode contact part 1 has a recess 14 in which the source electrode metallization layer 1 is removed.

[0043] Figure 2b The working principle of the semiconductor structure of the unit cell in Figure 1The structures are the same. In this regard, refer to the descriptions and working methods in the above text. However, when the gate voltage is higher than the threshold voltage, Figure 2c the current in the structure cannot flow directly vertically to the upper source metallization, but must flow through a longer distance to the source contact of the adjacent unit cell 100a.

[0044] Figure 3 a to Figure 3 d schematically show simplified method flows for implementing the structures in the unit cells 100a, 100b according to Figure 2b , c, with the focus on the implementation of the source contact 1.

[0045] As Figure 3 shown in a, in the first step, different layers or regions are first formed or deposited on the substrate such that the structural configuration 101 shown in Figure 3 a is achieved. Regarding layer growth, layer structuring, and the possible impacts and processing of the formed layers (especially the grown layers), methods and techniques known in principle can be used. The regions 8, 6, 9, 3, 7 in the upper region of the structure 101 have been structured in accordance with the subsequent component structure. The surface of the semiconductor component is also structured with an insulating layer 16.

[0046] Figure 3 b and Figure 3 c show a top view of the semiconductor component 101 and cross-sectional views of two unit cells 100a, 100b. As Figure 3 b and Figure 3 c show, the method then includes a lithography step of structuring the contact surface with a structuring mask 102, in which the insulating layer 16 of the unit cells 100a, 100b is selectively removed. Then, as Figure 3 shown in d, a contact metallization layer 15 is applied to form the source contact 1 of the structure, where the source contacts of the two unit cells 100a, 100b are structured differently.

[0047] Figure 4 a-c show additional preferred embodiments in a top view similar to Figure 2a , where the source contact 1 is structured differently.

[0048] Figure 4 a shows an embodiment in which the contact surface 13 of the source contact 1 with the underlying contacted n+ source region 7 is significantly smaller than the non-contacted source region 7 within the recess 14 area. Here, the lower limit of the contacted n+ region can be given by electromigration limitation or the maximum allowable increase in Rdson.

[0049] Figure 4b and 4c show further preferred embodiments of the source contact 1. Here, the source contact 1 can have a recess 14 that tapers or widens in the longitudinal direction L of the component, perpendicular to the trench extension direction. In addition, the source contact 1 can include only dot-shaped (punktuell) arranged contact surfaces 13 that contact the source region 7 located below them. Preferably, these regions are arranged only in the first unit cell of the two unit cells 100a, 100b. It is also possible to use a pattern different from the Figure 4 arrangement shown or a combination thereof.

[0050] As Figure 2a and Figure 4 shown, the source contact 1 can be arranged on one side of the trench structure 4 opposite to the source contact 1 on the opposite side of the trench structure 4. It is also possible that the source contacts arranged correspondingly on both sides of the trench structure 4 are not completely opposite to each other, but are arranged offset from each other.

[0051] The invention is not limited to the n-channel MISFET described in the embodiments, but can also be applied to p-channel MISFETs. In this case, the corresponding n and p doping are interchanged, and the sign of the voltage changes from positive to negative. In addition, the invention is not limited to semiconductor components based on silicon carbide, but can equally well be applied to other semiconductor materials, especially silicon or gallium nitride.

Claims

1. A transistor component (100), in particular a trench power MISFET, comprising a substrate (10), a source contact (1), a drain contact (2) and a trench structure (4), wherein the substrate is preferably made of silicon carbide (SiC), silicon (Si) or gallium nitride (GaN), and the trench structure has a gate (3). It is characterized in that The transistor component comprises a parallel circuit consisting of at least two unit cells (100a, 100b), wherein a contact surface (13) of a source contact (1) with a continuous source region (7) arranged thereunder for a second unit cell (100b) is smaller than for a first unit cell (100a).

2. The transistor component according to claim 1, characterized in that In a top view, the contact surface (13) of the source contact (1) has a contour that varies over the source regions (7) of the two unit cells (100a, 100b).

3. The transistor component according to claim 1 or 2, characterized in that: In a plan view, the contact surface (13) of the source contact (1) is at least partially configured as a rectangular contour, a polygonal contour and / or a circular contour.

4. A transistor component according to any one of the preceding claims, characterized in that The contact surface (13) of the source contact (1) has at least one local recess (14) in the form of a contact surface reduction, which is formed in at least one of the two unit cells (100a, 100b).

5. The transistor component according to claim 4, characterized in that The contact surface (13) of the source contact (1) has two recesses (14), which are arranged directly opposite each other on both sides of the trench structure (4) or are at least partially offset relative to each other.

6. The transistor component (100) according to any one of the preceding claims, characterized in that The source contact (1) contacts only a source region (7) of one of the two unit cells (100a, 100b), in particular the first unit cell (100a), which is located below the source contact.

7. A transistor component according to any one of the preceding claims, characterized in that For the source region (7) of one of the two unit cells, in particular the second unit cell (100b), there is no contact surface (13) of the source contact (1) arranged above the source region.

8. A transistor component according to any one of the preceding claims, characterized in that The two unit cells (100a, 100b) of the transistor component (100) have the same structural configuration except for the different configurations of the source contacts (1).

9. A transistor component according to any one of the preceding claims, characterized in that In a top view of the unit cell (100a, 100b), an area of ​​a contact surface (13) between the source contact portion (1) and a source region (7) of the unit cell (100a, 100b) located below the source contact portion is equal to or smaller than an area of ​​an adjacent recess (14) in the source contact portion (1).

10. A method for producing a transistor component (100) according to any one of claims 1 to 8, comprising a plurality of method steps for forming, in particular depositing, a layer sequence on a substrate (10), It is characterized in that The source contacts (1) are designed differently for two adjacent unit cells (100a, 100b) of the transistor component (100) such that the contact surface (13) of the source contact (1) to the continuous source region (7) arranged thereunder for the second unit cell (100b) is smaller than for the first unit cell (100a).

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