Anti-winding-plating and anti-pollution film coating carrier plate structure, film coating method and battery piece

Abstract

The invention relates to an anti-winding plating and anti-pollution film coating support plate structure, which is arranged in a hot filament chemical vapor deposition process cavity, and comprises a conveying support plate on which a silicon wafer is mounted; the spacing plate is positioned between the hot wire and the conveying carrier plate, one side of the spacing plate faces the hot wire, and the other side of the spacing plate faces the side, bearing the silicon wafers, of the conveying carrier plate; a first interval is arranged between the spacing plate and the conveying carrier plate, and a second interval is arranged between the spacing plate and the hot wire. In addition, the invention further relates to a film coating method adopting the carrier plate structure for film coating and a battery piece coated with the film coating method. According to the invention, the problems of winding plating and pollution can be avoided during film deposition, and the high-quality doped crystalline silicon layer without winding plating and pollution can be directly prepared.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and more specifically, to a coating carrier structure that prevents winding plating and pollution, a coating method using the coating carrier structure, and a solar cell coated by the coating method. Background Art

[0002] With the increasing depletion of fossil energy, solar cells have been developed in the long run due to their clean and renewable advantages. Among many photovoltaic cells, such as TOPCon (tunneling oxide passivation contact) cells, HJT (heterojunction) cells and XBC (cross-finger back contact) cells, vacuum coating technology is a key process for preparing solar cells. The quality of doped crystalline silicon thin films is directly related to the excellent electrical properties such as cell efficiency. At present, the main coating technologies in the industry are LPCVD (low pressure chemical vapor deposition) and PECVD (plasma enhanced chemical vapor deposition), but the films deposited by both technologies have different degrees of wrapping on the front, back and sides of the cell. The biggest impact of wrapping on the cell is that the wrapping area will accumulate defects, making it a recombination center for carrier transmission, which ultimately causes leakage current, a decrease in cell resistance, and attenuation of component performance. Therefore, in the doped crystalline silicon coating process, it is extremely important to prepare cells without wrapping for the electrical performance of the cell.

[0003] In addition, the generation of plating around is mainly due to the average molecular free path and diffusion rate of the reaction gas in the vacuum cavity. The smaller the average molecular free path, the greater the probability of gas collision. The higher the temperature, the faster the gas diffusion rate. The superposition of the two causes plating around. For example, when LPCVD is used to prepare doped crystalline silicon thin films, the reaction temperature reaches above 600°C, the gas pressure is 13-26Pa, the average molecular free path of the reaction gas silane is only about 0.1cm, and the diffusion rate is 25m / s at high temperature, which will cause plating around. Therefore, acid-base etching process is usually added after coating to remove the plating around area. In TOPCon cells, 1GW etching process accounts for about 7% (12 million) of the entire line investment, and the etching process is difficult. On the one hand, it cannot completely remove the plating around. On the other hand, it is affected by multiple etching factors, such as acid-base concentration, etching time and etching liquid circulation, and it is difficult to accurately control.

[0004] PECVD coating uses low-temperature plasma to generate glow discharge on the cathode of the process chamber, so that the sample is heated to a predetermined temperature, and then an appropriate amount of process gas is introduced. After a series of chemical reactions and plasma reactions, a solid film is formed on the sample surface; the reaction gas enters the furnace chamber from the air inlet and gradually diffuses to the sample surface. Under the action of the electric field excited by the RF source, the reaction gas decomposes into electrons, ions and active groups. The silicon source flow rate in PECVD reaches 1000sccm (standard milliliters / minute), H 2It can reach more than 10,000 sccm. The carrier filled with silicon wafers is made of graphite. A large amount of diffused gas will inevitably produce wrap-around plating on the sides and back of the cell under the action of the electric field.

[0005] Therefore, it is urgent to design a structure and method that can prevent plating bypass and pollution in the doped crystalline silicon coating process. Summary of the invention

[0006] In view of the deficiencies of the prior art, the purpose of the present invention is to provide a coating carrier structure and coating method that are anti-circuiting and anti-pollution. In the present invention, HWCVD (hot wire chemical vapor deposition) is used to prepare the doped crystalline silicon layer, the film layer has no ion damage, the average free path of the active group is about 10cm, which is almost equal to the distance from the hot wire to the silicon wafer / carrier, no collision reaction occurs between the gas groups, and the movement of the groups in space is not disturbed; and the cavity pressure is controlled as low as 1-10Pa, and the total amount of gas is reduced to within 3000sccm. At the same time, with the unique carrier structure design, a high-quality doped crystalline silicon layer without circuiting and pollution can be directly prepared.

[0007] In order to solve the above technical problems or achieve the above objectives, the present invention adopts the following technical solutions:

[0008] According to one aspect of the present invention, there is provided a coating carrier structure for preventing winding plating and pollution, the carrier structure being arranged in a process chamber of hot wire chemical vapor deposition, comprising:

[0009] A conveying carrier having a silicon wafer mounted thereon;

[0010] A spacer plate is positioned between the hot wire and the conveyor carrier, with one side of the spacer plate facing the hot wire and the other side of the spacer plate facing the side of the conveyor carrier carrying the silicon wafer;

[0011] Therein, a first distance is set between the partition plate and the conveying carrier plate, and a second distance is set between the partition plate and the hot wire.

[0012] In one embodiment of the present invention, the silicon wafer is placed and mounted on a conveyor carrier by a mechanical gripper.

[0013] In one embodiment of the present invention, the silicon wafer includes a plurality of silicon wafers uniformly distributed on a conveying carrier.

[0014] In one embodiment of the present invention, 0 cm < first spacing ≤ 20 cm, 5 cm ≤ second spacing ≤ 20 cm.

[0015] In one embodiment of the present invention, the dimension of the spacer plate is larger than the dimension of the transport carrier plate.

[0016] In one embodiment of the present invention, the second interval is greater than the first interval.

[0017] According to another aspect of the present invention, a coating method for preventing winding and pollution is provided. The coating method adopts the coating carrier structure for preventing winding and pollution as described above. The coating method comprises the following steps:

[0018] Fixing the spacer plate in a process chamber of hot wire chemical vapor deposition with one side of the spacer plate facing the hot wire;

[0019] The silicon wafer is placed and mounted on a conveyor carrier by a mechanical gripper;

[0020] The conveyor carrier with the silicon wafer mounted thereon is sent into a hot wire chemical vapor deposition process chamber so that the side of the conveyor carrier carrying the silicon wafer faces the other side of the spacer plate;

[0021] Controlling a first distance between the spacer plate and the conveying carrier plate and controlling a second distance between the spacer plate and the hot wire;

[0022] When the conveying carrier plate and the spacer plate are aligned, the coating process begins.

[0023] In one embodiment of the present invention, during film deposition, the pressure of the process chamber of the hot wire chemical vapor deposition is controlled at 1-10Pa.

[0024] In one embodiment of the present invention, the coating process adopts an I-IN-P coating process or an IN-IP coating process.

[0025] According to another aspect of the present invention, there is provided a battery cell, which is plated using the anti-wrap plating and anti-pollution plating method as described above.

[0026] The technical solution provided by the present invention has the following advantages compared with the prior art:

[0027] The present invention can improve the plating area of ​​doped crystalline silicon deposited by HWCVD vacuum coating, and can weaken it to be negligible, thereby avoiding battery leakage current; the present invention solves the problem of carrier contamination during IN continuous plating, and achieves a stable IN continuous plating process; the present invention can extend the service life of the carrier; the carrier structure of the present invention can be adapted to I-IN-P and IN-IP designs, reduce the number of silicon wafer flips, and save coating time. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings required for use in the description of the embodiments or the prior art are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 A schematic diagram of a coating carrier structure for preventing winding plating and pollution provided by an embodiment of the present invention is shown;

[0031] Figure 2 It is shown in Figure 1 Schematic diagram of the structure of the conveying carrier plate, spacer plate and hot wire distribution;

[0032] Figure 3 Shows the use of Figure 1 A schematic flow chart of a coating method for a carrier structure for anti-wrap and anti-pollution coating.

[0033] Among them, 1, conveying carrier; 2, silicon wafer; 3, spacer; 4, hot wire; D, first spacing; d, second spacing. DETAILED DESCRIPTION

[0034] In order to more clearly understand the above-mentioned purposes, features and advantages of the present disclosure, the embodiments of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0035] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0036] like Figure 1-2 As shown, an embodiment of the present invention provides a carrier structure for coating that prevents winding and pollution, and the carrier structure is arranged in a process chamber of hot wire chemical vapor deposition (HWCVD), and includes a conveying carrier 1, a silicon wafer 2, and a spacer 3. The conveying carrier 1 is mounted with a silicon wafer 2, and the spacer 3 is positioned between the hot wire 4 and the conveying carrier 1, with one side of the spacer 3 facing the hot wire 4 and the other side facing the side of the conveying carrier 1 carrying the silicon wafer 2. A first spacing D is set between the spacer 3 and the conveying carrier 1, and a second spacing d is set between the spacer 3 and the hot wire 4.

[0037] In the above-mentioned coating carrier structure of the present invention, preferably, the silicon wafer 2 is placed and mounted on the conveying carrier 1 by a mechanical gripper. Preferably, the silicon wafer 2 includes a plurality of silicon wafers 2 uniformly distributed on the conveying carrier 1, such as Figure 1As shown, nine silicon wafers 2 are evenly distributed and mounted or carried on the conveying carrier 1 .

[0038] In the above-mentioned film-plating carrier structure of the present invention, if Figure 2 As shown, preferably, 0cm<D≤20cm, 5cm≤d≤20cm, more preferably, the second distance d is greater than the first distance D. Of course, in other optional embodiments, the second distance d may be equal to the first distance D, or the second distance d may be less than the first distance D.

[0039] In the above-mentioned film-plating carrier structure of the present invention, if Figure 1-2 As shown, the size of the spacer 3 is larger than the size of the conveying carrier 1, that is, the length, width and area of ​​the spacer 3 are larger than the conveying carrier 1. Of course, in an alternative embodiment, the size of the spacer 3 can be exactly the same as the size of the conveying carrier 1.

[0040] like Figure 3 As shown, in the embodiment of the present invention, there is also provided a method using the above Figure 1-2 The coating method of the carrier structure for coating with anti-wrap plating and anti-pollution shown in the figure comprises the following steps:

[0041] S1: Fixing the spacer plate 3 in a process chamber of hot wire chemical vapor deposition (HWCVD) with one side of the spacer plate 3 facing the hot wire 4;

[0042] S2: placing and mounting the silicon wafer 2 on the conveying carrier 1 by means of a mechanical gripper;

[0043] S3: sending the carrier plate 1 with the silicon wafer 2 mounted thereon into a process chamber of a hot wire chemical vapor deposition HWCVD process and making the side of the carrier plate 1 carrying the silicon wafer 2 face the other side of the spacer plate 3;

[0044] S4: controlling a first distance D between the spacer plate 3 and the conveying carrier plate 1 and controlling a second distance d between the spacer plate 3 and the hot wire 4;

[0045] S5: When the positions of the conveying carrier plate 1 and the spacer plate 3 coincide with each other, the coating process is started.

[0046] In the above-mentioned coating method of the present invention, preferably, during coating, the pressure of the HWCVD process chamber is controlled at 1-10 Pa, so that the total amount of gas in the process chamber can be reduced to within 3000 sccm.

[0047] In the above-mentioned coating method of the present invention, the coating process can adopt an I-IN-P coating process or an IN-IP coating process. Among them, the I-IN-P coating process: coating an intrinsic layer, that is, the I layer, coating the back I layer after flipping the film, and then coating the N-type semiconductor layer, and then flipping the film to coat the P-type semiconductor layer. The IN-IP coating process: first coating the intrinsic layer, that is, the I layer, and then coating the N-type semiconductor layer, and then coating the I layer and the P-type semiconductor layer after flipping the film.

[0048] In addition, an embodiment of the present invention further provides a battery cell, which is plated using the anti-wrap plating and anti-pollution plating method as described above.

[0049] In the above-mentioned embodiment of the present invention, the carrier structure is mainly designed for coating in the HWCVD process chamber. Figure 1-2 As shown, the silicon wafer 2 is transported by a mechanical gripper and mounted on a transport carrier 1, and then enters the HWCVD process chamber as a whole. The spacer 3 is fixed inside the HWCVD process chamber. The distribution of the transport carrier 1, the spacer 3 and the hot wire 4 is shown in FIG. Figure 2 As shown, the first distance D between the spacer plate 3 and the conveying carrier plate 1 is controlled, and the second distance d between the spacer plate 3 and the hot wire 4 is controlled. When the conveying carrier plate 1 is conveyed to coincide with the spacer plate 3, the coating process begins.

[0050] Refer again Figure 2 , the range of the second spacing d between the conveying carrier 1 and the hot wire 4 is controlled to be 5cm≤d≤20cm, for example, d can be preferably 10cm. The range of the first spacing D between the spacer plate 3 and the conveying carrier 1 is controlled to be 0cm<D≤20cm, for example, D can be preferably 5cm. The carrier structure designed with this structure is used for coating in the HWCVD process chamber. The reaction gas in the process chamber can be uniformly deposited in the silicon wafer 2 area after high-temperature cracking by the hot wire 4, reducing the non-directionality of gas deposition film formation and effectively improving the phenomenon of film coating around the back. On the contrary, if there is no isolation of the spacer 3, the doping gas will be directly deposited on the uncovered areas of the silicon wafer 2 and the conveyor carrier 1 after decomposition. In the I-IN-P coating process or the IN-IP coating process, the IN continuous plating (plating the I layer, followed by plating the N-type semiconductor layer) will release the deposited phosphorus and oxygen atoms, which is not conducive to the preparation of the intrinsic silicon film layer, thereby causing IN mismatch and affecting the battery efficiency. The designed spacer 3 can protect the conveyor carrier 1 from being plated with the doped film over a large area, thereby further avoiding the occurrence of bypass plating during coating and avoiding contamination during IN continuous plating.

[0051] It can be seen that, on the one hand, the structure and method of the present invention can improve the plating area of ​​doped crystalline silicon deposited by HWCVD vacuum coating, which can be weakened to negligible, avoiding battery leakage current, that is, preventing plating from plating during coating; on the other hand, the present invention can solve the problem of contamination of the carrier during IN continuous plating, and achieve the stability of the IN continuous plating process, that is, preventing pollution during IN continuous plating. Therefore, by adopting the above structure and method of the present invention, plating and pollution problems can be avoided when depositing thin films, and there is no plating and pollution in the battery cell prepared thereby, and the electrical performance of the battery cell is not affected, and the performance is excellent.

[0052] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusions, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to the process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including a..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0053] The above is only an embodiment of the present application, and the embodiment enables those skilled in the art to understand and implement the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and features disclosed herein.

Claims

1. A coating carrier structure for preventing winding plating and pollution, characterized in that: The carrier structure is arranged in a process chamber of hot wire chemical vapor deposition, and comprises: A conveying carrier, on which a silicon wafer is mounted; A spacer plate, the spacer plate is positioned between the hot wire and the conveying carrier, one side of the spacer plate faces the hot wire, and the other side faces the side of the conveying carrier that carries the silicon wafer; Therein, a first distance is set between the spacer plate and the conveying carrier plate, and a second distance is set between the spacer plate and the hot wire.

2. The anti-circular plating and anti-pollution coating carrier structure according to claim 1, characterized in that: The silicon wafer is placed and mounted on the conveying carrier by a mechanical gripper.

3. The anti-circular plating and anti-pollution coating carrier structure according to claim 1, characterized in that: The silicon wafers include a plurality of silicon wafers uniformly distributed on the conveying carrier.

4. The anti-circular plating and anti-pollution coating carrier structure according to claim 1, characterized in that: 0cm<the first spacing≤20cm, 5cm≤the second spacing≤20cm.

5. The anti-circular plating and anti-pollution coating carrier structure according to claim 1, characterized in that: The size of the spacer plate is larger than the size of the conveying carrier plate.

6. The anti-circular plating and anti-pollution coating carrier structure according to claim 1, characterized in that: The second interval is greater than the first interval.

7. A coating method for preventing circumferential plating and pollution, characterized in that: The coating method adopts the anti-wrap-around and anti-pollution coating carrier structure as described in any one of claims 1 to 6, and the coating method comprises the following steps: Fixing the spacer plate in a process chamber of hot wire chemical vapor deposition and making one side of the spacer plate face the hot wire; The silicon wafer is placed and mounted on a conveyor carrier by a mechanical gripper; The conveyor carrier with the silicon wafer mounted thereon is sent into a process chamber of the hot wire chemical vapor deposition process so that the side of the conveyor carrier carrying the silicon wafer faces the other side of the spacer plate; Controlling a first distance between the spacer plate and the conveying carrier plate and controlling a second distance between the spacer plate and the hot wire; When the positions of the conveying carrier plate and the spacer plate coincide, the coating process begins.

8. The anti-circular plating and anti-pollution coating method according to claim 7, characterized in that: During coating, the pressure of the hot wire chemical vapor deposition process chamber is controlled at 1-10Pa.

9. The anti-circular plating and anti-pollution coating method according to claim 7, characterized in that: The coating process adopts an I-IN-P coating process or an IN-IP coating process.

10. A battery cell, characterized in that: The battery cell is plated using the anti-wrap-around and anti-pollution coating method as described in any one of claims 7 to 9.

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