Chip heat balance management method and system and chip

Abstract

The embodiment of the invention discloses a chip heat balance management method and system and a chip, and relates to the technical field of semiconductors. The method comprises the following steps: monitoring the temperature of a plurality of areas in a chip; judging whether the temperature of a region exceeds a preset temperature threshold value or not; if yes, the load or power of the area exceeding the preset temperature threshold value is adjusted. By monitoring the temperature of a plurality of areas in the chip, the load or power of the area in the chip is dynamically adjusted for the area with the overhigh local temperature in the chip to reduce the heat generated by the local area on the basis of the local temperature, so that the problem of local overheating of the chip is solved, the performance of the chip can be exerted to the maximum extent, and the reliability of the chip is improved. The heat management efficiency is improved, and the relationship between the chip performance and heat dissipation is effectively balanced, so that the heat management effect of the chip is convenient to optimize, and the risk of local aging in the chip is reduced. The invention is suitable for various types of chips.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a chip thermal balance management method, system and chip. Background Art

[0002] With the continuous development of integrated circuit technology, three-dimensional integrated circuits (3D-IC) are widely used in high-performance processors, memories and other complex systems due to their high device integration and small footprint. However, due to the multi-layer chip stacking, heat is easily accumulated and difficult to dissipate effectively, causing overheating problems.

[0003] In some traditional thermal management solutions, multiple temperature measurement points are generally set up inside the chip, relying on a global temperature control strategy. When the temperature of a certain part is too high, the entire system often takes global frequency reduction or shutdown measures, which fails to effectively balance the relationship between chip performance and heat dissipation. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a chip thermal balance management method, system and chip, which are convenient for optimizing the chip thermal management effect.

[0005] In a first aspect, an embodiment of the present invention provides a chip thermal balance management method, the method comprising: monitoring the temperatures of multiple regions in a chip; determining whether the temperature of any region exceeds a preset temperature threshold; if so, adjusting the load or power of the region exceeding the preset temperature threshold.

[0006] According to a specific implementation of an embodiment of the present application, after adjusting the load or power of the area exceeding the preset temperature threshold, the method further includes: dynamically adjusting and controlling the load or power of at least part of the area to balance the overall temperature of the chip.

[0007] According to a specific implementation method of an embodiment of the present application, the dynamic adjustment and control of the load or power of at least part of the area includes: based on the received load or power adjustment information of the area exceeding the preset temperature threshold, and the temperature information of other areas, at least part of the load of the area exceeding the preset temperature threshold is distributed to the area with lower temperature in other areas.

[0008] According to a specific implementation method of the embodiment of the present application, monitoring the temperatures of multiple areas in the chip includes: monitoring the temperatures of multiple processor cores inside the chip; wherein at least one processor core is correspondingly arranged for each area.

[0009] In a second aspect, the present invention also provides a chip thermal balance management method, the method comprising: monitoring the temperature of multiple interconnected grains; determining whether the temperature of any grain exceeds a preset temperature threshold; if so, adjusting the load or power of the grain that exceeds the preset temperature threshold.

[0010] According to a specific implementation of an embodiment of the present application, after adjusting the load or power of the grains exceeding the preset temperature threshold, the method further includes: dynamically adjusting and controlling the load or power of at least part of the grains to balance the overall temperature of the chip.

[0011] According to a specific implementation method of an embodiment of the present application, the dynamic adjustment controls the load or power of at least part of the grains, including: based on the received load or power adjustment information of the grains exceeding the preset temperature threshold, as well as the temperature information of other grains, at least part of the load of the grains exceeding the preset temperature threshold is distributed to the grains with lower temperature among the other grains.

[0012] In a third aspect, an embodiment of the present invention also provides a thermal balance management system for a chip, comprising: a temperature sensor configured to monitor the temperature of each processor core in the chip; a local temperature arbitration unit configured to receive temperature data monitored by the temperature sensor and determine whether the temperature of any processor core exceeds a preset temperature threshold; and a local load or power adjustment unit configured to adjust the load or power of the processor core whose temperature exceeds the temperature threshold when the local temperature arbitration unit determines that the temperature of a processor core exceeds the temperature threshold.

[0013] According to a specific implementation method of an embodiment of the present application, the system also includes: a load or power manager connected to each local load or power regulation unit, configured to receive load regulation feedback information from each local load or power regulation unit, and coordinate and control the load distribution between each processor core based on the load regulation feedback information.

[0014] According to a specific implementation method of an embodiment of the present application, the system also includes: a temperature balancing controller interconnected with each of the local temperature arbitration units and the load or power manager, respectively, configured to receive the temperature of each processor core provided by each of the local temperature arbitration units, and to receive the load distribution information provided by the load or power manager; according to the temperature information and load distribution information of each processor core, dynamically adjust the global thermal balancing strategy of the chip to optimize the overall temperature distribution of the chip.

[0015] According to a specific implementation method of an embodiment of the present application, the temperature balancing controller is specifically configured to determine whether there is a processor core with a lower temperature based on the temperature information and load distribution information of each processor core; if so, adjust the load distribution information and send it to the load or power manager so that the load or power manager allocates additional load to the processor core with the lower temperature.

[0016] In a fourth aspect, the present invention also provides a chip in an embodiment, comprising: at least one crystal grain, each crystal grain comprising at least two processor cores and any one of the above-mentioned thermal balance management systems connected to the processor cores.

[0017] In a fifth aspect, the present invention also provides a chip in an embodiment, comprising: at least two interconnected dies, each of which comprises at least one processor core and a thermal balance management system connected to the processor core; The thermal balance management system is configured to execute the chip thermal balance management method described in any of the aforementioned implementations to balance the temperature and load among multiple die.

[0018] The chip thermal balance management method, system and chip provided in the embodiments of the present invention monitor the temperatures of multiple areas in the chip, and based on the local temperature, dynamically adjust the load or power of the area in the chip where the local temperature is too high to reduce the heat generated in the local area. Compared with the management and control strategy that relies on a single global frequency reduction or shutdown, it not only solves the problem of local overheating of the chip, but also can maximize the performance of the chip, improve the efficiency of thermal management, and effectively balance the relationship between chip performance and heat dissipation, so as to optimize the chip thermal management effect and reduce the risk of local aging inside the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A schematic diagram of a process flow of an embodiment of a chip thermal balance management method of the present invention; Figure 2 It is a schematic flow chart of another embodiment of the chip thermal balance management method of the present invention; Figure 3 This is a schematic block diagram of the structure of an embodiment of a chip thermal balance management system of the present invention; Figure 4 A schematic diagram of a process flow of an embodiment of a chip thermal balance management method of the present invention; Figure 5 This is a schematic block diagram of the structure of a chip according to an embodiment of the present invention; Figure 6 This is a schematic block diagram of the structure of a chip according to an embodiment of the present invention; Figure 7 Schematic diagram for comparing the performance effects of the chip of the present invention. DETAILED DESCRIPTION

[0021] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0022] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In a multi-core processor chip, the performance of each processor core (CPU Core) varies due to factors such as process and heat dissipation. Under the same load, there are differences in power consumption and heat generation, which is manifested as uneven temperatures, resulting in a temperature gradient inside the chip. Especially under high load conditions, the temperature of some processor cores may exceed the preset temperature threshold, thus affecting the performance and stability of the entire chip.

[0024] Some traditional chip thermal management methods usually rely solely on a certain temperature measurement point. When the temperature of the local area where a certain temperature measurement point is located is too high, a global frequency reduction or shutdown is performed to avoid local overheating. This rough thermal management method cannot effectively balance the relationship between chip performance and heat dissipation, and it is easy to cause unnecessary performance loss of the chip as a whole, which is not conducive to system stability and overall performance.

[0025] To this end, an embodiment of the present invention provides a chip thermal balance management method, which is suitable for heat dissipation management for various types of chips, including but not limited to processor (CPU) chips, DCU (Deep-learning Computing Unit), GPU (Graphics Processing Unit) and other chips, or system chips (SoC) and integrated circuits (IC) including processors, GPUs, etc. During the operation of the chip, the core (Core, sometimes translated as core) and other computing units often generate too much heat due to excessive load, resulting in a rise in the temperature of the local area, which may accelerate the risk of local aging inside the chip, thereby affecting the stability and performance of the chip.

[0026] Figure 1 FIG. 1 is a flow chart of an embodiment of a chip thermal balance management method of the present invention; see FIG. Figure 1 , the chip thermal balance management method provided by the embodiment of the present invention includes: S110, monitoring the temperatures of multiple regions in the chip.

[0027] In this embodiment, the temperature of different areas can be monitored by setting multiple temperature sensors in the chip, and the temperature sensors can be distributed in different modules or areas of the chip, such as processor cores, cache modules, I / O interfaces, etc. Each temperature sensor collects temperature data of the area in real time according to its position and the characteristics of the monitored area.

[0028] S120: Determine whether the temperature of any area exceeds a preset temperature threshold.

[0029] In this embodiment, after obtaining the temperature data of each area of ​​the chip, the temperature of each area of ​​the chip is analyzed and judged. If the temperature of a certain area exceeds the preset temperature threshold, for example, exceeds 85°C, the area will be determined as a high temperature area. Of course, in actual applications, the temperature threshold can also be set to multiple levels, for example, 65°C, 75°C, 85°C, 90°C, 95°C, etc. Different thermal management strategies can also be adopted for different temperature thresholds. For example, if a short-term high temperature of 85°C~90°C occasionally occurs, a time threshold can be set specifically. If the duration of the high temperature is less than the time threshold, it can be ignored. For high temperatures exceeding 95°C, regardless of the duration, the temperature is adjusted directly by reducing the frequency, reducing the voltage or temporarily stopping the operation of the area to achieve precise control of the chip temperature, so that the chip can perform at its best working performance.

[0030] In this embodiment, after obtaining the temperature data of each area of ​​the chip, the temperature of each area of ​​the chip is analyzed and judged, and the average temperature is calculated. The average temperature is used as the temperature threshold. When the average temperature is lower than the preset temperature threshold, the chip is considered to be in the normal temperature range. If the temperature of a certain area is higher than the average temperature value, the area will be determined as a high temperature area, and the load or power consumption of the area will be reduced through the load or power controller. At the same time, the local load or power consumption information is fed back to the global load or power consumption management. The reduced load and power consumption will be allocated to other low temperature areas through global control, and different allocation strategies can be selected according to the temperature. If the temperature of a certain area is lower than the average temperature value, the area will be determined as a low temperature area, and the load or power consumption of the area will be increased through the load or power controller. While balancing the temperature inside the chip, it also ensures that the total load of the chip will not be reduced.

[0031] S130: If yes, adjust the load or power of the area exceeding the preset temperature threshold.

[0032] Specifically, if the temperature of a certain area in the chip exceeds a preset temperature threshold, the load or power adjustment unit can be triggered to reduce the heat generation in the area by reducing the load or power supply voltage of the processor core in the local area, thereby avoiding chip damage or performance degradation caused by local overheating and ensuring reliable operation of the system. Specifically, the load or power adjustment unit can adjust the load or power supply voltage through dynamic frequency adjustment (DVFS) technology, dynamic voltage control, etc.

[0033] The embodiment of the present invention provides a chip thermal balance management method, which monitors the temperatures of multiple areas in the chip and takes the local temperature as the basis. For the area in the chip where the local temperature is too high, the heat generated in the local area is reduced by dynamically adjusting the load or power of the area in the chip. Compared with the management and control strategy that relies on a single global frequency reduction or shutdown, it not only solves the problem of local overheating of the chip, but also can maximize the performance of the chip, improve the efficiency of thermal management, and effectively balance the relationship between chip performance and heat dissipation, so as to optimize the chip thermal management effect and reduce the risk of local aging inside the chip.

[0034] In some embodiments, monitoring the temperatures of multiple regions in the chip (S110) includes: monitoring the temperatures of multiple processor cores inside the chip; wherein each region corresponds to at least one processor core.

[0035] It should be noted that if Figure 3 , Figure 5 and Figure 6 As shown, the chip thermal balance management method provided in this embodiment is not only applicable to a single die with multiple cores configured as a package, but also applicable to an integrated circuit or chip system configured to integrate multiple dies.

[0036] See also Figure 2 In some embodiments, after adjusting the load or power of the area exceeding the preset temperature threshold, the method further includes: dynamically adjusting and controlling the load or power of at least part of the area so that the overall temperature of the chip tends to be balanced.

[0037] Specifically, after reducing the load or power of the area exceeding the preset temperature threshold, the load or power of other areas is dynamically adjusted to further balance the overall temperature of the chip.

[0038] For example, during the processing, based on the temperature information of each area acquired through monitoring, including the adjusted high-temperature area and other areas with lower temperatures, the load distribution is adjusted in real time according to the actual temperature of each area. For example, after a certain area is cooled, if there are still other areas with lower temperatures, part of the load of the aforementioned area can be transferred to the area with lower temperature, which not only helps to prevent local overheating, but also enables each area in the chip to achieve a more balanced state in load distribution.

[0039] In this embodiment, in the case of local temperature control, the adjustment strategies of different regions are adjusted dynamically in fine-grained manner in combination with the global temperature. For example, when the area with higher temperature gradually cools down, the load of the area with higher temperature can be increased in time through the balance controller responsible for global temperature management, without having to rely entirely on frequency reduction and other methods to avoid performance bottlenecks. As a result, each area of ​​the chip can maintain relatively low temperature fluctuations under different working conditions, achieve thermal balance management, thereby improving the overall thermal management effect of the chip, and then reducing the risk of local aging caused by excessive local temperature inside the chip.

[0040] Continue to view Figure 2 In some embodiments, the dynamic adjustment and control of the load or power of at least part of the area includes: based on the received load or power adjustment information of the area exceeding the preset temperature threshold and the temperature information of other areas, at least part of the load of the area exceeding the preset temperature threshold is distributed to the area with lower temperature in other areas.

[0041] Specifically, in this embodiment, when the temperature of the processor core or module in a certain area exceeds a preset threshold, its load or power will be adjusted to reduce the temperature of the area. In this process, not only the adjustment of the high-temperature area is monitored, but also the status of other areas is monitored based on the temperature data of other areas obtained. If the temperature of a certain area is significantly lower than that of other areas, at least part of the load of the area that exceeds the preset temperature threshold will be transferred to the low-temperature area for processing in a timely manner according to the preset load distribution algorithm. The specific load transfer distribution strategy can also be based on multiple factors, including the current temperature of each area, the idleness of each area, the workload, etc.

[0042] In this embodiment, the load inside the chip is dynamically distributed to ensure that each area can maintain a balanced working state under different workloads and temperature conditions, thereby avoiding low temperatures in some areas due to too low loads, thereby optimizing the overall performance and heat dissipation, and reducing the risk of local aging caused by local excessive temperatures inside the chip.

[0043] Embodiment 2 See also Figures 4 to 6, based on the same technical concept as the first embodiment, the difference is that, in this embodiment, the configuration is to perform thermal management on a chip having multiple dies. It should be noted that, Figure 6 The same component structure on each die (commonly known as "bare die" in the figure) is simplified. Specifically, the present invention also provides a method for thermal balance management of a chip, including: S210 , monitoring the temperatures of a plurality of interconnected dies.

[0044] In this embodiment, the chip includes multiple dies, each of which has multiple processor cores. A temperature sensor is provided inside each die, configured to monitor the temperature of the processor core in the die. All temperature information can be aggregated through an adapter to form global temperature data.

[0045] S220 , determining whether the temperature of any grain exceeds a preset temperature threshold.

[0046] Specifically, after obtaining the temperature information of each die, the temperature information of each die is analyzed to determine whether the temperature of a certain die exceeds a preset temperature threshold. The specific analysis and determination process can also be referred to the description of the above embodiment 1, which will not be repeated here.

[0047] S230, if yes, adjust the load or power of the die that exceeds the preset temperature threshold. When the temperature of a die exceeds the set threshold, the system will adjust the load or power of the die through the load or power adjustment unit to gradually reduce the temperature of the aforementioned die.

[0048] Based on the technical concept basically the same as that of the aforementioned embodiment 1, its specific implementation and technical effects are also basically similar, and they can be referenced to each other, so they will not be described in detail.

[0049] In some embodiments, after adjusting the load or power of the die that exceeds the preset temperature threshold, the method further includes: dynamically adjusting and controlling the load or power of at least part of the die to balance the overall temperature of the chip.

[0050] In some embodiments, the dynamic regulation controls the load or power of at least part of the grains, including: based on the received load or power regulation information of the grains exceeding the preset temperature threshold, as well as the temperature information of other grains, distributing at least part of the load of the grains exceeding the preset temperature threshold to the grains with lower temperature among the other grains.

[0051] In this embodiment, by coordinating the load distribution of the processor cores of each die according to the state of the local die and the state of the global die, thermal balance inside the entire chip can be achieved, thereby ensuring the overall performance stability of the chip.

[0052] Embodiment 3 Figure 3 This is a schematic block diagram of the structure of an embodiment of the chip thermal balance management system of the present invention; Figure 3 , the chip thermal balance management system provided by the embodiment of the present invention is described in detail.

[0053] See also Figure 3 As shown, the chip thermal balance management system provided by the embodiment of the present invention is configured to monitor and manage the chip operating temperature. Specifically, the system includes: A temperature sensor is configured to monitor the temperature of each processor core in the chip.

[0054] In this embodiment, a plurality of temperature sensors are configured inside the chip, which can be deployed in each processor core (Cpu Core) area. In some embodiments, the number of temperature sensors can be adjusted according to power consumption and physical area size to form a temperature measurement network. The temperature sensor can collect temperature data of each processor core in real time and transmit these data to the local temperature arbitration unit. It should be noted that these sensors can use different types of temperature monitoring technologies, such as silicon-based temperature sensors integrated in the chip or externally connected thermocouple sensors. In some embodiments, the temperature sensor can adjust the sampling frequency according to actual needs to optimize the accuracy and response speed of temperature monitoring.

[0055] The local temperature arbitration unit is configured to receive the temperature data monitored by the temperature sensor and determine whether the temperature of any processor core exceeds a preset temperature threshold.

[0056] The local temperature arbitration unit receives real-time temperature data from each temperature sensor and compares the data with a preset temperature threshold. The preset temperature threshold can be set according to the thermal design power consumption (TDP) of the chip or specific application requirements. For example, the set temperature threshold can vary between 85°C and 110°C. In some embodiments, the temperature arbitration unit can use dynamic threshold adjustment technology to adjust the temperature threshold in real time according to the workload or ambient temperature of the chip to enhance the adaptability of the system.

[0057] The local load or power adjustment unit is configured to adjust the load or power of the processor core whose temperature exceeds the temperature threshold when the local temperature arbitration unit determines that the temperature of a processor core exceeds the temperature threshold.

[0058] Specifically, when the local temperature arbitration unit detects that the temperature of a processor core exceeds a set threshold, it triggers the local load or power adjustment unit to reduce the load or power of the processor core in a variety of ways, such as reducing the operating frequency of the processor core, reducing the supply voltage, or temporarily scheduling the core's tasks to other processor cores. In some embodiments, the local adjustment unit can be combined with dynamic voltage frequency adjustment (DVFS) technology to achieve refined power control, thereby effectively reducing the temperature of the overheated core while minimizing the impact on overall performance.

[0059] Continue to view Figure 3 In some embodiments, the system further includes: a load or power manager connected to each local load or power regulation unit; the load or power manager is configured to receive load regulation feedback information from each local load or power regulation unit, and coordinate and control the load distribution between each processor core according to the load regulation feedback information.

[0060] In this embodiment, after the local load or power adjustment unit adjusts the overheating area, the local load or power adjustment unit feeds back the load or power adjustment result or status information to the load or power manager while adjusting. After receiving the adjustment feedback information, the load or power manager performs a comprehensive analysis and coordinates and controls the overall load of each processor core in the chip. Specifically, the load or power manager dynamically adjusts the load distribution between the processor cores according to the temperature status and current load conditions of different processor cores. For example, if a processor core has a high temperature and a heavy load, the load or power manager can transfer part of the computing tasks to the core processor cores in other areas with lower temperatures and lighter loads for execution. In this way, on the basis of local adjustment, combined with the global coordination of the load or power manager, dynamic load distribution between processor cores in different areas is achieved, thereby improving the balance between chip performance and heat dissipation.

[0061] In some embodiments, the load or power manager can optimize the load distribution scheme based on some specific scheduling algorithms, such as minimum load priority scheduling or temperature priority scheduling strategy. Through load transfer, not only can local overheating be prevented, but also the computing power of the low-temperature core can be fully utilized to improve the energy efficiency and performance of the entire chip. In addition, the load or power manager can also dynamically adjust the load distribution strategy according to the long-term temperature change trend to cope with different workloads and operating environments.

[0062] Figure 3 FIG. 1 is a schematic block diagram of a chip thermal balance management system according to an embodiment of the present invention. Figure 3As shown, in some embodiments, the system also includes: a temperature balancing controller interconnected with each of the local temperature arbitration units and the load or power manager, respectively, and the temperature balancing controller is configured to receive the temperature of each processor core provided by each of the local temperature arbitration units, and to receive load distribution information provided by the load or power manager.

[0063] In this embodiment, the temperature balance controller receives real-time temperature data from the processor core and load distribution information of each region through connections with multiple local temperature arbitration units and load or power managers. Specifically, the local temperature arbitration unit is responsible for collecting the temperature data of each processor core and transmitting it to the temperature balance controller; the load or power manager provides overall load distribution information, indicating which regions of the processor core are bearing a higher computing load and which regions of the processor core are under a lighter load. The temperature balance controller obtains the global temperature and load conditions inside the chip by summarizing these load information and local temperature information.

[0064] According to the temperature information and load distribution information of each processor core, the global thermal balance strategy of the chip is dynamically adjusted to optimize the overall temperature distribution of the chip.

[0065] Specifically, the temperature balance controller will dynamically adjust the overall thermal balance strategy based on the real-time temperature information and load distribution of each core. For example, when the temperature of a processor core is too high, the local temperature arbitration unit sends an indication signal, and the local load or power adjustment unit reduces the load of the corresponding processor core to reduce its heat generation. At the same time, the temperature balance controller will also coordinate the load distribution between the various processor cores based on the overall temperature and load distribution to ensure that the temperature inside the chip is balanced, thereby reducing the burden on the overheated area and ensuring the thermal balance of the overall regional temperature within the chip.

[0066] The temperature balancing controller is specifically configured to determine whether there is a processor core with a lower temperature based on the temperature information and load distribution information of each processor core. If so, adjust the load distribution information and send it to the load or power manager so that the load or power manager allocates additional load to the processor core with the lower temperature.

[0067] In this embodiment, by setting a temperature balance controller, it is configured to not only respond to the adjustment requirements of the area with too high temperature, but also to determine whether there is a core with lower temperature through real-time temperature information and load distribution information, so as to achieve global temperature balance adjustment. When the existence of a processor core with lower temperature is detected according to the acquired temperature data, the balance controller will adjust the load distribution strategy and send it to the load or power manager. The load or power manager will transfer part of the load to the processor core in the area with lower temperature to maintain global temperature balance and maximize the computing power of the chip, so as to achieve global temperature balance while achieving the maximum working performance of the chip.

[0068] like Figure 3 As shown, the present invention also provides a chip in an embodiment, including: at least one crystal grain, each crystal grain including at least two processor cores and a thermal balance management system as described in any of the above embodiments connected to the processor cores.

[0069] Embodiment 4 See also Figure 5 and Figure 6 As shown, the present invention also provides a chip in an embodiment, including: at least two interconnected dies, each of which includes at least one processor core and a thermal balance management system connected to the processor core; The thermal balance management system is configured to execute any one of the chip thermal balance management methods described in the second embodiment to balance the temperature and load among multiple die.

[0070] Specifically, multiple dies can be interconnected on a plane, or stacked in a vertical direction to form a 3D packaged chip.

[0071] See also Figure 5 and Figure 6 Schematically, multiple bare chips are interconnected through a packaging substrate, for example, a 2D, 2.5D or 3D chip. The temperature balance controller in each bare chip is interconnected with the load or power manager through the substrate. The thermal balance management system shares temperature information among multiple grains, and when the temperature of a certain local (grain) is too high, it sends an indication signal to the load or power adjustment unit of the grain, and at the same time transmits the temperature information to the temperature balance controllers of other chips. Each temperature balance controller performs corresponding load adjustment according to the received temperature information, thereby ensuring the temperature balance inside the entire chip package.

[0072] See also Figure 7 In the figure, S1 is a schematic diagram of the chip performance effect of the thermal balance management system provided by the embodiment of the present invention; S2 is a schematic diagram of the chip performance effect of the traditional single global thermal balance management system; Lmax is the upper limit of the chip temperature, power consumption and performance. Compared with the traditional chip thermal management strategy, according toFigure 7 As shown in the performance comparison, the chip in this embodiment not only controls the temperature of a single processor core through the temperature balance controller, but also ensures that the temperature fluctuation of all die areas in the entire chip package (especially in a multi-die interconnection structure) is controlled within a very small range through global coordination. For example, the system can ensure that the temperature fluctuation of each die area in the package is maintained within the range of ±1°C, ±3°C or ±5°C. Through this precise temperature control management, the chip can run efficiently while avoiding performance bottlenecks or hardware failures caused by excessively high or low temperatures.

[0073] Therefore, the chip provided in the embodiment of the present invention, through the thermal balance controller, executes the thermal balance control method described in the second embodiment, dynamically adjusts the load of the processor core of the grains in each region, maintains the temperature balance of each region inside the chip, and avoids overheating and performance bottlenecks. It is particularly suitable for packaging with multiple grains interconnected, because temperature information can be shared between different grains, and combined with local and global temperature and load balance management, it can optimize the thermal management of the entire system and ensure that the chip maintains stable temperature and performance under various workloads.

[0074] It should be noted that the scheme of this embodiment has corresponding specific technical features as the second embodiment, and its specific technical scheme and technical effects are similar to those of the second embodiment. Parts not described in detail can be referred to each other.

[0075] In addition, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0076] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0077] For the convenience of description, the above chip thermal balance management system is described as a part of the components, and is divided into various functional units / circuits / modules according to their functions. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.

[0078] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A chip thermal balance management method, characterized in that: The method comprises: Monitor the temperature of multiple areas in the chip; Determine whether the temperature of any area exceeds the preset temperature threshold; If so, the load or power to the area exceeding the preset temperature threshold is adjusted.

2. The chip thermal balance management method according to claim 1, characterized in that: After adjusting the load or power of the area exceeding the preset temperature threshold, the method further includes: dynamically adjusting and controlling the load or power of at least part of the area so that the overall temperature of the chip tends to be balanced.

3. The chip thermal balance management method according to claim 2, characterized in that: The dynamic adjustment and control of the load or power of at least part of the area includes: based on the received load or power adjustment information of the area exceeding the preset temperature threshold and the temperature information of other areas, allocating at least part of the load of the area exceeding the preset temperature threshold to the area with lower temperature in other areas.

4. The chip thermal balance management method according to claim 1 or 2, characterized in that: Monitoring the temperatures of multiple regions in the chip includes: monitoring the temperatures of multiple processor cores inside the chip; wherein each region corresponds to at least one processor core.

5. A chip thermal balance management method, characterized in that: The method comprises: monitoring the temperature of multiple interconnected dies; Determine whether the temperature of a die exceeds a preset temperature threshold; If so, the load or power of the die exceeding the preset temperature threshold is adjusted.

6. The chip thermal balance management method according to claim 5, characterized in that: After adjusting the load or power of the die that exceeds the preset temperature threshold, the method further includes: dynamically adjusting and controlling the load or power of at least part of the die to balance the overall temperature of the chip.

7. The chip thermal balance management method according to claim 6, characterized in that: The dynamic regulation controls the load or power of at least part of the grains, including: according to the received load or power regulation information of the grains exceeding the preset temperature threshold, and the temperature information of other grains, at least part of the load of the grains exceeding the preset temperature threshold is distributed to the grains with lower temperature among the other grains.

8. A chip thermal balance management system, characterized in that: include: a temperature sensor configured to monitor the temperature of each processor core in the chip; A local temperature arbitration unit, configured to receive the temperature data monitored by the temperature sensor and determine whether the temperature of a processor core exceeds a preset temperature threshold; The local load or power adjustment unit is configured to adjust the load or power of the processor core whose temperature exceeds the temperature threshold when the local temperature arbitration unit determines that the temperature of a processor core exceeds the temperature threshold.

9. The heat balance management system according to claim 8, characterized in that: The system also includes: a load or power manager connected to each local load or power regulation unit, configured to receive load regulation feedback information from each local load or power regulation unit, and coordinate and control the load distribution between each processor core according to the load regulation feedback information.

10. The heat balance management system according to claim 9, characterized in that: The system further comprises: a temperature balancing controller interconnected with each of the local temperature arbitration units and the load or power manager, respectively, configured to receive the temperature of each processor core provided by each of the local temperature arbitration units, and to receive load distribution information provided by the load or power manager; According to the temperature information and load distribution information of each processor core, the global thermal balance strategy of the chip is dynamically adjusted to optimize the overall temperature distribution of the chip.

11. The heat balance management system according to claim 10, characterized in that: The temperature balancing controller is specifically configured to determine whether there is a processor core with a lower temperature based on the temperature information and load distribution information of each processor core. If so, adjust the load distribution information and send it to the load or power manager so that the load or power manager allocates additional load to the processor core with the lower temperature.

12. A chip, characterized in that: include: At least one die, each die comprising at least two processor cores and a thermal balance management system according to any one of claims 8 to 11 connected to the processor cores.

13. A chip, characterized in that: include: At least two interconnected dies, each of which includes at least one processor core and a thermal balance management system connected to the processor core; The thermal balance management system is configured to execute the chip thermal balance management method according to any one of claims 5 to 7 to balance the temperature and load among multiple die.

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