Three-axis acceleration chip and manufacturing method

Abstract

According to the technical scheme, an X-axis direction detection capacitor bank, a Z-axis negative direction detection capacitor bank, a Y-axis direction detection capacitor bank and a Z-axis positive direction detection capacitor bank are arranged at intervals in the thickness direction, so that crosstalk of the X axis and the Y axis is avoided, the design difficulty is reduced, and the cost is reduced. The design patterns of the upper functional layer where the X-axis direction detection capacitor bank and the Z-axis negative direction detection capacitor bank are located and the design patterns of the lower functional layer where the Y-axis direction detection capacitor bank and the Z-axis positive direction detection capacitor bank are located are completely consistent, machining can be completed through the same layout and technology, and the time and cost of technology debugging are saved.

Description

Technical Field

[0001] The present application relates to the technical field of acceleration chips, and in particular to a three-axis acceleration chip and a manufacturing method thereof. Background Art

[0002] Capacitive three-axis acceleration chips have broad application prospects in the fields of military, automotive technology, consumer electronics, etc. Compared with piezoresistive and piezoelectric three-axis acceleration chips, capacitive three-axis acceleration chips have advantages such as wide usable temperature range, high sensitivity, and strong overload resistance. As the requirements for measurement accuracy in commercial and military fields are getting higher and higher, the market has also put forward higher requirements for the accuracy and stability of capacitive three-axis acceleration chips. At the same time, since capacitive three-axis acceleration chips are relatively mature in the development of domestic and foreign countries and have been successfully industrialized, the market entry threshold is low and the competition is fierce. Controlling and reducing costs has also become an urgent need for capacitive three-axis acceleration chip manufacturers.

[0003] Common three-axis acceleration chips are generally three-axis acceleration chips with three-axis sensitive structures arranged at intervals in the thickness direction, or three-axis acceleration chips integrated on the same plane. There are two types of three-axis acceleration chips integrated on the same plane, one is a three-axis acceleration chip with a shared mass block, and the other is a three-axis acceleration chip with separate mass blocks on each axis.

[0004] The use of a three-axis acceleration chip with intervals in the thickness direction, such as 202110578087.0 "A three-axis MEMS capacitive acceleration sensor and its preparation", avoids the problem of crosstalk between axes, but the dimension in the thickness direction is large. At the same time, the Z-axis sensitive capacitor adopts a sandwich structure, which reduces the stability of the chip.

[0005] Compared with a three-axis acceleration chip with a shared mass block, a three-axis acceleration chip with separated mass blocks is easier to avoid inter-axis crosstalk and has low design difficulty, but has low space utilization and low sensitivity per unit space.

[0006] The chip with shared mass block structure is smaller and more integrated, but the problem of three-axis crosstalk is inevitable.

[0007] Since the capacitors of the X and Y axes are usually in-plane detection structures, with the same sensing principles and similar capacitor structures, the resonant frequencies of the X and Y axes are closer, and the crosstalk of the X and Y axes is more difficult to eliminate. How to reduce the crosstalk of the X and Y axis in-plane acceleration measurement is a design difficulty of the common mass block acceleration chip, which greatly increases the time and difficulty of the early design. Summary of the invention

[0008] In order to solve or partially solve the problems existing in the related art, the present application provides a three-axis acceleration chip and a manufacturing method, which can effectively overcome the problem of crosstalk between axes of the three-axis acceleration chip in the prior art, while reducing the design difficulty.

[0009] In a first aspect, the present application provides a three-axis acceleration chip, characterized in that: it comprises an upper functional layer, an intermediate layer and a lower functional layer arranged in sequence from the top to the bottom of the three-axis acceleration chip; the upper functional layer is used to detect acceleration in the X-axis direction and the negative direction of the Z-axis, the lower functional layer is used to detect acceleration in the Y-axis direction and the positive direction of the Z-axis, and the intermediate layer is used to separate the upper functional layer and the lower functional layer;

[0010] The upper functional layer at least includes an upper mass block, an upper connection frame and an upper detection capacitor group, wherein the upper mass block is fixedly connected to the upper connection frame through an upper elastic beam, and the upper detection capacitor group includes two groups of X-axis direction detection capacitor groups and two groups of Z-axis negative direction detection capacitor groups, the two groups of X-axis direction detection capacitor groups are etched on the upper mass block in a mirror-symmetrical manner along the X-axis, and the two groups of Z-axis negative direction detection capacitor groups are etched on the upper mass block in a mirror-symmetrical manner along the Y-axis;

[0011] The middle layer is composed of a middle connecting frame and a middle shallow groove. The middle shallow groove is etched on the top and bottom of the middle layer. The height of the middle connecting frame is higher than the middle shallow groove. The middle shallow groove is located in the middle of the middle layer and is wrapped by the middle connecting frame.

[0012] The lower functional layer at least includes a lower mass block, a lower connection frame and a lower detection capacitor group, wherein the lower mass block is fixedly connected to the lower connection frame through a lower elastic beam, and the lower detection capacitor group includes two groups of Y-axis direction detection capacitor groups and two groups of Z-axis positive direction detection capacitor groups, the two groups of Y-axis direction detection capacitor groups are etched on the lower mass block in a mirror-symmetrical manner along the Y axis, and the two groups of Z-axis positive direction detection capacitor groups are etched on the lower mass block in a mirror-symmetrical manner along the X axis;

[0013] The upper functional layer and the lower functional layer are etched based on the same layout and process.

[0014] As an implementation of the first aspect, the three-axis acceleration chip also includes a substrate layer, the substrate layer is located below the lower functional layer, and is composed of a substrate connecting frame and a substrate shallow groove, the substrate connecting frame and the substrate shallow groove are a whole, the substrate shallow groove is located on the top of the substrate layer, and the substrate connecting frame is higher than the substrate shallow groove;

[0015] The substrate shallow groove is located in the middle of the substrate layer and is wrapped by the substrate connecting frame.

[0016] As an implementation of the first aspect, the middle shallow groove has a middle central boss, four middle bosses and four middle rectangular bosses, which are the same height as the middle connecting frame, the middle central boss, the four middle bosses and the four middle rectangular bosses are a whole, the middle boss is located in the middle of the middle shallow groove at the top of the middle layer, the four middle bosses are respectively located at the four inner corners of the middle connecting frame, and two of the four middle rectangular bosses are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis;

[0017] The substrate shallow groove is provided with a substrate center boss, four substrate bosses and four substrate rectangular bosses, which are the same height as the substrate connecting frame. The substrate shallow groove, the substrate center boss, the four substrate bosses and the four substrate rectangular bosses are a whole. The substrate center boss is located in the middle of the substrate shallow groove, and the four substrate bosses are respectively located at the four inner corners of the substrate connecting frame. Two of the four substrate rectangular bosses are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis.

[0018] As an implementation method of the first aspect, the upper mass block and the lower mass block also have anchor points, and the anchor points include a central anchor point, an external anchor point and a rectangular anchor point. The central anchor point is located at the center of the upper mass block and the lower mass block, the rectangular anchor point is located in the middle of each detection capacitor group, and the external anchor points are located at the four inner corners of the upper connecting frame and the lower connecting frame. The central anchor point and the external anchor points are fixedly connected to the elastic beam, and all the anchor points have the same height as the connecting frame.

[0019] As an implementation of the first aspect, each of the upper detection capacitor group and the lower detection capacitor group includes two groups of movable electrodes and two groups of fixed electrodes, the movable electrodes are composed of a plurality of movable comb teeth, and the fixed electrodes are composed of a plurality of fixed comb teeth;

[0020] Among them, the movable comb teeth of the upper detection capacitor group are all fixedly connected to the upper mass block, the movable comb teeth of the lower detection capacitor group are all fixedly connected to the lower mass block, and the fixed comb teeth are respectively fixedly connected to the rectangular anchor points.

[0021] As an implementation of the first aspect, the upper functional layer, the middle layer, the lower functional layer and the substrate layer are bonded into a whole;

[0022] The intermediate layer is bonded to the lower surface of the upper layer connecting frame and the upper surface of the lower layer connecting frame through the intermediate connecting frame, and the substrate layer is bonded to the lower surface of the lower layer connecting frame through the substrate connecting frame;

[0023] The lower surface of the central anchor point of the upper mass block is bonded to the upper surface of the intermediate central boss, and the lower surface of the central anchor point of the lower mass block is bonded to the upper surface of the central boss of the substrate;

[0024] The lower surfaces of the four rectangular anchor points of the upper mass block are respectively bonded to the upper surfaces of the four middle rectangular bosses, and the lower surfaces of the four rectangular anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate rectangular bosses;

[0025] The lower surfaces of the four external anchor points of the upper mass block are respectively bonded to the upper surfaces of the four intermediate bosses, and the lower surfaces of the four external anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate bosses;

[0026] Wherein, the bonding method is Si-SiO 2 Fusion bonding method.

[0027] As an implementation of the first aspect, each of the movable comb teeth is cross-arranged with each of the fixed comb teeth to form a comb tooth electrode, a single detection capacitor group is composed of two groups of comb tooth electrodes, a rectangular anchor point is provided between the two groups of comb tooth electrodes, and is used to connect all the fixed comb teeth, the fixed comb teeth of each two groups of comb tooth electrodes share one rectangular anchor point, and all the movable comb teeth are connected to the mass block;

[0028] Wherein, in the same detection direction, the comb teeth arrangement order of the two detection capacitor groups is opposite.

[0029] As an implementation manner of the first aspect, the movable comb teeth and the fixed comb teeth of the X-axis direction detection capacitor group and the Y-axis direction detection capacitor are comb teeth of equal height.

[0030] As an implementation method of the first aspect, the movable comb teeth and the fixed comb teeth of the Z-axis negative direction detection capacitor group and the Z-axis positive direction detection capacitor group are high-low difference comb teeth, the movable comb teeth are low comb teeth, and the fixed comb teeth are high comb teeth.

[0031] A second aspect of the present application provides a method for manufacturing a three-axis acceleration chip, comprising:

[0032] Step 1: making the middle layer. Step 1 specifically includes:

[0033] Prepare a heavily doped silicon wafer as an intermediate layer;

[0034] Using dry or wet etching to process shallow grooves and bosses on the upper and lower surfaces of the wafer, a middle shallow groove and a middle connecting frame, a middle center boss located on the upper surface of the wafer, four middle bosses, and four middle rectangular bosses are formed. The depth of the middle shallow groove is used to define the maximum travel of the sensitive structures of the upper functional layer and the lower functional layer on one side of the middle layer.

[0035] The SiO2 layer is grown on the upper and lower surfaces of the middle layer wafer by thermal oxidation;

[0036] Step 2: upper functional layer production, step 2 specifically includes:

[0037] preparing a heavily doped silicon wafer as an upper functional layer;

[0038] The upper connecting frame of the upper functional layer, the lower surface of the central anchor point, the lower surface of the external anchor point, the lower surface of the rectangular anchor point and the upper surface of the middle connecting frame of the middle layer, the upper surface of the middle central boss, the upper surfaces of the four middle bosses, and the upper surfaces of the four middle rectangular bosses are respectively bonded by Si-SiO2 melting;

[0039] Thin the wafer to the required thickness from the upper functional layer side and polish it to achieve precise control of the thickness of the upper functional layer;

[0040] Shallow grooves are formed by dry etching on one side of the upper functional layer to prepare for processing high and low comb capacitors of sensitive structures;

[0041] The acceleration sensitive structure of the upper functional layer is processed by DRIE etching on one side of the upper functional layer;

[0042] Step three, making the lower functional layer, step three specifically includes:

[0043] preparing a heavily doped silicon wafer as a lower functional layer;

[0044] The lower functional layer and the lower surface of the middle connecting frame of the middle layer are bonded by Si-SiO2 melt bonding;

[0045] Thin the wafer to the required thickness from the lower functional layer side and polish it to achieve precise control of the thickness of the lower functional layer;

[0046] Shallow grooves are formed by dry etching on one side of the lower functional layer to prepare for processing high and low comb capacitors of sensitive structures;

[0047] The acceleration sensitive structure of the lower functional layer is processed by DRIE etching on one side of the lower functional layer;

[0048] Step 4: making the substrate layer. Step 4 specifically includes:

[0049] preparing a heavily doped silicon wafer as a substrate layer;

[0050] A shallow groove and a boss are processed on the upper surface of the wafer by dry or wet etching to form a substrate shallow groove and a substrate connection frame, a substrate center boss located on the upper surface of the wafer, four substrate bosses, and four substrate rectangular bosses. The depth of the substrate shallow groove is used to define the maximum stroke of the lower functional layer sensitive structure on one side of the substrate layer.

[0051] Depositing a SiO2 layer on the upper surface of the substrate wafer;

[0052] The lower connecting frame of the lower functional layer, the lower surface of the central anchor point, the lower surface of the external anchor point, the lower surface of the rectangular anchor point and the upper surface of the substrate connecting frame of the substrate layer, the upper surface of the substrate central boss, the upper surfaces of the four substrate bosses and the upper surfaces of the four substrate rectangular bosses are respectively bonded by Si-SiO2 melt bonding.

[0053] The technical solution provided by this application may have the following beneficial effects:

[0054] The present application provides a three-axis acceleration chip and a manufacturing method, by spacing the X-axis direction detection capacitor group, the Z-axis negative direction detection capacitor group, the Y-axis direction detection capacitor group, and the Z-axis positive direction detection capacitor group in the thickness direction, the crosstalk of the X and Y axes is avoided, and the design difficulty is reduced. At the same time, the Z-axis positive and negative acceleration detection structures are separated in the thickness direction, avoiding the problem of crowded chip plane distribution caused by distribution in the same plane, small area occupied by the mass block, and low sensitivity. In the case of low crosstalk, the effective area of ​​the mass block is increased, thereby improving the sensitivity of the chip.

[0055] Since the design graphics of the upper functional layer and the lower functional layer in the vertical layered structure are exactly the same, the same layout and process can be used to complete the processing, saving the time and cost of process debugging.

[0056] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The above and other objects, features and advantages of the present application will become more apparent by describing in more detail exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0058] Figure 1 is a schematic diagram of the overall structure of a three-axis acceleration chip shown in an embodiment of the present application;

[0059] Figure 2 is a schematic diagram of the functional layer structure on a three-axis acceleration chip shown in an embodiment of the present application;

[0060] Figure 3is a schematic diagram of the intermediate layer structure of a three-axis acceleration chip shown in an embodiment of the present application;

[0061] Figure 4 Schematic diagram of the lower functional layer structure of the three-axis acceleration chip shown in the embodiment of the present application;

[0062] Figure 5 is a schematic diagram of the substrate layer structure of a three-axis acceleration chip shown in an embodiment of the present application;

[0063] Figure 6 is a schematic diagram of the anchor point distribution structure of a three-axis acceleration chip shown in an embodiment of the present application;

[0064] Figure 7 It is a schematic diagram of the high and low comb teeth arrangement of the Z-axis negative direction detection capacitor group of the three-axis acceleration chip shown in the embodiment of the present application;

[0065] Figure 8 It is a schematic diagram of the high and low comb teeth arrangement of the Z-axis positive direction detection capacitor group of the three-axis acceleration chip shown in the embodiment of the present application;

[0066] Fig. 9 Schematic diagram of the comb structure of the three-axis acceleration chip detection capacitor group shown in the embodiment of the present application;

[0067] Fig.10 It is a schematic diagram of the manufacturing process of the intermediate layer of the three-axis acceleration chip shown in the embodiment of the present application;

[0068] Fig.11 It is a schematic diagram of the process of manufacturing the functional layer on the three-axis acceleration chip shown in the embodiment of the present application;

[0069] Fig.12 It is a schematic diagram of the manufacturing process of the lower functional layer of the three-axis acceleration chip shown in the embodiment of the present application;

[0070] Fig.13 It is a schematic diagram of the manufacturing process of the substrate layer of the three-axis acceleration chip shown in the embodiment of the present application.

[0071] Explanation of symbols: 1-upper functional layer; 11-X1C; 12-X2C; 13-Z1-C; 14-Z2-C; 15-upper mass block; 16-upper connecting frame; 17-upper elastic beam; 2-middle layer; 21-middle connecting frame; 22-middle shallow groove; 23-middle center boss; 24-middle rectangular boss; 25-middle boss; 3-lower functional layer; 31-Y1C; 32-Y2C; 33-Z1 +C; 34-Z2+C; 35-lower layer mass block; 36-lower layer connecting frame; 37-lower layer elastic beam; 4-substrate layer; 41-substrate connecting frame; 42-substrate shallow groove; 43-substrate center boss; 44-substrate rectangular boss; 45-substrate boss; 51-center anchor point; 52-rectangular anchor point; 53-external anchor point; 6-mass block; 7-low comb teeth; 8-high comb teeth; 9-movable comb teeth; 10-fixed comb teeth. DETAILED DESCRIPTION

[0072] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0073] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application and the appended claims are also intended to include plural forms unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0074] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0075] Glossary:

[0076] X-axis: the direction extending along the X-axis in the spatial rectangular coordinate system, which is the axial direction in this application. Figure 1 The arrow in the middle points to the positive direction.

[0077] Y axis: the direction extending along the Y axis in the spatial rectangular coordinate system, which is the horizontal direction in this application. Figure 1 The arrow in the middle points to the positive direction.

[0078] Z axis: the direction extending along the Z axis in the spatial rectangular coordinate system, which is the longitudinal direction in this application. Figure 1 The arrow in the middle points to the positive direction.

[0079] The origin is Figure 1 The intersection of the X-axis, Y-axis, and Z-axis is located in the middle of the three-axis acceleration chip.

[0080] An embodiment of the present application provides a three-axis acceleration chip, including an upper functional layer 1, a middle layer 2 and a lower functional layer 3 arranged in sequence from the top to the bottom of the three-axis acceleration chip, the upper functional layer 1 is used to detect acceleration in the X-axis direction and the negative direction of the Z-axis, the lower functional layer 3 is used to detect acceleration in the Y-axis direction and the positive direction of the Z-axis, and the middle layer 2 is used to separate the upper functional layer 1 and the lower functional layer 3.

[0081] The upper functional layer 1 at least includes an upper mass block 15, an upper connection frame 16 and an upper detection capacitor group, wherein the upper mass block 15 is fixedly connected to the upper connection frame 16 through an upper elastic beam 17, and the upper detection capacitor group is two groups of X-axis direction detection capacitor groups and two groups of Z-axis negative direction detection capacitor groups. The two groups of X-axis direction detection capacitor groups are etched on the upper mass block 15 along the X-axis mirror symmetry, and the two groups of Z-axis negative direction detection capacitor groups are etched on the upper mass block 15 along the Y-axis mirror symmetry. The specific structure of the upper functional layer 1 is referenced Figure 2 shown.

[0082] Among them, the X-axis direction detection capacitor group and the Z-axis negative direction detection capacitor group are both connected to the upper mass block 15 to form a shared mass block structure, which increases the effective area of ​​the upper mass block 15 and further improves the sensitivity of the chip.

[0083] Specifically, there are at least four upper elastic beams 17 fixed to the upper connecting frame 16 , which respectively fix the four corners of the upper mass block 15 to the upper connecting frame 16 .

[0084] Among them, the two groups of X-axis detection capacitors are X1C11 and X2C12, X1C11 is etched on the upper mass block 15 along the positive direction of the X-axis, and X1C12 is etched on the upper mass block 15 along the negative direction of the X-axis. The two groups of Z-axis detection capacitors are Z1-C13 and Z2-C14, Z2-C14 is etched on the upper mass block 15 along the positive direction of the Y-axis, and Z1-C13 is etched on the upper mass block 15 along the negative direction of the Y-axis.

[0085] The middle layer 2 is composed of a middle connecting frame 21 and a middle shallow groove 22. The middle shallow groove 22 is etched on the top and bottom of the middle layer. The height of the middle connecting frame 21 is higher than the middle shallow groove 22. The middle shallow groove 22 is located in the middle position of the middle layer 2 and is wrapped by the middle connecting frame 21.

[0086] The lower functional layer 3 at least includes a lower mass block 35, a lower connection frame 36 and a lower detection capacitor group, wherein the lower mass block 35 is fixedly connected to the lower connection frame 36 through a lower elastic beam 37, and the lower detection capacitor group is two groups of Y-axis direction detection capacitor groups and two groups of Z-axis positive direction detection capacitor groups. The two groups of Y-axis direction detection capacitor groups are etched on the lower mass block 35 along the Y-axis mirror symmetry, and the two groups of Z-axis positive direction detection capacitor groups are etched on the lower mass block 35 along the X-axis mirror symmetry. The specific structure of the lower functional layer is referenced Figure 4 shown.

[0087] Among them, the Y-axis direction detection capacitor group and the Z-axis positive direction detection capacitor group are both connected to the lower mass block 35 to form a shared mass block structure, which increases the effective area of ​​the lower mass block 35 and further improves the sensitivity of the chip.

[0088] Specifically, there are at least four lower elastic beams 37 fixed to the lower connecting frame 36 , which respectively fix the four corners of the lower mass block 35 to the lower connecting frame 36 .

[0089] Among them, the two groups of Y-axis detection capacitors are Y1C31 and Y2C32, Y1C31 is etched on the lower mass block 35 along the positive direction of the Y-axis, and Y1C32 is etched on the lower mass block 35 along the negative direction of the Y-axis. The two groups of Z-axis detection capacitors are Z1+C33 and Z2+C34, Z1+C33 is etched on the lower mass block 35 along the positive direction of the X-axis, and Z2+C34 is etched on the lower mass block 35 along the negative direction of the X-axis.

[0090] The upper functional layer 1 and the lower functional layer 3 are etched based on the same layout and process.

[0091] Furthermore, after the etching process of the upper functional layer 1 and the lower functional layer 3 is completed, the upper mass block 15 and the lower mass block 35 are in a suspended state, and are fixedly connected to the upper connecting frame 16 and the lower connecting frame 36 through the upper elastic beam 17 and the lower elastic beam 37 respectively, so that the upper mass block 15 and the lower mass block 35 are stably suspended in the center of the upper connecting frame 16 and the lower connecting frame 36 respectively, and when the three-axis acceleration chip is subjected to acceleration in a certain direction, the mass block can move according to the direction of acceleration.

[0092] In this embodiment, by spacing the X-axis detection capacitor group, the Z-axis negative direction detection capacitor group, the Y-axis detection capacitor group, and the Z-axis positive direction detection capacitor group in the thickness direction, the crosstalk of the X and Y axes is avoided, and the design difficulty is reduced. At the same time, the positive and negative acceleration detection structures of the Z axis are separated in the thickness direction, avoiding the chip plane distribution crowding caused by the same plane distribution, and adopting the method of sharing the mass block of the X, Z / Y, and Z axes, under the condition of low crosstalk, the effective area of ​​the mass block is increased, thereby improving the sensitivity of the chip. Since the design graphics of the upper functional layer and the lower functional layer in the vertical layered structure are completely consistent, the same layout and process can be used to complete the processing, saving the time and cost of process debugging.

[0093] In the embodiment of the present application, the three-axis acceleration chip also includes a substrate layer 4, which is located below the lower functional layer 3 and is composed of a substrate connection frame 41 and a substrate shallow groove 42. The substrate connection frame 41 and the substrate shallow groove 42 are a whole, and the substrate shallow groove 42 is located at the top of the substrate layer 4. The substrate connection frame 41 is higher than the substrate shallow groove 42. The specific structure of the substrate layer 4 is referenced Figure 5 shown.

[0094] The substrate shallow groove 42 is located in the middle of the substrate layer 4 and is surrounded by the substrate connecting frame 41 .

[0095] In this embodiment, the substrate layer 4 provides a stable structural foundation for the three-axis acceleration chip, ensuring the structural integrity and stability of the chip during manufacturing and use. They form a heterojunction with the functional material and participate in realizing the functions of the device, providing a conductive path for the three-axis acceleration chip to accurately transmit and process electrical signals and work normally. The substrate layer 4 also participates in the heat conduction and heat dissipation process, helping the chip to quickly transfer the heat generated during operation, thereby improving the stability and service life of the chip.

[0096] In the embodiment of the present application, the middle shallow groove 22 has a middle center boss 23, four middle bosses 25 and four middle rectangular bosses 24, which are the same height as the middle connecting frame. The middle center boss 23, the four middle bosses 25 and the four middle rectangular bosses 24 are a whole. The middle boss 25 is located in the middle of the middle shallow groove 22 at the top of the middle layer 22. The four middle bosses 25 are respectively located at the four inner corners of the middle connecting frame 21. Two of the four middle rectangular bosses 24 are symmetrically arranged about the X axis, and the other two are symmetrically arranged about the Y axis. The specific structure of the middle layer 2 is referenced Figure 3 shown.

[0097] The substrate shallow groove 42 has a substrate center boss 43, four substrate bosses 45 and four substrate rectangular bosses 44, which are the same height as the substrate connection frame. The substrate shallow groove 42, the substrate center boss 43, the four substrate bosses 45 and the four substrate rectangular bosses 44 are a whole. The substrate center boss 43 is located in the middle of the substrate shallow groove. The four substrate bosses 45 are respectively located at the four inner corners of the substrate connection frame. Two of the four substrate rectangular bosses 44 are symmetrically arranged about the X axis, and the other two are symmetrically arranged about the Y axis. The specific structure of the substrate layer is referenced Figure 5 shown.

[0098] In this embodiment, by providing bosses on the middle layer 2 and the substrate layer 4, the structural stability of the middle layer 2 and the substrate layer 4 is enhanced to prevent deformation or damage when subjected to external impact or vibration. The reliability and durability of the acceleration chip are improved, and by providing bosses on the middle layer 2 and the substrate layer, the acceleration components can be arranged more compactly, thereby improving the integration of the chip, helping to reduce the size of the chip, reducing the manufacturing cost, and also facilitating the integration of the chip with other electronic components.

[0099] In the embodiment of the present application, the upper mass block 15 and the lower mass block 35 also have anchor points, and the anchor points include a central anchor point 51, an external anchor point 53 and a rectangular anchor point 52. The central anchor point 51 is located in the center of the upper mass block 15 and the lower mass block 35, the rectangular anchor point 52 is located in the middle of each detection capacitor group, and the external anchor point 53 is located at the four inner corners of the upper connecting frame 16 and the lower connecting frame 36. The central anchor point 51 and the external anchor point 53 are fixedly connected to the elastic beam, and all the anchor points have the same height as the connecting frame. The specific reference of the connection structure between the anchor point and the elastic beam is Figure 6 shown.

[0100] In the embodiment of the present application, each detection capacitor group of the upper detection capacitor group and the lower detection capacitor group includes two groups of movable electrodes and two groups of fixed electrodes, the movable electrodes are composed of multiple movable comb teeth 9, and the fixed electrodes are composed of multiple fixed comb teeth 10.

[0101] The movable comb teeth 9 of the upper detection capacitor group are all fixedly connected to the upper mass block 15 , the movable comb teeth 9 of the lower detection capacitor group are all fixedly connected to the lower mass block 35 , and the fixed comb teeth 10 are fixedly connected to the rectangular anchor points 52 .

[0102] Furthermore, each detection capacitor group includes the same number of movable comb teeth 9 and fixed comb teeth 10 .

[0103] In this embodiment, the detection capacitor is a detection interface that can sensitively capture the micro-displacement of the comb tooth structure caused by the inertial force. The change in the capacitance value of the detection capacitor is proportional to the displacement of the comb tooth structure, thereby measuring the change in the capacitance value of the detection capacitor to infer the magnitude and direction of the acceleration.

[0104] In the embodiment of the present application, the upper functional layer 1, the middle layer 2, the lower functional layer 3 and the substrate layer 4 are bonded into a whole.

[0105] The middle layer 2 is bonded to the lower surface of the upper layer connection frame 16 and the upper surface of the lower layer connection frame 36 through the middle connection frame 21 , and the substrate layer 4 is bonded to the lower surface of the lower layer connection frame 36 through the substrate connection frame 41 .

[0106] The lower surface of the central anchor point 51 of the upper mass block 15 is bonded to the upper surface of the middle central boss 23 , and the lower surface of the central anchor point 51 of the lower mass block 35 is bonded to the upper surface of the substrate central boss 43 .

[0107] The lower surfaces of the four rectangular anchor points 52 of the upper mass block 15 are bonded to the upper surfaces of the four middle rectangular bosses 24 respectively, and the lower surfaces of the four rectangular anchor points 52 of the lower mass block 35 are bonded to the upper surfaces of the four substrate rectangular bosses 44 respectively.

[0108] The lower surfaces of the four external anchor points 53 of the upper mass block 15 are bonded to the upper surfaces of the four intermediate bosses 25 , respectively. The lower surfaces of the four external anchor points 53 of the lower mass block 35 are bonded to the upper surfaces of the four substrate bosses 45 , respectively.

[0109] Specifically, the upper functional layer 1, the middle layer 2, the lower functional layer 3 and the substrate layer 4 are bonded together to form a three-axis acceleration chip. The specific structure is as follows: Figure 1 shown.

[0110] Wherein, the bonding method is Si-SiO 2 Fusion bonding method.

[0111] In this embodiment, Si-SiO 2 The bonding is completed by melt bonding. No adhesive or external electric field is required during the melt bonding process, which greatly simplifies the bonding process and speeds up chip manufacturing. After high-temperature annealing, Si-SiO 2 The melt-bonded surface will undergo a physical and chemical reaction to form a very strong bond connection, thereby improving the stability of the chip.

[0112] In the embodiment of the present application, each movable comb tooth 9 is arranged crosswise with each fixed comb tooth 10 to form a comb tooth electrode. A single detection capacitor group is composed of two groups of comb tooth electrodes. There is a rectangular anchor point 52 between the two groups of comb tooth electrodes for connecting all the fixed comb teeth 10. The fixed comb teeth of each two groups of comb tooth electrodes share a rectangular anchor point 52. All movable comb teeth 9 are connected to the mass block. The specific structure of the upper detection capacitor group and the lower detection capacitor group is referenced. Fig. 9 shown.

[0113] Wherein, in the same detection direction, the comb teeth arrangement order of the two detection capacitor groups is opposite.

[0114] In addition, after bonding, the detection capacitor groups of the upper functional layer 1 and the lower functional layer 3 are arranged vertically in the comb direction.

[0115] Specifically, the detection directions of the upper functional layer 1 and the lower functional layer 2 are different, and the X-axis detection capacitor group of the upper functional layer 1 and the Y-axis detection capacitor group of the lower functional layer 2 are prone to crosstalk when performing acceleration detection. This design method can eliminate or reduce the interference of other detection directions on the current detection direction, making the detection result of each detection direction more independent and accurate.

[0116] Furthermore, the two groups of X-axis direction detection capacitor groups have the same initial capacitance value, the two groups of Y-axis direction detection capacitor groups have the same initial capacitance value, and the two groups of Z-axis negative direction detection capacitor groups and the two groups of Z-axis positive direction detection capacitor groups have the same initial capacitance value.

[0117] In this embodiment, a detection capacitor group is formed by the comb-tooth electrode structure in the acceleration chip and the rectangular anchor point 52. When the acceleration chip is subjected to acceleration, the comb-tooth structure will undergo a slight displacement, which will change the capacitance value between the comb teeth and the rectangular anchor point 52, thereby realizing the detection of acceleration by the change in capacitance value, thereby achieving accurate measurement of acceleration. At the same time, by arranging the comb teeth of the detection capacitor group of the upper functional layer and the lower functional layer vertically, the detection performance of the detection capacitor group is improved, and interference and fluctuation are reduced, thereby making the detection result more accurate and stable.

[0118] In the embodiment of the present application, the movable comb teeth 9 and the fixed comb teeth 10 of the X-axis direction detection capacitor group and the Y-axis direction detection capacitor are comb teeth of equal height.

[0119] Specifically, when not subjected to the acceleration of the X-axis, the capacitance values ​​of X1C11 and X2C12 are the same. When subjected to the acceleration in the positive direction of the X-axis, the upper mass block 15 translates along the positive direction of the X-axis. Since the arrangement order of the comb teeth of the two detection capacitor groups is opposite, during the translation process, the movable comb teeth 9 of X1C11 move closer to the fixed comb teeth 10, so that the area of ​​the detection capacitor group plate increases, and the movable comb teeth 9 of X2C12 are separated from the fixed comb teeth 10, so that the area of ​​the detection capacitor group plate decreases, thereby increasing the capacitance value of X1C11 and decreasing the capacitance value of X2C12. Conversely, when subjected to the acceleration in the negative direction of the X-axis, the capacitance value of X1C11 decreases and the capacitance value of X2C12 increases. Through signal processing differential calculation, it can be concluded that the capacitance change caused by the X-axis acceleration is (ΔX1C-ΔX2C), thereby obtaining the X-axis acceleration and realizing the decoupling of the X-axis from the Y-axis and the Z-axis. When there is no acceleration of the Y axis, the capacitance values ​​of Y1C31 and Y2C32 are the same. When subjected to acceleration in the positive direction of the Y axis, the lower mass block 35 translates along the positive direction of the Y axis. Since the arrangement order of the comb teeth of the two detection capacitor groups is opposite, during the translation process, the movable comb teeth 9 of Y1C31 move closer to the fixed comb teeth 10, so that the area of ​​the detection capacitor group plate increases, and the movable comb teeth 9 of Y2C32 separate from the fixed comb teeth 10, so that the area of ​​the detection capacitor group plate decreases, thereby increasing the capacitance value of Y1C31 and decreasing the capacitance value of Y2C32. Conversely, when subjected to acceleration in the negative direction of the Y axis, the capacitance value of Y1C31 decreases and the capacitance value of Y2C32 increases. Through signal processing differential calculation, it can be concluded that the capacitance change caused by the Y axis acceleration is (ΔY1C-ΔY2C), thereby obtaining the Y axis acceleration and realizing the decoupling of the Y axis from the X axis and the Z axis.

[0120] Furthermore, the fixed comb teeth on the left and right sides of the rectangular anchor point 5 of a single detection capacitor group are arranged symmetrically, and the movable comb teeth on both sides are arranged asymmetrically, so that a single detection capacitor can be decoupled from the acceleration of the X-axis and the Y-axis.

[0121] In this embodiment, by setting the detection capacitor groups in different directions to move according to the corresponding detection directions, the detection of acceleration in different directions is achieved, and interference in other directions is avoided. In addition, the signal processing differential calculation is used to effectively eliminate interference factors such as common mode noise and temperature drift, thereby improving the detection accuracy and stability. Since the fixed comb teeth on the left and right sides of a single detection capacitor group are connected to the same rectangular anchor point 5, the stress of the rectangular anchor point 5 will cause the capacitance values ​​of the two detection capacitor groups in the same detection direction to increase and decrease, and the change amount is equal, and the total capacitance of the two detection capacitor groups remains unchanged, thereby eliminating the zero bias caused by the stress at the connection of the rectangular anchor point 5, further improving the accuracy of the chip.

[0122] In an embodiment of the present application, the movable comb teeth and fixed comb teeth of the Z-axis negative direction detection capacitor group and the Z-axis positive direction detection capacitor group are high-low difference comb teeth, the movable comb teeth 9 are low comb teeth 7, and the fixed comb teeth 10 are high comb teeth 8.

[0123] Among them, the comb teeth arrangement structure of the Z-axis negative direction detection capacitor group is referenced Figure 7 As shown, the high comb teeth 8 are fixed comb teeth 10, and the low comb teeth 7 are movable comb teeth 9. When not subject to acceleration, the lower surfaces of the high and low comb teeth are flush. Figure 8 As shown, the high comb teeth 8 are fixed comb teeth 10, and the low comb teeth 7 are movable comb teeth 9. When not subject to acceleration, the upper surfaces of the high and low comb teeth are flush.

[0124] Specifically, when subjected to the acceleration in the positive direction of the Z axis, the upper mass block 15 and the lower mass block 35 move in the positive direction of the Z axis, the movable comb teeth 9 of the two detection capacitor groups Z1-C13 and Z2-C14 move closer to the upper surface of the fixed comb teeth 10, and the area of ​​the lower surface detection capacitor group plates is reduced, so that the capacitance values ​​of Z1-C13 and Z2-C14 are reduced, and the area of ​​the upper surface detection capacitor group plates of Z1+C33 and Z2+C34 remains unchanged, so that the capacitance values ​​of Z1+C33 and Z2+C34 remain unchanged. Conversely, when subjected to the acceleration in the negative direction of the Z axis, When the Z axis acceleration is 0, the movable comb teeth 9 of the two detection capacitor groups Z1+C33 and Z2+C34 move closer to the lower surface of the fixed comb teeth 10, and the areas of the upper surface detection capacitor group plates are reduced, so that the capacitance values ​​of Z1+C33 and Z2+C34 are reduced, and the areas of the lower surface detection capacitor group plates of Z1-C13 and Z2-C14 remain unchanged, so that the capacitance values ​​of Z1-C13 and Z2-C14 remain unchanged. It can be concluded that the capacitance change caused by the Z axis acceleration is (ΔZ1-C+ΔZ2-C-(ΔZ1+C+ΔZ2+C)), thereby obtaining the Z axis acceleration.

[0125] Furthermore, through the design of the height difference comb teeth, it is ensured that when the chip is subjected to acceleration in the positive direction of the Z axis, the maximum translational stroke of the movable comb teeth 9 of the upper functional layer 1 in the positive direction of the Z axis does not exceed the height of the fixed comb teeth 10, that is, it will not exceed the surface of the upper wafer. Therefore, there is no need to add a top cover structure on the top of the upper functional layer 1, which is beneficial to reducing the thickness of the chip.

[0126] In this embodiment, the capacitance change caused by acceleration in three directions is calculated by differential signal processing, which effectively eliminates interference factors such as common mode noise and temperature drift, thereby improving the accuracy and stability of detection. Since there is a clear linear relationship between the capacitance change and the acceleration in three directions, the capacitance change can be converted into an acceleration value through simple linear calculation, thereby simplifying the data processing process and further improving the accuracy of detection. In addition, the method has strong resistance to external electromagnetic interference, temperature changes and other environmental factors, ensuring that acceleration can be accurately and stably measured in complex environments.

[0127] The present application also provides a method for manufacturing a three-axis acceleration chip, comprising:

[0128] Step 1: Make the middle layer 2. For details, refer to Fig.10 As shown, including:

[0129] S11: Prepare a heavily doped silicon wafer as the intermediate layer 2.

[0130] S12: Use dry or wet etching to process shallow grooves and bosses on the upper and lower surfaces of the wafer to form a middle shallow groove 22 and a middle connecting frame 21, a middle center boss 23 located on the upper surface of the wafer, four middle bosses 25, and four middle rectangular bosses 24. The depth of the middle shallow groove 22 is used to define the maximum stroke of the sensitive structures of the upper functional layer 1 and the lower functional layer 3 on one side of the middle layer 2.

[0131] S13: growing SiO2 layers on the upper and lower surfaces of the middle layer 2 wafer by means of thermal oxidation.

[0132] Step 2: Production of upper functional layer 1. For specific steps, refer to Fig.11 As shown, including:

[0133] S21: Prepare a heavily doped silicon wafer as the upper functional layer 1.

[0134] S22: The upper connecting frame 16 of the upper functional layer 1, the lower surface of the central anchor point 51, the lower surface of the external anchor point 53, the lower surface of the rectangular anchor point 52 and the upper surface of the middle connecting frame 21, the upper surface of the middle central boss 23, the upper surface of the four middle bosses 25, and the upper surface of the four middle rectangular bosses 24 of the middle layer 2 are respectively bonded by Si-SiO2 melt bonding.

[0135] S23: Thinning the wafer to a required thickness from one side of the upper functional layer 1 and polishing it to achieve precise control of the thickness of the upper functional layer 1.

[0136] S24: A shallow groove is formed on one side of the upper functional layer 1 by dry etching to prepare for processing the high and low comb capacitors of the sensitive structure.

[0137] S25: completing the processing of the acceleration sensitive structure of the upper functional layer 1 by DRIE etching on one side of the upper functional layer 1.

[0138] The acceleration sensitive structure is a comb-teeth structure of a detection capacitor group.

[0139] Step 3: Production of lower functional layer 3. For specific steps, refer to Fig.12 As shown, including:

[0140] S31: preparing a heavily doped silicon wafer as the lower functional layer 3.

[0141] S32: The lower functional layer 3 and the lower surface of the middle connecting frame 21 of the middle layer 2 are molten-bonded by Si—SiO2.

[0142] S33: Thinning the wafer to a required thickness from one side of the lower functional layer 3 and polishing it to achieve precise control of the thickness of the lower functional layer 3.

[0143] S34: A shallow groove is formed on one side of the lower functional layer 3 by dry etching to prepare for processing high and low comb-tooth capacitors of the sensitive structure.

[0144] S35: completing the processing of the acceleration sensitive structure of the lower functional layer 3 on one side of the lower functional layer 3 by DRIE etching.

[0145] The acceleration sensitive structure is a comb-teeth structure of a detection capacitor group.

[0146] Step 4: Fabrication of substrate layer 4. For details, refer to Fig.13 As shown, including:

[0147] S41: Prepare a heavily doped silicon wafer as the substrate layer 4.

[0148] S42: shallow grooves and bosses are processed on the upper surface of the wafer by dry or wet etching to form a substrate shallow groove 42 and a substrate connecting frame 41, a substrate center boss 43 located on the upper surface of the wafer, four substrate bosses 45, and four substrate rectangular bosses 44. The depth of the substrate shallow groove 42 is used to define the maximum stroke of the sensitive structure of the lower functional layer 3 on one side of the substrate layer 4.

[0149] S43: Depositing a SiO2 layer on the upper surface of the substrate layer 4 wafer.

[0150] S44: The lower connecting frame 41 of the lower functional layer 4, the lower surface of the central anchor point 51, the lower surface of the external anchor point 53, the lower surface of the rectangular anchor point 52 and the upper surface of the substrate connecting frame 41 of the substrate layer 4, the upper surface of the substrate central boss 43, the upper surfaces of the four substrate bosses 45, and the upper surfaces of the four substrate rectangular bosses 44 are respectively bonded by Si-SiO2 melt bonding.

[0151] In this embodiment, by forming the middle shallow groove 22 and the middle connecting frame 21 in the middle layer 2, the maximum stroke of the sensitive structure of the upper functional layer 1 and the lower functional layer 3 on one side of the middle layer 2 can be accurately controlled. This design ensures the accuracy and stability of the acceleration sensitive structure, thereby improving the measurement accuracy of the chip. At the same time, in the process of making the upper functional layer 1 and the lower functional layer 3, the wafer is thinned to the required thickness from the side of the upper functional layer 1 and the side of the lower functional layer 3, and polished, thereby achieving accurate control of the thickness of the upper and lower functional layers. This precise control helps to optimize the mechanical and electrical properties of the chip, improve the sensitivity and response speed of the chip, and the manufacturing method adopts Si-SiO2 melt bonding technology to achieve a firm connection between the upper functional layer 1, the middle layer 2, the lower functional layer 3 and the substrate layer 4, improve the structural strength of the chip, optimize the electrical properties of the chip, and ensure the stability and reliability of the chip in harsh environments.

[0152] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A three-axis acceleration chip, characterized in that: It includes an upper functional layer, a middle layer and a lower functional layer arranged in sequence from the top to the bottom of the three-axis acceleration chip; the upper functional layer is used to detect acceleration in the X-axis direction and the negative direction of the Z-axis, the lower functional layer is used to detect acceleration in the Y-axis direction and the positive direction of the Z-axis, and the middle layer is used to separate the upper functional layer and the lower functional layer; The upper functional layer at least includes an upper mass block, an upper connection frame and an upper detection capacitor group, wherein the upper mass block is fixedly connected to the upper connection frame through an upper elastic beam, and the upper detection capacitor group includes two groups of X-axis direction detection capacitor groups and two groups of Z-axis negative direction detection capacitor groups, the two groups of X-axis direction detection capacitor groups are etched on the upper mass block in a mirror-symmetrical manner along the X-axis, and the two groups of Z-axis negative direction detection capacitor groups are etched on the upper mass block in a mirror-symmetrical manner along the Y-axis; The middle layer is composed of a middle connecting frame and a middle shallow groove. The middle shallow groove is etched on the top and bottom of the middle layer. The height of the middle connecting frame is higher than the middle shallow groove. The middle shallow groove is located in the middle of the middle layer and is wrapped by the middle connecting frame. The lower functional layer at least includes a lower mass block, a lower connection frame and a lower detection capacitor group, wherein the lower mass block is fixedly connected to the lower connection frame through a lower elastic beam, and the lower detection capacitor group includes two groups of Y-axis direction detection capacitor groups and two groups of Z-axis positive direction detection capacitor groups, the two groups of Y-axis direction detection capacitor groups are etched on the lower mass block in a mirror-symmetrical manner along the Y axis, and the two groups of Z-axis positive direction detection capacitor groups are etched on the lower mass block in a mirror-symmetrical manner along the X axis; The upper functional layer and the lower functional layer are etched based on the same layout and process.

2. The three-axis acceleration chip according to claim 1, characterized in that: The three-axis acceleration chip also includes a substrate layer, which is located below the lower functional layer and consists of a substrate connection frame and a substrate shallow groove. The substrate connection frame and the substrate shallow groove are a whole. The substrate shallow groove is located on the top of the substrate layer, and the substrate connection frame is higher than the substrate shallow groove. Wherein, the substrate shallow groove is located in the middle of the substrate layer and is wrapped by the substrate connecting frame.

3. The three-axis acceleration chip according to claim 2, characterized in that: The middle shallow groove has a middle central boss, four middle bosses and four middle rectangular bosses, which are the same height as the middle connecting frame. The middle central boss, the four middle bosses and the four middle rectangular bosses are a whole. The middle boss is located in the middle of the middle shallow groove at the top of the middle layer. The four middle bosses are respectively located at the four inner corners of the middle connecting frame. Two of the four middle rectangular bosses are symmetrically arranged about the X axis, and the other two are symmetrically arranged about the Y axis. The substrate shallow groove is provided with a substrate center boss, four substrate bosses and four substrate rectangular bosses, which are the same height as the substrate connecting frame. The substrate shallow groove, the substrate center boss, the four substrate bosses and the four substrate rectangular bosses are a whole. The substrate center boss is located in the middle of the substrate shallow groove, and the four substrate bosses are respectively located at the four inner corners of the substrate connecting frame. Two of the four substrate rectangular bosses are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis.

4. The three-axis acceleration chip according to claim 3, characterized in that: The upper mass block and the lower mass block also have anchor points, which include a central anchor point, external anchor points and rectangular anchor points. The central anchor point is located in the center of the upper mass block and the lower mass block, the rectangular anchor point is located in the middle of each detection capacitor group, and the external anchor points are located at the four inner corners of the upper connecting frame and the lower connecting frame. The central anchor point and the external anchor points are fixedly connected to the elastic beam, and all the anchor points have the same height as the connecting frame.

5. The three-axis acceleration chip according to claim 4, characterized in that: Each of the upper detection capacitor group and the lower detection capacitor group includes two groups of movable electrodes and two groups of fixed electrodes, the movable electrodes are composed of a plurality of movable comb teeth, and the fixed electrodes are composed of a plurality of fixed comb teeth; Among them, the movable comb teeth of the upper detection capacitor group are all fixedly connected to the upper mass block, the movable comb teeth of the lower detection capacitor group are all fixedly connected to the lower mass block, and the fixed comb teeth are respectively fixedly connected to the rectangular anchor points.

6. The three-axis acceleration chip according to claim 5, characterized in that: The upper functional layer, the middle layer, the lower functional layer and the substrate layer are bonded into a whole; The intermediate layer is bonded to the lower surface of the upper layer connecting frame and the upper surface of the lower layer connecting frame through the intermediate connecting frame, and the substrate layer is bonded to the lower surface of the lower layer connecting frame through the substrate connecting frame; The lower surface of the central anchor point of the upper mass block is bonded to the upper surface of the intermediate central boss, and the lower surface of the central anchor point of the lower mass block is bonded to the upper surface of the central boss of the substrate; The lower surfaces of the four rectangular anchor points of the upper mass block are respectively bonded to the upper surfaces of the four middle rectangular bosses, and the lower surfaces of the four rectangular anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate rectangular bosses; The lower surfaces of the four external anchor points of the upper mass block are respectively bonded to the upper surfaces of the four intermediate bosses, and the lower surfaces of the four external anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate bosses; Wherein, the bonding method is Si-SiO2 melt bonding method.

7. The three-axis acceleration chip according to claim 6, characterized in that: Each of the movable comb teeth is arranged crosswise with each of the fixed comb teeth to form a comb tooth electrode. A single detection capacitor group is composed of two groups of comb tooth electrodes. There is a rectangular anchor point between the two groups of comb tooth electrodes for connecting all the fixed comb teeth. The fixed comb teeth of every two groups of comb tooth electrodes share one rectangular anchor point. All the movable comb teeth are connected to the mass block. Wherein, in the same detection direction, the comb teeth arrangement order of the two detection capacitor groups is opposite.

8. The three-axis acceleration chip according to claim 6, characterized in that: The movable comb teeth and the fixed comb teeth of the X-axis direction detection capacitor group and the Y-axis direction detection capacitor are comb teeth of equal height.

9. The three-axis acceleration chip according to claim 6, characterized in that: The movable comb teeth and fixed comb teeth of the Z-axis negative direction detection capacitor group and the Z-axis positive direction detection capacitor group are high-low difference comb teeth, the movable comb teeth are low comb teeth, and the fixed comb teeth are high comb teeth.

10. A method for manufacturing a three-axis acceleration chip, characterized in that: The three-axis acceleration chip according to any one of claims 1 to 9 comprises: Step 1: making the middle layer. Step 1 specifically includes: Prepare a heavily doped silicon wafer as an intermediate layer; Using dry or wet etching to process shallow grooves and bosses on the upper and lower surfaces of the wafer, a middle shallow groove and a middle connecting frame, a middle center boss located on the upper surface of the wafer, four middle bosses, and four middle rectangular bosses are formed. The depth of the middle shallow groove is used to define the maximum travel of the sensitive structures of the upper functional layer and the lower functional layer on one side of the middle layer. The SiO2 layer is grown on the upper and lower surfaces of the middle layer wafer by thermal oxidation; Step 2: upper functional layer production, step 2 specifically includes: preparing a heavily doped silicon wafer as an upper functional layer; The upper connecting frame of the upper functional layer, the lower surface of the central anchor point, the lower surface of the external anchor point, the lower surface of the rectangular anchor point and the upper surface of the middle connecting frame of the middle layer, the upper surface of the middle central boss, the upper surfaces of the four middle bosses, and the upper surfaces of the four middle rectangular bosses are respectively bonded by Si-SiO2 melting; Thin the wafer to the required thickness from the upper functional layer side and polish it to achieve precise control of the thickness of the upper functional layer; Shallow grooves are formed by dry etching on one side of the upper functional layer to prepare for processing high and low comb capacitors of sensitive structures; The acceleration sensitive structure of the upper functional layer is processed by DRIE etching on one side of the upper functional layer; Step three, making the lower functional layer, step three specifically includes: preparing a heavily doped silicon wafer as a lower functional layer; The lower functional layer and the lower surface of the middle connecting frame of the middle layer are bonded by Si-SiO2 melt bonding; Thin the wafer to the required thickness from the lower functional layer side and polish it to achieve precise control of the thickness of the lower functional layer; Shallow grooves are formed by dry etching on one side of the lower functional layer to prepare for processing high and low comb capacitors of sensitive structures; The acceleration sensitive structure of the lower functional layer is processed by DRIE etching on one side of the lower functional layer; Step 4: making the substrate layer. Step 4 specifically includes: preparing a heavily doped silicon wafer as a substrate layer; A shallow groove and a boss are processed on the upper surface of the wafer by dry or wet etching to form a substrate shallow groove and a substrate connection frame, a substrate center boss located on the upper surface of the wafer, four substrate bosses, and four substrate rectangular bosses. The depth of the substrate shallow groove is used to define the maximum stroke of the lower functional layer sensitive structure on one side of the substrate layer. Depositing a SiO2 layer on the upper surface of the substrate wafer; The lower connecting frame of the lower functional layer, the lower surface of the central anchor point, the lower surface of the external anchor point, the lower surface of the rectangular anchor point and the upper surface of the substrate connecting frame of the substrate layer, the upper surface of the substrate central boss, the upper surfaces of the four substrate bosses and the upper surfaces of the four substrate rectangular bosses are respectively bonded by Si-SiO2 melt bonding.

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