A three-axis acceleration chip and a manufacturing method thereof

Abstract

This application relates to a three-axis acceleration chip and a manufacturing method. In the technical solution of this application, by spacing the X-axis direction detection capacitor group, the Z-axis negative direction detection capacitor group, the Y-axis direction detection capacitor group, and the Z-axis positive direction detection capacitor group in the thickness direction, crosstalk between the X and Y axes is avoided, reducing the design difficulty. Moreover, the upper functional layer where the X-axis direction detection capacitor group and the Z-axis negative direction detection capacitor group are located, and the lower functional layer where the Y-axis direction detection capacitor group and the Z-axis positive direction detection capacitor group are located have exactly the same designed patterns, and can be processed using the same layout and process, saving the time and cost of process debugging.

Description

Technical Field

[0001] The present application relates to the technical field of acceleration chips, and in particular to a three-axis acceleration chip and a manufacturing method thereof. Background Art

[0002] Capacitive three-axis accelerometers have broad application prospects in military, automotive, and consumer electronics sectors. Compared to piezoresistive and piezoelectric three-axis accelerometers, capacitive three-axis accelerometers offer advantages such as a wide operating temperature range, high sensitivity, and strong overload resistance. As measurement accuracy requirements in both commercial and military applications increase, the market is also placing higher demands on the accuracy and stability of capacitive three-axis accelerometers. Furthermore, due to the relatively mature development and successful industrialization of capacitive three-axis accelerometers both domestically and internationally, the market entry threshold is low and competition is fierce. Controlling and reducing costs has become a pressing need for capacitive three-axis accelerometer manufacturers.

[0003] Common three-axis acceleration chips are generally three-axis acceleration chips with three-axis sensitive structures arranged at intervals in the thickness direction, or three-axis acceleration chips integrated on the same plane. There are two types of three-axis acceleration chips integrated on the same plane. One is a three-axis acceleration chip with a shared mass block, and the other is a three-axis acceleration chip with separate mass blocks on each axis.

[0004] The use of a three-axis acceleration chip with intervals in the thickness direction, such as 202110578087.0 "A three-axis MEMS capacitive acceleration sensor and its preparation", avoids the problem of crosstalk between axes, but the thickness direction dimension is large. At the same time, since the Z-axis sensitive capacitor adopts a sandwich structure, the stability of the chip is reduced.

[0005] Compared with the three-axis acceleration chip with a shared mass block, the three-axis acceleration chip with separated mass blocks is easier to avoid inter-axis crosstalk and has lower design difficulty, but has low space utilization and low sensitivity per unit space.

[0006] The chip with shared mass block structure is smaller and more integrated, but it inevitably suffers from the problem of three-axis crosstalk.

[0007] Because the capacitors for the X and Y axes typically use an in-plane detection structure, share the same sensing principles, and have similar capacitor structures, their resonant frequencies are closer, making crosstalk between the X and Y axes more difficult to eliminate. Reducing crosstalk in X and Y-axis in-plane acceleration measurement is a design challenge for common-mass accelerometer chips, significantly increasing the time and difficulty of initial design. Summary of the Invention

[0008] To solve or partially solve the problems existing in the related art, the present application provides a three-axis acceleration chip and a manufacturing method thereof, which can effectively overcome the problem of cross-axis crosstalk in the existing three-axis acceleration chip and reduce the design difficulty at the same time.

[0009] In a first aspect of the present application, a three-axis acceleration chip is provided, which is characterized in that it includes an upper functional layer, an intermediate layer, and a lower functional layer sequentially arranged from the top to the bottom of the three-axis acceleration chip; the upper functional layer is used to detect the acceleration in the X-axis direction and the negative Z-axis direction, the lower functional layer is used to detect the acceleration in the Y-axis direction and the positive Z-axis direction, and the intermediate layer is used to separate the upper functional layer and the lower functional layer;

[0010] The upper functional layer at least includes an upper mass block, an upper connection frame, and an upper detection capacitor group. Among them, the upper mass block is fixedly connected to the upper connection frame through an upper elastic beam. The upper detection capacitor group includes two X-axis direction detection capacitor groups and two negative Z-axis direction detection capacitor groups. The two X-axis direction detection capacitor groups are etched on the upper mass block symmetrically about the X-axis, and the two negative Z-axis direction detection capacitor groups are etched on the upper mass block symmetrically about the Y-axis;

[0011] The intermediate layer is composed of an intermediate connection frame and an intermediate shallow groove. The top and bottom of the intermediate layer are etched with the intermediate shallow groove. The height of the intermediate connection frame is higher than that of the intermediate shallow groove. The intermediate shallow groove is located in the middle of the intermediate layer and is wrapped by the intermediate connection frame;

[0012] The lower functional layer at least includes a lower mass block, a lower connection frame, and a lower detection capacitor group. Among them, the lower mass block is fixedly connected to the lower connection frame through a lower elastic beam. The lower detection capacitor group includes two Y-axis direction detection capacitor groups and two positive Z-axis direction detection capacitor groups. The two Y-axis direction detection capacitor groups are etched on the lower mass block symmetrically about the Y-axis, and the two positive Z-axis direction detection capacitor groups are etched on the lower mass block symmetrically about the X-axis;

[0013] Among them, the upper functional layer and the lower functional layer are etched based on the same layout and process.

[0014] As an implementation of the first aspect, the three-axis acceleration chip further includes a substrate layer, which is located below the lower functional layer and is composed of a substrate connection frame and a substrate shallow groove. The substrate connection frame and the substrate shallow groove are an integral body. The substrate shallow groove is located at the top of the substrate layer, and the substrate connection frame is higher than the substrate shallow groove;

[0015] Among them, the substrate shallow groove is located in the middle of the substrate layer and is wrapped by the substrate connection frame.

[0016] As an implementation of the first aspect, the intermediate shallow groove has an intermediate central boss, four intermediate bosses, and four intermediate rectangular bosses, which have the same height as the intermediate connection border. The intermediate central boss, the four intermediate bosses, and the four intermediate rectangular bosses form a whole. The intermediate bosses are located at the middle position of the intermediate shallow groove on the top of the intermediate layer. The four intermediate bosses are respectively located at the four inner corners of the intermediate connection border. For the four intermediate rectangular bosses, two of them are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis.

[0017] The substrate shallow groove has a substrate central boss, four substrate bosses, and four substrate rectangular bosses, which have the same height as the substrate connection border. The substrate shallow groove, the substrate central boss, the four substrate bosses, and the four substrate rectangular bosses form a whole. The substrate central boss is located at the middle position of the substrate shallow groove. The four substrate bosses are respectively located at the four inner corners of the substrate connection border. For the four substrate rectangular bosses, two of them are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis.

[0018] As an implementation of the first aspect, the upper mass block and the lower mass block further have anchor points, which include a central anchor point, external anchor points, and rectangular anchor points. The central anchor point is located at the center of the upper mass block and the lower mass block. The rectangular anchor points are located at the middle positions of each detection capacitor group. The external anchor points are located at the four inner corners of the upper connection border and the lower connection border. The central anchor point and the external anchor points are both fixedly connected to the elastic beams. All the anchor points have the same height as the connection border.

[0019] As an implementation of the first aspect, each detection capacitor group of the upper detection capacitor group and the lower detection capacitor group includes two groups of movable electrodes and two groups of fixed electrodes. The movable electrodes are composed of multiple movable comb teeth, and the fixed electrodes are composed of multiple fixed comb teeth.

[0020] Among them, the movable comb teeth of the upper detection capacitor group are all fixedly connected to the upper mass block, the movable comb teeth of the lower detection capacitor group are all fixedly connected to the lower mass block, and the fixed comb teeth are respectively fixedly connected to the rectangular anchor points.

[0021] As an implementation of the first aspect, the upper functional layer, the intermediate layer, the lower functional layer, and the substrate layer are bonded into a whole.

[0022] The intermediate layer is bonded to the lower surface of the upper connection border and the upper surface of the lower connection border through the intermediate connection border. The substrate layer is bonded to the lower surface of the lower connection border through the substrate connection border.

[0023] The lower surface of the central anchor point of the upper mass block is bonded to the upper surface of the middle central boss, and the lower surface of the central anchor point of the lower mass block is bonded to the upper surface of the substrate central boss;

[0024] The lower surfaces of the four rectangular anchor points of the upper mass block are respectively bonded to the upper surfaces of the four middle rectangular bosses, and the lower surfaces of the four rectangular anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate rectangular bosses;

[0025] The lower surfaces of the four outer anchor points of the upper mass block are respectively bonded to the upper surfaces of the four middle bosses, and the lower surfaces of the four outer anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate bosses;

[0026] Among them, the bonding method is the Si - SiO2 fusion bonding method.

[0027] As an implementation manner of the first aspect, each movable comb tooth and each fixed comb tooth are arranged in a cross - pattern to form a comb - tooth electrode. A single detection capacitor group is composed of two groups of comb - tooth electrodes. There is a rectangular anchor point between the two groups of comb - tooth electrodes for connecting all the fixed comb teeth. The fixed comb teeth of every two groups of comb - tooth electrodes share one such rectangular anchor point, and all the movable comb teeth are connected to the mass block;

[0028] Among them, in the same detection direction, the comb - tooth arrangement orders of the two groups of detection capacitor groups are opposite.

[0029] As an implementation manner of the first aspect, the movable comb teeth and the fixed comb teeth of the X - axis direction detection capacitor group and the Y - axis direction detection capacitor are of the same height.

[0030] As an implementation manner of the first aspect, the movable comb teeth and the fixed comb teeth of the Z - axis negative - direction detection capacitor group and the Z - axis positive - direction detection capacitor group are of different heights. The movable comb teeth are low - height comb teeth, and the fixed comb teeth are high - height comb teeth.

[0031] The second aspect of the present application provides a manufacturing method of a three - axis acceleration chip, including:

[0032] Step 1, manufacturing the intermediate layer. Step 1 specifically includes:

[0033] Prepare a heavily - doped silicon wafer as the intermediate layer;

[0034] Adopt dry or wet etching to process shallow grooves and bosses on the upper and lower surfaces of the wafer to form intermediate shallow grooves and intermediate connection frames, a middle central boss located on the upper surface of the wafer, four middle bosses, and four middle rectangular bosses. The depth of the intermediate shallow groove is used to define the maximum stroke of the sensitive structures of the upper functional layer and the lower functional layer on one side of the intermediate layer;

[0035] Grow SiO2 layers on the upper and lower surfaces of the intermediate layer wafer by means of thermal oxidation;

[0036] Step 2, fabrication of the upper functional layer, which specifically includes:

[0037] Prepare a heavily doped silicon wafer as the upper functional layer;

[0038] The upper layer of the upper functional layer is connected to the border, the lower surface of the central anchor, the lower surface of the external anchor, the lower surface of the rectangular anchor, and the upper surface of the intermediate connection border, the upper surface of the intermediate central boss, the upper surfaces of the four intermediate bosses, and the upper surfaces of the four intermediate rectangular bosses of the intermediate layer through Si-SiO2 fusion bonding;

[0039] Thin the wafer from one side of the upper functional layer to the required thickness and polish it to achieve precise control of the thickness of the upper functional layer;

[0040] Dry-etch shallow grooves on one side of the upper functional layer to prepare for processing the high-low comb capacitors of the sensitive structure;

[0041] Complete the processing of the acceleration-sensitive structure of the upper functional layer by DRIE etching on one side of the upper functional layer;

[0042] Step 3, fabrication of the lower functional layer, which specifically includes:

[0043] Prepare a heavily doped silicon wafer as the lower functional layer;<x

[0044] The lower functional layer is bonded to the lower surface of the intermediate connection border of the intermediate layer through Si-SiO2 fusion bonding;

[0045] Thin the wafer from one side of the lower functional layer to the required thickness and polish it to achieve precise control of the thickness of the lower functional layer;

[0046] Dry-etch shallow grooves on one side of the lower functional layer to prepare for processing the high-low comb capacitors of the sensitive structure;

[0047] Complete the processing of the acceleration-sensitive structure of the lower functional layer by DRIE etching on one side of the lower functional layer;

[0048] Step 4, fabrication of the substrate layer, which specifically includes:

[0049] Prepare a heavily doped silicon wafer as the substrate layer;

[0050] Use dry or wet etching to process shallow grooves and bosses on the upper surface of the wafer to form substrate shallow grooves, substrate connection borders, a substrate central boss located on the upper surface of the wafer, four substrate bosses, and four substrate rectangular bosses. The depth of the substrate shallow grooves is used to define the maximum stroke of the sensitive structure of the lower functional layer on one side of the substrate layer;

[0051] Deposit a SiO2 layer on the upper surface of the substrate layer wafer;

[0052] The lower layer of the lower functional layer, the lower surface of the central anchor point, the lower surface of the external anchor point, the lower surface of the rectangular anchor point are respectively and the upper surface of the substrate connection border of the substrate layer, the upper surface of the substrate central convex platform, the upper surfaces of the four substrate convex platforms, and the upper surfaces of the four substrate rectangular convex platforms are bonded by Si-SiO2 fusion bonding.

[0053] The technical solution provided by this application may include the following beneficial effects:

[0054] This application provides a three-axis acceleration chip and a manufacturing method. By spacing the X-axis direction detection capacitor group, the Z-axis negative direction detection capacitor group, the Y-axis direction detection capacitor group, and the Z-axis positive direction detection capacitor group in the thickness direction, crosstalk between the X and Y axes is avoided, and the design difficulty is reduced. At the same time, the Z-axis positive and negative acceleration detection structures are separated in the thickness direction, avoiding the problems of crowded chip planar distribution, small area occupied by the mass block, and low sensitivity caused by distribution in the same plane. In the case of low crosstalk, the effective area of the mass block is increased, thereby improving the sensitivity of the chip.

[0055] Since the design patterns of the upper functional layer and the lower functional layer in the vertical layered structure are exactly the same, the same layout and process can be used for processing, saving the time and cost of process debugging.

[0056] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this application. [[ID=,17]] Brief Description of the Drawings

[0057] By describing the exemplary embodiments of this application in more detail in conjunction with the drawings, the above and other objects, features, and advantages of this application will become more obvious. Among them, in the exemplary embodiments of this application, the same reference numerals generally represent the same components.

[0058] Figure 1 It is a schematic diagram of the overall structure of the three-axis acceleration chip shown in the embodiment of this application;

[0059] Figure 2 It is a schematic diagram of the upper functional layer structure of the three-axis acceleration chip shown in the embodiment of this application;

[0060] Figure 3 It is a schematic diagram of the intermediate layer structure of the three-axis acceleration chip shown in the embodiment of this application;

[0061] Figure 4 It is a schematic diagram of the lower functional layer structure of the three-axis acceleration chip shown in the embodiment of this application;

[0062] Figure 5It is a schematic diagram of the substrate layer structure of the three-axis acceleration chip shown in the embodiments of the present application;

[0063] Figure 6 It is a schematic diagram of the anchor point distribution structure of the three-axis acceleration chip shown in the embodiments of the present application;

[0064] Figure 7 It is a schematic diagram of the high and low comb tooth arrangement of the Z-axis negative direction detection capacitor group of the three-axis acceleration chip shown in the embodiments of the present application;

[0065] Figure 8 It is a schematic diagram of the high and low comb tooth arrangement of the Z-axis positive direction detection capacitor group of the three-axis acceleration chip shown in the embodiments of the present application;

[0066] Figure 9 It is a schematic diagram of the comb tooth structure of the detection capacitor group of the three-axis acceleration chip shown in the embodiments of the present application;

[0067] Figure 10 It is a schematic diagram of the manufacturing process of the intermediate layer of the three-axis acceleration chip shown in the embodiments of the present application;

[0068] Figure 11 It is a schematic diagram of the manufacturing process of the upper functional layer of the three-axis acceleration chip shown in the embodiments of the present application;

[0069] Figure 12 It is a schematic diagram of the manufacturing process of the lower functional layer of the three-axis acceleration chip shown in the embodiments of the present application;

[0070] Figure 13 It is a schematic diagram of the manufacturing process of the substrate layer of the three-axis acceleration chip shown in the embodiments of the present application.

[0071] Symbol description: 1 - upper functional layer; 11 - X1C; 12 - X2C; 13 - Z1-C; 14 - Z2-C; 15 - upper mass block; 16 - upper connection frame; 17 - upper elastic beam; 2 - intermediate layer; 21 - intermediate connection frame; 22 - intermediate shallow groove; 23 - intermediate center boss; 24 - intermediate rectangular boss; 25 - intermediate boss; 3 - lower functional layer; 31 - Y1C; 32 - Y2C; 33 - Z1+C; 34 - Z2+C; 35 - lower mass block; 36 - lower connection frame; 37 - lower elastic beam; 4 - substrate layer; 41 - substrate connection frame; 42 - substrate shallow groove; 43 - substrate center boss; 44 - substrate rectangular boss; 45 - substrate boss; 51 - center anchor point; 52 - rectangular anchor point; 53 - external anchor point; 6 - mass block; 7 - low comb tooth; 8 - high comb tooth; 9 - movable comb tooth; 10 - fixed comb tooth. Detailed implementation manners

[0072] Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0073] The terms used in the present application are for the purpose of describing specific embodiments only and are not intended to limit the present application. The singular forms "a", "the", and "said" used in the present application and the appended claims are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0074] It should be understood that although the terms "first", "second", "third", etc. may be used in the present application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present application, "a plurality" means two or more unless otherwise specifically defined.

[0075] Glossary:

[0076] X-axis: The direction extending along the X-axis in a three-dimensional rectangular coordinate system, which is the axial direction in the present application, Figure 1 and the arrow indicates the positive direction.

[0077] Y-axis: The direction extending along the Y-axis in a three-dimensional rectangular coordinate system, which is the transverse direction in the present application, Figure 1 and the arrow indicates the positive direction.

[0078] Z-axis: The direction extending along the Z-axis in a three-dimensional rectangular coordinate system, which is the longitudinal direction in the present application, Figure 1 and the arrow indicates the positive direction.

[0079] wherein, the origin is Figure 1 the intersection of the X-axis, Y-axis, and Z-axis in the middle position of the three-axis acceleration chip.

[0080] An embodiment of the present application provides a three-axis acceleration chip, which includes an upper functional layer 1, an intermediate layer 2, and a lower functional layer 3 arranged in sequence from the top to the bottom of the three-axis acceleration chip. The upper functional layer 1 is used to detect accelerations in the X-axis direction and the negative Z-axis direction. The lower functional layer 3 is used to detect accelerations in the Y-axis direction and the positive Z-axis direction. The intermediate layer 2 is used to separate the upper functional layer 1 and the lower functional layer 3.

[0081] The upper functional layer 1 at least includes an upper mass block 15, an upper connection frame 16, and an upper detection capacitor group. Among them, the upper mass block 15 is fixedly connected to the upper connection frame 16 through an upper elastic beam 17. The upper detection capacitor group includes two X-axis direction detection capacitor groups and two negative Z-axis direction detection capacitor groups. The two X-axis direction detection capacitor groups are etched on the upper mass block 15 in mirror symmetry along the X-axis. The two negative Z-axis direction detection capacitor groups are etched on the upper mass block 15 in mirror symmetry along the Y-axis. The specific structure of the upper functional layer 1 is shown in Figure 2 as follows.

[0082] Among them, both the X-axis direction detection capacitor group and the negative Z-axis direction detection capacitor group are connected to the upper mass block 15, forming a shared mass block structure, which increases the effective area of the upper mass block 15, thereby improving the sensitivity of the chip.

[0083] Specifically, there are at least 4 upper elastic beams 17 fixed to the upper connection frame 16, which respectively fix the four corners of the upper mass block 15 to the upper connection frame 16.

[0084] Among them, the two X-axis direction detection capacitor groups are X1C11 and X2C12 respectively. X1C11 is etched on the upper mass block 15 along the positive X-axis direction, and X1C12 is etched on the upper mass block 15 along the negative X-axis direction. The two Z-axis direction detection capacitors are Z1-C13 and Z2-C14 respectively. Z2-C14 is etched on the upper mass block 15 along the positive Y-axis direction, and Z1-C13 is etched on the upper mass block 15 along the negative Y-axis direction.

[0085] The intermediate layer 2 is composed of an intermediate connection frame 21 and an intermediate shallow groove 22. The top and bottom of the intermediate layer are etched with the intermediate shallow groove 22. The height of the intermediate connection frame 21 is higher than that of the intermediate shallow groove 22. The intermediate shallow groove 22 is located at the middle position of the intermediate layer 2 and is wrapped by the intermediate connection frame 21.

[0086] The lower functional layer 3 at least includes a lower mass block 35, a lower connecting frame 36, and a lower detection capacitor group. Among them, the lower mass block 35 is fixedly connected to the lower connecting frame 36 through a lower elastic beam 37. The lower detection capacitor group includes two Y-axis direction detection capacitor groups and two Z-axis positive direction detection capacitor groups. The two Y-axis direction detection capacitor groups are etched on the lower mass block 35 in a mirror symmetry along the Y-axis, and the two Z-axis positive direction detection capacitor groups are etched on the lower mass block 35 in a mirror symmetry along the X-axis. For the specific structure of the lower functional layer, refer to Figure 4 as shown.

[0087] Among them, both the Y-axis direction detection capacitor group and the Z-axis positive direction detection capacitor group are connected to the lower mass block 35, forming a shared mass block structure, which increases the effective area of the lower mass block 35, thereby improving the sensitivity of the chip.

[0088] Specifically, there are at least 4 lower elastic beams 37 fixed to the lower connecting frame 36, which respectively fix the four corners of the lower mass block 35 to the lower connecting frame 36.

[0089] Among them, the two Y-axis direction detection capacitor groups are Y1C31 and Y2C32 respectively. Y1C31 is etched on the lower mass block 35 along the positive Y-axis direction, and Y1C32 is etched on the lower mass block 35 along the negative Y-axis direction. The two Z-axis direction detection capacitors are Z1+C33 and Z2+C34 respectively. Z1+C33 is etched on the lower mass block 35 along the positive X-axis direction, and Z2+C34 is etched on the lower mass block 35 along the negative X-axis direction.

[0090] Among them, the upper functional layer 1 and the lower functional layer 3 are etched based on the same layout and process.

[0091] Furthermore, after the etching process of the upper functional layer 1 and the lower functional layer 3 is completed, the upper mass block 15 and the lower mass block 35 are in a suspended state, and are fixedly connected to the upper connecting frame 16 and the lower connecting frame 36 through the upper elastic beam 17 and the lower elastic beam 37 respectively, so that the upper mass block 15 and the lower mass block 35 are stably suspended in the center of the upper connecting frame 16 and the lower connecting frame 36 respectively. When the three-axis acceleration chip is subjected to an acceleration in a certain direction, the mass block can move according to the acceleration direction.

[0092] In this embodiment, by spacing the X-axis direction detection capacitor group, the Z-axis negative direction detection capacitor group, the Y-axis direction detection capacitor group, and the Z-axis positive direction detection capacitor group in the thickness direction, crosstalk between the X and Y axes is avoided, and the design difficulty is reduced. At the same time, the Z-axis positive and negative acceleration detection structures are separated in the thickness direction, avoiding overcrowding in the chip plane distribution caused by distribution in the same plane. Moreover, the method of sharing the mass block for the X, Z / Y, and Z axes is adopted. In the case of low crosstalk, the effective area of the mass block is increased, thereby improving the sensitivity of the chip. Since the design patterns of the upper functional layer and the lower functional layer in the vertical layered structure are exactly the same, the same layout and process can be used for processing, saving the time and cost of process debugging.

[0093] In the embodiment of the present application, the three-axis acceleration chip further includes a substrate layer 4, which is located below the lower functional layer 3 and is composed of a substrate connection frame 41 and a substrate shallow groove 42. The substrate connection frame 41 and the substrate shallow groove 42 are an integral body. The substrate shallow groove 42 is located at the top of the substrate layer 4, and the substrate connection frame 41 is higher than the substrate shallow groove 42. For the specific structure of the substrate layer 4, refer to Figure 5 as shown.

[0094] Among them, the substrate shallow groove 42 is located at the middle position of the substrate layer 4 and is surrounded by the substrate connection frame 41.

[0095] In this embodiment, the substrate layer 4 provides a stable structural foundation for the three-axis acceleration chip, ensuring the structural integrity and stability of the chip during manufacturing and use. They form a heterojunction with the functional material, participate in realizing the functions of the device, provide a conduction path for accurately transmitting and processing electrical signals of the three-axis acceleration chip, and for normal operation. Moreover, the substrate layer 4 also participates in the heat conduction and heat dissipation processes, helping the chip quickly transfer the heat generated during operation, improving the stability and service life of the chip.

[0096] In the embodiment of the present application, the middle shallow groove 22 has a middle center boss 23, four middle bosses 25, and four middle rectangular bosses 24, which have the same height as the middle connection frame. The middle center boss 23, the four middle bosses 25, and the four middle rectangular bosses 24 are an integral body. The middle boss 25 is located at the middle position of the middle shallow groove 22 at the top of the middle layer 22. The four middle bosses 25 are respectively located at the four inner corners of the middle connection frame 21. For the four middle rectangular bosses 24, two of them are symmetrically arranged about the X axis, and the other two are symmetrically arranged about the Y axis. For the specific structure of the middle layer 2, refer to Figure 3 as shown.

[0097] On the substrate shallow groove 42, there are a substrate center boss 43, four substrate bosses 45 and four substrate rectangular bosses 44, which have the same height as the substrate connection border. The substrate shallow groove 42, the substrate center boss 43, the four substrate bosses 45 and the four substrate rectangular bosses 44 form an integral body. The substrate center boss 43 is located in the middle of the substrate shallow groove. The four substrate bosses 45 are respectively located at the four inner corners of the substrate connection border. For the four substrate rectangular bosses 44, two of them are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis. For the specific structure of the substrate layer, refer to Figure 5 as shown.

[0098] In this embodiment, by providing bosses on the intermediate layer 2 and the substrate layer 4, the structural stability of the intermediate layer 2 and the substrate layer 4 is enhanced, preventing deformation or damage when subjected to external impacts or vibrations. The reliability and durability of the acceleration chip are improved. Moreover, by providing bosses on the intermediate layer 2 and the substrate layer, the acceleration components can be arranged more compactly, thereby improving the integration degree of the chip, helping to reduce the size of the chip, lowering the manufacturing cost, and also facilitating the integration of the chip with other electronic components.

[0099] In the embodiment of the present application, the upper mass block 15 and the lower mass block 35 also have anchor points. The anchor points include a center anchor point 51, an external anchor point 53 and a rectangular anchor point 52. The center anchor point 51 is located at the center of the upper mass block 15 and the lower mass block 35. The rectangular anchor point 52 is located at the middle position of each detection capacitor group. The external anchor point 53 is located at the four inner corners of the upper connection border 16 and the lower connection border 36. Both the center anchor point 51 and the external anchor point 53 are fixedly connected to the elastic beam. All the anchor points have the same height as the connection border. For the connection structure between the anchor points and the elastic beam, refer to Figure 6 as shown.

[0100] In the embodiment of the present application, each detection capacitor group of the upper detection capacitor group and the lower detection capacitor group includes two groups of movable electrodes and two groups of fixed electrodes. The movable electrodes are composed of a plurality of movable comb teeth 9, and the fixed electrodes are composed of a plurality of fixed comb teeth 10.

[0101] Among them, the movable comb teeth 9 of the upper detection capacitor group are all fixedly connected to the upper mass block 15, and the movable comb teeth 9 of the lower detection capacitor group are all fixedly connected to the lower mass block 35. The fixed comb teeth 10 are respectively fixedly connected to the rectangular anchor points 52.

[0102] Furthermore, the number of movable comb teeth 9 and the number of fixed comb teeth 10 included in each detection capacitor group are the same.

[0103] In this embodiment, the detection capacitor serves as a detection interface and can sensitively capture the micro-displacement of the comb structure caused by the inertial force. The change in the capacitance value of the detection capacitor is proportional to the displacement of the comb structure, thereby realizing the measurement of the change in the capacitance value of the detection capacitor to deduce the magnitude and direction of the acceleration.

[0104] In the embodiment of the present application, the upper functional layer 1, the intermediate layer 2, the lower functional layer 3, and the substrate layer 4 are bonded into a whole.

[0105] The intermediate layer 2 is bonded to the lower surface of the upper connection frame 16 and the upper surface of the lower connection frame 36 through the intermediate connection frame 21, and the substrate layer 4 is bonded to the lower surface of the lower connection frame 36 through the substrate connection frame 41.

[0106] The lower surface of the central anchor point 51 of the upper mass block 15 is bonded to the upper surface of the intermediate central boss 23, and the lower surface of the central anchor point 51 of the lower mass block 35 is bonded to the upper surface of the substrate central boss 43.

[0107] The lower surfaces of the four rectangular anchor points 52 of the upper mass block 15 are respectively bonded to the upper surfaces of the four intermediate rectangular bosses 24, and the lower surfaces of the four rectangular anchor points 52 of the lower mass block 35 are respectively bonded to the upper surfaces of the four substrate rectangular bosses 44.

[0108] The lower surfaces of the four external anchor points 53 of the upper mass block 15 are respectively bonded to the upper surfaces of the four intermediate bosses 25, and the lower surfaces of the four external anchor points 53 of the lower mass block 35 are respectively bonded to the upper surfaces of the four substrate bosses 45.

[0109] Specifically, the whole formed by bonding the upper functional layer 1, the intermediate layer 2, the lower functional layer 3, and the substrate layer 4 is a three-axis acceleration chip, and the specific structure is as Figure 1 shown.

[0110] Among them, the bonding method is the Si-SiO2 fusion bonding method.

[0111] In this embodiment, the bonding is completed by the Si-SiO2 fusion bonding method. During the fusion bonding process, no adhesive is required, nor is an external electric field required. This greatly simplifies the bonding process, speeds up the chip manufacturing speed, and after high-temperature annealing treatment, physical and chemical reactions will occur on the surface bonded by Si-SiO2 to form a very strong bond connection, thereby improving the stability of the chip.

[0112] In an embodiment of the present application, each movable comb tooth 9 and each fixed comb tooth 10 are arranged in a cross pattern to form a comb tooth electrode. A single detection capacitor group is composed of two groups of comb tooth electrodes. There is a rectangular anchor 52 between the two groups of comb tooth electrodes for connecting all the fixed comb teeth 10. The fixed comb teeth of every two groups of comb tooth electrodes share a rectangular anchor 52. All the movable comb teeth 9 are connected to the mass block. For the specific structures of the upper detection capacitor group and the lower detection capacitor group, refer to Figure 9 as shown.

[0113] Among them, in the same detection direction, the arrangement orders of the comb teeth of the two detection capacitor groups are opposite.

[0114] In addition, for the triaxial acceleration chip after bonding, the comb tooth directions of the detection capacitor groups of the upper functional layer 1 and the lower functional layer 3 are arranged perpendicularly.

[0115] Specifically, the detection directions of the upper functional layer 1 and the lower functional layer 2 are different. Moreover, crosstalk is likely to occur when the X-axis direction detection capacitor group of the upper functional layer 1 and the Y-axis direction detection capacitor group of the lower functional layer 2 perform acceleration detection. By this design method, the interference from other detection directions to the current detection direction can be eliminated or reduced, making the detection results of each detection direction more independent and accurate.

[0116] Furthermore, the initial capacitance values of the two groups of X-axis direction detection capacitor groups are the same, the initial capacitance values of the two groups of Y-axis direction detection capacitor groups are the same, and the initial capacitance values of the two groups of Z-axis negative direction detection capacitor groups and the two groups of Z-axis positive direction detection capacitor groups are the same.

[0117] In this embodiment, a detection capacitor group is formed by the comb tooth electrode structure in the acceleration chip and the rectangular anchor 52. When the acceleration chip is subjected to an acceleration, the comb tooth structure will undergo a small displacement, which will change the capacitance value between the comb teeth and the rectangular anchor 52, realizing the detection of acceleration by using the change in capacitance value, achieving precise measurement of acceleration. At the same time, by arranging the comb tooth directions of the detection capacitor groups of the upper functional layer and the lower functional layer perpendicularly, the detection performance of the detection capacitor group is improved, and interference and fluctuations are reduced, thereby making the detection results more accurate and stable.

[0118] In an embodiment of the present application, the movable comb teeth 9 and the fixed comb teeth 10 of the X-axis direction detection capacitor group and the Y-axis direction detection capacitor are comb teeth of equal height.

[0119] Specifically, when there is no acceleration in the X-axis direction, the capacitance values of X1C11 and X2C12 are the same. When an acceleration in the positive X-axis direction is applied, the upper mass block 15 translates in the positive X-axis direction. Since the comb tooth arrangement orders of the two groups of detection capacitor arrays are opposite, during the translation process, the movable comb teeth 9 of X1C11 approach the fixed comb teeth 10, increasing the area of the plates of the detection capacitor array, while the movable comb teeth 9 of X2C12 separate from the fixed comb teeth 10, decreasing the area of the plates of the detection capacitor array. As a result, the capacitance value of X1C11 increases and the capacitance value of X2C12 decreases. Conversely, when an acceleration in the negative X-axis direction is applied, the capacitance value of X1C11 decreases and the capacitance value of X2C12 increases. Through signal processing differential calculation, the capacitance change amount caused by the X-axis acceleration can be obtained as (ΔX1C - ΔX2C), thereby calculating the X-axis acceleration and achieving decoupling of the X-axis from the Y-axis and Z-axis. When there is no acceleration in the Y-axis direction, the capacitance values of Y1C31 and Y2C32 are the same. When an acceleration in the positive Y-axis direction is applied, the lower mass block 35 translates in the positive Y-axis direction. Since the comb tooth arrangement orders of the two groups of detection capacitor arrays are opposite, during the translation process, the movable comb teeth 9 of Y1C31 approach the fixed comb teeth 10, increasing the area of the plates of the detection capacitor array, while the movable comb teeth 9 of Y2C32 separate from the fixed comb teeth 10, decreasing the area of the plates of the detection capacitor array. As a result, the capacitance value of Y1C31 increases and the capacitance value of Y2C32 decreases. Conversely, when an acceleration in the negative Y-axis direction is applied, the capacitance value of Y1C31 decreases and the capacitance value of Y2C32 increases. Through signal processing differential calculation, the capacitance change amount caused by the Y-axis acceleration can be obtained as (ΔY1C - ΔY2C), thereby calculating the Y-axis acceleration and achieving decoupling of the Y-axis from the X-axis and Z-axis.

[0120] Furthermore, the fixed comb teeth on the left and right sides of the rectangular anchor 5 of a single detection capacitor array are symmetrically arranged, and the movable comb teeth on both sides are asymmetrically arranged, so that a single detection capacitor can achieve decoupling of the X-axis and Y-axis accelerations.

[0121] In this embodiment, by setting the detection capacitor arrays in different directions to translate according to the corresponding detection directions, the detection of accelerations in different directions is realized, avoiding interference in other directions. Moreover, signal processing differential calculation effectively eliminates interference factors such as common-mode noise and temperature drift, improving the detection accuracy and stability. Since the fixed comb teeth on the left and right sides of a single detection capacitor array are connected to the same rectangular anchor 5, the stress of the rectangular anchor 5 will cause the capacitance values of the two groups of detection capacitor arrays in the same detection direction to increase for one and decrease for the other, and the change amounts are equal, and the total capacitance of the two groups of detection capacitor arrays remains unchanged. Thus, the zero bias caused by the stress at the connection of the rectangular anchor 5 can be eliminated, further improving the accuracy of the chip.

[0122] In an embodiment of the present application, the movable comb teeth and the fixed comb teeth of the Z-axis negative direction detection capacitor group and the Z-axis positive direction detection capacitor group are comb teeth with a height difference. The movable comb teeth 9 are low comb teeth 7, and the fixed comb teeth 10 are high comb teeth 8.

[0123] Among them, the comb tooth arrangement structure of the Z-axis negative direction detection capacitor group refers to Figure 7 as shown. Among them, the high comb teeth 8 are fixed comb teeth 10, and the low comb teeth 7 are movable comb teeth 9. When there is no acceleration, the lower surfaces of the high and low comb teeth are flush. The comb tooth arrangement structure of the Z-axis positive direction detection capacitor group refers to Figure 8 as shown. Among them, the high comb teeth 8 are fixed comb teeth 10, and the low comb teeth 7 are movable comb teeth 9. When there is no acceleration, the upper surfaces of the high and low comb teeth are flush.

[0124] Specifically, when subjected to an acceleration in the positive Z-axis direction, the upper mass block 15 and the lower mass block 35 translate in the positive Z-axis direction. The movable comb teeth 9 of the two groups of detection capacitors Z1-C13 and Z2-C14 approach the upper surface of the fixed comb teeth 10, and the areas of the plates of the lower surface detection capacitor group decrease, causing the capacitance values of Z1-C13 and Z2-C14 to decrease. The areas of the plates of the upper surface detection capacitor groups of Z1+C33 and Z2+C34 remain unchanged, resulting in the capacitance values of Z1+C33 and Z2+C34 remaining unchanged. Conversely, when subjected to an acceleration in the negative Z-axis direction, the movable comb teeth 9 of the two groups of detection capacitors Z1+C33 and Z2+C34 approach the lower surface of the fixed comb teeth 10, and the areas of the plates of the upper surface detection capacitor group decrease, causing the capacitance values of Z1+C33 and Z2+C34 to decrease. The areas of the plates of the lower surface detection capacitor groups of Z1-C13 and Z2-C14 remain unchanged, resulting in the capacitance values of Z1-C13 and Z2-C14 remaining unchanged. It can be obtained that the capacitance change amount caused by the Z-axis acceleration is (ΔZ1-C + ΔZ2-C - (ΔZ1+C + ΔZ2+C)), and thus the Z-axis acceleration can be calculated.

[0125] Furthermore, through the design of the comb teeth with a height difference, it is ensured that when the chip is subjected to an acceleration in the positive Z-axis direction, the maximum stroke of the movable comb teeth 9 of the upper functional layer 1 translating in the positive Z-axis direction acceleration does not exceed the height of the fixed comb teeth 10, that is, it will not exceed the upper surface of the upper wafer. Therefore, there is no need to add a top cover structure on the top of the upper functional layer 1, which is beneficial to reducing the thickness of the chip.

[0126] In this embodiment, by performing signal processing differential calculation on the capacitance value changes caused by accelerations in three directions, interference factors such as common-mode noise and temperature drift are effectively eliminated, thereby improving the detection accuracy and stability. Since there is a clear linear relationship between the capacitance value changes and the accelerations in three directions, the capacitance changes can be converted into acceleration values through simple linear calculations, thus simplifying the data processing process and further improving the detection accuracy. Moreover, this method has strong resistance to environmental factors such as external electromagnetic interference and temperature changes, ensuring accurate and stable acceleration measurement in complex environments.

[0127] This application also provides a manufacturing method for a three-axis acceleration chip, including:

[0128] Step 1, manufacturing the intermediate layer 2. The specific steps are as follows Figure 10 shown, including:

[0129] S11: Prepare a heavily doped silicon wafer as the intermediate layer 2.

[0130] S12: Use dry or wet etching to process shallow grooves and protrusions on the upper and lower surfaces of the wafer to form an intermediate shallow groove 22, an intermediate connection frame 21, an intermediate center protrusion 23 on the upper surface of the wafer, four intermediate protrusions 25, and four intermediate rectangular protrusions 24. The depth of the intermediate shallow groove 22 is used to define the maximum stroke of the sensitive structures of the upper functional layer 1 and the lower functional layer 3 on one side of the intermediate layer 2.

[0131] S13: Grow SiO2 layers on the upper and lower surfaces of the intermediate layer 2 wafer by thermal oxidation.

[0132] Step 2, manufacturing the upper functional layer 1. The specific steps are as follows Figure 11 shown, including:

[0133] S21: Prepare a heavily doped silicon wafer as the upper functional layer 1.

[0134] S22: The lower surfaces of the upper connection frame 16, the center anchor 51, the external anchor 53, and the rectangular anchor 52 of the upper functional layer 1 are respectively and fused-bonded with the upper surfaces of the intermediate connection frame 21, the intermediate center protrusion 23, the four intermediate protrusions 25, and the four intermediate rectangular protrusions 24 of the intermediate layer 2 through Si-SiO2 melting.

[0135] S23: Thin the wafer from one side of the upper functional layer 1 to the required thickness and polish it to achieve precise control of the thickness of the upper functional layer 1.

[0136] S24: Dry-etch a shallow groove on one side of the upper functional layer 1 to prepare for processing high and low comb capacitors of the sensitive structure.

[0137] S25: On one side of the upper functional layer 1, the processing of the acceleration-sensitive structure of the upper functional layer 1 is completed by DRIE etching.

[0138] Among them, the acceleration-sensitive structure is a comb structure of a detection capacitor group.

[0139] Step three, fabricating the lower functional layer 3. The specific steps are as follows Figure 12 shown, including:

[0140] S31: Prepare a heavily doped silicon wafer as the lower functional layer 3.

[0141] S32: Perform Si-SiO2 fusion bonding between the lower functional layer 3 and the lower surface of the intermediate connection frame 21 of the intermediate layer 2.

[0142] S33: Thin the wafer from one side of the lower functional layer 3 to the required thickness and polish it to achieve precise control of the thickness of the lower functional layer 3.

[0143] S34: Dry-etch a shallow groove on one side of the lower functional layer 3 to prepare for processing the high and low comb capacitors of the sensitive structure.

[0144] S35: On one side of the lower functional layer 3, the processing of the acceleration-sensitive structure of the lower functional layer 3 is completed by DRIE etching.

[0145] Among them, the acceleration-sensitive structure is a comb structure of a detection capacitor group.

[0146] Step four, fabricating the substrate layer 4. The specific steps are as follows Figure 13 shown, including:

[0147] S41: Prepare a heavily doped silicon wafer as the substrate layer 4.

[0148] S42: Use dry or wet etching to process shallow grooves and protrusions on the upper surface of the wafer to form a substrate shallow groove 42, a substrate connection frame 41, a substrate center protrusion 43 located on the upper surface of the wafer, four substrate protrusions 45, and four substrate rectangular protrusions 44. The depth of the substrate shallow groove 42 is used to define the maximum stroke of the sensitive structure of the lower functional layer 3 on one side of the substrate layer 4.

[0149] S43: Deposit a SiO2 layer on the upper surface of the substrate layer 4 wafer.

[0150] S44: Perform Si-SiO2 fusion bonding between the lower connection frame 41 of the lower functional layer 4, the lower surfaces of the central anchor 51, the external anchor 53, the rectangular anchor 52, and the upper surfaces of the substrate connection frame 41, the substrate center protrusion 43, the four substrate protrusions 45, and the four substrate rectangular protrusions 44 of the substrate layer 4 respectively.

[0151] In this embodiment, by fabricating an intermediate shallow trench 22 and an intermediate connection border 21 in the intermediate layer 2, the maximum stroke of the sensitive structures of the upper functional layer 1 and the lower functional layer 3 on one side of the intermediate layer 2 can be precisely controlled. This design ensures the accuracy and stability of the acceleration-sensitive structure, thereby improving the measurement accuracy of the chip. At the same time, during the fabrication of the upper functional layer 1 and the lower functional layer 3, the wafers are thinned to the required thickness from one side of the upper functional layer 1 and one side of the lower functional layer 3 respectively and polished, achieving precise control of the thicknesses of the upper and lower functional layers. This precise control helps to optimize the mechanical and electrical properties of the chip, improve the sensitivity and response speed of the chip. Moreover, this manufacturing method uses the Si-SiO2 fusion bonding technology to achieve a firm connection between the upper functional layer 1, the intermediate layer 2, the lower functional layer 3 and the substrate layer 4, improve the structural strength of the chip, optimize the electrical properties of the chip, and ensure the stability and reliability of the chip under harsh environments.

[0152] The embodiments of the present application have been described above. The above description is exemplary and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art in the technical field without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications or improvements to the technologies in the market, or to enable other ordinary skill in the art in the technical field to understand the embodiments disclosed herein.

Claims

1. A three-axis acceleration chip, characterized in that: It includes an upper functional layer, an intermediate layer, and a lower functional layer arranged in sequence from the top to the bottom of the three-axis acceleration chip; the upper functional layer is used to detect the acceleration in the X-axis direction and the negative Z-axis direction, the lower functional layer is used to detect the acceleration in the Y-axis direction and the positive Z-axis direction, and the intermediate layer is used to separate the upper functional layer and the lower functional layer; The upper functional layer at least includes an upper mass block, an upper connection frame, and an upper detection capacitor group. Among them, the upper mass block is fixedly connected to the upper connection frame through an upper elastic beam. The upper detection capacitor group includes two X-axis direction detection capacitor groups and two negative Z-axis direction detection capacitor groups. The two X-axis direction detection capacitor groups are etched on the upper mass block in mirror symmetry along the X-axis, and the two negative Z-axis direction detection capacitor groups are etched on the upper mass block in mirror symmetry along the Y-axis; The intermediate layer consists of an intermediate connection frame and an intermediate shallow groove. The intermediate shallow groove is etched on both the top and the bottom of the intermediate layer. The height of the intermediate connection frame is higher than that of the intermediate shallow groove. The intermediate shallow groove is located in the middle position of the intermediate layer and is wrapped by the intermediate connection frame; The lower functional layer at least includes a lower mass block, a lower connection frame, and a lower detection capacitor group. Among them, the lower mass block is fixedly connected to the lower connection frame through a lower elastic beam. The lower detection capacitor group includes two Y-axis direction detection capacitor groups and two positive Z-axis direction detection capacitor groups. The two Y-axis direction detection capacitor groups are etched on the lower mass block in mirror symmetry along the Y-axis, and the two positive Z-axis direction detection capacitor groups are etched on the lower mass block in mirror symmetry along the X-axis; Among them, the upper functional layer and the lower functional layer are etched and processed based on the same layout and process.

2. The triaxial acceleration chip according to claim 1, wherein: The three-axis acceleration chip further includes a substrate layer, which is located below the lower functional layer and consists of a substrate connection frame and a substrate shallow groove. The substrate connection frame and the substrate shallow groove are an integral body. The substrate shallow groove is located on the top of the substrate layer, and the substrate connection frame is higher than the substrate shallow groove; Among them, the substrate shallow groove is located in the middle position of the substrate layer and is wrapped by the substrate connection frame.

3. The triaxial acceleration chip according to claim 2, characterized in that, The intermediate shallow groove has an intermediate central boss, four intermediate bosses, and four intermediate rectangular bosses, which have the same height as the intermediate connection frame. The intermediate central boss, the four intermediate bosses, and the four intermediate rectangular bosses are an integral body. The intermediate boss is located in the middle position of the intermediate shallow groove on the top of the intermediate layer. The four intermediate bosses are respectively located at the four inner corners of the intermediate connection frame. For the four intermediate rectangular bosses, two are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis; The substrate shallow trench has a substrate center boss, four substrate bosses and four substrate rectangular bosses, which have the same height as the substrate connection frame. The substrate shallow trench, the substrate center boss, the four substrate bosses and the four substrate rectangular bosses form an integral body. The substrate center boss is located at the middle position of the substrate shallow trench. The four substrate bosses are respectively located at the four inner corners of the substrate connection frame. For the four substrate rectangular bosses, two of them are symmetrically arranged about the X-axis, and the other two are symmetrically arranged about the Y-axis.

4. The triaxial acceleration chip according to claim 3, characterized in that, The upper mass block and the lower mass block also have anchor points, which include a center anchor point, external anchor points and rectangular anchor points. The center anchor point is located at the center of the upper mass block and the lower mass block. The rectangular anchor points are located at the middle positions of each detection capacitor group. The external anchor points are located at the four inner corners of the upper connection frame and the lower connection frame. The center anchor point and the external anchor points are both fixedly connected to the elastic beams. All the anchor points have the same height as the connection frame.

5. The triaxial acceleration chip according to claim 4, wherein: Each detection capacitor group of the upper detection capacitor group and the lower detection capacitor group includes two groups of movable electrodes and two groups of fixed electrodes. The movable electrodes are composed of a plurality of movable comb teeth, and the fixed electrodes are composed of a plurality of fixed comb teeth. Among them, the movable comb teeth of the upper detection capacitor group are all fixedly connected to the upper mass block, the movable comb teeth of the lower detection capacitor group are all fixedly connected to the lower mass block, and the fixed comb teeth are respectively fixedly connected to the rectangular anchor points.

6. The triaxial acceleration chip according to claim 5, characterized in that, The upper functional layer, the intermediate layer, the lower functional layer and the substrate layer are bonded into an integral body. The intermediate layer is bonded to the lower surface of the upper connection frame and the upper surface of the lower connection frame through the intermediate connection frame. The substrate layer is bonded to the lower surface of the lower connection frame through the substrate connection frame. The lower surface of the center anchor point of the upper mass block is bonded to the upper surface of the intermediate center boss, and the lower surface of the center anchor point of the lower mass block is bonded to the upper surface of the substrate center boss. The lower surfaces of the four rectangular anchor points of the upper mass block are respectively bonded to the upper surfaces of the four intermediate rectangular bosses, and the lower surfaces of the four rectangular anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate rectangular bosses. The lower surfaces of the four external anchor points of the upper mass block are respectively bonded to the upper surfaces of the four intermediate bosses, and the lower surfaces of the four external anchor points of the lower mass block are respectively bonded to the upper surfaces of the four substrate bosses. Among them, the bonding method is the Si-SiO2 fusion bonding method.

7. The triaxial acceleration chip according to claim 6, wherein Each movable comb tooth and each fixed comb tooth are arranged in a cross pattern to form a comb electrode. A single detection capacitor group is composed of two groups of comb electrodes. There is a rectangular anchor point between the two groups of comb electrodes for connecting all the fixed comb teeth. The fixed comb teeth of every two groups of comb electrodes share one rectangular anchor point. All the movable comb teeth are connected to the mass block. Among them, in the same detection direction, the comb tooth arrangement orders of the two detection capacitor groups are opposite.

8. The triaxial acceleration chip according to claim 6, wherein The movable comb teeth and fixed comb teeth of the X-axis direction detection capacitor group and the Y-axis direction detection capacitor are of the same height.

9. The triaxial acceleration chip according to claim 6, characterized in that, The movable comb teeth and fixed comb teeth of the Z-axis negative direction detection capacitor group and the Z-axis positive direction detection capacitor group are of different heights, with the movable comb teeth being the lower ones and the fixed comb teeth being the higher ones.

10. A manufacturing method of a three-axis acceleration chip, characterized in that, Applied to the three-axis acceleration chip according to any one of claims 1-9, it includes: Step 1, manufacturing the intermediate layer. Step 1 specifically includes: Prepare a heavily doped silicon wafer as the intermediate layer; Use dry or wet etching to process shallow grooves and protrusions on the upper and lower surfaces of the wafer to form intermediate shallow grooves and intermediate connection frames, an intermediate central protrusion on the upper surface of the wafer, four intermediate protrusions, and four intermediate rectangular protrusions. The depth of the intermediate shallow grooves is used to define the maximum stroke of the sensitive structures of the upper functional layer and the lower functional layer on one side of the intermediate layer; Grow SiO2 layers on the upper and lower surfaces of the intermediate layer wafer by thermal oxidation; Step 2, manufacturing the upper functional layer. Step 2 specifically includes: Prepare a heavily doped silicon wafer as the upper functional layer; The upper connection frame of the upper functional layer, the lower surfaces of the central anchor point, the external anchor points, and the rectangular anchor points are respectively melt-bonded to the upper surfaces of the intermediate connection frame, the intermediate central protrusion, the four intermediate protrusions, and the four intermediate rectangular protrusions of the intermediate layer through Si-SiO2; Thin the wafer from one side of the upper functional layer to the required thickness and polish it to achieve precise control of the thickness of the upper functional layer; Dry-etch a shallow groove on one side of the upper functional layer to prepare for processing the high-low comb teeth capacitors of the sensitive structure; Complete the processing of the acceleration sensitive structure of the upper functional layer by DRIE etching on one side of the upper functional layer; Step 3, manufacturing the lower functional layer. Step 3 specifically includes: Prepare a heavily doped silicon wafer as the lower functional layer; The lower functional layer is melt-bonded to the lower surface of the intermediate connection frame of the intermediate layer through Si-SiO2; Thin the wafer from one side of the lower functional layer to the required thickness and polish it to achieve precise control of the thickness of the lower functional layer; Dry-etch a shallow groove on one side of the lower functional layer to prepare for processing the high-low comb teeth capacitors of the sensitive structure; Complete the processing of the acceleration sensitive structure of the lower functional layer by DRIE etching on one side of the lower functional layer; Step 4, manufacturing the substrate layer. Step 4 specifically includes: Prepare a heavily doped silicon wafer as the substrate layer; Use dry or wet etching to process shallow grooves and protrusions on the upper surface of the wafer to form substrate shallow grooves and substrate connection frames, a substrate central protrusion on the upper surface of the wafer, four substrate protrusions, and four substrate rectangular protrusions. The depth of the substrate shallow grooves is used to define the maximum stroke of the sensitive structure of the lower functional layer on one side of the substrate layer; Deposit a SiO2 layer on the upper surface of the substrate layer wafer; The lower connection frame of the lower functional layer, the lower surfaces of the central anchor point, the external anchor points, and the rectangular anchor points are respectively melt-bonded to the upper surfaces of the substrate connection frame, the substrate central protrusion, the four substrate protrusions, and the four substrate rectangular protrusions of the substrate layer through Si-SiO2.

Images