Electric leakage path positioning method, testing system, positioning device and medium

Abstract

The invention discloses an electric leakage path positioning method, a test system, a positioning device and a medium, and relates to the technical field of chip design. And determining a first processor and a power supply chip connected with the source leakage pin based on the acquisition of the source leakage pin and the target leakage pin of the leakage chip. The voltage output state of the power supply output pin corresponding to the power supply chip is determined through the power supply power-off processing of the electric leakage chip, and the power supply output pin will have no voltage output. A target electric leakage pin of the electric leakage chip is converted from an original output line in a power output pin as a load pin to a current state into a state that a power attribute participates in or logic operation of a voltage output state. Or logical operation is carried out according to the voltage output states of the target electric leakage pin and the power supply output pin to obtain an operation result, calculation is carried out by replacing an actual voltage value with the voltage output states, tracing and troubleshooting can be rapidly and effectively carried out by adopting basic logical operation, and positioning of an electric leakage path existing in the electric leakage phenomenon is completed.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a leakage path positioning method, a test system, a positioning device and a medium. Background Art

[0002] At present, some chips on the market have leakage, that is, the output voltage from the chip's general purpose input / output pin (GPIO) is fed to the chip's power input terminal, thus affecting the function of the product to which the chip belongs. It is impossible to simulate the leakage of the entire design circuit during the schematic design stage, and it is time-consuming and laborious for circuit designers to manually distinguish.

[0003] After designing the circuit schematic, it is impossible to simulate the leakage of the designed circuit, and actual measurement can only be performed after the product is completed. When leakage anomalies occur, circuit designers rely on manual investigation of each pin and corresponding path of the corresponding chip, which increases the cost and time cost of manual investigation, and also reduces the efficiency of locating and investigating the leakage path. If the problem cannot be solved, the product will be re-produced, further increasing the cost of product development, and even corresponding to product project delays.

[0004] Therefore, how to improve the efficiency of locating and troubleshooting the leakage path of products caused by chip leakage and reduce the cost is an urgent problem that technical personnel in this field need to solve. Summary of the invention

[0005] The purpose of the present invention is to provide a leakage path positioning method, a test system, a positioning device and a medium to solve the problems of high leakage path detection cost and low detection efficiency for leakage phenomena.

[0006] In order to solve the above technical problems, the present invention provides a method for locating a leakage path, comprising:

[0007] Obtaining the source leakage pin and the target leakage pin of the leakage chip; and determining the first processor and the power chip connected to the source leakage pin; wherein the first processor is connected to the power chip; and the power chip is connected to the target leakage pin of the leakage chip through the power output pin;

[0008] Powering off the power supply of the leakage chip, and determining the voltage output state of the power output pin based on the output state of the enable pin of the first processor;

[0009] An operation result is obtained by performing an OR logic operation according to the voltage output states corresponding to the target leakage pin and the power output pin, so as to determine the external leakage paths of the source leakage pin and the target leakage pin according to the operation result.

[0010] On the one hand, powering off the power supply of the leakage chip and determining the voltage output state of the power output pin based on the output state of the enable pin of the first processor include:

[0011] In the case of power-off processing, obtaining a voltage output state of an enable pin of the first processor connected to the power chip and a voltage output state of a power input pin corresponding to the power chip;

[0012] Performing an AND logic operation according to the voltage output state of the enable pin and the voltage input state of the power input pin to obtain a first operation result;

[0013] Determine the working state of the power chip according to the first operation result;

[0014] When the working state of the power chip is 0, determining that there is no voltage signal on the power output pin;

[0015] The voltage output state corresponding to the power output pin is set to 0.

[0016] On the other hand, when it is determined that the voltage output state of the power output pin is 0, the pin attribute of the target leakage pin is changed from a load attribute to a power attribute, and the voltage output state of the target leakage pin is consistent with the output state of the source leakage pin; wherein, the voltage output state of the pin corresponding to the power attribute participates in an OR logic operation; the voltage output state of the pin corresponding to the load attribute does not participate in an OR logic operation.

[0017] On the other hand, determining the external leakage paths of the source leakage pin and the target leakage pin according to the calculation result includes:

[0018] If the calculation result is 1, it is determined that leakage occurs in the connection line between the first processor, the power chip and the power chip corresponding to the source leakage pin and the target leakage pin, and the connection line between the first processor, the power chip and the leakage chip is used as the leakage path.

[0019] On the other hand, the process of determining the leakage chip includes:

[0020] Obtaining attribute information of each pin of each test chip;

[0021] Detecting the property information of each of the pins by a leakage analyzer to obtain leakage parameters corresponding to each of the pins;

[0022] A leakage chip is determined in each of the test chips according to the leakage parameter.

[0023] On the other hand, the attribute information at least includes the pin withstand voltage value, the power rail corresponding to each pin, and the pin type; the attribute information of each pin is detected by a leakage analyzer to obtain the leakage parameters corresponding to each pin, including:

[0024] Applying a first voltage value to each of the pins to obtain a second voltage value of a power rail corresponding to each of the pins; wherein the first voltage value is less than the pin withstand voltage value;

[0025] If the second voltage value is not 0, the pin corresponding to the second voltage value not 0 is used as a leakage pin;

[0026] The chip model to which each of the pins belongs, the pin number corresponding to each of the pins in the test chip, the pin configuration, the pin voltage, the power rail, the leakage pin and the leakage state are used as the leakage parameters corresponding to each of the pins.

[0027] On the other hand, before detecting the attribute information of each pin by a leakage analyzer to obtain the leakage parameter corresponding to each pin, the method further includes:

[0028] Acquire a leakage parameter database in advance; wherein the leakage parameter database pre-stores the leakage parameters of the initial test chip;

[0029] Determining whether there is a chip model of the test chip in the leakage parameter database;

[0030] If not, the process proceeds to the step of detecting the property information of each of the pins by a leakage analyzer to obtain leakage parameters corresponding to each of the pins.

[0031] In order to solve the above technical problems, the present invention also provides a leakage path test system, the test system includes a test device and a host computer; the leakage detector includes a leakage chip, a first processor and a power chip; the leakage chip is connected to the first processor through a source leakage pin; the first processor is connected to the power chip; the power chip is connected to the target leakage pin of the leakage chip through a power output pin;

[0032] The host computer is connected to the leakage detector to execute the steps of the leakage path positioning method described above.

[0033] In order to solve the above technical problems, the present invention further provides a leakage path positioning device, comprising:

[0034] Memory for storing computer programs;

[0035] The second processor is used to implement the steps of the leakage path locating method when executing the computer program.

[0036] In order to solve the above technical problem, the present invention also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the leakage path locating method as described above are implemented.

[0037] The beneficial effect of the present invention is that, firstly, based on the acquisition of the source leakage pin and the target leakage pin of the leakage chip, the first processor and the power chip connected to the source leakage pin are determined, so that the connection line between the power chip and the leakage chip is based on the connection between the power output pin of the power chip and the target leakage pin of the leakage chip. Secondly, by powering off the power supply (i.e., the total power supply) of the leakage chip, the voltage output state of the power output pin corresponding to the power chip is determined based on the output state of the enable pin of the first processor, and its power output pin will have no voltage output. At this time, the target leakage pin of the leakage chip is transformed from the original output line from the power output pin as a load pin to the current power attribute participating in the voltage output state or logic operation. Finally, according to the voltage output state of each target leakage pin and the power output pin, the operation result is obtained by performing an or logic operation, and the actual voltage value is replaced by the voltage output state for calculation. The basic logic operation can be used to quickly and effectively trace and troubleshoot, and the leakage path where the leakage phenomenon exists can be located. In summary, in the leakage path troubleshooting scenario when leakage occurs in the schematic design stage and the leakage simulation stage after the circuit schematic is designed, leakage simulation test is performed according to the circuit schematic, and the leakage path is located by simulating the power-off process, and leakage simulation detection is implemented to find out the potential leakage path in time, so as to simplify the operation data of each chip and reduce the simulation requirements to prevent leakage from occurring during actual use. Compared with manual troubleshooting, it saves troubleshooting costs and R&D costs and improves troubleshooting efficiency. In the leakage path troubleshooting scenario when the chip actually leaks, the actual voltage value is replaced by basic logic operation data to improve troubleshooting efficiency.

[0038] In addition, the present invention also provides a leakage path testing system, a leakage path positioning device and a medium, which have the same beneficial effects as the above-mentioned leakage path positioning method. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A flow chart of a method for locating a leakage path provided by an embodiment of the present invention;

[0041] Figure 2 A schematic diagram of analog connection of a chip provided by an embodiment of the present invention;

[0042] Figure 3 A method based on the embodiment of the present invention is provided Figure 2 Simulated power-on timing diagram;

[0043] Figure 4 A method based on the embodiment of the present invention is provided Figure 2 Simulated power-off timing diagram;

[0044] Figure 5 A schematic diagram of the positioning principle of a leakage path provided by an embodiment of the present invention;

[0045] Figure 6 A flow chart of a leakage parameter database determined by using a leakage analyzer for detection provided by an embodiment of the present invention;

[0046] Figure 7 A structural diagram of a leakage path positioning device provided by an embodiment of the present invention;

[0047] Figure 8 A structural diagram of a leakage path positioning device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0048] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] The core of the present invention is to provide a leakage path positioning method, a test system, a positioning device and a medium to solve the problems of high leakage path detection cost and low detection efficiency for leakage phenomena.

[0050] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0051] Some chips on the market have leakage, which causes the entire product to malfunction. Users need to manually troubleshoot to find the leakage path during actual application, which increases the cost and time of manual troubleshooting, causes the product to be re-produced, and even causes the project delivery time to be delayed. The leakage path positioning method provided by the present invention can solve the above technical problems.

[0052] Figure 1 A flowchart of a method for locating a leakage path provided by an embodiment of the present invention is shown in FIG. Figure 1 As shown, the method includes:

[0053] S11: Acquire the source leakage pin and the target leakage pin of the leakage chip; and determine the first processor and the power chip connected to the source leakage pin;

[0054] Wherein, the first processor is connected to the power chip; the power chip is connected to the target leakage pin of the leakage chip through the power output pin;

[0055] S12: powering off the power supply of the leakage chip, and determining the voltage output state of the power output pin based on the output state of the enable pin of the first processor;

[0056] S13: performing an OR logic operation according to the voltage output states corresponding to the target leakage pin and the power output pin to obtain an operation result, so as to determine the external leakage path of the source leakage pin and the target leakage pin according to the operation result.

[0057] Specifically, the application scenario of this embodiment can be applied to the schematic diagram stage to perform leakage simulation on the entire chip design circuit to determine the external leakage path between the leakage pins, and add components to the connection circuit corresponding to the leakage path to avoid leakage. It can also be applied to the scene of checking and locating the leakage path after the leakage phenomenon actually occurs during actual use, etc., which is not limited here. It is worth noting that the current leakage simulation is a simulation of the chip schematic circuit design through the simulation program of the host computer. Regarding the actual leakage path investigation, it can be based on the connection between the host computer and the chip design circuit to conduct the host computer investigation. It should be noted that the leakage path does not correspond to the flow path of the current inside the chip, but the current path of the connection circuit corresponding to other chips involved between the source leakage pin and the target leakage pin.

[0058] The determination of the leakage chip can be based on searching the corresponding database stored in multiple test chips to see whether the leakage parameters of each pin corresponding to each test chip are in a leakage state. If so, the test chip to which it belongs is used as the leakage chip. It can also be based on a new test chip to measure the leakage parameters of each pin in real time through a leakage analyzer to determine whether there is a leakage state, etc., which is not limited here. It can be understood that the existence of the database is also determined by actually measuring each pin of multiple test chips in advance using a leakage analyzer.

[0059] The source leakage pins and target leakage pins of the leakage chip appear in pairs. There may be one or more corresponding source leakage pins in the leakage parameters of a leakage chip, and the number of its corresponding target leakage pins will also correspond to one or more, and there will also be one or more corresponding leakage paths.

[0060] Figure 2 A schematic diagram of a chip simulation connection provided by an embodiment of the present invention, such as Figure 2 As shown, the connection devices of the chip are generally divided into three types of devices, the chip itself, the first processor that issues control instructions to the chip, and the power chip that manages the chip, so as to realize the actual functional operation of the chip. Figure 2 The input-output (IO) level conversion chip can be located inside the leakage chip or can be set up separately as a leakage chip. Its timing control chip is connected to the power chip and the first processor. The role of the timing control chip here is to assist in checking the leakage path by simulating the timing changes corresponding to each pin during the power-on and power-off process.

[0061] The source leakage pin and the target leakage pin are led out from the first processor by the source leakage pin, and the target leakage pin is led into the leakage chip. Here, the first processor and the power chip connected by the source leakage pin are determined, which corresponds to the direct connection between the first processor and the leakage chip, and the power chip connected by the source leakage pin is indirectly connected, such as Figure 2 As shown, it is based on the direct connection between the first processor and the power chip. The power chip is connected to the target leakage pin of the leakage chip through the power output pin. Taking the leakage of the PIN7 pin (source leakage pin) of the IO level conversion chip of IC2 of the leakage chip integrated circuit (IC) to the PIN2 pin (target leakage pin) of the IO level conversion chip as an example, the first processor is connected to the power chip through the enable pin (PIN4 pin), and the power output pin of the power chip (the pin that outputs the voltage corresponding to 1V8) is connected to the target leakage pin (PIN2_1V8 pin) of the leakage chip. Table 1 is based on Figure 2 The chip leakage parameter table is shown in Table 1. After the IC is tested by the leakage detector, the corresponding leakage pin is PIN7 pin, and the target leakage pin is PIN2_1V8 pin.

[0062] Table 1

[0063]

[0064] When there is no leakage in the chip, Figure 2In the power-on process, after the main power supply is supplied, the timing control IC starts to work and generates a specific timing enable signal output to PowerIC2 and PowerIC3. When the enable signal EN1 is output to PowerIC2, PowerIC2 generates a 3V3 power output, and then when the enable signal EN2 is output to PowerIC3, PowerIC3 generates a 1V2 power output. The microcontroller unit (MCU) starts to work normally. After the MCU works normally, it controls PIN4 to output an enable signal to Power_IC1, generates a 1V8 power supply, and IC2 and the IO level conversion IC start to work. In the normal power-off process, the MCU first pulls down the PIN4 enable signal, PowerIC1 stops working, the 1V8 power disappears, and IC2 and the IO level conversion IC stop working. Due to the need for data preservation, only when the MCU detects that IC2 stops working, the MCU will notify the timing control chip through PIN2 to pull down the EN2 signal first, PowerIC3 stops working, the 1V2 power disappears, and the MCU stops working. When the EN1 signal is pulled low, PowerIC2 stops working, the 3V3 power supply disappears, and the entire system enters a sleep state.

[0065] It is worth noting that the first processor may be an MCU or other devices with control logic, which is not limited here.

[0066] Since chip IC2 is a leakage chip, its corresponding IO level conversion chip is located on chip IC2, which has leakage. In the corresponding power-off process, different scenarios can be processed here. If the current application scenario is a leakage simulation scenario, the corresponding power-off process is a simulated power-off process. If the current application scenario is an actual scenario where leakage has occurred, the power-off process is a real power-off process.

[0067] The power-off process of the leakage chip in this embodiment is to pull down the level of the enable pin of the first processor, which corresponds to no voltage signal on the power output pin of the connected power chip Power IC, and also corresponds to the voltage output state represented by binary code as 0.

[0068] When there is no voltage signal at the power output pin, since the power output pin and the target leakage pin are in the same connection line, it is impossible to supply power to the leakage chip for load. However, there is leakage at the target leakage pin, and the voltage output state of the actual target leakage pin is a voltage signal output, which is encoded in binary as 1. The voltage output states corresponding to the target leakage pin and the power output pin are respectively or logically operated to obtain the operation result, which is 1, corresponding to the connection line between the first processor and the power chip, the connection line between the power chip and the leakage chip, and the connection line between the first processor and the leakage chip as the leakage path.

[0069] A method for locating a leakage path provided by an embodiment of the present invention obtains a source leakage pin and a target leakage pin in a leakage chip; and determines a first processor and a power chip connected to the source leakage pin; wherein the first processor is connected to the power chip; the power chip is connected to the target leakage pin of the leakage chip through a power output pin; the power of the leakage chip is powered off, and the voltage output state of the power output pin is determined based on the output state of the enable pin of the first processor; an OR logic operation is performed according to the voltage output states corresponding to the target leakage pin and the power output pin to obtain an operation result, so as to determine the leakage path outside the source leakage pin and the target leakage pin according to the operation result. First, based on the acquisition of the source leakage pin and the target leakage pin of the leakage chip, the first processor and the power chip connected to the source leakage pin are determined, so as to obtain that the connection line between the power chip and the leakage chip is based on the power output pin of the power chip and the target leakage pin of the leakage chip. Secondly, by powering off the power supply (i.e., the total power supply) of the leakage chip, the voltage output state of the power output pin corresponding to the power chip is determined based on the output state of the enable pin of the first processor, and its power output pin will have no voltage output. At this time, the target leakage pin of the leakage chip is changed from the original output line from the power output pin, as a load pin, to the current power attribute participating in the voltage output state OR logic operation. Finally, the operation result is obtained by performing OR logic operation according to the voltage output state of the target leakage pin and the power output pin, and the actual voltage value is replaced by the voltage output state for calculation. The basic logic operation can be used to quickly and effectively trace and troubleshoot, and the leakage path where the leakage phenomenon exists is located. In summary, in the leakage path troubleshooting scenario corresponding to the schematic design stage and the leakage simulation stage after the circuit schematic is designed, the leakage simulation test is performed according to the circuit schematic, and the leakage path is located by simulating the power-off process, and the leakage simulation detection is realized to find out the potential leakage path in time, so as to simplify the operation data of each chip and reduce the simulation requirements, so as to prevent leakage from occurring during actual use. Compared with the manual troubleshooting method, it saves the troubleshooting cost and R&D cost and improves the troubleshooting efficiency. In the leakage path troubleshooting scenario corresponding to the chip when the leakage phenomenon actually occurs, the actual voltage value is replaced by the data of basic logic operation to improve the troubleshooting efficiency.

[0070] In some embodiments, powering off the power supply of the leakage chip and determining the voltage output state of the power output pin based on the output state of the enable pin of the first processor include:

[0071] In the case of power-off processing, obtaining a voltage output state of an enable pin connected to the power chip of the first processor and a voltage output state of a power input pin corresponding to the power chip;

[0072] Performing an AND logic operation according to the voltage output state of the enable pin and the voltage input state of the power input pin to obtain a first operation result;

[0073] Determine the working state of the power chip according to the first operation result;

[0074] When the working state of the power chip is 0, it is determined that there is no voltage signal on the power output pin;

[0075] Set the voltage output state corresponding to the power output pin to 0.

[0076] Specifically, Figure 2 As shown, during the power-off process, the first processor is connected to the power chip through the enable signal corresponding to the enable pin, which is given to the power chip. During the normal power-on process, the voltage output state of the enable signal of the enable pin is a voltage signal. During the power-off process, the first processor pulls down the enable signal, and the voltage output state of the enable signal of the enable pin is a no-voltage signal. The power input pin and the enable pin are connected to the same line, and the voltage input state of the power input pin is a no-voltage signal, so the power chip stops working. The presence or absence of the voltage signal corresponding to the voltage output state is represented by binary coding, with a voltage signal of "1" and a no-voltage signal of "0". The voltage output state of the enable pin and the voltage input state of the power input pin of the AND logic operation are both "0", which corresponds to the first operation result that the working state of the power chip is stopped working. At this time, combined with Figure 2 For example, the 1V8 power outputted by the corresponding power output pin disappears, that is, the voltage output state of the power output pin is a no-voltage signal, and the corresponding binary code is set to 0.

[0077] The process of determining the voltage output state of the power output pin provided in this embodiment is that after power-off processing, it corresponds to no voltage signal on the voltage output pin, which is expressed in binary coding to facilitate subsequent logical operations and save computing costs.

[0078] In some embodiments, when it is determined that the voltage output state of the power output pin is 0, the pin attribute of the target leakage pin is changed from a load attribute to a power attribute, and the voltage output state of the target leakage pin is consistent with the output state of the source leakage pin; wherein, the voltage output state of the pin corresponding to the power attribute participates in an OR logic operation; the voltage output state of the pin corresponding to the load attribute does not participate in an OR logic operation.

[0079] Specifically, the power output pin and the target leakage pin are connected to the same line, which corresponds to the situation where leakage exists. However, under normal circumstances, the pin attribute of the target leakage pin is a load attribute, and the load attribute requires the connection of a load resistor, that is, an external signal source needs to be connected, as an input type pin, it serves as a power input. The power attribute is used to provide power or grounding, corresponding to the power output. Since there is leakage at the current target leakage pin, the pin attribute corresponding to the target leakage pin is converted to a power attribute, and there is a voltage signal. The voltage output state of the target leakage pin is consistent with the output state of the source leakage pin, that is, the voltage output state is set to 1 using binary coding. In this embodiment, the voltage output state corresponding to the power attribute of the PIN pin attribute is distinguished from the participation in the OR logic operation, and the voltage output state corresponding to its load attribute does not participate in the OR operation.

[0080] In this embodiment, when the voltage output state of the power output pin is 0, the pin attribute of the target leakage pin changes from a load attribute to a power attribute, so as to participate in the subsequent "OR logic" operation.

[0081] In some embodiments, determining the external leakage paths of the source leakage pin and the target leakage pin according to the calculation result includes:

[0082] If the operation result is 1, it is determined that leakage occurs in the connection line between the first processor, the power chip and the leakage chip corresponding to the source leakage pin and the target leakage pin, and the connection line between the first processor, the power chip and the leakage chip is used as a leakage path.

[0083] Specifically, the operation result is determined by performing an OR logic operation on the voltage output states corresponding to the target leakage pin and the power output pin, and the power output state of the target leakage pin is 1, that is, there is an output of a voltage signal. The power output state of the source leakage pin is 0, and the operation result obtained by the corresponding OR logic operation is 1, which confirms that there is a leakage phenomenon at present, corresponding to the leakage path being the connection line between the first processor, the power chip and the leakage chip externally connected to the source leakage pin and the target leakage pin.

[0084] Combination Figure 2 From the above, we can see that the source leakage pin of the leakage parameter is PIN7 pin, the target leakage pin is PIN2_1V8 pin, and the corresponding leakage path is the connection line between PIN4 pin of the first processor and PIN4_EN pin of the power chip PowerIC1, the connection line between the power output pin 1V8 pin of the power chip PowerIC1 and the PIN2_1V8 pin corresponding to the IO level conversion chip, and the connection line from PIN7 pin of the first processor to the IO level conversion chip.

[0085] In addition, in addition to the interface display of the host computer, the presentation process of the leakage path can also be assisted by the timing control method. In the normal power-off process, the MCU first pulls down the PIN4 enable signal, PowerIC1 stops working, the 1V8 power disappears, and IC2 and the IO level conversion IC stop working. Due to the need for data preservation, only when the MCU detects that IC2 stops working, the MCU will notify the timing control chip through PIN2 to first pull down the EN2 signal, PowerIC3 stops working, the 1V2 power disappears, and the MCU stops working. After pulling down the EN1 signal, PowerIC2 stops working, and the 3V3 power disappears. The entire system enters a dormant state.

[0086] The normal power-on process is: after the main power supply is supplied, the timing control IC starts to work, and generates a specific timing enable signal output to PowerIC2 and PowerIC3. When the enable signal EN1 is output to PowerIC2, PowerIC2 generates a 3V3 power output, and then when the enable signal EN2 is output to PowerIC3, PowerIC3 generates a 1V2 power output. The MCU starts to work normally. After the MCU works normally, the control PIN4 outputs the enable signal to Power_IC1, generates a 1V8 power supply, and IC2 and the IO level conversion IC start to work. Figure 3 A method based on the embodiment of the present invention is provided Figure 2 The simulated power-on timing diagram is as follows: Figure 3 As shown, the input time of the total power supply is set to 0s, EN1 of the timing control IC is 10ms, EN2 is 20ms, and the power startup time of PowerIC1, 2 and PowerIC3 is 5ms.

[0087] When power-off simulation is performed, due to the leakage inside the IO level conversion chip, that is, the PIN7 pin leaks 3V voltage to the PIN2 pin, which will cause a 3V voltage to exist on all device pins connected to PIN2, that is, 1. When the MCU pulls down the EN of PowerIC1 through PIN4, the 1V8 power output does disappear. However, the 3V voltage of the IO level conversion chip will continue to power PIN2 of IC2. The result of the "OR" logic operation of this pin during software simulation is still 1, which will cause IC2 to work all the time. However, the MCU cannot perform the power-off process because it detects that IC2 is working all the time. Figure 4 A method based on the embodiment of the present invention is provided Figure 2 The simulated power-off timing diagram is as follows: Figure 4 As shown, the level signal of the corresponding PIN4_EN pin is a low level signal, and the level signals of the corresponding other pins are high level signals.

[0088] This embodiment provides a method for determining the external leakage path of the source leakage pin and the target leakage pin according to the calculation result, using binary code to replace the actual voltage value, and the operation of the IC chip is an AND operation. Only when all conditions (power supply, enable) are 1, the IC works (the state is 1). The leakage behavior of the IC chip is simulated by performing an "OR" operation on all connected PIN pins in the circuit. When leakage actually occurs, the corresponding operation result is 1, which simplifies the simulation operation data, reduces the requirements for simulation, and improves the troubleshooting efficiency.

[0089] In some embodiments, the process of determining the leakage chip includes:

[0090] Obtaining attribute information of each pin of each test chip;

[0091] The property information of each pin is detected by a leakage analyzer to obtain the leakage parameters corresponding to each pin;

[0092] The leakage chip is determined in each test chip based on the leakage parameters.

[0093] Specifically, the determination of the leakage chip is based on the existence of the corresponding leakage pin under the leakage parameter, and the corresponding test chip. The attribute information of the pin is based on the subsequent testing process of the leakage analyzer corresponding to the attribute information of the pin. First, the power supply pins of the test chip are normally powered. The test chip can be placed on the leakage analyzer, and the leakage data of each pin is recorded according to the detection. The recorded leakage data is used as the leakage parameter to determine whether there is a leakage pin. If so, the test chip with the leakage pin will be used as a leakage chip.

[0094] The leakage chip determination process provided in this embodiment improves the accuracy of leakage pin testing based on the leakage parameters measured by the leakage analyzer. At the same time, it also lays the foundation for determining the leakage path in the subsequent simulation of leakage phenomena and provides an important basis.

[0095] In some embodiments, the attribute information includes at least the pin withstand voltage value, the power rail corresponding to each pin, and the pin type; the attribute information of each pin is detected by a leakage analyzer to obtain the leakage parameters corresponding to each pin, including:

[0096] Applying a first voltage value to each pin to obtain a second voltage value of a power rail corresponding to each pin; wherein the first voltage value is less than the pin withstand voltage value;

[0097] If there is a second voltage value that is not 0, the pin corresponding to the second voltage value that is not 0 is used as a leakage pin;

[0098] The chip model to which each pin belongs, the pin number corresponding to each pin in the test chip, the pin configuration, the pin voltage, the power rail, the leakage pin and the leakage state are used as the leakage parameters corresponding to each pin.

[0099] Specifically, during the detection process using the leakage analyzer, it mainly applies a first voltage value to each pin, where the first voltage value is less than the pin withstand voltage value. The probe on the power rail in the attribute information of each pin is used for detection to obtain the second voltage value of the power rail corresponding to each pin. If the second voltage value is 0, it means that there is no leakage to the corresponding power rail. If the second voltage value is not 0, it means that the chip corresponding to the pin has leakage, and the pin is regarded as a leakage pin, that is, there is an abnormal voltage value.

[0100] The leakage parameter determination process provided in this embodiment is based on the comparison of the leakage analyzer corresponding to the abnormal voltage value, so as to facilitate the discovery of potential leakage paths in the subsequent leakage simulation process.

[0101] In some embodiments, before detecting the property information of each pin by a leakage analyzer to obtain the leakage parameter corresponding to each pin, the method further includes:

[0102] Acquire a leakage parameter database in advance; wherein the leakage parameter database pre-stores the leakage parameters of the initial test chip;

[0103] Determining whether the chip model of the test chip exists in the leakage parameter database;

[0104] If not, the process proceeds to the step of detecting the property information of each pin by a leakage analyzer to obtain the leakage parameters corresponding to each pin.

[0105] Specifically, before determining the leakage parameters, the process of acquiring the leakage parameters corresponding to the current test chip is based on a pre-established leakage parameter database, which is used to store the leakage parameters of the test chip. For determining the leakage parameters of the current test chip, it is necessary to check whether the chip model of the current test chip exists in the leakage parameter database. If it exists, the next test chip can be found for detection. If it does not exist, it means that it is a new test chip and can be obtained directly through the leakage analyzer.

[0106] It should be noted that in order to make the leakage parameters of the test chip in the leakage parameter database consistent and to facilitate the subsequent unified investigation, the leakage parameters of the test chip already stored in the leakage parameter database are also obtained through the leakage analyzer.

[0107] Before determining the leakage parameters of the current test chip provided in this embodiment, a comparison is first made with other test chips in the leakage parameter database to prevent repeated determination of the leakage parameters and improve the detection efficiency of the leakage parameters.

[0108] Figure 5 A schematic diagram of the positioning principle of a leakage path provided by an embodiment of the present invention, such as Figure 5 As shown, for the design stage of the schematic diagram, for a new IC chip, first check whether the parameters of the IC chip exist in the device library. If so, it means that the IC chip already exists in the device library, which means it is an old IC chip, and directly call the device library module to configure the pins of the IC chip. If it does not exist, measure it through the leakage analyzer and summarize its leakage parameters into the library. At the same time, set the pin type of the IC chip, and the leakage path can be determined through the power-on and power-off timing relationship to output the result.

[0109] Leakage analyzer: An instrument specifically used for chip leakage analysis. Place the chip on the leakage analyzer, set the configuration of each pin through the software, input the voltage value, automatically perform leakage detection on all pins of the chip, and generate the library leakage parameters corresponding to the chip.

[0110] Device library module: For the chips used in the design, the leakage analyzer can be used to automatically detect the leakage pins of the chips. Each chip only needs to be tested once, and the test results are saved to automatically form the leakage device library parameters. The parameters include various pin configuration parameters of the chip and their corresponding leakage parameters. There is no need to repeat the test when using the chip in the future.

[0111] Schematic simulation module: Import the complete schematic and automatically identify the chip used in the schematic. If the chip exists in the device library, all the pin configuration parameters and leakage parameters of the chip can be directly called. If the chip does not exist in the device library, leakage analysis must be performed through a leakage analyzer to form pin configuration and leakage parameters. According to the actual usage scenario, the pin configuration parameters of the chip can be selected to set the overall power-on and power-off timing. Finally, all possible leakage configurations and paths are obtained through simulation.

[0112] The specific steps are as follows:

[0113] First, import the designed complete schematic diagram. The system will automatically identify all chip models contained in the schematic diagram and compare them with the existing chip models in the device library. If the chip model already exists in the system, the system will directly call the leakage parameter configuration of the chip. If the chip model does not exist in the system, it can be tested through the leakage analyzer to automatically generate the leakage parameter configuration of the chip. Table 2 is a chip leakage parameter table. As shown in Table 2, the chip model, pin attribute information and corresponding leakage parameters are set. The leakage parameters here mainly include chip model, pin number, pin configuration, pin voltage, leakage and corresponding leakage pin and leakage status.

[0114] Table 2

[0115]

[0116] If the chip model does not exist in the system, you can place the physical chip in the leakage analyzer and set the chip pin configuration through the software. The leakage analyzer will automatically detect the chip leakage and generate the corresponding leakage parameters. At the same time, the chip pin configuration and corresponding leakage parameters will be saved in the device library.

[0117] After extracting the leakage parameters of all chips in the schematic, the possible leakage paths under various power-on and power-off sequences can be simulated by setting the overall power-on and power-off sequences of the schematic (simulating the power-on and power-off sequences under different system-on-chip (SOC) configurations).

[0118] Figure 6 A flowchart of a leakage parameter database determined by using a leakage analyzer is provided in an embodiment of the present invention, such as Figure 6 As shown, including:

[0119] S21: Set the current chip pin attributes;

[0120] S22: Start testing;

[0121] S23: chip power supply pin power supply;

[0122] S24: calling the pin test program for testing;

[0123] S25: record pin test data;

[0124] S26: Determine whether all pin tests are completed, if yes, proceed to step S27, if no, return to step S24;

[0125] S27: Forming a leakage database of the current chip.

[0126] Furthermore, the present invention also provides a leakage path test system, the test system comprising a test device and a host computer; the test device comprising a leakage chip, a first processor and a power chip; the leakage chip is connected to the first processor via a source leakage pin; the first processor is connected to the power chip; the power chip is connected to a target leakage pin of the leakage chip via a power output pin;

[0127] The host computer is connected to the testing device to execute the steps of the above leakage path positioning method.

[0128] It should be noted that this embodiment corresponds to a test scenario. In combination with the above embodiments, it can be based on a pure software simulation scenario to find out potential leakage path problems in the schematic design stage without the need for a physical stage. The test scenario in this embodiment can be based on the sample situation. Before the chips are mass-produced, there is a leakage detector. The connection relationship corresponding to the leakage detector is the same as the connection relationship between the leakage chip, the first processor and the power chip in the above embodiments, which will not be repeated here.

[0129] It is connected to the leakage detector through the upper computer, and performs the investigation and positioning of the leakage path of the leakage detector.

[0130] It should be noted that the leakage detector detects the leakage of the chip, and the detection of the overall leakage path at the board level is performed through simulation.

[0131] For an introduction to a leakage path testing system provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. The system has the same beneficial effects as the above leakage path locating method.

[0132] The above describes in detail various embodiments corresponding to the method for locating a leakage path. On this basis, the present invention also discloses a leakage path locating device corresponding to the above method. Figure 7 A structural diagram of a leakage path positioning device provided by an embodiment of the present invention. Figure 7 As shown, the leakage path positioning equipment includes:

[0133] The acquisition module 11 is used to acquire the source leakage pin and the target leakage pin of the leakage chip; and determine the first processor and the power chip connected to the source leakage pin; wherein the first processor is connected to the power chip; and the power chip is connected to the target leakage pin of the leakage chip through the power output pin;

[0134] A first determining module 12, configured to power off the power supply of the leakage chip and determine a voltage output state of a power output pin based on an output state of an enable pin of the first processor;

[0135] The second determination module 13 is used to perform an OR logic operation according to the voltage output states corresponding to the target leakage pin and the power output pin to obtain an operation result, so as to determine the external leakage path of the source leakage pin and the target leakage pin according to the operation result.

[0136] Since the embodiments of the device part correspond to the above embodiments, please refer to the description of the embodiments of the method part for the embodiments of the device part, and will not be repeated here.

[0137] For an introduction to a leakage path locating device provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. It has the same beneficial effects as the above leakage path locating method.

[0138] Figure 8 A structural diagram of a leakage path positioning device provided by an embodiment of the present invention, such as Figure 8 As shown, the device comprises:

[0139] A memory 21, used for storing computer programs;

[0140] The second processor 22 is used to implement the steps of the leakage path location method when executing the computer program.

[0141] The leakage path positioning device provided in this embodiment may include but is not limited to a tablet computer, a laptop computer, or a desktop computer.

[0142] Among them, the second processor 22 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The second processor 22 can be implemented in at least one hardware form of a digital signal processor (DSP), a field-programmable gate array (FPGA), and a programmable logic array (PLA). The second processor 22 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the second processor 22 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the second processor 22 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0143] The memory 21 may include one or more computer-readable storage media, which may be non-transitory. The memory 21 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 21 is at least used to store the following computer program 211, wherein, after the computer program is loaded and executed by the second processor 22, it can implement the relevant steps of the leakage path locating method disclosed in any of the aforementioned embodiments. In addition, the resources stored in the memory 21 may also include an operating system 212 and data 213, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 212 may include Windows, Unix, Linux, etc. The data 213 may include but is not limited to data involved in the leakage path locating method, etc.

[0144] In some embodiments, the leakage path positioning device may further include a display screen 23 , an input / output interface 24 , a communication interface 25 , a power supply 26 , and a communication bus 27 .

[0145] Those skilled in the art can understand that Figure 8 The structure shown in the figure does not constitute a limitation on the positioning device of the leakage path, and may include more or less components than those shown in the figure.

[0146] The second processor 22 implements the leakage path locating method provided by any of the above embodiments by calling the instructions stored in the memory 21 .

[0147] For an introduction to a leakage path positioning device provided by the present invention, please refer to the above method embodiment, and the present invention will not be repeated here. It has the same beneficial effects as the above leakage path positioning method.

[0148] Furthermore, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by the second processor 22, the steps of the method for locating the leakage path as described above are implemented.

[0149] It is understandable that if the method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium to execute all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0150] For an introduction to a computer-readable storage medium provided by the present invention, please refer to the above method embodiment, which will not be described in detail herein. The present invention has the same beneficial effects as the above leakage path locating method.

[0151] The above is a detailed introduction to a method for locating a leakage path, a test system, a positioning device and a medium provided by the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referenced to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the present invention.

[0152] It should also be noted that, in this specification, relational terms such as first and second, etc. are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

Claims

1. A method for locating a leakage path, characterized in that: include: Obtaining the source leakage pin and the target leakage pin of the leakage chip; and determining the first processor and the power chip connected to the source leakage pin; wherein the first processor is connected to the power chip; and the power chip is connected to the target leakage pin of the leakage chip through the power output pin; Powering off the power supply of the leakage chip, and determining the voltage output state of the power output pin based on the output state of the enable pin of the first processor; An operation result is obtained by performing an OR logic operation according to the voltage output states corresponding to the target leakage pin and the power output pin, so as to determine the external leakage paths of the source leakage pin and the target leakage pin according to the operation result.

2. The method for locating a leakage path according to claim 1, characterized in that: Powering off the power supply of the leakage chip and determining the voltage output state of the power output pin based on the output state of the enable pin of the first processor include: In the case of power-off processing, obtaining a voltage output state of an enable pin of the first processor connected to the power chip and a voltage output state of a power input pin corresponding to the power chip; Performing an AND logic operation according to the voltage output state of the enable pin and the voltage input state of the power input pin to obtain a first operation result; Determine the working state of the power chip according to the first operation result; When the working state of the power chip is 0, determining that there is no voltage signal on the power output pin; The voltage output state corresponding to the power output pin is set to 0.

3. The method for locating a leakage path according to claim 2, characterized in that: When it is determined that the voltage output state of the power output pin is 0, the pin attribute of the target leakage pin is changed from a load attribute to a power attribute, and the voltage output state of the target leakage pin is consistent with the output state of the source leakage pin; wherein, the voltage output state of the pin corresponding to the power attribute participates in an OR logic operation; the voltage output state of the pin corresponding to the load attribute does not participate in an OR logic operation.

4. The method for locating a leakage path according to claim 3, characterized in that: Determining the external leakage paths of the source leakage pin and the target leakage pin according to the calculation result includes: If the calculation result is 1, it is determined that leakage occurs in the connection line between the first processor, the power chip and the power chip corresponding to the source leakage pin and the target leakage pin, and the connection line between the first processor, the power chip and the leakage chip is used as the leakage path.

5. The method for locating a leakage path according to claim 1, characterized in that: The process of determining the leakage chip includes: Obtaining attribute information of each pin of each test chip; Detecting the property information of each of the pins by a leakage analyzer to obtain leakage parameters corresponding to each of the pins; A leakage chip is determined in each of the test chips according to the leakage parameter.

6. The method for locating a leakage path according to claim 5, characterized in that: The attribute information includes at least the pin withstand voltage value, the power rail corresponding to each pin, and the pin type; Detecting the property information of each of the pins by a leakage analyzer to obtain leakage parameters corresponding to each of the pins, including: Applying a first voltage value to each of the pins to obtain a second voltage value of a power rail corresponding to each of the pins; wherein the first voltage value is less than the pin withstand voltage value; If the second voltage value is not 0, the pin corresponding to the second voltage value not 0 is used as a leakage pin; The chip model to which each of the pins belongs, the pin number corresponding to each of the pins in the test chip, the pin configuration, the pin voltage, the power rail, the leakage pin and the leakage state are used as the leakage parameters corresponding to each of the pins.

7. The method for locating a leakage path according to claim 6, characterized in that: Before detecting the property information of each pin by a leakage analyzer to obtain the leakage parameters corresponding to each pin, the method further includes: Acquire a leakage parameter database in advance; wherein the leakage parameter database pre-stores the leakage parameters of the initial test chip; Determining whether there is a chip model of the test chip in the leakage parameter database; If not, the process proceeds to the step of detecting the property information of each of the pins by a leakage analyzer to obtain leakage parameters corresponding to each of the pins.

8. A leakage path testing system, characterized in that: The test system includes a test device and a host computer; the leakage detector includes a leakage chip, a first processor and a power chip; the leakage chip is connected to the first processor through a source leakage pin; the first processor is connected to the power chip; the power chip is connected to the target leakage pin of the leakage chip through a power output pin; The host computer is connected to the leakage detector to execute the steps of the leakage path positioning method described in any one of claims 1 to 7 above.

9. A leakage path positioning device, characterized in that: include: Memory for storing computer programs; The second processor is used to implement the steps of the leakage path locating method as claimed in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method for locating a leakage path according to any one of claims 1 to 7 are implemented.

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