Power loop control duration determination method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a power loop control duration determination method, electronic equipment and a storage medium. The power supply loop control parameter determination method comprises the following steps: detecting working parameters of multi-path output voltage; judging whether the working parameter of each path of output voltage in the multiple paths of output voltage meets a preset requirement or not; configuring a loop control coefficient of each path of output voltage according to a judgment result; and determining the loop control duration of the multi-path output voltage based on the loop control coefficient. According to the scheme of the embodiment, the loop control coefficient is adjusted under the condition that an external circuit is not added, so that the loop control duration is adjusted through adjustment of the loop control coefficient, the loop response speed of the residual output voltage is increased, and the dynamic performance is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of power supplies, and in particular to a method for determining a power loop control duration, an electronic device, and a storage medium. Background Art

[0002] For power supplies with multiple output voltages, the following solutions are currently available: one is that one chip controls only one output voltage, and multiple output voltages require multiple chips to control. The other is that each output voltage is controlled by an independent loop, which runs in sequence. The loop control time of each output voltage is the same, and the implemented loop control time is the cumulative sum of the loop control time of each output voltage. After setting, it is fixed and unchanged to ensure that the loop control of each output voltage is completed. Summary of the invention

[0003] Embodiments of the present disclosure provide a method for determining a power loop control duration, an electronic device, and a storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides a method for determining a power loop control duration, the method comprising:

[0005] Detect the working parameters of multiple output voltages;

[0006] Determining whether an operating parameter of each of the multiple output voltages meets preset requirements;

[0007] configuring a loop control coefficient of each output voltage according to the judgment result;

[0008] The loop control duration of the multiple output voltages is determined based on the loop control coefficient.

[0009] In a second aspect, an embodiment of the present disclosure provides an electronic device, the electronic device comprising:

[0010] one or more processors;

[0011] A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the power loop control duration determination method;

[0012] One or more input / output I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

[0013] In a third aspect, an embodiment of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method for determining the power loop control duration is implemented.

[0014] The disclosed embodiment detects the operating parameters of multiple output voltages and configures the loop control coefficient of each output voltage according to whether the operating parameters meet preset requirements, thereby adjusting the loop control coefficient without adding an external circuit, and determining the loop control duration of the multiple output voltages based on the loop control coefficient, thereby adjusting the loop control duration, improving the loop response speed of the remaining output voltages, and improving the dynamic performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In the accompanying drawings of the embodiments of the present disclosure:

[0016] Figure 1 A flow chart of a method for determining a power loop control duration provided by an embodiment of the present disclosure;

[0017] Figure 2 A block diagram of the electronic device provided in the embodiment of the present disclosure;

[0018] Figure 3 A block diagram of the computer-readable storage medium provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to enable those skilled in the art to better understand the technical solution of the present disclosure, the communication perception data processing method and computer-readable storage medium provided by the embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0020] The present disclosure will be described more fully below with reference to the accompanying drawings, but the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as being limited to the embodiments set forth below. On the contrary, the purpose of providing these embodiments is to make the present disclosure thorough and complete, and will enable those skilled in the art to fully understand the scope of the present disclosure.

[0021] The accompanying drawings of the embodiments of the present disclosure are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used together with the detailed embodiments to explain the present disclosure, and do not constitute a limitation of the present disclosure. By describing the detailed embodiments with reference to the accompanying drawings, the above and other features and advantages will become more apparent to those skilled in the art.

[0022] The present disclosure may be described with reference to plan views and / or cross-sectional views by means of ideal schematic views of the present disclosure. Therefore, the exemplary illustrations may be modified according to manufacturing techniques and / or tolerances.

[0023] In the absence of conflict, the various embodiments of the present disclosure and the various features therein may be combined with each other.

[0024] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure. The term "and / or" as used in the present disclosure includes any and all combinations of one or more related enumerated items. The singular forms "one" and "the" as used in the present disclosure are also intended to include plural forms, unless the context clearly indicates otherwise. The terms "including", "made of..." as used in the present disclosure specify the presence of the features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof.

[0025] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meaning as commonly understood by those of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless explicitly defined in this disclosure.

[0026] The present disclosure is not limited to the embodiments shown in the drawings, but includes modifications of the configurations formed based on the manufacturing process. Therefore, the regions illustrated in the drawings have schematic properties, and the shapes of the regions shown in the drawings illustrate the specific shapes of the regions of the elements, but are not intended to be limiting.

[0027] For power supplies with multiple output voltages, the following solutions are currently available:

[0028] One is that one chip controls only one output voltage, and multiple output voltages require multiple chips to control. This solution will increase the cost and area of ​​the multiple output voltage power supply.

[0029] The other is that each output voltage is controlled by an independent loop and runs in sequence. The loop control time of each output voltage is the same. The implemented loop control time is the cumulative sum of the loop control time of each output voltage. It is fixed after setting to ensure that the loop control of each output voltage is completed. Since the implemented loop control time is the cumulative sum of the loop control time of each output voltage and remains unchanged, when a certain output voltage is in an abnormal working state or a certain output voltage is in a fault protection state, the loop response speed of the remaining normal output voltage is fixed and cannot be improved or optimized.

[0030] The disclosed embodiment detects the operating parameters of multiple output voltages and configures the loop control coefficient of each output voltage according to whether the operating parameters meet preset requirements, thereby adjusting the loop control coefficient without adding an external circuit, and determining the loop control duration of the multiple output voltages based on the loop control coefficient, thereby adjusting the loop control duration, improving the loop response speed of the remaining output voltages, and improving the dynamic performance.

[0031] The power loop control duration determination method of the embodiment of the present disclosure can be executed by any electronic device that needs to perform power loop control duration adjustment, such as a terminal device or a server. The terminal device may include but is not limited to: vehicle-mounted equipment, user equipment (UE), mobile equipment, computing equipment, wearable devices, etc., for example, including but not limited to cellular phones, cordless phones, personal digital assistants (PDA), portable computers, etc. The power loop control duration determination method can be implemented by a processor calling a computer-readable program instruction stored in a memory, or it can be implemented by a server.

[0032] The following is a detailed introduction to the embodiments of the present disclosure.

[0033] The present disclosure provides a method for determining the power loop control duration. Figure 1 As shown, the method may include steps S11 to S14:

[0034] Step S11, detecting the operating parameters of the multiple output voltages.

[0035] The embodiments of the present disclosure relate to the field of power supplies, and in particular to a power supply control loop in which a chip controls multiple output voltages, each output voltage having an independent control loop, and the control loops between the output voltages do not affect each other.

[0036] In the embodiment of the present disclosure, the operating parameter may include but is not limited to a voltage value and / or an operating status identification bit.

[0037] In the embodiment of the present disclosure, the voltage value and / or the working status identification bit of each output voltage may be detected respectively.

[0038] Step S12: determining whether the operating parameters of each output voltage among the multiple output voltages meet the preset requirements.

[0039] In the embodiment of the present disclosure, when the operating parameter includes a voltage value and / or an operating status identification bit, determining whether the operating parameter of each output voltage among the multiple output voltages meets the preset requirements may include:

[0040] Determine whether the voltage value of each output voltage is within a preset voltage range; and,

[0041] Determine whether the working state identification bit of each output voltage is a preset normal state identification bit.

[0042] In the disclosed embodiment, the voltage values ​​of multiple output voltages can be detected in real time, and then the voltage value of each output voltage can be compared to see whether it is within a preset voltage range. The preset voltage range can be defined according to the needs, and the detailed values ​​of the preset voltage range are not limited. For example, it can include but is not limited to: a voltage range within ±10% of the preset voltage setting value, and the range includes a voltage value within ±10% of the voltage setting value.

[0043] In the embodiment of the present disclosure, the preset voltage setting value refers to a continuously constant output voltage after being processed and having a stable value.

[0044] In the disclosed embodiment, the working state identification bits of multiple output voltages can be detected in real time, and then it is determined whether the working state identification bit of each output voltage is a normal state identification bit. The normal state identification bit can be defined according to the needs, and the detailed representation method of the normal state identification bit is not limited. For example, it can be represented by a digital identification 1.

[0045] Step S13: configuring the loop control coefficient of each output voltage according to the judgment result.

[0046] In the embodiment of the present disclosure, when the working parameters include a voltage value and a working status flag, configuring the loop control coefficient of each output voltage according to the judgment result may include: performing the following operations for any output voltage:

[0047] When the voltage value of any output voltage is within a preset voltage range and the working state identification bit of any output voltage is a normal state identification bit, the loop control coefficient of each output voltage is set to the first coefficient.

[0048] In the embodiment of the present disclosure, there is no limitation on the specific value of the first coefficient, which can be defined according to the requirements.

[0049] In the embodiment of the present disclosure, the first coefficient may satisfy: greater than 0, and less than or equal to 1.

[0050] In the embodiment of the present disclosure, for example, the first coefficient may be 1. When it is detected that the voltage value of the first output voltage is within ±10% (including ±10%) of the voltage setting value and the working state identification bit is the normal working identification bit, the loop control coefficient K1 of the first output voltage is configured to be 1 (first coefficient); when it is detected that the voltage value of the second output voltage is within ±10% (including ±10%) of the voltage setting value and the working state identification bit is the normal working identification bit, the loop control coefficient K2 of the second output voltage is configured to be 1 (first coefficient).

[0051] In the embodiment of the present disclosure, when the working parameters include a voltage value and a working status flag, configuring the loop control coefficient of each output voltage according to the judgment result also includes: performing the following operations for any output voltage:

[0052] When the voltage value of any output voltage is not within the preset voltage range and / or the working state identification bit of any output voltage is not the normal state identification bit, the loop control coefficient of any output voltage is set to a second coefficient; the second coefficient is smaller than the first coefficient.

[0053] In the embodiment of the present disclosure, there is no limitation on the detailed value of the second coefficient, which can be defined according to the requirements.

[0054] In the embodiment of the present disclosure, the second coefficient may satisfy: greater than or equal to 0, and less than 1.

[0055] In the embodiment of the present disclosure, the value of the second coefficient can be further subdivided and determined according to the situation that the voltage value of any output voltage is not within the preset voltage range and / or the working status identification bit of any output voltage is not the normal state identification bit.

[0056] In the embodiment of the present disclosure, when the voltage value of any output voltage is not within the preset voltage range, and / or the working state identification bit of any output voltage is not the normal state identification bit, setting the loop control coefficient of any output voltage to the second coefficient may include:

[0057] When the voltage value of any output voltage is not within the preset voltage range and the working state identification bit of any output voltage is the normal state identification bit, and when the voltage value of any output voltage is within the preset voltage range and the working state identification bit of any output voltage is not the normal state identification bit, setting the loop control coefficient of any output voltage to the third coefficient;

[0058] When the voltage value of any output voltage is not within the preset voltage range, and the working status identification bit of any output voltage is not the normal status identification bit, the loop control coefficient of any output voltage is set to the fourth coefficient; the third coefficient is greater than the fourth coefficient; the second coefficient includes the third coefficient and the fourth coefficient.

[0059] In an embodiment of the present disclosure, for example, when the load power of a certain output voltage is reduced and the output voltage value is within a preset voltage range and enters an energy-saving working state, the corresponding working state identification bit is set. After detecting this abnormal working state identification bit, the loop control coefficient of the output voltage of the path can be set to the third coefficient.

[0060] In the embodiment of the present disclosure, the third coefficient may be greater than 0 and less than 1. For example, the third coefficient may be 0.5.

[0061] In the embodiment of the present disclosure, the fourth coefficient may satisfy the condition that it is greater than or equal to 0 and less than the third coefficient. For example, the fourth coefficient may be 0.

[0062] In the embodiment of the present disclosure, for example, when it is detected that the working status identification bit of the first output voltage is an abnormal working identification bit, and the output voltage is within ±10% (including ±10%) of the voltage setting value, the loop control coefficient K1 of the first output voltage is 0.5 (the third coefficient); when it is detected that the voltage value of the third output voltage is within ±10% (including ±10%) of the voltage setting value and the working status identification bit is an abnormal working identification bit, the loop control coefficient K3 of the third output voltage can be configured to be 0.5 (the third coefficient).

[0063] In the embodiment of the present disclosure, for example, when it is detected that the working status flag of the second output voltage is an abnormal working status flag and the output voltage value is outside the voltage setting value ±10%, the loop control coefficient K2 of the second output is configured to be 0 (the fourth coefficient).

[0064] In the embodiment of the present disclosure, when the operating parameter only includes the voltage value, the loop control coefficient of any output voltage can be set only according to whether the voltage value of any output voltage is within a preset voltage range.

[0065] In the embodiment of the present disclosure, when the operating parameters include voltage values, the loop control coefficient of each output voltage is configured according to the judgment result, including:

[0066] When the voltage value of any output voltage is within the preset voltage range, setting the loop control coefficient of each output voltage to the fifth coefficient;

[0067] When the voltage value of any output voltage is not within the preset voltage range, the loop control coefficient of each output voltage is set to a sixth coefficient; the sixth coefficient is smaller than the fifth coefficient.

[0068] There is no limitation on the specific values ​​of the fifth coefficient and the sixth coefficient, and they can be defined as required. For example, the fifth coefficient can be greater than 0 and less than or equal to 1, for example, the fifth coefficient can be 1.

[0069] In an embodiment of the present disclosure, when the voltage value of a certain output voltage exceeds a preset voltage range, the loop control coefficient of this output voltage can be reduced, and the loop control coefficient of this output voltage can be set to a sixth coefficient. The sixth coefficient can satisfy the requirement of being greater than or equal to 0 and less than 1. For example, the sixth coefficient can be 0.

[0070] In the embodiment of the present disclosure, when the working parameters only include the working state flag, the loop control coefficient of any output voltage can be set only according to whether the working state flag of any output voltage is a normal state flag.

[0071] In the embodiment of the present disclosure, when the working parameter includes a working state identification bit, configuring the loop control coefficient of each output voltage according to the judgment result may include:

[0072] When the working state identification bit of any output voltage is the normal state identification bit, the loop control coefficient of each output voltage is set to the seventh coefficient;

[0073] When the working state identification bit of any output voltage is not the normal state identification bit, the loop control coefficient of each output voltage is set to the eighth coefficient; the eighth coefficient is smaller than the seventh coefficient.

[0074] In the embodiment of the present disclosure, the detailed values ​​of the seventh coefficient and the eighth coefficient are not limited and can be defined as required. For example, the seventh coefficient can be greater than 0 and less than or equal to 1, for example, the seventh coefficient can be 1.

[0075] In an embodiment of the present disclosure, when the working status identification bit of a certain output voltage is not the normal status identification bit, the loop control coefficient of this output voltage can be reduced, and the loop control coefficient of this output voltage can be set to the eighth coefficient. The eighth coefficient can satisfy the requirement of being greater than or equal to 0 and less than 1. For example, the eighth coefficient can be 0.

[0076] Step S14: determining the loop control duration of the multiple output voltages based on the loop control coefficients.

[0077] In an embodiment of the present disclosure, determining the loop control duration of multiple output voltages based on the loop control coefficient may include:

[0078] Determining a first loop control duration of each output voltage based on a loop control coefficient;

[0079] The second loop control duration of the multiple output voltages is determined according to the first loop control duration of each output voltage.

[0080] In the embodiment of the present disclosure, the loop control duration of the multiple output voltages may refer to the loop control period, the first loop control duration refers to the first loop control period, and the second loop control duration refers to the second loop control period. Determining the first loop control duration of each output voltage based on the loop control coefficient includes:

[0081] Determine the operation time required for the control loop of each output voltage;

[0082] The operation duration is multiplied by the loop control coefficient corresponding to each output voltage to obtain the first loop control duration corresponding to each output voltage.

[0083] In the embodiment of the present disclosure, when the multiple output voltages include a first output voltage, a second output voltage, and a third output voltage, the operation time required for the control loop of the first output voltage is T1, the operation time required for the control loop of the second output voltage is T2, and the operation time required for the control loop of the third output voltage is T3. If the loop control coefficient of the first output voltage is obtained as K1, the loop control coefficient of the second output voltage is K2, and the loop control coefficient of the third output voltage is K3 through the aforementioned loop control coefficient determination scheme, then the first loop control time corresponding to the first output voltage is T1×K1, the second loop control time corresponding to the second output voltage is T2×K2, and the third loop control time corresponding to the third output voltage is T3×K3.

[0084] In the disclosed embodiment, in the process of adjusting the loop control coefficient of the multiple output voltages according to the working parameters of each output voltage, the first loop control duration of each output voltage is changed accordingly, thereby affecting the overall loop control duration (i.e., the second loop control duration) of the multiple output voltages, providing a technical basis for the overall performance adjustment of the multiple output voltages. For example, if the loop control coefficient of any one or more output voltages is reduced, the second loop control duration of the multiple output voltages controlled by a control chip will eventually become shorter, thereby improving the dynamic response speed of the remaining output voltages.

[0085] In the embodiment of the present disclosure, determining the second loop control duration of the multiple output voltages according to the first loop control duration may include:

[0086] The accumulated sum of the first loop control duration corresponding to each output voltage is obtained as the second loop control duration of the multiple output voltages.

[0087] In the embodiments of the present disclosure, for example, when the multiple output voltages include a first output voltage, a second output voltage and a third output voltage, the first loop control duration corresponding to the first output voltage is T1×K1, the second loop control duration corresponding to the second output voltage is T2×K2, and the third loop control duration corresponding to the third output voltage is T3×K3, the second loop control duration of the multiple output voltages is T=T1×K1+T2×K2+T3×K3.

[0088] In the disclosed embodiment, within the second loop control time, the loop operation unit can complete the loop operation of each output voltage, and the loop operation result is output to the power conversion unit to achieve power conversion.

[0089] In the embodiment of the present disclosure, for example, when it is detected that the voltage value of the first output voltage is within ±10% (including ±10%) of the voltage setting value and the working status identification bit is the normal working identification bit, the loop control coefficient K1 of the first output voltage is configured to be 1; when it is detected that the voltage value of the second output voltage is within ±10% (including ±10%) of the voltage setting value and the working status identification bit is the normal working identification bit, the loop control coefficient K2 of the second output voltage is configured to be 1; when it is detected that the voltage value of the third output voltage is within ±10% (including ±10%) of the voltage setting value and the working status identification bit is the abnormal working identification bit, the loop control coefficient K3 of the third output voltage is configured to be 0.5. The operation time required for the control loop of the first output voltage is T1, the operation time required for the control loop of the second output voltage is T2, and the operation time required for the control loop of the third output voltage is T3. The second loop control time for controlling multiple output voltages is equal to T=T1×K1+T2×K2+T3×K3=T1+T2+0.5T3, and the total loop control time is adjusted to T1+T2+0.5T3.

[0090] In the embodiment of the present disclosure, for example, when it is detected that the working status identification bit of the first output voltage is the normal working identification bit and the output voltage value is outside ±10% of the voltage setting value, or when it is detected that the working status identification bit of the first output voltage is the abnormal working identification bit and the output voltage is within ±10% (including ±10%) of the voltage setting value, the loop control coefficient K1 of the first output voltage is configured to be 0.5; when it is detected that the working status identification bit of the second output voltage is the abnormal working identification bit and the output voltage value is outside ±10% of the output voltage setting value, the loop control coefficient K2 of the second output is configured to be 0; when the working status identification bit of the third output voltage is the normal working identification bit and the output voltage is within ±10% (including ±10%) of the output voltage setting value, the loop control coefficient K3 of the third output voltage is configured to be 1. The operation time required for the control loop of the first output voltage is T1, the operation time required for the control loop of the second output voltage is T2, and the operation time required for the control loop of the third output voltage is T3. The second loop control time for controlling multiple output voltages is equal to T=T1×K1+T2×K2+T3×K3=0.5T1+T3, and the total loop control time is adjusted to 0.5T1+T3.

[0091] The disclosed embodiment scheme configures the loop control coefficient of each output voltage according to the voltage value and / or working status identification bit of each output voltage without adding external circuits, optimizes and improves the loop response speed of the remaining output voltages, and improves the dynamic performance of multiple output voltages.

[0092] In the disclosed embodiment, the detection module can detect the voltage value and / or the working status identification bit of each output voltage in real time, the judgment module can compare and judge the voltage value and the working status identification bit detected by the detection module, the configuration module can set the loop control coefficient of each output voltage according to the comparison and judgment result, the first determination module can calculate the first loop control duration of each output voltage according to the loop control coefficient of the output voltage, the second determination module can calculate the second loop control duration of multiple output voltages according to the first loop control duration, the loop operation module can perform loop control calculation on each output voltage within the second loop control duration, and output the calculation result to the power conversion module, and the power conversion module completes the power conversion.

[0093] The present disclosure also provides an electronic device 100, such as Figure 2 As shown, the electronic device 100 includes:

[0094] One or more processors 101;

[0095] A memory 102 having one or more programs stored thereon, and when the one or more programs are executed by the one or more processors 101, the one or more processors 101 implement the power loop control duration determination method;

[0096] One or more input / output I / O interfaces 103 are connected between the processor 101 and the memory 102 and are configured to implement information interaction between the processor 101 and the memory 102 .

[0097] Among them, the processor 101 is a device with data processing capabilities, including but not limited to a central processing unit (CPU) and the like; the memory 102 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH); the I / O interface (read-write interface) 103 is connected between the processor 101 and the memory 102, and can realize information interaction between the processor 101 and the memory 102, including but not limited to a data bus (Bus) and the like.

[0098] In some embodiments, the processor 101 , the memory 102 , and the I / O interface 103 are connected to each other via a bus 104 , and further connected to other components of the computing device.

[0099] The present disclosure also provides a computer-readable storage medium 200, such as Figure 3 As shown, a computer program is stored on the computer-readable storage medium 200, and when the computer program is executed by the processor, the method for determining the power loop control duration is implemented.

[0100] Those skilled in the art will appreciate that all or some of the functional modules / units disclosed above may be implemented as software, firmware, hardware, or a suitable combination thereof.

[0101] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation.

[0102] Some physical components or all physical components may be implemented as software executed by a processor, such as a central processing unit (CPU), a digital signal processor or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-temporary medium) and a communication medium (or temporary medium). As known to those of ordinary skill in the art, the term computer storage medium includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules or other data). Computer storage media include, but are not limited to, random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory (FLASH) or other disk storage; read-only compact disk (CD-ROM), digital versatile disk (DVD) or other optical disk storage; magnetic cassettes, magnetic tapes, disk storage or other magnetic storage; any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically embodies computer readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0103] The present disclosure has disclosed example embodiments, and although specific terms are employed, they are used and should be interpreted only in a general illustrative sense and not for limiting purposes. In some instances, it will be apparent to those skilled in the art that, unless otherwise expressly stated, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments. Therefore, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the scope of the present disclosure as set forth in the appended claims.

Claims

1. A method for determining the duration of a power loop control, It is characterized in that The method comprises: Detect the working parameters of multiple output voltages; Determining whether an operating parameter of each of the multiple output voltages meets preset requirements; configuring a loop control coefficient of each output voltage according to the judgment result; The loop control duration of the multiple output voltages is determined based on the loop control coefficient.

2. The method for determining the power loop control duration according to claim 1, It is characterized in that The operating parameters include voltage value and / or operating status identification bit; The determining whether the operating parameter of each output voltage among the multiple output voltages meets the preset requirements includes: Determine whether the voltage value of each output voltage is within a preset voltage range; and / or, It is determined whether the working state identification bit of each output voltage is a preset normal state identification bit.

3. The method for determining power loop control parameters according to claim 2, It is characterized in that In the case where the working parameter includes the voltage value and the working state identification bit, configuring the loop control coefficient of each output voltage according to the judgment result includes: performing the following operations for any output voltage: When the voltage value of any one of the output voltages is within the preset voltage range and the working state identification bit of any one of the output voltages is the normal state identification bit, the loop control coefficient of each of the output voltages is set to the first coefficient.

4. The method for determining the power loop control duration according to claim 3, It is characterized in that In the case where the working parameter includes the voltage value and the working state identification bit, configuring the loop control coefficient of each output voltage according to the judgment result further includes: performing the following operations for any output voltage: When the voltage value of any one of the output voltages is not within the preset voltage range, and / or the working status identification bit of any one of the output voltages is not the normal status identification bit, the loop control coefficient of any one of the output voltages is set to a second coefficient; the second coefficient is smaller than the first coefficient.

5. The method for determining the power loop control duration according to claim 4, It is characterized in that When the voltage value of any one of the output voltages is not within the preset voltage range, and / or the working state identification bit of any one of the output voltages is not the normal state identification bit, setting the loop control coefficient of any one of the output voltages to a second coefficient comprises: When the voltage value of any one of the output voltages is not within the preset voltage range and the working state identification bit of any one of the output voltages is the normal state identification bit, and when the voltage value of any one of the output voltages is within the preset voltage range and the working state identification bit of any one of the output voltages is not the normal state identification bit, setting the loop control coefficient of any one of the output voltages to a third coefficient; When the voltage value of any one of the output voltages is not within the preset voltage range and the working status identification bit of any one of the output voltages is not the normal status identification bit, the loop control coefficient of any one of the output voltages is set to the fourth coefficient; the third coefficient is greater than the fourth coefficient; and the second coefficient includes the third coefficient and the fourth coefficient.

6. The method for determining the power loop control duration according to claim 2, It is characterized in that In the case where the operating parameter includes the voltage value, configuring the loop control coefficient of each output voltage according to the judgment result includes: When the voltage value of any output voltage is within the preset voltage range, setting the loop control coefficient of each output voltage to the fifth coefficient; When the voltage value of any output voltage is not within the preset voltage range, the loop control coefficient of each output voltage is set to a sixth coefficient; and the sixth coefficient is smaller than the fifth coefficient.

7. The method for determining the power loop control duration according to claim 2, It is characterized in that In the case where the working parameter includes the working state identification bit, configuring the loop control coefficient of each output voltage according to the judgment result includes: When the working state identification bit of any output voltage is the normal state identification bit, setting the loop control coefficient of each output voltage to the seventh coefficient; When the working state identification bit of any output voltage is not the normal state identification bit, the loop control coefficient of each output voltage is set to the eighth coefficient; and the eighth coefficient is smaller than the seventh coefficient.

8. The method for determining the power loop control duration according to claim 1, It is characterized in that Determining the loop control duration of the multiple output voltages based on the loop control coefficients includes: Determining a first loop control duration of each output voltage based on the loop control coefficient; The second loop control duration of the multiple output voltages is determined according to the first loop control duration of each output voltage.

9. The method for determining the power loop control duration according to claim 8, It is characterized in that The determining the first loop control duration of each output voltage based on the loop control coefficient includes: Determining the operation time required for the control loop of each output voltage; The operation duration is multiplied by a loop control coefficient corresponding to each output voltage to obtain a first loop control duration corresponding to each output voltage.

10. The method for determining the power loop control duration according to claim 9, It is characterized in that The determining the second loop control duration of the multiple output voltages according to the first loop control duration includes: The accumulated sum of the first loop control durations corresponding to each output voltage is obtained as the second loop control duration of the multiple output voltages.

11. An electronic device, It is characterized in that The electronic device comprises: one or more processors; A memory having one or more programs stored thereon, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method for determining the power loop control duration according to any one of claims 1 to 10; One or more input / output I / O interfaces are connected between the processor and the memory and are configured to implement information interaction between the processor and the memory.

12. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method for determining the power loop control duration according to any one of claims 1 to 10.

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