Output voltage stabilizing circuit for LDO (Low Dropout Regulator), LDO, chip and electronic equipment

Abstract

The invention relates to the technical field of voltage stabilizing circuits, and discloses an output voltage stabilizing circuit for an LDO (low dropout regulator), the LDO, a chip and electronic equipment, the LDO adopts an off-chip capacitor-free design, the output voltage stabilizing circuit comprises a dummy load unit, the dummy load unit is arranged at the output end of the LDO; the LDO comprises a dummy load unit and a time sequence control unit, and the time sequence control unit is configured to control the dummy load unit to be started firstly under the condition that it is monitored that a load circuit of the LDO needs to be started, and control the load circuit to be started again after a first preset time is delayed, the current change slope when the load circuit is started is larger than the current change slope when the dummy load unit is started. By introducing the dummy load unit and combining the dummy load unit and the control time sequence of the load circuit, soft start of the LDO load is achieved on the premise that an external capacitor is not needed, the load transient response capacity of the LDO is greatly improved, and power consumption and cost do not need to be increased.

Description

Technical Field

[0001] The present application relates to the technical field of voltage stabilization circuits, and in particular to an output voltage stabilization circuit for an LDO, an LDO, a chip, and an electronic device. Background Art

[0002] LDO (Low Dropout Regulator) is a commonly used stable voltage source in chip circuits, mainly used to supply power to various functional modules in the chip to ensure the normal operation of the chip. When the load of the LDO has a large step (for example, some chips are set to sleep mode for low power design. When they suddenly return to normal state from sleep mode, the power consumption will rise rapidly from nearly 0 power consumption to mA level within us level time), an external capacitor is required to improve the load transient response capability of the LDO. However, an external capacitor type LDO needs to be connected to a capacitor in the board-level application system, which will increase the area of ​​the printed circuit board.

[0003] In the related art, the bandwidth of the LDO is also designed to be higher to improve the load transient response capability of the LDO, but this will lead to a significant increase in power consumption. Summary of the invention

[0004] The present application provides an output voltage stabilization circuit for an LDO, an LDO, a chip, and an electronic device, which solves the technical problem that a sudden change in chip load affects the stability of the LDO output voltage. By introducing a dummy load unit and combining the control timing of the dummy load unit and the load circuit, soft start and soft shutdown of the LDO load are achieved without an off-chip capacitor, which greatly improves the load transient response capability of the LDO without increasing power consumption and cost.

[0005] In order to achieve the above objectives, the main technical solutions adopted in this application include:

[0006] In a first aspect, an embodiment of the present application provides an output voltage stabilization circuit for an LDO, wherein the LDO adopts a design without external capacitors, and the output voltage stabilization circuit includes: a dummy load unit, wherein the dummy load unit is arranged at the output end of the LDO; a timing control unit, wherein the timing control unit is configured to control the dummy load unit to start first when it is detected that the load circuit of the LDO needs to be started, and control the load circuit to start again after a delay of a first preset time, wherein the current change slope when the load circuit is started is greater than the current change slope when the dummy load unit is started.

[0007] The output voltage stabilization circuit proposed in the embodiment of the present application is applied to an LDO designed without an external capacitor, and a dummy load unit is set at the output end of the LDO, and the dummy load unit is controlled to start first through the timing control unit, and then the load circuit is controlled to start after a delay of the first preset time, and the current change slope when the load circuit starts is greater than the current change slope when the dummy load unit starts, so that the LDO has sufficient time to respond to the load mutation. Therefore, the present application can realize the soft start of the LDO load without an external capacitor by controlling the startup timing of the dummy load unit and the load circuit and the current change rate at startup, which not only reduces the impact of the load mutation on the LDO voltage stabilization effect, ensures that the output voltage of the LDO remains stable, greatly improves the load transient response capability of the LDO, but also effectively saves the printed circuit board space of the chip circuit and reduces the chip power loss.

[0008] Optionally, in some embodiments of the present application, the output voltage stabilization circuit further includes: an off-chip load insertion detection unit, which is configured to detect whether an off-chip load is inserted to generate a detection signal; wherein, when the timing control unit determines that an off-chip load is inserted according to the detection signal, it determines that the load circuit of the LDO needs to be started.

[0009] Optionally, in some embodiments of the present application, the off-chip load insertion detection unit includes: a first resistor, one end of the first resistor is suitable for connecting to a detection pin; a second resistor, one end of the second resistor is connected to the other end of the first resistor and has a first node, and the other end of the second resistor is grounded; a first comparator, the positive input end of the first comparator is connected to the first node, the negative input end of the first comparator is suitable for connecting to a reference voltage, and the output end of the first comparator is used to output the detection signal.

[0010] The off-chip load insertion detection unit proposed in the embodiment of the present application forms a voltage divider circuit through a first resistor and a second resistor to detect a voltage change when an external load is inserted, and compares the voltage change with a reference voltage through a first comparator to determine whether an external load is inserted based on the comparison result, thereby being able to accurately identify the insertion of the off-chip load, and ensuring that the timing control unit promptly determines the startup requirement of the LDO load circuit when an off-chip load is inserted.

[0011] Optionally, in some embodiments of the present application, the timing control unit includes: a first delay module, which is configured to output a start signal after delaying the first preset time when it is determined according to the detection signal that an off-chip load is inserted; a control module, which is configured to control the dummy load unit to start when it is determined according to the detection signal that an off-chip load is inserted, and control the load circuit to start when the start signal is received.

[0012] The embodiment of the present application controls the dummy load unit to start first when it is determined that there is an off-chip load inserted through the control module, and controls the load circuit to delay for a period of time after starting the dummy load unit through the first delay module. Therefore, the embodiment of the present application starts the dummy load unit before starting the load circuit, so as to effectively buffer the impact of the load circuit startup on the LDO, realize the soft start of the LDO during the period when the load changes from zero to heavy load, reduce the LDO output voltage fluctuation caused by starting the load circuit, and improve the voltage stabilization effect of the LDO.

[0013] Optionally, in some embodiments of the present application, the timing control unit also includes: a second delay module, the second delay module is configured to output a shutdown signal after a delay of a second preset time when it is determined according to the detection signal that the off-chip load is unplugged; the control module is also configured to control the load circuit to be shut down when it is determined according to the detection signal that the off-chip load is unplugged, and control the dummy load unit to be shut down when the shutdown signal is received, wherein the current change slope when the dummy load unit is shut down is less than the current change slope when the load circuit is shut down.

[0014] In the embodiment of the present application, the control module controls the load circuit to be turned off first when it is determined that an off-chip load is unplugged, and controls the dummy load unit to be turned off after a delay of a period of time after the load circuit is turned off through the second delay module. Therefore, in the embodiment of the present application, the dummy load unit is turned off after the load circuit is turned off, so as to effectively buffer the impact of the load circuit turning off on the LDO, realize the soft shutdown of the LDO during the period when the load changes from heavy load to zero, avoid overshoot of the LDO output voltage, and improve the reliability of the LDO.

[0015] Optionally, in some embodiments of the present application, the first delay module includes: a first counter, an enable end of the first counter is connected to the output end of the off-chip load insertion detection unit; a first AND gate, a first input end of the first AND gate is connected to the first output end of the first counter, a second input end of the first AND gate is connected to the second output end of the first counter, and the output end of the first AND gate is used to output the start signal.

[0016] The embodiment of the present application uses a first counter to accurately time the first preset time in a clock counting manner, and generates an accurate start signal through a logic circuit composed of the first counter and the first AND gate, so as to achieve precise control of the start timing of the dummy load unit and the load circuit, thereby ensuring that the dummy load unit starts running before the load circuit starts, so as to achieve soft start of the LDO during the period when the load changes from zero to heavy load, reduce the LDO output voltage fluctuation caused by the sudden start of the load circuit, and greatly improve the voltage stabilization effect and reliability of the LDO.

[0017] Optionally, in some embodiments of the present application, the second delay module includes: a first inverter, the input end of the first inverter is connected to the output end of the off-chip load insertion detection unit; a second counter, the enable end of the second counter is connected to the output end of the first inverter; a second AND gate, the first input end of the second AND gate is connected to the first output end of the second counter, the second input end of the second AND gate is connected to the second output end of the second counter, and the output end of the second AND gate is used to output the shutdown signal.

[0018] In the embodiment of the present application, the second counter is used to accurately time the second preset time in a clock counting manner, and an accurate shutdown signal is generated by a logic circuit composed of the second counter, the first inverter, and the second AND gate, so as to achieve precise control of the shutdown timing of the dummy load unit and the load circuit, thereby ensuring that the dummy load unit is shut down after the load circuit is shut down, so as to achieve soft shutdown of the LDO during the period when the load changes from heavy load to zero, avoid the overshoot of the LDO output voltage caused by the sudden shutdown of the load circuit, and greatly improve the voltage stabilization effect and reliability of the LDO.

[0019] Optionally, in some embodiments of the present application, the control module includes:

[0020] a third AND gate, wherein a first input terminal of the third AND gate is connected to an output terminal of the external load insertion detection unit, a second input terminal of the third AND gate is adapted to receive the start signal, and an output signal of the third AND gate is used to control the start or shut down of the load circuit;

[0021] a second inverter, wherein an input terminal of the second inverter is adapted to receive the shutdown signal;

[0022] A first OR gate, wherein a first input end of the first OR gate is connected to an output end of the off-chip load insertion detection unit, a second input end of the first OR gate is connected to an output end of the second inverter, and an output signal of the first OR gate is used to control the start or stop of the dummy load unit.

[0023] In the embodiment of the present application, the logic circuit obtained by combining the third AND gate, the second inverter and the first OR gate responds promptly to the start signal and the shutdown signal to accurately control the start and shutdown of the dummy load unit, thereby improving the voltage stabilization effect of the LDO.

[0024] Optionally, in some embodiments of the present application, the timing control unit is further configured to control the dummy load unit to be turned off after the load circuit is started.

[0025] The embodiment of the present application can reduce unnecessary current consumption by controlling the dummy load unit to be turned off after the load circuit is started, thereby reducing the overall power consumption of the LDO when the LDO output voltage reaches a stable state.

[0026] Optionally, in some embodiments of the present application, the dummy load unit and the load circuit are respectively connected in parallel to the output end of the LDO.

[0027] In a second aspect, an embodiment of the present application provides an LDO, comprising: an output feedback circuit; an output voltage stabilization circuit according to the embodiment of the first aspect above, wherein the output voltage stabilization circuit is arranged corresponding to the output feedback circuit to buffer the voltage fluctuation of the output feedback circuit when a sudden change occurs in the load of the LDO.

[0028] The LDO proposed in the embodiment of the present application adopts a design without external capacitors, and timely detects the sudden change of the load through the above-mentioned output voltage stabilization circuit to buffer the voltage fluctuation of the output feedback circuit, thereby realizing soft start of the LDO load without the need for external capacitors, which not only reduces the impact of the sudden change of the load on the voltage stabilization effect of the LDO and ensures that the output voltage of the LDO remains stable, but also effectively saves the printed circuit board space of the chip circuit and reduces the chip power loss.

[0029] Optionally, in some embodiments of the present application, an on-chip capacitor is further provided at the output end of the LDO, and the on-chip capacitor is connected in parallel with the dummy load unit and the load circuit respectively.

[0030] In a third aspect, an embodiment of the present application provides a chip, including:

[0031] According to the LDO described in the embodiment of the second aspect, the LDO is suitable for providing power supply to the load circuit in the chip.

[0032] The chip proposed in the embodiment of the present application realizes soft start of the LDO load by adopting an LDO designed without external capacitors, thereby providing a stable power supply for the load circuit of the chip, which not only reduces the impact of load mutations on the LDO voltage stabilization effect and ensures that the output voltage of the LDO remains stable, but also effectively saves the printed circuit board space of the chip circuit and reduces the chip power loss.

[0033] In a fourth aspect, an embodiment of the present application provides an electronic device, including:

[0034] The output voltage stabilization circuit according to the embodiment of the first aspect; or

[0035] The LDO according to the embodiment of the second aspect; or

[0036] A chip according to the embodiment of the third aspect above.

[0037] The electronic device proposed in the embodiment of the present application realizes soft start of the LDO load through any one of the above-mentioned output voltage stabilization circuit, LDO and chip, which not only ensures that the output voltage of the LDO remains stable to maintain the normal operation of the electronic device, but also effectively saves the printed circuit board space of the chip circuit and reduces the chip power loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] Figure 1 It is a structural diagram of LDO in the related art;

[0040] Figure 2 A schematic diagram of the structure of an output voltage stabilization circuit for LDO proposed in an embodiment of the present application;

[0041] Figure 3 A schematic diagram of the circuit structure of a load insertion detection unit proposed in an embodiment of the present application;

[0042] Figure 4 A schematic diagram of the circuit structure of the timing control unit proposed in the embodiment of the present application;

[0043] Figure 5 A schematic diagram of a signal waveform proposed in an embodiment of the present application;

[0044] Figure 6This is a schematic diagram of the circuit structure of the LDO proposed in the embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0046] like Figure 1 As shown, LDO usually uses an operational amplifier (OPA) U1, a switch tube Q 1 The sampling circuit forms a voltage stabilizing circuit with a negative feedback mechanism, wherein the resistor R1 and the resistor R2 are connected in series to form a sampling circuit, the drain of the switch tube Q1 is connected to the power supply VDD, the source of the switch tube Q1 is used as the output terminal OUT of the LDO to output a stable voltage, and the source of the switch tube Q1 is connected to the sampling circuit, and the positive input terminal of the operational amplifier U1 is connected to the reference voltage V REF0 The negative input terminal of the operational amplifier U1 is connected to the connection node of the resistor R1 and the resistor R2, and the output terminal of the operational amplifier U1 is connected to the gate of the switch tube Q1. The operational amplifier U1 is used to compare the voltage value at the connection node of the resistor R1 and the resistor R2 with the reference voltage V REF0 , and adjust the gate voltage of the switch tube Q1 according to the comparison result to control the conduction degree of the switch tube Q1, thereby adjusting the voltage and current of the output terminal OUT to achieve voltage stabilization of the power supply VDD.

[0047] The on-chip load of LDO usually has a large step mutation. For example, some chips are set to sleep mode for low power design. When they suddenly return to normal state from sleep mode, the power consumption will rise rapidly from nearly 0 to mA level within us level time. This step mutation will cause the voltage regulation effect of LDO. When the load changes from zero to heavy load, it is easy to cause a large drop in the LDO output voltage. When the load changes from heavy load to zero, it is easy to cause a large overshoot in the LDO output voltage.

[0048] In one application scenario of the related technology, an external capacitor is required to improve the load transient response capability of the LDO, but the external capacitor type LDO needs to be connected to an external capacitor in the board-level application system, which will increase the area of ​​the printed circuit board. In another application scenario of the related technology, the bandwidth of the LDO is also designed to be higher to improve the load transient response capability of the LDO, but this will greatly increase the power consumption. It can be seen that the related technology is difficult to meet the performance requirements of maintaining a stable output voltage under sudden load changes.

[0049] The embodiment of the present application provides an output voltage stabilization circuit 10 for LDO. The output voltage stabilization circuit 10 can be used in a mixed digital-analog circuit chip and supply power to a load circuit 20 in the chip to ensure the normal operation of the chip.

[0050] In the embodiment of the present application, the LDO adopts a design without external capacitors, such as Figure 2 As shown, the output voltage stabilization circuit 10 includes a dummy load unit 100 and a timing control unit 200 .

[0051] In which, the dummy load unit 100 is set at the output end OUT of the LDO, and the timing control unit 200 is configured to control the dummy load unit 100 to start first when it is detected that the load circuit 20 of the LDO needs to be started, and control the load circuit 20 to start again after a delay of a first preset time, wherein the current change slope when the load circuit 20 is started is greater than the current change slope when the dummy load unit 100 is started.

[0052] In some embodiments of the present application, the dummy load unit 100 and the load circuit 20 are connected in parallel at the output end of the LDO. The load circuit 20 is the internal load of the LDO chip. When an external load is inserted, the LDO needs to provide power to the external load, so the load circuit 20 needs to be started. When no external load is inserted, the LDO does not need to provide power to the external load, so the load circuit 20 can be turned off to achieve low power design. When the LDO provides power to the external load of the chip, the load current I is output through the output end of the LDO. L , the load current I output by the dummy load unit 100 and the load circuit 20 to the LDO L To conduct diversion, such as Figure 2 As shown, the current I 1 Flowing through the load circuit 20, the current I 2 flows through the dummy load unit 100 .

[0053] The embodiment of the present application introduces a dummy load unit 100, and controls the startup timing of the dummy load unit 100 and the load circuit 20 through a timing control unit 200 to adjust the load change rate of the output end, wherein the current I 1 The change slope is greater than the current I 2 Therefore, the timing control unit 200 controls the dummy load unit 100 to start first, and then controls the load circuit 20 to start after a first preset time delay, so that the current I L The changes in the LDO voltage are buffered, so that the LDO has sufficient time to respond to the sudden load change, and can achieve soft start of the LDO load without the need for external capacitors, reducing the impact of sudden load changes on the LDO voltage regulation effect and ensuring that the output voltage of the LDO remains stable.

[0054] In addition, the output voltage stabilization circuit 10 proposed in the embodiment of the present application can be applied to an LDO designed without an external capacitor, and there is no need to connect a large external capacitor to suppress the LDO output voltage fluctuation caused by sudden load changes. Therefore, the output voltage stabilization circuit 10 proposed in the embodiment of the present application can not only ensure that the output voltage of the LDO remains stable, but also effectively save printed circuit board space and reduce chip power loss.

[0055] In some embodiments of the present application, the above-mentioned output voltage stabilization circuit 10 also includes an off-chip load insertion detection unit 300, which is configured to detect whether there is an off-chip load insertion to generate a detection signal; wherein the above-mentioned timing control unit 200 determines that the load circuit 20 of the LDO needs to be started when it is determined according to the detection signal that there is an off-chip load insertion.

[0056] like Figure 3 As shown, in some embodiments of the present application, the off-chip load insertion detection unit 300 includes a first resistor R3 , a second resistor R4 and a first comparator 301 .

[0057] One end of the first resistor R3 is suitable for connecting to the detection pin PIN, one end of the second resistor R4 is connected to the other end of the first resistor R3 and has a first node, the other end of the second resistor R4 is grounded, the positive input end of the first comparator 301 is connected to the above-mentioned first node, and the negative input end of the first comparator 301 is suitable for connecting to the reference voltage V REF The output terminal of the first comparator 301 is used to output the detection signal CMP_OUT.

[0058] Specifically, the first resistor R3 and the second resistor R4 are connected in series to form a voltage divider circuit, and the connection node of the first resistor R3 and the second resistor R4 is used as the first node, and the feedback voltage of the detection pin PIN is output through the first node. The feedback voltage can represent the voltage change when the external load is inserted. REF The feedback voltage is sent to the negative input terminal of the first comparator 301, and the feedback voltage is sent to the positive input terminal of the first comparator 301. The first comparator 301 compares the reference voltage V REF The detection signal CMP_OUT is outputted based on the size between the above feedback voltage. If the detection signal CMP_OUT is at a high level, it indicates that an off-chip load is inserted. If the detection signal CMP_OUT is at a low level, it indicates that no off-chip load is inserted.

[0059] Therefore, the off-chip load insertion detection unit 300 proposed in the embodiment of the present application forms a voltage divider circuit through the first resistor R3 and the second resistor R4 to detect the voltage change when the external load is inserted, and compares the reference voltage with the feedback voltage representing the voltage change through the first comparator 301 to determine whether the external load is inserted according to the comparison result, so as to accurately identify the insertion of the off-chip load, so as to ensure that the timing control unit 200 can timely determine the startup requirement of the LDO load circuit 20 when the off-chip load is inserted.

[0060] In some embodiments of the present application, the input end of the timing control unit 200 is connected to the output end of the above-mentioned off-chip load insertion detection unit 300 to control the startup timing of the dummy load unit 100 and the load circuit 20 according to the detection signal CMP_OUT generated by the off-chip load insertion detection unit 300.

[0061] Figure 4 The circuit structure of the timing control unit 200 is shown. Specifically, the timing control unit 200 includes a first delay module 210 and a control module 220, wherein the first delay module 210 is configured to output a start signal after a delay of a first preset time when it is determined according to the detection signal CMP_OUT that an off-chip load is inserted, and the control module 220 is configured to control the dummy load unit 100 to start when it is determined according to the detection signal CMP_OUT that an off-chip load is inserted, and control the load circuit 20 to start when the above-mentioned start signal is received.

[0062] In the embodiment of the present application, the control module 220 controls the dummy load unit 100 to start first when it is determined that there is an off-chip load inserted, and controls the load circuit 20 to delay for a period of time after starting the dummy load unit 100 through the first delay module 210, so as to effectively buffer the impact of the start-up of the load circuit 20 on the LDO, realize the soft start of the LDO during the period when the load changes from zero to heavy load, reduce the LDO output voltage fluctuation caused by starting the load circuit 20, and improve the voltage regulation effect of the LDO.

[0063] Furthermore, if Figure 4 As shown, the above-mentioned first delay module 210 includes a first counter 211 and a first AND gate 212, wherein the enable terminal EN of the first counter 211 is connected to the output terminal of the off-chip load insertion detection unit 300, the first input terminal of the first AND gate 212 is connected to the first output terminal of the first counter 211, the second input terminal of the first AND gate 212 is connected to the second output terminal of the first counter 211, and the output terminal of the first AND gate 212 is used to output the above-mentioned start signal.

[0064] In the embodiment of the present application, the control module 220 generates a driving signal EN2 for starting the dummy load unit 100 when the detection signal CMP_OUT is at a high level. At the same time, the start signal is generated by delaying the first counter 211 and the first AND gate 212, and then the control module 220 generates a driving signal EN1 for starting the internal load 20 in response to the start signal, so that the dummy load unit 100 is started first, and then the load circuit 20 is controlled to start after a delay of the first preset time. Specifically, the first counter 211 is provided with n output terminals, wherein the output terminal Q n-1 and output Q n As the first output terminal and the second output terminal of the first counter 211, respectively. When the detection signal CMP_OUT is at a high level, the enable terminal EN of the first counter 211 is pulled high to trigger the first counter 211 to start working, and at the same time, the preset clock pulse is sent to the CLK terminal of the first counter 211. The first counter 211 counts based on the preset clock pulse, and when the count reaches the first pre-designed value, the output terminal Q n-1 and output Q n At the same time, a high level is output, thereby generating a start signal through the first AND gate 212. That is to say, the time from the start of the first counter 211 to the count reaching the first pre-designed value is taken as the first preset time.

[0065] In the embodiment of the present application, the first counter 211 is used to accurately count the first preset time in a clock counting manner, and an accurate start signal is generated by a logic circuit composed of the first counter 211 and the first AND gate 212, so as to achieve precise control of the start timing of the dummy load unit 100 and the load circuit 20. The dummy load unit 100 is started before the load circuit 20 is started, so that the current I flowing through the dummy load unit 100 is 2 As the dummy load unit 100 is started, the load current I L The voltage is increased in advance to buffer the sudden load impact on the LDO caused by the load circuit 20 when it is started, so as to achieve soft start of the LDO during the period when the load changes from zero to heavy load, reduce the fluctuation of the LDO output voltage and improve the voltage regulation effect and reliability of the LDO.

[0066] In some other embodiments of the present application, the above-mentioned timing control unit 200 also includes a second delay module 230, which is configured to output a shutdown signal after delaying for a second preset time when it is determined according to the detection signal CMP_OUT that the off-chip load is unplugged. The control module 220 is also configured to control the load circuit 20 to be shut down when it is determined according to the detection signal CMP_OUT that the off-chip load is unplugged, and control the dummy load unit 100 to be shut down when receiving the above-mentioned shutdown signal, wherein the current change slope when the dummy load unit 100 is shut down is less than the current change slope when the load circuit 20 is shut down.

[0067] In the embodiment of the present application, the control module 220 controls the load circuit 20 to be turned off first when it is determined that an off-chip load has been unplugged, and controls the dummy load unit 100 to delay for a period of time after turning off the load circuit 20 through the second delay module 230, so as to effectively buffer the impact of the load circuit 20 turning off on the LDO, realize the soft shutdown of the LDO during the period when the load changes from heavy load to zero, avoid a large overshoot of the LDO output voltage, and improve the reliability of the LDO.

[0068] Furthermore, if Figure 4 As shown, the above-mentioned second delay module 230 includes a first inverter 231, a second counter 232 and a second AND gate 233, wherein the input end of the first inverter 231 is connected to the output end of the off-chip load insertion detection unit 300, the enable end EN of the second counter 232 is connected to the output end of the first inverter 231, the first input end of the second AND gate 233 is connected to the first output end of the second counter 232, the second input end of the second AND gate 233 is connected to the second output end of the second counter 232, and the output end of the second AND gate 233 is used to output the above-mentioned shutdown signal.

[0069] In some embodiments of the present application, the control module 220 generates a driving signal EN1 for shutting down the load circuit 20 when the detection signal CMP_OUT is at a low level. At the same time, the first inverter 231, the second counter 232, and the second AND gate 233 delay the generation of a shutdown signal, and then the control module 220 generates a driving signal EN2 for shutting down the dummy load unit 100 in response to the shutdown signal, so that the load circuit 20 is first shut down, and then the dummy load unit 100 is controlled to shut down after a delay of a second preset time. Specifically, the second counter 232 is provided with n output terminals, wherein the output terminal Q n-1 and output Q n They serve as the first output terminal and the second output terminal of the second counter 232, respectively. When the detection signal CMP_OUT is at a low level, the enable terminal of the second counter 232 is pulled high by the inversion of the first inverter 231 to trigger the second counter 232 to start working, and at the same time, the preset clock pulse is sent to the CLK terminal of the second counter 232. The second counter 232 counts based on the preset clock pulse, and when the count reaches the second preset value, the second counter 232 outputs the second clock pulse through the output terminal Q. n-1 and output Q n At the same time, a high level is output, thereby generating a start signal through the second AND gate 233. That is to say, the time from the start of the second counter 232 to the count reaching the second pre-designed value is taken as the second preset time.

[0070] In the embodiment of the present application, the second counter 232 is used to accurately count the second preset time in a clock counting manner, and the logic circuit composed of the second counter 232, the first inverter 231, and the second AND gate 233 generates an accurate shutdown signal to achieve precise control of the shutdown timing of the dummy load unit 100 and the load circuit 20. The dummy load unit 100 is shut down after the load circuit 20 is shut down, so that the load current I L The voltage of the LDO decreases gradually to achieve soft shutdown of the LDO when the load changes from heavy load to zero, thus avoiding large overshoot of the LDO output voltage and improving the voltage regulation effect and reliability of the LDO.

[0071] Figure 4 The circuit structure of the control module 220 is also shown. Figure 4As shown, the control module 220 includes a third AND gate 221, a second inverter 222 and a first OR gate 223, wherein the first input end of the third AND gate 221 is connected to the output end of the off-chip load insertion detection unit 300, the second input end of the third AND gate 221 is suitable for receiving the above-mentioned start signal, the output signal of the third AND gate 221 is used to control the start or shutdown of the load circuit 20, the input end of the second inverter 222 is suitable for receiving the above-mentioned shutdown signal, the first input end of the first OR gate 223 is connected to the output end of the off-chip load insertion detection unit 300, the second input end of the first OR gate 223 is connected to the output end of the second inverter 222, and the output signal of the first OR gate 223 is used to control the start or shutdown of the dummy load unit 100.

[0072] Specifically, when the detection signal CMP_OUT output by the off-chip load insertion detection unit 300 is at a high level, it indicates that an off-chip load is inserted. At this time, the first input terminal of the first OR gate 223 is pulled high, so the driving signal EN2 generated by the output terminal of the first OR gate 223 is at a high level, and then the dummy load unit 100 is controlled to start according to the driving signal EN2. In addition, the first input terminal of the third AND gate 221 is first pulled high, and the second input terminal of the third AND gate 221 is pulled high after receiving the start signal. Therefore, the driving signal EN1 generated by the output terminal of the third AND gate 221 after the delay of the first delay module 210 is at a high level, and then the load circuit 20 is controlled to start after starting the dummy load unit 100 according to the driving signal EN1, so as to realize the soft start of the LDO.

[0073] When the detection signal CMP_OUT output by the off-chip load insertion detection unit 300 is at a low level, it indicates that there is no off-chip load insertion phenomenon. At this time, the first input terminal of the third AND gate 221 is pulled low, so the driving signal EN1 generated by the output terminal of the third AND gate 221 is at a low level, and then the load circuit 20 is controlled to be turned off according to the driving signal EN1. In addition, the first input terminal of the first OR gate 223 is first pulled low, and the second input terminal of the first OR gate 223 is pulled low after receiving the shutdown signal through the inversion processing of the second inverter 222, so the driving signal EN2 generated by the output terminal of the first OR gate 223 after the delay of the second delay module 230 is at a low level, and then the dummy load unit 100 is controlled to be turned off after the load circuit 20 is turned off according to the driving signal EN2, so as to realize the soft shutdown of the LDO.

[0074] In some embodiments of the present application, the timing control unit 200 is further configured to control the dummy load unit 100 to be turned off after the load circuit 20 is started, so that the load current I L When a stable state is reached, the dummy load unit 100 is controlled to be turned off to reduce unnecessary current consumption and lower the overall power consumption of the LDO.

[0075] In some other embodiments of the present application, when the load circuit 20 of the LDO needs to be started, the dummy load unit 100 is controlled to start in advance. L When the load current I reaches a stable state, the load circuit 20 is controlled to start. L When the load circuit 20 of the LDO needs to be turned off, the dummy load unit 100 is controlled to start in advance. L When the load current I reaches a stable state, the load circuit 20 is controlled to be turned off. L When the steady state is reached again, the dummy load unit 100 is controlled to be closed.

[0076] Specifically, Figure 5 As shown, when it is determined that there is an off-chip load inserted, the timing control unit 200 generates a high-level driving signal EN2, and the dummy load unit 100 is controlled to start first according to the driving signal EN2. At this time, the current I flowing through the dummy load unit 100 is 2 From zero to I B , and then the timing control unit 200 generates a high-level driving signal EN1 after delaying the first preset time, and controls the load circuit 20 to start after the dummy load unit 100 according to the driving signal EN1. At this time, the current I flowing through the load circuit 20 is 1 From zero step up to I A , which can adjust the load current I at the LDO output L The load current I L When the stable state is reached, the driving signal EN2 is pulled down to a low level. It can be obtained that the embodiment of the present application controls the dummy load unit 100 to start first, and the current I 2 The slope of change is less than the current I 1 The change slope of the load increases, thus prolonging the response time of the LDO to the load change from zero to heavy load, making the load current I L The rising rate of the voltage is buffered, thus achieving the soft start of the LDO.

[0077] When it is determined that there is no off-chip load inserted, the driving signal EN2 is pulled high in advance, and the dummy load unit 100 is controlled to start in advance according to the driving signal EN2. At this time, the current I flowing through the dummy load unit 100 is 2 From zero to I B , load current I L There is also a small increase. LWhen the stable state is reached, the driving signal EN1 is pulled down by the timing control unit 200, and the load circuit 20 is controlled to be turned off after the dummy load unit 100 is started according to the driving signal EN1. At this time, the current I flowing through the load circuit 20 is 1 by I A The step decreases to zero and finally the load current I L When the stable state is reached again, the driving signal EN2 is pulled low to control the dummy load unit 100 to be turned off. At this time, the current I flowing through the dummy load unit 100 is 2 by I B linearly decreases to zero, thus making the load current I L It can be seen that the embodiment of the present application controls the dummy load unit 100 to start first, then controls the load circuit 20 to shut down, and finally controls the dummy load unit 100 to shut down, and when the dummy load unit 100 is shut down, the current I 2 The slope of change is less than the current I when the load circuit 20 is turned off 1 The change slope of the load current I L The falling rate of the LDO is buffered, achieving soft shutdown of the LDO.

[0078] It should be noted that the first preset time needs to exceed the current I 2 From zero to I B Time t 0 , to ensure that the dummy load unit 100 is started stably before starting the load circuit 20. Similarly, when the load circuit 20 of the LDO needs to be turned off, the advance time for controlling the pre-start of the dummy load unit 100 also needs to exceed the current I 2 From zero to I B Time t 0 , to ensure that the dummy load unit 100 is stably started before the load circuit 20 is turned off.

[0079] Accordingly, please refer to Figure 6 An embodiment of the present application provides an LDO, which includes an output feedback circuit 30 and an output voltage stabilization circuit 10 in the above embodiment, wherein the output voltage stabilization circuit 10 is configured corresponding to the output feedback circuit 30 to buffer the voltage fluctuation of the output feedback circuit 30 when the load of the LDO suddenly changes.

[0080] like Figure 6 As shown, an on-chip capacitor C1 is further provided at the output end of the LDO, and the on-chip capacitor C1 is connected in parallel with the dummy load unit 100 and the load circuit 20 respectively.

[0081] The embodiment of the present application introduces a dummy load unit 100 into the output voltage stabilization circuit 10, and controls the startup timing of the dummy load unit 100 and the load circuit 20 to adjust the load change rate at the output end, thereby being able to achieve soft start of the LDO load without the need for an external capacitor, thereby reducing the impact of load mutations on the LDO voltage stabilization effect, and ensuring that the output voltage of the LDO remains stable. In addition, the LDO proposed in the embodiment of the present application adopts a non-chip external capacitor design, and does not require an external large capacitor to suppress the LDO output voltage fluctuation caused by load mutations, which can not only ensure that the output voltage of the LDO remains stable, but also effectively save the printed circuit board space of the chip circuit and reduce the chip power loss.

[0082] Accordingly, an embodiment of the present application provides a chip, including the LDO in the above embodiment, and the LDO is suitable for providing power supply to the load circuit 20 in the chip.

[0083] The embodiment of the present application proposes an LDO designed without external capacitors, and introduces a dummy load unit 100 in the output voltage stabilization circuit 10 of the LDO. By controlling the startup timing of the dummy load unit 100 and the load circuit 20, the load change rate at the output end is adjusted, thereby being able to achieve soft start of the LDO load without the need for an external capacitor, thereby reducing the impact of load mutations on the LDO voltage stabilization effect, and ensuring that the output voltage of the LDO remains stable. In addition, the chip proposed in the embodiment of the present application does not require an external large capacitor to suppress the LDO output voltage fluctuation caused by load mutations, which can not only ensure that the output voltage of the LDO remains stable, but also effectively save the printed circuit board space of the chip circuit and reduce the chip power loss.

[0084] An embodiment of the present application further provides an electronic device, comprising the output voltage stabilization circuit 10 in the above embodiment, or the LDO in the above embodiment, or the chip in the above embodiment.

[0085] The electronic device proposed in the embodiment of the present application, through the above-mentioned output voltage stabilization circuit 10 or the LDO or chip including the above-mentioned output voltage stabilization circuit 10, not only ensures that the output voltage of the LDO remains stable to maintain the normal operation of the electronic device, but also effectively saves the printed circuit board space of the chip circuit and reduces the chip power loss.

[0086] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0087] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0088] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0089] The various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.

[0090] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

[0091] Although the embodiments of the present application have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. An output voltage stabilization circuit for LDO, characterized in that: The LDO adopts a design without external capacitors, and the output voltage stabilization circuit includes: A dummy load unit, wherein the dummy load unit is arranged at an output end of the LDO; A timing control unit, wherein the timing control unit is configured to control the dummy load unit to start first when it is detected that the load circuit of the LDO needs to be started, and control the load circuit to start again after a first preset delay time, wherein a current change slope when the load circuit is started is greater than a current change slope when the dummy load unit is started.

2. The output voltage stabilization circuit according to claim 1, characterized in that: Also includes: an off-chip load insertion detection unit, wherein the off-chip load insertion detection unit is configured to detect whether an off-chip load is inserted to generate a detection signal; Wherein, when the timing control unit determines according to the detection signal that an off-chip load is inserted, it determines that the load circuit of the LDO needs to be started.

3. The output voltage stabilization circuit according to claim 2, characterized in that: The off-chip load insertion detection unit comprises: A first resistor, one end of which is suitable for connecting to a detection pin; a second resistor, one end of the second resistor being connected to the other end of the first resistor and having a first node, and the other end of the second resistor being grounded; A first comparator, wherein a positive input terminal of the first comparator is connected to the first node, a negative input terminal of the first comparator is suitable for accessing a reference voltage, and an output terminal of the first comparator is used to output the detection signal.

4. The output voltage stabilization circuit according to claim 2, characterized in that: The timing control unit comprises: A first delay module, wherein the first delay module is configured to output a start signal after delaying the first preset time when it is determined according to the detection signal that there is an off-chip load inserted; A control module is configured to control the dummy load unit to start up when it is determined according to the detection signal that an off-chip load is inserted, and control the load circuit to start up when the start signal is received.

5. The output voltage stabilization circuit according to claim 4, characterized in that: The timing control unit also includes: A second delay module, wherein the second delay module is configured to output a shutdown signal after a second preset delay time when it is determined according to the detection signal that the off-chip load is unplugged; The control module is also configured to control the load circuit to shut down when it is determined according to the detection signal that an off-chip load is unplugged, and to control the dummy load unit to shut down when the shutdown signal is received, wherein the current change slope when the dummy load unit is shut down is smaller than the current change slope when the load circuit is shut down.

6. The output voltage stabilization circuit according to claim 4, characterized in that: The first delay module comprises: A first counter, wherein an enable terminal of the first counter is connected to an output terminal of the off-chip load insertion detection unit; A first AND gate, wherein a first input end of the first AND gate is connected to a first output end of the first counter, a second input end of the first AND gate is connected to a second output end of the first counter, and an output end of the first AND gate is used to output the start signal.

7. The output voltage stabilization circuit according to claim 5, characterized in that: The second delay module comprises: A first inverter, wherein an input end of the first inverter is connected to an output end of the off-chip load insertion detection unit; a second counter, wherein an enable terminal of the second counter is connected to an output terminal of the first inverter; A second AND gate, wherein the first input terminal of the second AND gate is connected to the first output terminal of the second counter, the second input terminal of the second AND gate is connected to the second output terminal of the second counter, and the output terminal of the second AND gate is used to output the shutdown signal.

8. The output voltage stabilization circuit according to claim 5, characterized in that: The control module comprises: a third AND gate, wherein a first input terminal of the third AND gate is connected to an output terminal of the external load insertion detection unit, a second input terminal of the third AND gate is adapted to receive the start signal, and an output signal of the third AND gate is used to control the start or shut down of the load circuit; a second inverter, wherein an input terminal of the second inverter is adapted to receive the shutdown signal; A first OR gate, wherein a first input end of the first OR gate is connected to an output end of the off-chip load insertion detection unit, a second input end of the first OR gate is connected to an output end of the second inverter, and an output signal of the first OR gate is used to control the start or stop of the dummy load unit.

9. The output voltage stabilization circuit according to any one of claims 1 to 8, characterized in that: The timing control unit is further configured to control the dummy load unit to be turned off after the load circuit is started.

10. The output voltage stabilization circuit according to claim 1, characterized in that: The dummy load unit and the load circuit are respectively connected in parallel to the output end of the LDO.

11. An LDO, characterized in that: include: Output feedback circuit; According to any one of claims 1 to 10, the output voltage stabilization circuit is arranged corresponding to the output feedback circuit to buffer the voltage fluctuation of the output feedback circuit when a load of the LDO suddenly changes.

12. The LDO according to claim 11, characterized in that: The output end of the LDO is also provided with an on-chip capacitor, and the on-chip capacitor is connected in parallel with the dummy load unit and the load circuit respectively.

13. A chip, characterized in that: include: According to the LDO of claim 11 or 12, the LDO is suitable for providing power supply to a load circuit in the chip.

14. An electronic device, characterized in that: include: The output voltage stabilization circuit according to any one of claims 1 to 10; or The LDO according to claim 11 or 12; or The chip according to claim 13.

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