Low dropout linear regulator circuit and low dropout linear regulator

Abstract

The invention discloses a low-dropout linear regulator circuit and a low-dropout linear regulator. The low-dropout linear regulator circuit comprises a power tube, and a source electrode of the power tube is connected with input voltage; the circuit also comprises a first sampling tube, a second sampling tube, an external triode, a first current mirror with two mirror image tubes, a counter, and a digital-to-analog converter circuit. The collector electrode of the external triode is connected with the drain electrode of the power tube; a drain electrode of a first mirror image tube of the first current mirror is connected with a drain electrode of the first sampling tube, and a drain electrode of a second mirror image tube of the first current mirror is connected with a drain electrode of the second sampling tube; the plus count input of the counter is connected between the drain electrode of the second sampling tube and the drain electrode of the second mirror image tube, and the minus count input of the counter is connected between the drain electrode of the first sampling tube and the drain electrode of the first mirror image tube; and the digital-to-analog converter circuit is respectively connected with the output end of the counter and the base electrode of the external triode. According to the invention, load current can be shared by the external triodes, and temperature rise and power consumption of a chip are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low voltage drop linear regulator circuit and a low voltage drop linear regulator. Background Art

[0002] The LDO circuit (low dropout linear regulator) is a common functional module in integrated circuits, which is mainly used to convert the high-voltage domain power supply in the system into a stable output power supply in the low-voltage domain. Compared with the switching power supply, the LDO circuit is a linear step-down circuit. Due to its simple structure and low cost, it is widely used in many application scenarios.

[0003] However, current LDO circuits have certain limitations in terms of load capacity, and their performance is usually limited by the power loss of the power tube. When the voltage drop on the power tube is large, it will cause significant power loss, causing the chip temperature to rise. In severe cases, this thermal effect may trigger the over-temperature protection mechanism or burn the chip, affecting the normal operation of the system.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a low voltage drop linear regulator circuit and a low voltage drop linear regulator to at least solve the problem that the power tube of the existing low voltage drop linear regulator is prone to cause the chip temperature to rise when the voltage drop is large.

[0006] The embodiment of the present invention provides the following technical solutions: The embodiment of the present invention provides a low voltage drop linear regulator circuit, including a power tube, wherein the source of the power tube is connected to an input voltage, and the low voltage drop linear regulator circuit also includes a first sampling tube, a second sampling tube, an external triode, a first current mirror having two mirror tubes, a counter, and a digital-to-analog converter circuit; The source of the first sampling tube, the source of the second sampling tube, and the emitter of the external triode are respectively connected to the input voltage, the gate of the first sampling tube, the gate of the second sampling tube, and the gate of the power tube are connected to each other, and the collector of the external triode is connected to the drain of the power tube; The drain of the first mirror tube of the first current mirror is connected to the drain of the first sampling tube, and the drain of the second mirror tube of the first current mirror is connected to the drain of the second sampling tube; the up-count input of the counter is connected between the drain of the second sampling tube and the drain of the second mirror tube, and the down-count input of the counter is connected between the drain of the first sampling tube and the drain of the first mirror tube; The digital-to-analog converter circuit is connected to the output end of the counter and the base of the external transistor respectively, and the digital-to-analog converter circuit can control the base current of the external transistor according to the output value of the counter.

[0007] Furthermore, a freewheeling resistor is included, and the freewheeling resistor is connected between the input voltage and the base of the external transistor.

[0008] Furthermore, a clamping diode is included, wherein the anode of the clamping diode is grounded, and the cathode is connected to the drain of the power tube.

[0009] Further, the first current mirror includes a bias current source and a first reference tube; The first reference tube obtains the bias current output by the bias current source. The first reference tube forms a current mirror with the first mirror tube and the second mirror tube respectively, and the first mirror tube and the second mirror tube can mirror the bias current flowing through the first reference tube.

[0010] Further, the digital-to-analog converter circuit includes a second current mirror having a plurality of mirror tubes and a plurality of switch MOS tubes; The second current mirror comprises a reference current source, a second reference tube and a plurality of third mirror tubes, the second reference tube obtains the current of the reference current source, the second reference tube and the plurality of third mirror tubes respectively form a current mirror, and the mirror tube sizes of the plurality of third mirror tubes gradually increase; The plurality of switch MOS tubes are correspondingly connected to the plurality of third mirror tubes, and the switch MOS tubes are used to control whether the current mirrored by the corresponding third mirror tube is output as the base current of the external transistor.

[0011] Further, the counter is a 7-bit counter, and the number of the third mirror tube and the number of the switch MOS tube are seven respectively; The multiple switch MOS tubes control the current of the corresponding third mirror tube according to the output value of the counter to determine whether to output the current as the base current of the external transistor.

[0012] Furthermore, the size ratio of the seven mirror tubes of the third mirror tubes is 1:1:2:4:8:16:32:64.

[0013] Further, the counter counts up when the second sampling current flowing through the second sampling tube is greater than the second mirror current flowing through the second mirror tube; counts down when the first sampling current flowing through the first sampling tube is less than the first mirror current flowing through the first mirror tube; and stops counting when the first sampling current or the second sampling current is between the first mirror current and the second mirror current.

[0014] Furthermore, the external transistor is a PNP transistor.

[0015] The present invention further provides a low voltage dropout linear regulator, comprising any of the above-mentioned low voltage dropout linear regulator circuits.

[0016] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects: A low voltage difference linear regulator circuit of the present invention, a counter can perform addition and subtraction counting according to a first sampling current flowing through a first sampling tube, a first mirror current flowing through a first mirror tube, a second sampling current flowing through a second sampling tube, and a second mirror current flowing through a second mirror tube, and then a digital-to-analog converter circuit controls the base current of an external transistor according to an output value of the counter, so that the external transistor can provide a load current together with a power tube, thereby being able to share the load current with the external transistor, so as to solve the problem in the prior art that the current flowing through the power tube is too large, causing the chip temperature to rise, and greatly reducing the temperature rise and power consumption of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 is a circuit diagram of an existing low voltage drop linear regulator; Figure 2 A circuit diagram of a low voltage dropout linear regulator circuit of the present invention; Figure 3 The current waveforms of the internal power tube and the external triode of the low voltage difference linear regulator circuit of the present invention when the load current changes slowly; Figure 4 The low voltage difference linear regulator circuit of the present invention is an internal power tube and an external triode current waveform when the load current changes rapidly. DETAILED DESCRIPTION

[0019] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0020] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0021] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0022] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0023] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0024] like Figure 1 The existing low-dropout linear regulator shown in the figure, when applied to a vehicle power supply, has an input voltage of up to 28V and an output voltage of 5V. The voltage difference on the power tube is 23V. For an output current of 300mA, the power tube loss reaches 5V*300mA=6.9W, which is a huge loss. It will undoubtedly cause the chip temperature to rise and trigger the over-temperature protection, and in severe cases, the chip will be burned.

[0025] The working principle of the existing low-dropout linear regulator is as follows: the error amplifier A1 is used to clamp the vref voltage and the resistor feedback voltage, and the power tube is used to provide the load current Iload, so that the output voltage Vout = (1 + R1 / R2) * vref, providing other modules with a stable voltage that is independent of the input voltage VIN.

[0026] Based on this, this specification embodiment proposes a processing solution: Figure 2 As shown, a low voltage difference linear regulator of the present invention can control the current of the external transistor pnp according to the current flowing through the power tube Mp, so as to use the external transistor pnp to share part of the load current, thereby reducing the power consumption and chip temperature rise of the power tube Mp inside the low voltage difference linear regulator.

[0027] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0028] like Figures 2~4 As shown, a low voltage difference linear regulator circuit of the present invention includes a power tube Mp, the source of the power tube Mp is connected to the input voltage, the gate of the power tube Mp is connected to the operational amplifier, the drain of the power tube Mp is grounded through two resistors connected in series, the drain of the power tube Mp is also connected to an equivalent resistor RL and an equivalent capacitor CL, and the equivalent resistor RL and the equivalent capacitor CL are arranged in parallel and are both connected between the drain of the power tube Mp and the ground.

[0029] The positive input terminal of the operational amplifier is connected between two resistors connected in series, and the negative input terminal is connected to a reference voltage.

[0030] The power tube Mp may be a P-type MOS tube.

[0031] Furthermore, the low voltage difference linear regulator circuit also includes a first sampling tube Ms1, a second sampling tube Ms2, an external triode pnp, a first current mirror having two mirror tubes, a counter 10 and a digital-to-analog converter circuit 20; the source of the first sampling tube Ms1, the source of the second sampling tube Ms2, and the emitter of the external triode pnp are respectively connected to the input voltage, the gate of the first sampling tube Ms1, the gate of the second sampling tube Ms2, and the gate of the power tube Mp are connected to each other, and the collector of the external triode pnp is connected to the drain of the power tube Mp; the first mirror tube M2 of the first current mirror The drain is connected to the drain of the first sampling tube Ms1, and the drain of the second mirror tube M3 of the first current mirror is connected to the drain of the second sampling tube Ms2; the plus counting input of the counter 10 is connected between the drain of the second sampling tube Ms2 and the drain of the second mirror tube M3, and the minus counting input is connected between the drain of the first sampling tube Ms1 and the drain of the first mirror tube M2; the digital-to-analog converter circuit 20 is respectively connected to the output end of the counter 10 and the base of the external transistor pnp, and the digital-to-analog converter circuit 20 can control the base current Ib of the external transistor pnp according to the output value of the counter 10.

[0032] The power tube Mp forms a current mirror with the first sampling tube Ms1 and the second sampling tube Ms2 respectively, so that the first sampling tube Ms1 and the second sampling tube Ms2 can sample the current flowing through the power tube Mp.

[0033] The first sampling tube Ms1 and the second sampling tube Ms2 are both P-type MOS tubes; the external transistor pnp is a PNP-type transistor.

[0034] Specifically, the first current mirror includes a bias current source, a first reference tube M1, a first mirror tube M2 and a second mirror tube M3; the first reference tube M1 obtains the bias current output by the bias current source, the first reference tube M1 and the first mirror tube M2 and the second mirror tube M3 respectively form a current mirror, and the first mirror tube M2 and the second mirror tube M3 can mirror the bias current flowing through the first reference tube M1.

[0035] More specifically, the first reference tube M1, the first mirror tube M2 and the second mirror tube M3 are all N-type MOS tubes, and the drain of the first reference tube M1 is respectively connected to the output end of the bias current source and the gate of the first reference tube M1, and the source of the first reference tube M1 is grounded; the gate of the first mirror tube M2, the gate of the second mirror tube M3 and the gate of the first reference tube M1 are connected to each other, and the source of the first mirror tube M2 and the source of the second mirror tube M3 are both grounded.

[0036] The counter 10 is an add-and-subtract counter, and the counter 10 has two input signals (an add-count input and a subtract-count input), and the two input signals respectively control the add-count or the subtract-count of the counter.

[0037] The counter 10 counts up when the second sampling current Is2 flowing through the second sampling tube Ms2 is greater than the second mirror current Iu flowing through the second mirror tube M3; counts down when the first sampling current Is1 flowing through the first sampling tube Ms1 is less than the first mirror current Id flowing through the first mirror tube M2; and stops counting when the first sampling current Is1 or the second sampling current Is2 is between the first mirror current Id and the second mirror current Iu.

[0038] Specifically, when the second sampling current Is2 is greater than the second mirror current Iu, the count-up input of the counter 10 is high, and the counter 10 counts up; when the first sampling current Is1 is less than the first mirror current Id, the count-down input of the counter 10 is low, and the counter 10 counts down.

[0039] Furthermore, the digital-to-analog converter circuit 20 includes a second current mirror having multiple mirror tubes and multiple switch MOS tubes 24; the second current mirror includes a reference current source 21, a second reference tube 22 and multiple third mirror tubes 23, the second reference tube 22 obtains the current of the reference current source 21, the second reference tube 22 and the multiple third mirror tubes 23 respectively form a current mirror, and the mirror tube size of the multiple third mirror tubes 23 gradually increases; the multiple switch MOS tubes 24 are correspondingly connected to the multiple third mirror tubes 23, and the switch MOS tubes 24 are used to control whether the current mirrored by the corresponding third mirror tube 23 is output as the base current Ib of the external transistor pnp.

[0040] The second reference transistor 22 , the third mirror transistor 23 and the switch MOS transistor 24 are all N-type MOS transistors.

[0041] Specifically, the drain of the second reference tube 22 is respectively connected to the output end of the reference current source 21 and the gate of the second reference tube 22, the gates of the plurality of third mirror tubes 23 are interconnected with the gate of the second reference tube 22, the drain of each third mirror tube 23 is connected to the source of the corresponding switch MOS tube 24, and the source of each third mirror tube 23 is grounded.

[0042] The drain of each switch MOS tube 24 is connected to the base of the external transistor pnp, and the gate of each switch MOS tube 24 is controlled by the counter 10. The counter 10 can control whether the switch MOS tube 24 is turned on by controlling the gate current of the switch MOS tube 24.

[0043] Furthermore, the counter 10 is a 7-bit counter, and there are seven third mirror tubes 23 and seven switch MOS tubes 24; multiple switch MOS tubes 24 control the current of the corresponding third mirror tube 23 as the base current Ib output of the external transistor pnp according to the output value of the counter 10.

[0044] The output value of the counter 10 is a 7-bit binary signal, which can be converted into a base current Ib signal of the external transistor pnp by a digital-to-analog converter circuit formed by a third current mirror, thereby controlling the base current Ib of the external transistor pnp.

[0045] Furthermore, the size ratio of the seven third mirror tubes 23 is 1:1:2:4:8:16:32:64.

[0046] In some of the embodiments, the low voltage difference linear regulator circuit further includes a freewheeling resistor Rb, and the freewheeling resistor Rb is connected between the input voltage and the base of the external transistor pnp.

[0047] The freewheeling resistor Rb is used to ensure that the Vbe of the transistor is 0 when the base current Ib is 0, so as to ensure that the external transistor pnp will not be turned on and there is no leakage current.

[0048] In some of the embodiments, the low voltage difference linear regulator circuit further includes a clamping diode zener, wherein the anode of the clamping diode zener is grounded, and the cathode is connected to the drain of the power tube Mp.

[0049] The clamping diode zener is used when a single power tube Mp cannot provide current and discharge current, and the current can be discharged through the clamping diode zener.

[0050] like Figure 2 As shown, when the load current is 0 and the current of the external transistor pnp remains unchanged, it is equivalent to charging the equivalent capacitor CL, and the output voltage Vout will surge, which may damage the internal devices.

[0051] A specific working principle of a low voltage drop linear regulator circuit of the present invention is as follows: The present invention can obtain the first sampling current Is1 and the second sampling current Is2 of the power tube current Ipower by connecting the first sampling tube Ms1 and the second sampling tube Ms2 in parallel with the power tube Mp. The first sampling current Is1 and the second sampling current Is2 are compared with two reference currents Id and Iu (Id: the first mirror current; Iu: the second mirror current), and two logic signals counter+ and counter- are generated according to the comparison result. Counter+ and counter- are used as input signals of the add-subtract counter 10 to control the addition and subtraction of the counter 10 respectively. The output of the counter 10 is a 7-bit binary signal Q<6:0>.

[0052] The digital-to-analog converter circuit 20 is used to convert the output Q<6:0> of the counter 10 into the base current Ib of the external transistor pnp, and has a third current mirror. The initial current of the third current mirror is Ibin. The mirror tube sizes of the plurality of third mirror tubes 23 are 1:1:2:4:8:16:32:64. The plurality of third mirror currents generated by the plurality of third mirror tubes 23 are 1*Ibin, 2*Ibin, 4*Ibin, 8*Ibin, 16*Ibin, 32*Ibin, and 64*Ibin, respectively. The plurality of third mirror currents are respectively generated by the output signal Q<6:0> of the counter 10 <0> , Q <1> , Q <2> , Q <3> , Q <4> , Q <5> , Q <6> The multiple switch MOS tubes 24 controlled by the counter 10 determine whether the third mirror current flows through the external transistor pnp as a part of the Ib current. <x>When high, the Q <x>The power tube Mp controlled by the signal is turned on, and the corresponding third mirror current of this path will be superimposed on the base current Ib, Q <x>When it is low, the current in this path is 0.

[0053] For example, for the output signal Q<6:0>=0101001 of the counter 10, Ib=1*Ibin+8*Ibin+32*Ibin =41*Ibin, for Q<6:0>=0010111, Ib=1*Ibin+2*Ibin+4*Ibin+16*Ibin=23*Ibin. Therefore, the larger the value corresponding to the output signal Q<6:0>, the larger the base current Ib, and the larger the current Ipnp of the external transistor pnp. Conversely, the smaller the value corresponding to Q<6:0>, the smaller the current Ipnp of the external transistor pnp.

[0054] Specifically, when the load current Iload is too large, the second sampling current Is2 obtained by sampling will be larger. When the second sampling current Is2 exceeds the second mirror current Iu, that is, the power tube current Ipower exceeds the threshold value Iact_pnp (the activation current of the external transistor), counter+ is high level valid, the counter 10 starts to count up, the value of Q<6:0> starts to increase, the base current Ib increases, and the current Ipnp flowing through the external transistor pnp increases. When the load current Iload becomes smaller, the first sampling current Is1 obtained by sampling will be smaller. When the first sampling current Is1 exceeds the first mirror current Id, that is, the power tube current Ipower is less than the threshold value Ideat_pnp (the shutdown current of the external transistor), counter- is low level valid, the counter 10 starts to count down, the value of Q<6:0> starts to decrease, the base current Ib decreases, and the current Ipnp flowing through the external transistor pnp decreases. When the load current Iload is between Ideact_pnp and Iact_pnp, the counter 10 stops counting and the current Ipnp remains unchanged.

[0055] Attached Figure 3 The figure shows the current waveforms of the internal power tube Mp and the external transistor pnp when the load current of the architecture proposed by the present invention changes slowly. Taking the maximum load current Iload of 250mA as an example, it can be seen from the figure that when the load current Iload starts to rise slowly, the power tube current Ipower follows the rise of the load current Iload, and the two currents are the same in magnitude. At this time, there is no current in the external transistor pnp, and the current Ipnp flowing through the external transistor pnp is 0. When the load current Iload reaches Iact_pnp, the external transistor pnp starts to have current, and the current Ipnp rises with the rise of the load current Iload, and the power tube current Ipower maintains the Iact_pnp value unchanged, that is, the load current Iload that is more than Iact_pnp is provided by the external transistor pnp, until the upper limit of the external transistor pnp. When the load current Iload begins to decrease slowly, the current of the external transistor pnp remains unchanged temporarily, and the power tube current Ipower decreases first with the decrease of the load current Iload. When the power tube current Ipower is less than Ideat_pnp, the current Ipnp begins to decrease. At this time, the power tube current Ipower remains unchanged. As the load current Iload continues to decrease, the current Ipnp also gradually decreases until it is 0. At this time, the external transistor pnp has no current, and the load current Iload is the power tube current. If Iload further decreases to 0, the power tube current will also follow Iload to decrease to 0.

[0056] Attached Figure 4 The figure shows the current waveforms of the internal power tube Mp and the external transistor pnp when the load current of the architecture proposed by the present invention changes rapidly. It can be seen from the figure that when the load current Iload quickly jumps to the maximum value, since the external transistor pnp is driven by the counter, the increase of the current Ipnp is relatively slow. At this time, the current of the power tube Mp will first follow the load current Iload to reach the maximum value, and then with the increase of the current Ipnp, the power tube current Ipower slowly decreases to the vicinity of Iact_pnp, and then the counter stops counting, Ipnp no longer increases, and Ipower no longer decreases, and both remain unchanged, and the sum of the two is still equal to the total load current. When the load current Iload quickly jumps from the maximum value to 0, similarly, the current Ipnp remains unchanged at first, the power tube current Ipower drops rapidly to 0, and continues to drop below 0, that is, it changes from providing current to the output to discharging current from the output to the ground, and then as the current Ipnp decreases, the power tube MpIpower also slowly rises from a negative current to 0, and finally the load current Iload is 0, and the power tube current Ipower and the current Ipnp are also 0.

[0057] The present invention generates an input control signal of the counter 10 by sampling the current of the power tube Mp and comparing it with two reference currents respectively. When the power tube current is greater than a certain value (such as greater than the second mirror current Iu), the counter 10 performs an addition operation. The larger the output binary signal value is, the larger the base current converted by the digital-to-analog converter circuit 20 is, and the larger the current of the external transistor pnp is; when the power tube current is less than a certain value (such as less than the first mirror current Id), the counter 10 performs a subtraction operation. The smaller the output binary signal value is, the smaller the base current converted by the digital-to-analog converter circuit 20 is, and the smaller the current of the external transistor pnp is; when the current of the power tube Mp is between two thresholds, the counter 10 stops counting, and the current of the external transistor pnp remains unchanged.

[0058] A low voltage difference linear regulator circuit of the present invention connects an external transistor PNP outside a chip in parallel with a power tube Mp inside the chip, and samples the current of the internal power tube Mp to control the current size of the external transistor PNP. The internal power tube Mp and the external transistor PNP jointly provide current for the load, which greatly reduces the temperature rise and power consumption of the chip and expands the upper limit of the output current of the LDO (low voltage difference linear regulator).

[0059] The present invention further provides a low voltage dropout linear regulator, comprising any of the above-mentioned low voltage dropout linear regulator circuits.

[0060] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0061] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.< / x> < / x> < / x>

Claims

1. A low voltage drop linear regulator circuit, comprising a power tube, wherein the source of the power tube is connected to an input voltage, characterized in that: The low voltage difference linear regulator circuit also includes a first sampling tube, a second sampling tube, an external triode, a first current mirror with two mirror tubes, a counter and a digital-to-analog converter circuit; The source of the first sampling tube, the source of the second sampling tube, and the emitter of the external triode are respectively connected to the input voltage, the gate of the first sampling tube, the gate of the second sampling tube, and the gate of the power tube are connected to each other, and the collector of the external triode is connected to the drain of the power tube; The drain of the first mirror tube of the first current mirror is connected to the drain of the first sampling tube, and the drain of the second mirror tube of the first current mirror is connected to the drain of the second sampling tube; the up-count input of the counter is connected between the drain of the second sampling tube and the drain of the second mirror tube, and the down-count input of the counter is connected between the drain of the first sampling tube and the drain of the first mirror tube; The digital-to-analog converter circuit is connected to the output end of the counter and the base of the external transistor respectively, and the digital-to-analog converter circuit can control the base current of the external transistor according to the output value of the counter.

2. The low voltage dropout linear regulator circuit according to claim 1, characterized in that: It also includes a freewheeling resistor, which is connected between the input voltage and the base of the external transistor.

3. The low voltage dropout linear regulator circuit according to claim 1, characterized in that: It also includes a clamping diode, wherein the anode of the clamping diode is grounded, and the cathode is connected to the drain of the power tube.

4. The low voltage dropout linear regulator circuit according to claim 1, characterized in that: The first current mirror comprises a bias current source and a first reference tube; The first reference tube obtains the bias current output by the bias current source. The first reference tube forms a current mirror with the first mirror tube and the second mirror tube respectively, and the first mirror tube and the second mirror tube can mirror the bias current flowing through the first reference tube.

5. The low voltage dropout linear regulator circuit according to claim 1, characterized in that: The digital-to-analog converter circuit includes a second current mirror having a plurality of mirror tubes and a plurality of switch MOS tubes; The second current mirror comprises a reference current source, a second reference tube and a plurality of third mirror tubes, the second reference tube obtains the current of the reference current source, the second reference tube and the plurality of third mirror tubes respectively form a current mirror, and the mirror tube sizes of the plurality of third mirror tubes gradually increase; The plurality of switch MOS tubes are correspondingly connected to the plurality of third mirror tubes, and the switch MOS tubes are used to control whether the current mirrored by the corresponding third mirror tube is output as the base current of the external transistor.

6. The low voltage dropout linear regulator circuit according to claim 5, characterized in that: The counter is a 7-bit counter, and the number of the third mirror tubes and the number of the switch MOS tubes are seven respectively; The multiple switch MOS tubes control the current of the corresponding third mirror tube according to the output value of the counter to determine whether to output the current as the base current of the external transistor.

7. The low voltage dropout linear regulator circuit according to claim 6, characterized in that: The mirror tube size ratio of the seven third mirror tubes is 1:1:2:4:8:16:32:

64.

8. The low voltage dropout linear regulator circuit according to any one of claims 1 to 7, characterized in that: The counter counts up when the second sampling current flowing through the second sampling tube is greater than the second mirror current flowing through the second mirror tube; counts down when the first sampling current flowing through the first sampling tube is less than the first mirror current flowing through the first mirror tube; and stops counting when the first sampling current or the second sampling current is between the first mirror current and the second mirror current.

9. The low voltage dropout linear regulator circuit according to claim 8, characterized in that: The external transistor is a PNP transistor.

10. A low voltage dropout linear regulator, characterized in that: It comprises a low voltage dropout linear regulator circuit as described in any one of claims 1 to 9.

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