A low-dropout linear regulator circuit and low-dropout linear regulator

Abstract

The application discloses a low-dropout linear voltage regulator circuit and a low-dropout linear voltage regulator, and the low-dropout linear voltage regulator circuit comprises a power tube, the source of the power tube is connected with an input voltage; the low-dropout linear voltage regulator circuit further comprises a first sampling tube, a second sampling tube, an external triode, a first current mirror with two mirror tubes, a counter and a digital-to-analog converter circuit; the collector of the external triode is connected with the drain of the power tube; the drain of the first mirror tube of the first current mirror is connected with the drain of the first sampling tube, and the drain of the second mirror tube of the first current mirror is connected with the drain of the second sampling tube; the plus counting input of the counter is connected between the drain of the second sampling tube and the drain of the second mirror tube, and the minus counting input of the counter is connected between the drain of the first sampling tube and the drain of the first mirror tube; the digital-to-analog converter circuit is connected with the output of the counter and the base of the external triode respectively. The application can share the load current by the external triode, and the chip temperature rise and power consumption are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a low-dropout linear regulator circuit and a low-dropout linear regulator. BACKGROUND

[0002] LDO circuit (low-dropout linear regulator) is a common functional module in integrated circuits, mainly used for converting high-voltage domain power in the system into stable output power in the low-voltage domain. Compared with switching power supply, LDO circuit belongs to linear voltage reduction circuit, and is widely used in many application scenarios due to its simple structure, low cost and other advantages.

[0003] However, the current LDO circuit has certain limitations in load capacity, and its performance is usually limited by power tube power loss. When the voltage drop on the power tube is large, it will cause significant power loss, thereby causing the chip temperature to rise. In severe cases, this thermal effect may trigger an over-temperature protection mechanism or burn the chip, affecting the normal operation of the system.

[0004] Therefore, there is a need for a new technical solution. SUMMARY

[0005] Therefore, the embodiments of the present application provide a low-dropout linear regulator circuit and a low-dropout linear regulator to at least solve the problem that the power tube of the existing low-dropout linear regulator is prone to causing the chip temperature to rise when the voltage drop is large.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] The embodiments of the present application provide a low-dropout linear regulator circuit, comprising a power tube, the source of the power tube is connected with an input voltage, and the low-dropout linear regulator circuit further comprises a first sampling tube, a second sampling tube, an external triode, a first current mirror with two mirror tubes, a counter and a digital-to-analog converter circuit.

[0008] The source of the first sampling tube, the source of the second sampling tube and the emitter of the external triode are respectively connected with the input voltage, the gate of the first sampling tube, the gate of the second sampling tube and the gate of the power tube are connected with each other, and the collector of the external triode is connected with the drain of the power tube.

[0009] The drain of the first mirror tube of the first current mirror is connected with the drain of the first sampling tube, and the drain of the second mirror tube of the first current mirror is connected with the drain of the second sampling tube; the count-in input of the counter is connected between the drain of the second sampling tube and the drain of the second mirror tube, and the count-out input of the counter is connected between the drain of the first sampling tube and the drain of the first mirror tube.

[0010] The digital-to-analog converter circuit is connected with the output of the counter and the base of the external transistor, and the digital-to-analog converter circuit can control the base current of the external transistor according to the output value of the counter.

[0011] Further, a freewheeling resistor is connected between the input voltage and the base of the external transistor.

[0012] Further, a clamping diode is provided, with the anode connected to the ground and the cathode connected to the drain of the power transistor.

[0013] Further, the first current mirror comprises a bias current source and a first reference tube.

[0014] The first reference tube obtains the bias current output by the bias current source, and the first reference tube and the second mirror tube form a current mirror, and the first mirror tube and the second mirror tube can mirror the bias current flowing through the first reference tube.

[0015] Further, the digital-to-analog converter circuit comprises a second current mirror with multiple mirror tubes and multiple switch MOS tubes.

[0016] The second current mirror comprises a reference current source, a second reference tube and multiple third mirror tubes, the second reference tube obtains the current of the reference current source, and the second reference tube and multiple third mirror tubes form a current mirror, and the sizes of the multiple third mirror tubes gradually increase.

[0017] The multiple switch MOS tubes are connected with the multiple third mirror tubes, and the switch MOS tube is used to control whether the current mirrored by the corresponding third mirror tube is output as the base current of the external transistor.

[0018] Further, the counter is a 7-bit counter, and the third mirror tube and the switch MOS tube are seven respectively.

[0019] The multiple switch MOS tubes control whether the current of the corresponding third mirror tube is output as the base current of the external transistor according to the output value of the counter.

[0020] Further, the sizes of the seven third mirror tubes are in the ratio of 1:1:2:4:8:16:32:64.

[0021] Further, the counter counts up when the second sampling current flowing through the second sampling tube is greater than the second mirror current flowing through the second mirror tube, counts down when the first sampling current flowing through the first sampling tube is less than the first mirror current flowing through the first mirror tube, and stops counting when the first sampling current or the second sampling current is between the first mirror current and the second mirror current.

[0022] Further, the external triode is a PNP type triode.

[0023] The application further provides a low-dropout linear regulator comprising the low-dropout linear regulator circuit as any of the above.

[0024] Compared with the prior art, the application has at least the following beneficial effects:

[0025] The low-dropout linear regulator circuit can count up or down according to the first sampling current flowing through the first sampling tube, the first mirror current flowing through the first mirror tube, the second sampling current flowing through the second sampling tube and the second mirror current flowing through the second mirror tube, and then the digital-to-analog converter circuit controls the base current of the external triode according to the output value of the counter, so that the external triode can provide load current together with the power tube, thereby sharing the load current with the external triode, and the problem of temperature rise of the chip caused by too large current flowing through the power tube in the prior art is solved, and the temperature rise and power consumption of the chip are greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0027] Figure 1 The circuit diagram of the existing low-dropout linear regulator;

[0028] Figure 2 The circuit diagram of the low-dropout linear regulator circuit of the application;

[0029] Figure 3 The current waveforms of the internal power tube and the external triode of the low-dropout linear regulator circuit of the application when the load current changes slowly;

[0030] Figure 4 The current waveforms of the internal power tube and the external triode of the low-dropout linear regulator circuit of the application when the load current changes rapidly. DETAILED DESCRIPTION

[0031] The embodiments of the present application will be described below in detail with reference to the accompanying drawings.

[0032] The above and other aspects of the present application will become more apparent by describing in detail the embodiments thereof with reference to the attached drawings in which:

[0033] It is to be understood that the foregoing description is that of certain examples of the application and that numerous changes in the details of construction and the combination and arrangement of parts can be made by those skilled in the art without departing from the scope of the application.

[0034] It is also to be understood that the following description is only one of the various aspects of the present application. Accordingly, various modifications can be made in detail to the embodiments of the present application without changing the overall scope of the application.

[0035] In addition, in the following description, numerous specific details are provided in order to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the application can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth.

[0036] As Figure 1The existing low dropout linear regulator shown in the figure, when applied to the vehicle power supply, the input voltage is up to 28V, the output voltage is 5V, the voltage difference on the power tube is 23V, for the output current of 300mA, the power tube loss reaches 5V*300mA=6.9W, which is a great loss, which will undoubtedly cause the chip temperature to rise and trigger the over-temperature protection, and in severe cases it will burn the chip.

[0037] The working principle of the existing low dropout linear regulator is that the error amplifier A1 is used to clamp the vref voltage and the resistance feedback voltage, and the power tube is used to provide the load current Iload, so that the output voltage Vout=(1+R1 / R2)*vref provides a stable voltage for other modules, which is independent of the input voltage VIN.

[0038] Based on this, the embodiment of the present application proposes a processing scheme: as Figure 2 The low dropout linear regulator of the present application can control the current size of the external triode pnp according to the current size flowing through the power tube Mp, so as to share part of the load current by using the external triode pnp, so as to reduce the power consumption and chip temperature rise of the power tube Mp inside the low dropout linear regulator.

[0039] The technical solutions provided by the embodiments of the present application are described below with reference to the accompanying drawings.

[0040] As Figures 2-4 The low dropout linear regulator circuit of the present application includes a power tube Mp, the source of the power tube Mp is connected with the input voltage, the gate of the power tube Mp is connected with the operational amplifier, the drain of the power tube Mp is connected with the ground through two series resistors, and the drain of the power tube Mp is also connected with an equivalent resistor RL and an equivalent capacitor CL, and the equivalent resistor RL and the equivalent capacitor CL are connected in parallel and are both connected between the drain of the power tube Mp and the ground.

[0041] Among them, the positive input end of the operational amplifier is connected between the two series resistors, and the negative input end is connected with the reference voltage.

[0042] Among them, the power tube Mp can be a P-type MOS tube.

[0043] Further, the low dropout linear regulator circuit further comprises a first sampling tube Ms1, a second sampling tube Ms2, an external pnp transistor, a first current mirror with two mirror tubes, a counter 10 and a digital-to-analog converter circuit 20; the source of the first sampling tube Ms1, the source of the second sampling tube Ms2 and the emitter of the external pnp transistor are respectively connected with the input voltage, the gate of the first sampling tube Ms1, the gate of the second sampling tube Ms2 and the gate of the power tube Mp are connected with each other, and the collector of the external pnp transistor is connected with the drain of the power tube Mp; the drain of the first mirror tube M2 of the first current mirror is connected with the drain of the first sampling tube Ms1, and the drain of the second mirror tube M3 of the first current mirror is connected with the drain of the second sampling tube Ms2; the count-up input of the counter 10 is connected between the drain of the second sampling tube Ms2 and the drain of the second mirror tube M3, and the count-down input of the counter 10 is connected between the drain of the first sampling tube Ms1 and the drain of the first mirror tube M2; the digital-to-analog converter circuit is connected with the output of the counter 10 and the base of the external pnp transistor, respectively, and the digital-to-analog converter circuit 20 can control the base current Ib of the external pnp transistor according to the output value of the counter 10.

[0044] Wherein, the power tube Mp and the first sampling tube Ms1 and the second sampling tube Ms2 form a current mirror, so that the first sampling tube Ms1 and the second sampling tube Ms2 can sample the current flowing through the power tube Mp.

[0045] Wherein, the first sampling tube Ms1 and the second sampling tube Ms2 are both P-type MOS tubes; the external pnp transistor is a PNP-type transistor.

[0046] Specifically, the first current mirror comprises a bias current source, a first reference tube M1, a first mirror tube M2 and a second mirror tube M3; the first reference tube M1 obtains the bias current output by the bias current source, the first reference tube M1 and the first mirror tube M2 and the second mirror tube M3 form a current mirror, and the first mirror tube M2 and the second mirror tube M3 can mirror the bias current flowing through the first reference tube M1.

[0047] More specifically, the first reference tube M1, the first mirror tube M2 and the second mirror tube M3 are all N-type MOS tubes, and the drain of the first reference tube M1 is connected with the output of the bias current source and the gate of the first reference tube M1, respectively, and the source of the first reference tube M1 is grounded; the gate of the first mirror tube M2, the gate of the second mirror tube M3 and the gate of the first reference tube M1 are connected with each other, and the source of the first mirror tube M2 and the source of the second mirror tube M3 are both grounded.

[0048] Wherein, the counter 10 is a count-up and count-down counter, and the counter 10 has two input signals (count-up input and count-down input) for controlling the count-up or count-down of the counter.

[0049] Wherein, the counter 10 adds count when the second sampling current Is2 flowing through the second sampling tube Ms2 is greater than the second mirror current Iu flowing through the second mirror tube M3; the counter 10 subtracts count when the first sampling current Is1 flowing through the first sampling tube Ms1 is less than the first mirror current Id flowing through the first mirror tube M2; the counter 10 stops counting when the first sampling current Is1 or the second sampling current Is2 is between the first mirror current Id and the second mirror current Iu.

[0050] Specifically, when the second sampling current Is2 is greater than the second mirror current Iu, the add count input of the counter 10 is high, and at this time the counter 10 adds count; when the first sampling current Is1 is less than the first mirror current Id, the subtract count input of the counter 10 is low, and at this time the counter 10 subtracts count.

[0051] Further, the digital-to-analog converter circuit 20 comprises a second current mirror having a plurality of mirror tubes and a plurality of switch MOS tubes 24; the second current mirror comprises a reference current source 21, a second reference tube 22 and a plurality of third mirror tubes 23, the second reference tube 22 obtains the current of the reference current source 21, the second reference tube 22 and the plurality of third mirror tubes 23 form a current mirror respectively, and the mirror tube size of the plurality of third mirror tubes 23 gradually increases; the plurality of switch MOS tubes 24 are connected with the plurality of third mirror tubes 23 correspondingly, and the switch MOS tube 24 is used for controlling whether the current mirrored by the corresponding third mirror tube 23 is output as the base current Ib of the external triode pnp.

[0052] Wherein, the second reference tube 22, the third mirror tube 23 and the switch MOS tube 24 are all N-type MOS tubes.

[0053] Specifically, the drain of the second reference tube 22 is connected with the output end of the reference current source 21 and the gate of the second reference tube 22 respectively, the gates of the plurality of third mirror tubes 23 are connected with each other, the drain of each third mirror tube 23 is connected with the source of the corresponding switch MOS tube 24, and the source of each third mirror tube 23 is grounded.

[0054] Wherein, the drain of each switch MOS tube 24 is connected with the base of the external triode pnp, and the gate of each switch MOS tube 24 is controlled by the counter 10, and the counter 10 can control whether the switch MOS tube 24 is turned on by controlling the gate current of the switch MOS tube 24.

[0055] Further, the counter 10 is a 7-bit counter, and the third mirror tube 23 and the switch MOS tube 24 are seven respectively; the plurality of switch MOS tubes 24 control whether the current of the corresponding third mirror tube 23 is output as the base current Ib of the external triode pnp according to the output value of the counter 10.

[0056] The output value of counter 10 is a 7-bit binary signal. This output signal can be converted into the base current Ib signal of the external transistor PNP by the digital-to-analog converter circuit composed of the third current mirror, thereby controlling the base current Ib of the external transistor PNP.

[0057] Furthermore, the size ratio of the seven third mirror tubes 23 is 1:1:2:4:8:16:32:64.

[0058] In some embodiments, the low-dropout linear regulator circuit also includes a freewheeling resistor Rb connected between the input voltage and the base of an external transistor pnp.

[0059] The freewheeling resistor Rb is used to ensure that the transistor's Vbe is 0 when the base current Ib is 0, so that the external transistor PNP will not conduct and there is no leakage current.

[0060] In some embodiments, the low-dropout linear regulator circuit also includes a clamping diode zener, with the anode of the clamping diode zener grounded and the cathode connected to the drain of the power transistor Mp.

[0061] A clamping diode zener is used to both supply and discharge current when a single power transistor Mp cannot do so, so that current can be discharged through the clamping diode zener.

[0062] like Figure 2 As shown, when the load current is 0 and the current of the external transistor PNP remains constant, it is equivalent to charging the equivalent capacitor CL, which will cause the output voltage Vout to spike, potentially damaging internal components.

[0063] The specific working principle of a low-dropout linear regulator circuit according to the present invention is as follows:

[0064] This invention uses a first sampling transistor Ms1 and a second sampling transistor Ms2 connected in parallel with the power transistor Mp to obtain the first sampling current Is1 and the second sampling current Is2 of the power transistor current Ipower. The first sampling current Is1 and the second sampling current Is2 are compared with two reference currents Id and Iu (Id: first mirror current; Iu: second mirror current), and two logic signals counter+ and counter- are generated according to the comparison result. counter+ and counter- are used as input signals of the up-down counter 10 to control the up and down of the counter 10, respectively. The output of the counter 10 is a 7-bit binary signal Q<6:0>.

[0065] The digital-to-analog converter circuit 20 is used to convert the output Q<6:0> of the counter 10 into the base current Ib of the external transistor pnp, which has a third current mirror, the initial current of the third current mirror is Ibin, the mirror size of the plurality of third mirror tubes 23 is 1:1:2:4:8:16:32:64, the plurality of third mirror currents generated on the plurality of third mirror tubes 23 are 1*Ibin, 2*Ibin, 4*Ibin, 8*Ibin, 16*Ibin, 32*Ibin, 64*Ibin respectively, and the plurality of third mirror currents are determined by the plurality of switch MOS tubes 24 controlled by the output signals Q<0>, Q<1>, Q<2>, Q<3>, Q<4>, Q<5>, Q<6> of the counter 10 whether the third mirror current flows through the external transistor pnp as part of the Ib current. Among them, the output signals of the counter 10 are all high level effective, that is, when Q <x>For high times, the Q <x>The signal-controlled power transistor Mp is turned on, and the corresponding third mirror current is superimposed into the base current Ib, Q <x>When the value is low, the current in this circuit is 0.

[0066] For example, for the output signal Q<6:0>=0101001 of counter 10, Ib=1*Ibin+8*Ibin+32*Ibin

[0067] =41*Ibin. For Q<6:0>=0010111, Ib=1*Ibin+2*Ibin+4*Ibin+16*Ibin=23*Ibin. Therefore, the larger the value of the output signal Q<6:0>, the larger the base current Ib, and the larger the current Ipnp of the external transistor PNP. Conversely, the smaller the value of Q<6:0>, the smaller the current Ipnp of the external transistor PNP.

[0068] Specifically, when the load current Iload is too large, the second sampling current Is2 obtained through sampling will be larger. When the second sampling current Is2 exceeds the second mirror current Iu, that is, when the power transistor current Ipower exceeds the threshold Iact_pnp (the activation current of the external transistor), counter+ is active high, counter 10 starts counting, the value of Q<6:0> starts to increase, the base current Ib increases, and the current Ipnp flowing through the external transistor pnp increases. When the load current Iload decreases, the first sampling current Is1 obtained through sampling will be smaller. When the first sampling current Is1 exceeds the first mirror current Id, that is, when the power transistor current Ipower is less than the threshold Ideact_pnp (the turn-off current of the external transistor), counter- is active low, counter 10 starts counting down, the value of Q<6:0> starts to decrease, the base current Ib decreases, and the current Ipnp flowing through the external transistor pnp decreases. When the load current Iload is between Ideact_pnp and Iact_pnp, counter 10 stops counting, and the current Ipnp remains unchanged.

[0069] Appendix Figure 3 The figure shows the current waveforms of the internal power transistor Mp and the external transistor PNP in the architecture proposed in this invention when the load current changes slowly. Taking a maximum load current Iload of 250mA as an example, it can be seen from the figure that when the load current Iload begins to rise slowly, the power transistor current Ipower follows the rise of the load current Iload, and the two currents are of the same magnitude. At this time, there is no current in the external transistor PNP, and the current Ipnp flowing through the external transistor PNP is 0. When the load current Iload reaches Iact_pnp, the external transistor PNP starts to have current, and the current Ipnp rises along with the load current Iload. The power transistor current Ipower remains unchanged at the value of Iact_pnp. That is to say, the load current Iload that exceeds Iact_pnp is provided by the external transistor PNP, up to the upper limit of the external transistor PNP. When the load current Iload begins to decrease slowly, the current of the external transistor PNP remains unchanged temporarily. The power transistor current Ipower decreases along with the load current Iload. When the power transistor current Ipower is less than Ideact_pnp, the current Ipnp begins to decrease. At this point, the power transistor current Ipower remains unchanged. As the load current Iload continues to decrease, the current Ipnp also gradually decreases until it reaches 0. At this point, the external transistor PNP has no current, and the load current Iload is entirely the power transistor current. If Iload further decreases to 0, the power transistor current will also decrease to 0 along with Iload.

[0070] Appendix Figure 4 The figure shows the current waveforms of the internal power transistor Mp and the external transistor Pnp when the load current changes rapidly. As can be seen from the figure, when the load current Iload rapidly jumps to its maximum value, the increase in current Ipnp is relatively slow because the external transistor Pnp is driven by the counter. At this time, the current of the power transistor Mp will first follow the load current Iload to reach its maximum value. Then, as the current Ipnp increases, the power transistor current Ipower slowly decreases to around Iact_pnp. After that, the counter stops counting, Ipnp no longer increases, and Ipower no longer decreases; both remain constant, and their sum is still equal to the total load current. When the load current Iload jumps rapidly from its maximum value to 0, similarly, the current Ipnp remains unchanged at first, while the power transistor current Ipower drops rapidly to 0 and continues to drop below 0. That is, the current that was originally supplying current to the output changes to discharging current from the output to ground. Then, as the current Ipnp decreases, the power transistor current MpIpower also slowly rises from a negative current to 0. Finally, the load current Iload is 0, and the power transistor currents Ipower and Ipnp are also 0.

[0071] The application generates the input control signal of the counter 10 by sampling the current of the power tube Mp and comparing it with two reference currents respectively, when the current of the power tube is greater than a certain value (such as greater than the second mirror current Iu), the counter 10 performs addition operation, the greater the binary signal value outputted is, the greater the base current converted by the digital-to-analog converter circuit 20 is, and the greater the current of the external transistor pnp is; when the current of the power tube is less than a certain value (such as less than the first mirror current Id), the counter 10 performs subtraction operation, the smaller the binary signal value outputted is, the smaller the base current converted by the digital-to-analog converter circuit 20 is, and the smaller the current of the external transistor pnp is; when the current of the power tube Mp is between the two threshold values, the counter 10 stops counting, and the current of the external transistor pnp remains unchanged.

[0072] The low-dropout linear regulator circuit of the application uses the external transistor pnp outside the chip and the power tube Mp inside the chip in parallel, samples the current of the internal power tube Mp to realize the control of the current size of the external transistor pnp, and the internal power tube Mp and the external transistor pnp outside the chip jointly provide current for the load, which greatly reduces the temperature rise and power consumption of the chip and expands the upper limit of the output current of the ldo (low-dropout linear regulator).

[0073] The application further provides a low-dropout linear regulator comprising the low-dropout linear regulator circuit as any one of the above.

[0074] In the specification, the same and similar parts among various embodiments can be referred to each other, and each embodiment focuses on the difference from other embodiments. Especially, for the product embodiment described later, since it is corresponding to the method, the description is relatively simple, and the related parts can be referred to the part of the system embodiment.

[0075] The above is merely a specific implementation of the application, but the protection scope of the application is not limited to this, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the application, which should be covered in the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.< / x> < / x> < / x>

Claims

1. A low dropout linear regulator circuit comprising a power transistor, the source of the power transistor being connected to an input voltage, characterized in that, The low dropout linear regulator circuit further comprises a first sampling tube, a second sampling tube, an external triode, a first current mirror with two mirror tubes, a counter and a digital-to-analog converter circuit; The source of the first sampling tube, the source of the second sampling tube and the emitter of the external triode are connected with the input voltage respectively, the gate of the first sampling tube, the gate of the second sampling tube and the gate of the power tube are connected with each other, and the collector of the external triode is connected with the drain of the power tube; The drain of the first mirror tube of the first current mirror is connected with the drain of the first sampling tube, and the drain of the second mirror tube of the first current mirror is connected with the drain of the second sampling tube; the count-in input of the counter is connected between the drain of the second sampling tube and the drain of the second mirror tube, and the count-out input of the counter is connected between the drain of the first sampling tube and the drain of the first mirror tube; The digital-to-analog converter circuit is connected with the output of the counter and the base of the external triode respectively, and the digital-to-analog converter circuit can control the base current of the external triode according to the output value of the counter.

2. The low dropout linear regulator circuit of claim 1, wherein, A freewheeling resistor is further included, which is connected between the input voltage and the base of the external triode.

3. The low dropout linear regulator circuit of claim 1, wherein, A clamping diode is further included, the anode of which is grounded, and the cathode of which is connected with the drain of the power tube.

4. The low dropout linear regulator circuit of claim 1, wherein, The first current mirror comprises a bias current source and a first reference tube; The first reference tube obtains the bias current output by the bias current source, the first reference tube and the first mirror tube and the second mirror tube form a current mirror respectively, and the first mirror tube and the second mirror tube can mirror the bias current flowing through the first reference tube.

5. The low dropout linear regulator circuit of claim 1, wherein, The digital-to-analog converter circuit comprises a second current mirror with multiple mirror tubes and multiple switch MOS tubes; The second current mirror comprises a reference current source, a second reference tube and multiple third mirror tubes, the second reference tube obtains the current of the reference current source, the second reference tube and multiple third mirror tubes form a current mirror respectively, and the sizes of the mirror tubes of multiple third mirror tubes gradually increase; Multiple switch MOS tubes are connected with multiple third mirror tubes respectively, and the switch MOS tubes are used to control whether the current mirrored by the corresponding third mirror tube is output as the base current of the external triode.

6. The low dropout linear regulator circuit of claim 5, wherein, The counter is a 7-bit counter, and the third mirror tubes and the switch MOS tubes are seven respectively; The multiple switch MOS tubes control whether the current of the corresponding third mirror tube is output as the base current of the external triode according to the output value of the counter.

7. The low dropout linear regulator circuit of claim 6, wherein, The sizes of the mirror tubes of the seven third mirror tubes are in the ratio of 1:1:2:4:8:16:32:

64.

8. The low dropout linear regulator circuit according to any one of claims 1 to 7, wherein, The counter counts up when a second sampling current flowing through the second sampling tube is greater than a second mirror current flowing through the second mirror tube; counts down when a first sampling current flowing through the first sampling tube is less than a first mirror current flowing through the first mirror tube; and stops counting when the first sampling current or the second sampling current is between the first mirror current and the second mirror current.

9. The low dropout linear regulator circuit of claim 8, wherein, The external triode is a PNP type triode.

10. A low-dropout linear voltage regulator, comprising: The low-dropout linear regulator circuit comprises the low-dropout linear regulator circuit as claimed in any one of claims 1-9.

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