LDO circuit and chip

Abstract

The invention discloses an LDO circuit and a chip, and relates to the technical field of integrated circuits. The LDO circuit comprises an LDO power supply output end, a reference voltage input end, a reference current input end, an LDO feedback control loop and a current limiting protection circuit. The LDO feedback control loop comprises an error amplifier and an LDO power tube, and the error amplifier can adjust the magnitude of current flowing through the LDO power tube based on the reference voltage and the output voltage so as to keep the output voltage stable. The current-limiting protection circuit comprises a current mirror bias branch and a current mirror current-limiting branch, and the current mirror bias branch can provide corresponding bias current based on reference current. The current mirror current limiting branch circuit limits the current flowing through the LDO power tube based on the bias current, so that the current flowing through the LDO power tube does not exceed a first preset current limiting threshold value. The current-limiting protection setting of the LDO circuit has the advantages of being high in current-limiting precision, high in response speed and small in overall circuit power consumption.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a LDO circuit and chip. Background Art

[0002] Low Dropout Regulator (LDO) is widely used in chips due to its simple structure, low output noise, fast transient response, etc. In actual application environment, when the load current changes rapidly or the input voltage is unstable, LDO may have overcurrent phenomenon, that is, the output current exceeds the preset maximum current threshold, which may cause the chip temperature to rise, and even cause chip damage or system abnormal operation.

[0003] In order to protect the LDO and the chip used in it from damage, a current limiting protection setting can usually be performed on the LDO. However, the current limiting protection setting currently applied to the LDO circuit has the disadvantages of low current limiting accuracy, slow response speed and high power consumption of the overall circuit. Summary of the invention

[0004] The main purpose of the present application is to provide an LDO circuit, aiming to solve the problems of low current limiting accuracy, slow response speed and high overall circuit power consumption in the current limiting protection setting of the existing LDO circuit.

[0005] To achieve the above purpose, the LDO circuit proposed in this application includes:

[0006] LDO power supply output terminal;

[0007] A reference voltage input terminal, used for inputting a reference voltage;

[0008] A reference current input terminal, used for inputting a reference current;

[0009] An LDO feedback control loop, wherein the LDO feedback control loop is connected to the LDO power supply output terminal and the reference voltage input terminal respectively; the LDO feedback control loop comprises an error amplifier and an LDO power tube; the error amplifier is used to adjust the current flowing through the LDO power tube based on the reference voltage and the output voltage of the LDO power supply output terminal to keep the output voltage of the LDO power supply output terminal stable;

[0010] A current limiting protection circuit, the current limiting protection circuit comprising:

[0011] A current mirror bias branch, the current mirror bias branch is connected to the reference current input terminal, and the current mirror bias branch is used to provide a corresponding bias current based on the reference current;

[0012] A current mirror current limiting branch, wherein the current mirror current limiting branch is respectively connected to the current mirror bias branch and the LDO feedback control loop, and the current mirror current limiting branch is used to limit the current flowing through the LDO power tube based on the bias current, so that the current flowing through the LDO power tube does not exceed a first preset current limiting threshold.

[0013] In one embodiment, the LDO circuit includes a plurality of current mirror current limiting branches; each of the plurality of current mirror current limiting branches has an enable signal input terminal, and the enable signal input terminal is used to input an enable signal for controlling the current mirror current limiting branch to be in an on state / off state;

[0014] The multiple current mirror current limiting branches are used to limit the current flowing through the LDO power tube based on the bias current so that the output current value of the LDO power supply output end does not exceed a second preset current limiting threshold; wherein the second preset current limiting threshold is the product of the number of the current mirror current limiting branches in the on state and the first preset current limiting threshold.

[0015] In one embodiment, the LDO circuit includes a first power supply terminal; the LDO power tube is a first MOS tube, and the LDO feedback control loop also includes a second MOS tube and a third MOS tube;

[0016] The source of the first MOS tube and the source of the second MOS tube are connected to the first power supply end, and the drain of the first MOS tube is connected to the LDO power supply output end; the gate of the first MOS tube, the gate of the second MOS tube, and the drain of the second MOS tube are connected to the source of the third MOS tube; the gate of the third MOS tube is connected to the output end of the error amplifier;

[0017] The error amplifier is used to adjust the current flowing through the third MOS tube according to the reference voltage and the output voltage of the LDO power supply output end, so as to adjust the current of the first MOS tube.

[0018] In one embodiment, the LDO feedback control loop further includes a first resistor and a second resistor; one end of the first resistor and the drain of the first MOS tube are connected to the LDO power supply output terminal; the other end of the first resistor and one end of the second resistor are connected to the non-inverting input terminal of the error amplifier; the other end of the second resistor is grounded; the inverting input terminal of the error amplifier is connected to the reference voltage input terminal;

[0019] The error amplifier is used to adjust the current flowing through the third MOS tube according to the reference voltage and the voltage sampled at the other end of the first resistor.

[0020] In one embodiment, the current mirror bias branch includes a third resistor, a fourth MOS transistor and a fifth MOS transistor; the current mirror current limiting branch includes a sixth MOS transistor, a seventh MOS transistor and an eighth MOS transistor;

[0021] One end of the third resistor, the reference current input end, the gate of the fourth MOS tube and the gate of the seventh MOS tube are connected; the other end of the third resistor, the drain of the fourth MOS tube, the gate of the fifth MOS tube and the gate of the eighth MOS tube are connected; the source of the fourth MOS tube is connected to the drain of the fifth MOS tube; the gate of the sixth MOS tube is connected to the first enable signal input end; the drain of the sixth MOS tube is connected to the drain of the third MOS tube; the source of the sixth MOS tube is connected to the drain of the seventh MOS tube; the source of the seventh MOS tube is connected to the drain of the eighth MOS tube; the source of the eighth MOS tube and the source of the fifth MOS tube are grounded.

[0022] In one embodiment, the LDO circuit includes three current mirror current limiting branches; the first current mirror current limiting branch includes the sixth MOS tube, the seventh MOS tube and the eighth MOS tube, the second current mirror current limiting branch includes the ninth MOS tube, the tenth MOS tube and the eleventh MOS tube, and the third current mirror current limiting branch includes the twelfth MOS tube, the thirteenth MOS tube and the fourteenth MOS tube;

[0023] The gate of the ninth MOS tube is connected to the second enable signal input terminal; the source of the ninth MOS tube is connected to the drain of the tenth MOS tube; the source of the tenth MOS tube is connected to the drain of the eleventh MOS tube; the source of the eleventh MOS tube is grounded; the drain of the ninth MOS tube is connected to the drain of the third MOS tube; the gate of the tenth MOS tube is connected to the gate of the fourth MOS tube; the gate of the eleventh MOS tube is connected to the gate of the fifth MOS tube;

[0024] The gate of the twelfth MOS tube is connected to the third enable signal input terminal; the source of the twelfth MOS tube is connected to the drain of the thirteenth MOS tube; the source of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube; the source of the fourteenth MOS tube is grounded; the drain of the tenth MOS tube is connected to the drain of the third MOS tube; the gate of the thirteenth MOS tube is connected to the gate of the fourth MOS tube; the gate of the thirteenth MOS tube is connected to the gate of the fifth MOS tube.

[0025] In one embodiment, the LDO circuit further includes:

[0026] A reference circuit, wherein a first output terminal of the reference circuit is connected to the reference voltage input terminal, and a second output terminal of the reference circuit is connected to the reference current input terminal; the reference circuit is used to provide the reference voltage and the reference current.

[0027] In one embodiment, the LDO circuit further includes a first power supply terminal, and the reference circuit includes a fifteenth MOS transistor, a sixteenth MOS transistor, a seventeenth MOS transistor, an eighteenth MOS transistor, an operational amplifier, a first triode circuit, a second triode circuit, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor;

[0028] The source of the fifteenth MOS tube, the source of the sixteenth MOS tube, the source of the seventeenth MOS tube, and the source of the eighteenth MOS tube are connected to the first power supply end; the gate of the fifteenth MOS tube, the gate of the sixteenth MOS tube, the gate of the seventeenth MOS tube, and the gate of the eighteenth MOS tube are connected to the output end of the operational amplifier; the drain of the fifteenth MOS tube, the first end of the first triode circuit, and one end of the fourth resistor are connected to the inverting input end of the operational amplifier; the drain of the sixteenth MOS tube, the non-inverting input end of the operational amplifier, and one end of the fifth resistor are connected to one end of the sixth resistor; the drain of the seventeenth MOS tube and the reference voltage input end are connected to one end of the seventh resistor; the drain of the eighteenth MOS tube is connected to the reference current input end. an input end thereof; the other end of the fifth resistor is connected to the first end of the second triode circuit; the second end of the first triode circuit, the other end of the fourth resistor, the second end of the second triode circuit, the other end of the sixth resistor and the other end of the seventh resistor are grounded; wherein the first triode circuit comprises a plurality of first triodes, the emitters of the plurality of first triodes are all connected to the first end of the first triode circuit, the collectors of the plurality of first triodes and the bases of the plurality of first triodes are all connected to the second end of the first triode circuit; the second triode circuit comprises a plurality of second triodes, the emitters of the plurality of second triodes are all connected to the first end of the second triode circuit, the collectors of the plurality of second triodes and the bases of the plurality of second triodes are all connected to the second end of the second triode circuit.

[0029] In one embodiment, the LDO circuit further includes a load resistor and a load capacitor, one end of the load resistor and one end of the load capacitor are connected to the LDO power supply output terminal, and the other end of the load resistor and the other end of the load capacitor are grounded.

[0030] The present application also proposes a chip, wherein the chip includes the LDO circuit as described above.

[0031] The technical solution of the present application adopts an LDO circuit, including an LDO power supply output terminal, a reference voltage input terminal, a reference current input terminal, an LDO feedback control loop and a current limiting protection circuit. Among them, the error amplifier adjusts the current flowing through the LDO power tube based on the reference voltage and the output voltage of the LDO power supply output terminal to keep the output voltage of the LDO power supply output terminal stable. In the negative feedback regulation process of the LDO feedback control loop, in order to limit the current of the LDO power tube, the present application sets a current limiting protection circuit, which includes a current mirror bias branch and a current mirror current limiting branch. The current mirror bias branch provides a corresponding bias current based on the reference current. The current mirror current limiting branch is used to limit the current flowing through the LDO power tube based on the bias current, so that the current flowing through the LDO power tube does not exceed the first preset current limiting threshold, and the output current of the load end does not exceed the first preset current limiting threshold, and will not cause damage to the LDO circuit and the chip used therein. In this way, the present application realizes the current limiting protection of the LDO circuit, and the output current can be limited by the current mirror structure of the current limiting protection circuit, which reduces the error caused by the use of resistors and comparator structures in the traditional structure, and the current limiting protection has high accuracy. If the output current at the load end exceeds the first preset current limiting threshold, the current of the LDO power tube drops rapidly, the output voltage at the output end of the LDO power supply drops rapidly, and the response speed of the current limiting protection is fast. In addition, the current limiting protection circuit of the present application only needs to consume the current of two branches, the current mirror bias branch and the current mirror current limiting branch, and the overall LDO circuit power consumption is very low. In this way, compared with the prior art, the LDO circuit of the present application has high current limiting accuracy, fast response speed, and low overall circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0033] Figure 1 An electronic circuit diagram of an embodiment of an LDO circuit provided by the present application;

[0034] Figure 2 An electronic circuit diagram of a reference circuit of an embodiment of an LDO circuit provided in the present application;

[0035] Figure 3 This is a schematic diagram of simulation results of the output voltage and load current of an embodiment of the LDO circuit provided in the present application changing with the output load resistance.

[0036] Description of Figure Numbers:

[0037]

[0038]

[0039] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0042] In addition, the descriptions of "first", "second", etc. in this application are only for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0043] Low Dropout Regulator (LDO) is mainly used to convert input voltage into stable output voltage. It is widely used in various chips due to its simple structure, low output noise, fast transient response and other advantages. In order to protect the LDO and its applied chips from damage, the LDO can usually be set with current limiting protection. However, the existing current limiting protection settings applied to LDO circuits have the disadvantages of low current limiting accuracy, slow response speed and high overall circuit power consumption.

[0044] The present application provides a LDO circuit.

[0045] See also Figure 1 In one embodiment of the present application, the LDO circuit includes:

[0046] LDO power supply output terminal;

[0047] A reference voltage input terminal, used for inputting a reference voltage;

[0048] A reference current input terminal, used for inputting a reference current;

[0049] An LDO feedback control loop 10, the LDO feedback control loop 10 is connected to the LDO power supply output terminal and the reference voltage input terminal respectively; the LDO feedback control loop 10 includes an error amplifier EA and an LDO power tube; the error amplifier EA is used to adjust the current flowing through the LDO power tube based on the reference voltage and the output voltage of the LDO power supply output terminal to keep the output voltage of the LDO power supply output terminal stable;

[0050] The current limiting protection circuit 20 includes:

[0051] A current mirror bias branch 21, the current mirror bias branch 21 is connected to the reference current input terminal, and the current mirror bias branch 21 is used to provide a corresponding bias current based on the reference current;

[0052] The current mirror current limiting branch 22 is connected to the current mirror bias branch 21 and the LDO feedback control loop 10 respectively. The current mirror current limiting branch 22 is used to limit the current flowing through the LDO power tube based on the bias current so that the current flowing through the LDO power tube does not exceed the first preset current limiting threshold.

[0053] In this embodiment, the LDO feedback control loop 10 can adjust the current flowing through the LDO power tube based on the reference voltage and the output voltage of the LDO power output terminal to keep the output voltage of the LDO power output terminal stable. For example, the LDO power tube can be a PMOS tube. When the output voltage of the LDO power output terminal suddenly increases, the error amplifier EA can detect the change based on the reference voltage, causing the output of the error amplifier EA to also increase, and the current of the LDO power tube is adjusted to be smaller, so that the output voltage of the LDO power output terminal is reduced. When the output voltage of the LDO power output terminal suddenly decreases, the error amplifier EA can detect the change based on the reference voltage, causing the output of the error amplifier EA to also decrease, and the current of the LDO power tube is adjusted to be larger, so that the output voltage of the LDO power output terminal is reduced. Therefore, when the output voltage of the LDO power output terminal changes, the error amplifier EA can adjust the conduction degree of the LDO power tube, and then adjust the current of the LDO power tube, so as to keep the output voltage of the LDO power output terminal stable.

[0054] It should be noted that when the load current changes rapidly or the input voltage is unstable, an overcurrent phenomenon may occur in the LDO circuit. In this embodiment, a current limiting protection circuit 20 is provided to perform current limiting protection on the circuit. Among them, the current limiting protection circuit 20 includes a current mirror bias branch 21 and a current mirror current limiting branch 22. The current mirror bias branch 21 can provide a corresponding bias current based on a reference current, and the current mirror current limiting branch 22 can limit the current flowing through the LDO power tube based on the bias current, so that the current flowing through the LDO power tube does not exceed the first preset current limiting threshold. In this way, this embodiment can limit the current of the LDO power tube. If the load end current exceeds the first preset current limiting threshold, the current of the LDO power tube drops rapidly, and the output voltage of the LDO power supply output end drops rapidly, and the response speed of the current limiting protection is fast.

[0055] In this embodiment, the first preset current limiting threshold that meets the requirements can be set by setting the first preset current limiting threshold and the width of the LDO power tube, the length of the LDO power tube and the parameter values ​​of other MOS tubes in the LDO feedback control loop 10. Among them, the current of the LDO power tube of the LDO feedback control loop 10 is limited by the current mirror structure of the current limiting protection circuit 20, which reduces the error caused by the use of resistors and comparator structures in the traditional structure, and the current limiting protection has high accuracy.

[0056] In this embodiment, when the output current at the load end exceeds the first preset current limiting threshold, since the LDO power tube of the LDO feedback control loop 10 cannot provide a current output exceeding the first preset current limiting threshold, the output voltage of the LDO power supply output end decreases, and the current limiting protection responds quickly.

[0057] In this embodiment, in addition to the LDO feedback control loop 10, the current limiting protection circuit 20 only needs to consume two branch currents, namely the current mirror bias branch 21 and the current mirror current limiting branch 22, and the overall LDO circuit power consumption is very low.

[0058] In the present application, the error amplifier EA adjusts the current flowing through the LDO power tube based on the reference voltage and the output voltage of the LDO power output terminal to keep the output voltage of the LDO power output terminal stable. In the negative feedback regulation process of the LDO feedback control loop 10, in order to limit the current of the LDO power tube, the present application sets a current limiting protection circuit 20, which includes a current mirror bias branch 21 and a current mirror current limiting branch 22. The current mirror bias branch 21 provides a corresponding bias current based on the reference current. The current mirror current limiting branch 22 is used to limit the current flowing through the LDO power tube based on the bias current, so that the current flowing through the LDO power tube does not exceed the first preset current limiting threshold. In this way, the present application realizes the current limiting protection of the LDO circuit, and the output current value of the LDO power output terminal is limited by the current mirror structure of the current limiting protection circuit 20, which reduces the error caused by the resistor and comparator structure in the traditional structure, and the current limiting protection has high accuracy. If the output current at the load end exceeds the first preset current limiting threshold, the current of the LDO power tube drops rapidly, the output voltage at the LDO power supply output end drops rapidly, and the response speed of the current limiting protection is fast. In addition, the current limiting protection circuit 20 of the present application only needs to consume two branch currents, namely the current mirror bias branch 21 and the current mirror current limiting branch 22, and the overall LDO circuit power consumption is very low. In this way, compared with the prior art, the LDO circuit of the present application has high current limiting accuracy, fast response speed, and low overall circuit power consumption.

[0059] See also Figure 1 In one embodiment of the present application, the LDO circuit includes a plurality of current mirror current limiting branches 22; each of the plurality of current mirror current limiting branches 22 has an enable signal input terminal, and the enable signal input terminal is used to input an enable signal for controlling the current mirror current limiting branch 22 to be in an on state / off state;

[0060] The multiple current mirror current limiting branches 22 are used to limit the current flowing through the LDO power tube based on the bias current so that the output current value of the LDO power supply output end does not exceed the second preset current limiting threshold; wherein the second preset current limiting threshold is the product of the number of current mirror current limiting branches 22 in the on state and the first preset current limiting threshold.

[0061] In this embodiment, multiple current mirror current limiting branches 22 are added, and the enable signal of the current mirror current limiting branch 22 can be set by communication with an external host computer, so that multi-speed adjustment of different current limiting thresholds of current limiting protection can be achieved. For example, when the enable signal is used to indicate that the three current mirror current limiting branches 22 are in the on state, the second preset current limiting threshold is equal to 3 multiplied by the first preset current limiting threshold. In this way, the second preset current limiting threshold can be dynamically adjusted by the input enable signal, and different levels of second preset current limiting thresholds can be set according to actual needs and protection strategies, ensuring that the LDO circuit can perform flexible current protection under different load conditions, and has a multi-speed fine overcurrent protection mechanism.

[0062] See also Figure 1 In one embodiment of the present application, the LDO circuit includes a first power supply terminal; the LDO power tube is a first MOS tube MP1, and the LDO feedback control loop 10 also includes a second MOS tube MP2 and a third MOS tube MP3;

[0063] The source of the first MOS tube MP1 and the source of the second MOS tube MP2 are connected to the first power supply terminal, and the drain of the first MOS tube MP1 is connected to the LDO power supply output terminal; the gate of the first MOS tube MP1, the gate of the second MOS tube MP2, the drain of the second MOS tube MP2 are connected to the source of the third MOS tube MP3; the gate of the third MOS tube MP3 is connected to the output terminal of the error amplifier EA;

[0064] The error amplifier EA is used to adjust the current flowing through the third MOS tube MP3 according to the reference voltage and the output voltage of the LDO power supply output terminal, so as to adjust the current of the first MOS tube MP1.

[0065] The LDO feedback control loop 10 also includes a first resistor R1 and a second resistor R2; one end of the first resistor R1 and the drain of the first MOS tube MP1 are connected to the LDO power supply output terminal; the other end of the first resistor R1 and one end of the second resistor R2 are connected to the non-inverting input terminal of the error amplifier EA; the other end of the second resistor R2 is grounded; the inverting input terminal of the error amplifier EA is connected to the reference voltage input terminal;

[0066] The error amplifier EA is used to adjust the current flowing through the third MOS transistor MP3 according to the reference voltage and the voltage sampled at the other end of the first resistor R1.

[0067] See also Figure 1 In one embodiment of the present application, the LDO circuit also includes a load resistor RL and a load capacitor CL, one end of the load resistor RL and one end of the load capacitor CL are connected to the LDO power supply output end, and the other end of the load resistor RL and the other end of the load capacitor CL are grounded.

[0068] It should be noted that the first MOS transistor MP1, the second MOS transistor MP2 and the third MOS transistor MP3 can all be PMOS transistors. The first MOS transistor MP1 and the second MOS transistor MP2 form a current mirror. In this embodiment, the ratio of the width-to-length ratio of the second MOS transistor MP2 to the width-to-length ratio of the first MOS transistor MP1 is set to K, that is,

[0069] K*(W2 / L2)=W1 / L1

[0070] Wherein, K is a proportionality coefficient, W2 is a width of the second MOS transistor MP2, L2 is a length of the second MOS transistor MP2, W1 is a width of the first MOS transistor MP1, and L1 is a length of the first MOS transistor MP1;

[0071] Then, the current value flowing through the first MOS transistor MP1 is K times the current value flowing through the second MOS transistor MP2, that is,

[0072] K*I2=I1

[0073] Wherein, I2 is the current value flowing through the second MOS transistor MP2, and I1 is the current value flowing through the first MOS transistor MP1.

[0074] It should be noted that the load circuit can be equivalent to a load resistor RL and a load capacitor CL connected in parallel, and the load capacitor CL can filter out high-frequency noise to stabilize the output voltage Vout.

[0075] It should be noted that when the load resistance RL suddenly increases (the output current at the load end suddenly decreases), causing the output voltage to suddenly increase, the feedback voltage VFB also increases, causing the output voltage of the error amplifier EA to increase, the gate-source voltage of the third MOS tube MP3 to decrease, the current flowing through the third MOS tube MP3 to decrease, the current flowing through the first MOS tube MP1 to also decrease, the output voltage Vout decreases accordingly, and the feedback voltage VFB also decreases until VFB=VBG (VBG is the reference voltage), so the output of the LDO feedback control loop 10 remains stable. Similarly, when the load resistance RL suddenly decreases (the output current suddenly increases), causing the output voltage to suddenly decrease, the feedback voltage VFB also decreases, causing the output voltage of the error amplifier EA to increase, the gate-source voltage of the third MOS tube MP3 to increase, the current flowing through the third MOS tube MP3 to increase, the current flowing through the first MOS tube MP1 to also increase, the output voltage Vout increases accordingly, and the feedback voltage VFB also increases until VFB=VBG, and the output of the LDO feedback control loop 10 remains stable. Therefore, when the output current at the load end changes and causes the output voltage Vout to fluctuate, the LDO feedback control loop 10 will timely adjust the current flowing through the third MOS transistor MP3 to limit the current flowing through the first MOS transistor MP1, thereby ensuring the stability of the output voltage Vout.

[0076] It should be noted that the relationship between the feedback voltage VFB and the output voltage Vout is:

[0077] VFB=Vout*R2 / (R1+R2)

[0078] Then the relationship between the output voltage Vout and the reference voltage VBG is:

[0079] Vout=VFB*(R1+R2) / R2=VBG*(R1+R2) / R2

[0080] In this way, the present embodiment can stabilize the output voltage Vout at a voltage value near VBG*(R1+R2) / R2 through the LDO feedback control loop 10.

[0081] See also Figure 1 In one embodiment of the present application, the current mirror bias branch 21 includes a third resistor R3, a fourth MOS transistor MN4 and a fifth MOS transistor MN5; the current mirror current limiting branch 22 includes a sixth MOS transistor MN6, a seventh MOS transistor MN7 and an eighth MOS transistor MN8;

[0082] One end of the third resistor R3, the reference current input end, the gate of the fourth MOS tube MN4 and the gate of the seventh MOS tube MN7 are connected; the other end of the third resistor R3, the drain of the fourth MOS tube MN4, the gate of the fifth MOS tube MN5 and the gate of the eighth MOS tube MN8 are connected; the source of the fourth MOS tube MN4 is connected to the drain of the fifth MOS tube MN5; the gate of the sixth MOS tube MN6 is connected to the first enable signal input end; the drain of the sixth MOS tube MN6 is connected to the drain of the third MOS tube MP3; the source of the sixth MOS tube MN6 is connected to the drain of the seventh MOS tube MN7; the source of the seventh MOS tube MN7 is connected to the drain of the eighth MOS tube MN8; the source of the eighth MOS tube MN8 and the source of the fifth MOS tube MN5 are grounded.

[0083] In this embodiment, the sixth MOS transistor MN6 is set to be in an on state, so as to limit the current flowing through the second MOS transistor MP2, wherein the maximum current I2 flowing through the second MOS transistor MP2 is the current of the current mirror current limiting branch 22, that is, the reference current IREF.

[0084] K*I2=I1

[0085] The first preset current limiting threshold is K*IREF, that is, the maximum current flowing through the first MOS tube MP1 is K*IREF, that is, the output current does not exceed K*IREF. In this way, accurate current limiting of the output current of the LDO power supply output terminal is achieved.

[0086] See also Figure 3 , Figure 3 The figure is a schematic diagram of the simulation results of the output voltage of the LDO power supply output terminal changing with the output load resistance. Among them, M1 is the curve of the output voltage changing with the load resistance RL, and M2 is the curve of the load current passing through the load resistance RL changing with the load resistance RL.

[0087] When the load resistance RL is relatively large, for example, when the preset load resistance RL is 900Ω, the current at the load end reaches the maximum, which is a current value that does not exceed the first preset current limiting threshold. Then when the load resistance RL is greater than 900Ω, as the load resistance RL increases, the output voltage at the output end of the LDO power supply remains stable, specifically stable near the voltage value of VBG*(R1+R2) / R2. According to Ohm's law, at this time, the load current decreases as the load resistance RL increases. When the load resistance RL is less than 900Ω, as the load resistance RL decreases, since the maximum current of the first MOS tube MP1 does not exceed the first preset current limiting threshold, the load current does not exceed the first preset current limiting threshold, and the load current is almost a maximum current constant. According to Ohm's law, at this time, the output voltage at the output end of the LDO power supply decreases as the load resistance RL decreases. It can be seen that this embodiment can achieve precise current limiting protection for the LDO circuit.

[0088] See also Figure 1 In one embodiment of the present application, the LDO circuit includes three current mirror current limiting branches 22; the first current mirror current limiting branch 22 includes a sixth MOS tube MN6, a seventh MOS tube MN7 and an eighth MOS tube MN8, the second current mirror current limiting branch 22 includes a ninth MOS tube MN9, a tenth MOS tube MN10 and an eleventh MOS tube MN11, and the third current mirror current limiting branch 22 includes a twelfth MOS tube MN12, a thirteenth MOS tube MN13 and a fourteenth MOS tube MN14;

[0089] The gate of the ninth MOS transistor MN9 is connected to the second enable signal input terminal; the source of the ninth MOS transistor MN9 is connected to the drain of the tenth MOS transistor MN10; the source of the tenth MOS transistor MN10 is connected to the drain of the eleventh MOS transistor MN11; the source of the eleventh MOS transistor MN11 is grounded; the drain of the ninth MOS transistor MN9 is connected to the drain of the third MOS transistor MP3; the gate of the tenth MOS transistor MN10 is connected to the gate of the fourth MOS transistor MN4; the gate of the eleventh MOS transistor MN11 is connected to the gate of the fifth MOS transistor MN5;

[0090] The gate of the twelfth MOS tube MN12 is connected to the third enable signal input terminal; the source of the twelfth MOS tube MN12 is connected to the drain of the thirteenth MOS tube MN13; the source of the thirteenth MOS tube MN13 is connected to the drain of the fourteenth MOS tube MN14; the source of the fourteenth MOS tube MN14 is grounded; the drain of the tenth MOS tube MN10 is connected to the drain of the third MOS tube MP3; the gate of the thirteenth MOS tube MN13 is connected to the gate of the fourth MOS tube MN4; the gate of the thirteenth MOS is connected to the gate of the fifth MOS tube MN5.

[0091] In this embodiment, the current mirror uses a common source and common gate current mirror to reduce the error of the current mirror. Among them, the third resistor R3, the fourth MOS tube MN4 and the fifth MOS tube MN5 are the self-bias structure of the current mirror. It is known that the current mirror current limiting branch 22 is the reference current IREF. According to the current formula of the MOS tube saturation region:

[0092]

[0093] Among them, μ n is the electron mobility, C ox is the gate oxide capacitance per unit area, W is the width of the MOS tube, L is the length of the MOS tube, V GS is the gate-source voltage of the MOS tube, V TH is the threshold voltage of the MOS tube.

[0094] Then the voltage at point P1 is:

[0095]

[0096] Therefore, the voltage at point P2 is:

[0097] VB2=VB1+IREF·R3

[0098] In this way, the operating voltage of the MOS tube in the saturation region can be calculated, and then a suitable reference current IREF can be provided according to the selection of MOS tubes with different parameters, so that the reference current IREF is adapted to the operating state of the MOS tube in the saturation region.

[0099] In this embodiment, the fourth MOS tube MN4 to the fourteenth MOS tube MN14 can all be NMOS tubes, and the fourth MOS tube MN4, the seventh MOS tube MN7, the tenth MOS tube MN10, and the thirteenth MOS tube MN13 have the same width-to-length ratio, and the fifth MOS tube MN5, the eighth MOS tube MN8, the eleventh MOS tube MN11, and the fourteenth MOS tube MN14 have the same width-to-length ratio, so the branch currents of the first current mirror current limiting branch where the eighth MOS tube MN8 is located, the second current mirror current limiting branch where the eleventh MOS tube MN11 is located, and the third current mirror current limiting branch where the fourteenth MOS tube MN14 is located are all equal to the reference current IREF. Among them, the sixth MOS tube MN6, the ninth MOS tube MN9, and the twelfth MOS tube MN12 are switch tubes of the three current mirror current limiting branches 22, which are controlled by the enable signal. By default, only the sixth MOS tube MN6 can be turned on, so the maximum current flowing through the second MOS tube MP2 and the third MOS tube MP3 is IREF. Because the first MOS tube MP1 and the second MOS tube MP2 are in a current mirror relationship, the width-to-length ratio relationship is:

[0100] K*(W2 / L2)=W1 / L1

[0101] Therefore, the maximum current flowing through the first MOS tube MP1 is K*IREF, that is, the second preset current limiting threshold is K*IREF. When the output current at the load end is greater than K*IREF, the LDO power tube cannot provide it, so the output voltage Vout will drop and force the output current at the load end to decrease, thereby protecting the safety of the LDO circuit. Analogously, if the sixth MOS tube MN6, the ninth MOS tube MN9 and the twelfth MOS tube MN12 are all turned on, the maximum current flowing through the first MOS tube MP1 is 3K*IREF, that is, the second current threshold is 3K*IREF. When the output current at the load end is greater than 3K*IREF, the LDO power tube cannot provide it, so the output voltage Vout will drop and force the output current to decrease, thereby protecting the safety of the LDO circuit. In this way, the present embodiment can provide three gears of the second preset current limiting threshold, which are K*IREF, 2K*IREF and 3K*IREF, respectively, which improves the adaptability of the LDO circuit to multiple scenarios. It is understandable that the current mirror current limiting branch 22 can also be N paths, where N is a positive integer of 2 or greater than 3, and N can be specifically set according to specific current limiting requirements, which is not limited here.

[0102] In this embodiment, for the current limiting protection accuracy, a current mirror method is adopted, and the magnitude of the output current has a mirror relationship with the current value of the current limiting protection, which reduces the error caused by the resistor and comparator structure used in the traditional structure. For the response speed of the current limiting protection, the output of the error amplifier EA directly controls the current of the third MOS tube MP3, and the current limiting protection circuit 20 limits the current of the third MOS tube MP3, and then copies the current through the current mirror formed by the first MOS tube MP1 and the second MOS tube MP2 to obtain the current of the first MOS tube MP1, that is, the current of the LDO power tube, which can limit the output current from the source, reducing the protection response time. The structure of the current limiting protection circuit 20 is simple, and the current of a single current mirror current limiting branch 22 can be very low, thereby realizing a low power consumption design.

[0103] See also Figure 1 In one embodiment of the present application, the LDO circuit further includes:

[0104] The reference circuit 30 has a first output terminal connected to a reference voltage input terminal, and a second output terminal connected to a reference current input terminal; the reference circuit 30 is used to provide a reference voltage and a reference current.

[0105] It should be noted that the reference circuit 30 can be a low-voltage bandgap reference source circuit. Among them, the low-voltage bandgap reference source circuit can provide a stable reference voltage within a wide operating voltage range, and the reference voltage and reference current outputted by it are not easily affected by temperature changes, and the output of the reference voltage and reference current is relatively stable. In this way, the circuit design can be simplified, the additional power consumption and complexity can be reduced, and the stability of the LDO circuit can be enhanced and the current limiting accuracy can be improved.

[0106] See also Figure 2 In one embodiment of the present application, the LDO circuit further includes a first power supply terminal, and the reference circuit 30 includes a fifteenth MOS transistor MP15, a sixteenth MOS transistor MP16, a seventeenth MOS transistor MP17, an eighteenth MOS transistor MP18, an operational amplifier OP, a first triode circuit Qm1, a second triode circuit Qm2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, and a seventh resistor R7;

[0107] The source of the fifteenth MOS tube MP15, the source of the sixteenth MOS tube MP16, the source of the seventeenth MOS tube MP17, and the source of the eighteenth MOS tube MP18 are connected to the first power supply terminal; the gate of the fifteenth MOS tube MP15, the gate of the sixteenth MOS tube MP16, the gate of the seventeenth MOS tube MP17, and the gate of the eighteenth MOS tube MP18 are connected to the output terminal of the operational amplifier OP; the drain of the fifteenth MOS tube MP15, the first end of the first triode circuit Qm1, and one end of the fourth resistor R4 are connected to the inverting input terminal of the operational amplifier OP; The drain of the MOS tube MP16, the non-inverting input terminal of the operational amplifier OP, one end of the fifth resistor R5 and one end of the sixth resistor R6 are connected; the drain of the seventeenth MOS tube MP17, the reference voltage input terminal and one end of the seventh resistor R7 are connected; the drain of the eighteenth MOS tube MP18 is connected to the reference current input terminal; the other end of the fifth resistor R5 is connected to the first end of the second triode circuit Qm2; the second end of the first triode circuit Qm1, the other end of the fourth resistor R4, the second end of the second triode circuit Qm2, the other end of the sixth resistor R6 and the other end of the seventh resistor R7 are grounded.

[0108] It should be noted that the first triode circuit Qm1 includes a plurality of first triodes connected in parallel, and the second triode circuit Qm2 includes a plurality of second triodes connected in parallel. In this embodiment, the first triode and the second triode may be triodes with the same parameters, and the ratio of the number of the first triode to the number of the second triode is n. Among them, the emitters of the plurality of first triodes are all connected to the first end of the first triode circuit Qm1, and the collectors of the plurality of first triodes and the bases of the plurality of first triodes are all connected to the second end of the first triode circuit Qm1; the second triode circuit Qm2 includes a plurality of second triodes, the emitters of the plurality of second triodes are all connected to the first end of the second triode circuit Qm2, and the collectors of the plurality of second triodes and the bases of the plurality of second triodes are all connected to the second end of the second triode circuit Qm2.

[0109] It should be noted that the fourth resistor R4, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 of this embodiment are all zero temperature coefficient resistors, whose resistance values ​​do not change with temperature, so as to output a relatively stable reference voltage and reference current.

[0110] In this embodiment, the reference circuit 30 is specifically a low-voltage bandgap reference source circuit, which is connected to the first power supply terminal as an input and can output a reference voltage VBG with a zero temperature coefficient and a reference current IREF with a zero temperature coefficient. Among them, the fifteenth MOS tube MP15 to the eighteenth MOS tube MP18 can all be PMOS tubes, which together form a PMOS current mirror, and its gate voltage is adjusted by the output of the operational amplifier OP. The virtual short and virtual break characteristics of the operational amplifier OP are used to keep the voltage at point X and point Y the same size, which is equal to VBE1. Select a suitable value to make R6=R4, so the current flowing through the resistors R6 and R4 is the same, and the following current formula is obtained:

[0111]

[0112] Among them, I R6 is the current value flowing through the sixth resistor R6, I R4 is the current value flowing through the fourth resistor R4, VBE2 is the voltage difference between the first end and the second end of the second transistor circuit Qm2, and VBE1 is the voltage difference between the first end and the second end of the first transistor circuit Qm1.

[0113] but:

[0114]

[0115] Among them, I R5 is the current value flowing through the fifth resistor R5, n is the ratio of the number of the first transistor to the number of the second transistor, which can generally be 8, V T is the thermal voltage of the first transistor / the second transistor.

[0116] Therefore, the current flowing through the seventeenth MOS tube MP17 is equal to the sum of the currents of the resistors R5 and R6, and the expression is as follows:

[0117]

[0118] The current flows through the resistor R7 to obtain the reference voltage VBG. At the same time, the eighteenth MOS tube MP18 copies the current through the current mirror to obtain a reference current IREF, and the result is:

[0119]

[0120] In this embodiment, when R5 and R6 satisfy the relationship (R 2 / R 1 )lnn≈17.2, the output reference voltage VBG and the reference current IREF can have a zero temperature coefficient.

[0121] In this way, this embodiment can provide a reference voltage VBG with a zero temperature coefficient, whose voltage value does not change with temperature; it can provide a reference current IREF with a zero temperature coefficient, whose current value does not change with temperature. The provided reference voltage VBG and reference current IREF are both relatively stable, thereby improving the current limiting protection accuracy of the LDO circuit.

[0122] The present application also proposes a chip, which includes an LDO circuit. The specific structure of the LDO circuit refers to the above-mentioned embodiment. Since the present chip adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be described one by one here.

[0123] The above description is only an exemplary embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the technical concept of the present application, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application.

Claims

1. An LDO circuit, characterized in that: include: LDO power supply output terminal; A reference voltage input terminal, used for inputting a reference voltage; A reference current input terminal, used for inputting a reference current; An LDO feedback control loop, wherein the LDO feedback control loop is connected to the LDO power supply output terminal and the reference voltage input terminal respectively; The LDO feedback control loop includes an error amplifier and an LDO power tube; the error amplifier is used to adjust the current flowing through the LDO power tube based on the reference voltage and the output voltage of the LDO power output end to keep the output voltage of the LDO power output end stable; A current limiting protection circuit, the current limiting protection circuit comprising: A current mirror bias branch, the current mirror bias branch is connected to the reference current input terminal, and the current mirror bias branch is used to provide a corresponding bias current based on the reference current; A current mirror current limiting branch, wherein the current mirror current limiting branch is respectively connected to the current mirror bias branch and the LDO feedback control loop, and the current mirror current limiting branch is used to limit the current flowing through the LDO power tube based on the bias current, so that the current flowing through the LDO power tube does not exceed a first preset current limiting threshold.

2. The LDO circuit according to claim 1, wherein: The LDO circuit comprises a plurality of current mirror current limiting branches; each of the plurality of current mirror current limiting branches has an enable signal input terminal, and the enable signal input terminal is used to input an enable signal for controlling the current mirror current limiting branch to be in an on state / off state; The multiple current mirror current limiting branches are used to limit the current flowing through the LDO power tube based on the bias current so that the output current value of the LDO power supply output end does not exceed a second preset current limiting threshold; wherein the second preset current limiting threshold is the product of the number of the current mirror current limiting branches in the on state and the first preset current limiting threshold.

3. The LDO circuit according to claim 1, wherein: The LDO circuit includes a first power supply terminal; the LDO power tube is a first MOS tube, and the LDO feedback control loop also includes a second MOS tube and a third MOS tube; The source of the first MOS tube and the source of the second MOS tube are connected to the first power supply end, and the drain of the first MOS tube is connected to the LDO power supply output end; the gate of the first MOS tube, the gate of the second MOS tube, and the drain of the second MOS tube are connected to the source of the third MOS tube; The gate of the third MOS tube is connected to the output end of the error amplifier; The error amplifier is used to adjust the current flowing through the third MOS tube according to the reference voltage and the output voltage of the LDO power supply output end, so as to adjust the current of the first MOS tube.

4. The LDO circuit according to claim 3, characterized in that: The LDO feedback control loop also includes a first resistor and a second resistor; one end of the first resistor and the drain of the first MOS tube are connected to the LDO power supply output end; the other end of the first resistor and one end of the second resistor are connected to the non-inverting input end of the error amplifier; the other end of the second resistor is grounded; the inverting input end of the error amplifier is connected to the reference voltage input end; The error amplifier is used to adjust the current flowing through the third MOS tube according to the reference voltage and the voltage sampled at the other end of the first resistor.

5. The LDO circuit according to claim 3, characterized in that: The current mirror bias branch includes a third resistor, a fourth MOS tube and a fifth MOS tube; the current mirror current limiting branch includes a sixth MOS tube, a seventh MOS tube and an eighth MOS tube; One end of the third resistor, the reference current input end, the gate of the fourth MOS tube and the gate of the seventh MOS tube are connected; the other end of the third resistor, the drain of the fourth MOS tube, the gate of the fifth MOS tube and the gate of the eighth MOS tube are connected; the source of the fourth MOS tube is connected to the drain of the fifth MOS tube; the gate of the sixth MOS tube is connected to the first enable signal input end; the drain of the sixth MOS tube is connected to the drain of the third MOS tube; the source of the sixth MOS tube is connected to the drain of the seventh MOS tube; the source of the seventh MOS tube is connected to the drain of the eighth MOS tube; the source of the eighth MOS tube and the source of the fifth MOS tube are grounded.

6. The LDO circuit according to claim 5, characterized in that: The LDO circuit includes three current mirror current limiting branches; the first current mirror current limiting branch includes the sixth MOS tube, the seventh MOS tube and the eighth MOS tube, the second current mirror current limiting branch includes the ninth MOS tube, the tenth MOS tube and the eleventh MOS tube, and the third current mirror current limiting branch includes the twelfth MOS tube, the thirteenth MOS tube and the fourteenth MOS tube; The gate of the ninth MOS tube is connected to the second enable signal input terminal; the source of the ninth MOS tube is connected to the drain of the tenth MOS tube; the source of the tenth MOS tube is connected to the drain of the eleventh MOS tube; the source of the eleventh MOS tube is grounded; the drain of the ninth MOS tube is connected to the drain of the third MOS tube; the gate of the tenth MOS tube is connected to the gate of the fourth MOS tube; the gate of the eleventh MOS tube is connected to the gate of the fifth MOS tube; The gate of the twelfth MOS tube is connected to the third enable signal input terminal; the source of the twelfth MOS tube is connected to the drain of the thirteenth MOS tube; the source of the thirteenth MOS tube is connected to the drain of the fourteenth MOS tube; the source of the fourteenth MOS tube is grounded; the drain of the tenth MOS tube is connected to the drain of the third MOS tube; the gate of the thirteenth MOS tube is connected to the gate of the fourth MOS tube; the gate of the thirteenth MOS tube is connected to the gate of the fifth MOS tube.

7. The LDO circuit according to claim 1, wherein: The LDO circuit further includes: A reference circuit, wherein a first output terminal of the reference circuit is connected to the reference voltage input terminal, and a second output terminal of the reference circuit is connected to the reference current input terminal; the reference circuit is used to provide the reference voltage and the reference current.

8. The LDO circuit according to claim 7, wherein: The LDO circuit also includes a first power supply terminal, and the reference circuit includes a fifteenth MOS tube, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, an operational amplifier, a first triode circuit, a second triode circuit, a fourth resistor, a fifth resistor, a sixth resistor, and a seventh resistor; The source of the fifteenth MOS tube, the source of the sixteenth MOS tube, the source of the seventeenth MOS tube, and the source of the eighteenth MOS tube are connected to the first power supply end; the gate of the fifteenth MOS tube, the gate of the sixteenth MOS tube, the gate of the seventeenth MOS tube, and the gate of the eighteenth MOS tube are connected to the output end of the operational amplifier; the drain of the fifteenth MOS tube, the first end of the first triode circuit, and one end of the fourth resistor are connected to the inverting input end of the operational amplifier; the drain of the sixteenth MOS tube, the non-inverting input end of the operational amplifier, and one end of the fifth resistor are connected to one end of the sixth resistor; the drain of the seventeenth MOS tube and the reference voltage input end are connected to one end of the seventh resistor; the drain of the eighteenth MOS tube is connected to the reference current input end. an input end thereof; the other end of the fifth resistor is connected to the first end of the second triode circuit; the second end of the first triode circuit, the other end of the fourth resistor, the second end of the second triode circuit, the other end of the sixth resistor and the other end of the seventh resistor are grounded; wherein the first triode circuit comprises a plurality of first triodes, the emitters of the plurality of first triodes are all connected to the first end of the first triode circuit, the collectors of the plurality of first triodes and the bases of the plurality of first triodes are all connected to the second end of the first triode circuit; the second triode circuit comprises a plurality of second triodes, the emitters of the plurality of second triodes are all connected to the first end of the second triode circuit, the collectors of the plurality of second triodes and the bases of the plurality of second triodes are all connected to the second end of the second triode circuit.

9. The LDO circuit according to any one of claims 1 to 8, characterized in that: It also includes a load resistor and a load capacitor, one end of the load resistor and one end of the load capacitor are connected to the LDO power supply output end, and the other end of the load resistor and the other end of the load capacitor are grounded.

10. A chip, characterized in that: The invention comprises the LDO circuit as claimed in any one of claims 1 to 9.

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