Electronic equipment and eMMC rate mode switching method and device thereof

Abstract

The invention provides an electronic device and an eMMC rate mode switching method and device thereof. The rate mode switching method comprises the following steps: sending a first rate mode switching instruction and a clock signal to an eMMC; wherein the first rate mode switching instruction indicates that the eMMC is switched from a current working rate mode to a target working mode; determining a transmission delay value of a clock signal in response to a failure of switching the eMMC to the target working mode; and resending the first rate mode switching instruction and the clock signal matched with the transmission delay value to the eMMC so as to synchronize the first rate mode switching instruction and the clock signal. By setting the transmission delay value of the clock signal, the synchronization of the transmission of the first rate mode switching instruction and the clock signal can be ensured as much as possible, and the switching success rate of the rate mode of the eMMC is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of electronic devices, and in particular to an electronic device and an eMMC rate mode switching method and device thereof. Background Art

[0002] Embedded Multi Media Card (eMMC) is a standard specification for embedded memory established by the MMC Association, mainly for terminal devices such as mobile phones or tablets. eMMC consists of Flash, Flash controller (including multiple registers) and data transmission interface. Different specifications of eMMC can work in different speed modes, mainly including Legacy mode, High Speed ​​(HS) mode, HS200 mode, HS400 mode, HS400ES mode, etc.

[0003] At present, during the rate mode switching process of eMMC, for example, switching from Legacy mode to HS mode, or switching from HS mode to higher speed mode, due to the material difference of the eMMC device itself, the transmission stability is poor or the wiring between components is not good. As a result, the cmdline (command line) read and write operations are not synchronized with the CLK (ClockSignal) provided by the controller, resulting in some commands or transmissions being unable to be successfully sampled by the clock signal, which leads to the failure of the rate mode switching. Summary of the invention

[0004] The present invention provides an electronic device and an eMMC rate mode switching method and device thereof, so as to improve the success rate of the eMMC working rate mode switching.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] In a first aspect, a rate mode switching method of an eMMC is provided, the rate mode switching method comprising:

[0007] Sending a first rate mode switching instruction and a clock signal to the eMMC; wherein the first rate mode switching instruction instructs the eMMC to switch from a current working rate mode to a target working mode, the current working rate mode of the eMMC is an HS mode or a legacy mode, and the working rate of the target working mode is greater than the rate of the current working rate mode;

[0008] In response to the eMMC failing to switch to the target operating mode, determining a transmission delay value of a clock signal;

[0009] The first rate mode switching instruction and a clock signal matching the transmission delay value are resent to the eMMC to synchronize the first rate mode switching instruction and the clock signal.

[0010] Optionally, determining a transmission delay value of the clock signal includes:

[0011] One clock cycle T of the clock signal is equally divided into N values, and i / N•T is determined as the transmission delay value of resending the clock signal to the eMMC for the i-th time.

[0012] Optionally, determining a transmission delay value of the clock signal includes:

[0013] A binary search is performed on one clock cycle of the clock signal to determine a propagation delay value of the clock signal.

[0014] Optionally, after the step of resending the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, the method further includes:

[0015] In response to the eMMC successfully switching to the target operating mode, a subsequent eMMC initialization process is executed.

[0016] Optionally, after the step of resending the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, the method further includes:

[0017] In response to the eMMC failing to switch to the target operating mode, determining whether the number of times the first rate mode switching instruction is resent reaches a number threshold;

[0018] In response to the number of times reaching the number threshold, a second rate mode switching instruction is sent to the eMMC to instruct the eMMC to switch from the current working rate mode to the Legacy mode.

[0019] In a second aspect, a rate mode switching device for an eMMC is provided, the rate mode switching device comprising:

[0020] A sending module, configured to send a first rate mode switching instruction and a clock signal to the eMMC; wherein the first rate mode switching instruction instructs the eMMC to switch from a current working rate mode to a target working mode, the current working rate mode of the eMMC is an HS mode or a legacy mode, and the working rate of the target working mode is greater than the rate of the current working rate mode;

[0021] A determination module, configured to determine a transmission delay value of a clock signal in response to a failure of the eMMC to switch to the target operating mode;

[0022] The sending module is further used to resend the first rate mode switching instruction and a clock signal matching the transmission delay value to the eMMC to synchronize the first rate mode switching instruction and the clock signal.

[0023] Optionally, the determining module is specifically used to:

[0024] One clock cycle T of the clock signal is equally divided into N values, and i / N•T is determined as the transmission delay value of resending the clock signal to the eMMC for the i-th time.

[0025] Optionally, the determining module is specifically used to:

[0026] A binary search is performed on one clock cycle of the clock signal to determine a propagation delay value of the clock signal.

[0027] Optionally, after the sending module resends the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, it is further used to call the initialization module;

[0028] The initialization module is used to execute a subsequent eMMC initialization process in response to the eMMC successfully switching to the target working mode.

[0029] Optionally, after the sending module resends the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, it is further used to call the judgment module;

[0030] The judgment module is used to determine whether the number of times the first rate mode switching instruction is repeatedly sent reaches a number threshold in response to the eMMC failing to switch to the target working mode; and in response to the number reaching the number threshold, call the sending module to send a second rate mode switching instruction to the eMMC; the second rate mode switching instruction is used to instruct the eMMC to switch from the current working rate mode to the Legacy mode.

[0031] In a third aspect, an electronic device is provided, comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, wherein when the processor executes the computer program, the eMMC rate mode switching method described in any one of the first aspects is implemented.

[0032] In a fourth aspect, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the eMMC rate mode switching method described in any one of the first aspects is implemented.

[0033] In a fifth aspect, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the eMMC rate mode switching method as described in any one of the first aspects is implemented.

[0034] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0035] The positive and progressive effect of the present disclosure is that the present disclosure can ensure that the transmission of the first rate mode switching instruction is synchronized with the clock signal as much as possible by setting the transmission delay value of the clock signal, thereby improving the success rate of switching the rate mode of the eMMC. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1a A timing diagram of a rate mode switching instruction being transmitted earlier than a clock signal in a rate mode switching process of an EMMC provided by the prior art;

[0037] Figure 1b A timing diagram of a rate mode switching instruction being transmitted later than a clock signal in a rate mode switching process of an EMMC provided by the prior art;

[0038] Figure 2 A flow chart of a rate mode switching method of an EMMC provided by an exemplary embodiment of the present disclosure;

[0039] Figure 3 A flow chart of a rate mode switching device of an EMMC provided by an exemplary embodiment of the present disclosure;

[0040] Figure 4 The present invention provides a schematic structural diagram of an electronic device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0042] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0043] At present, in the eMMC communication protocol, only the eMMC devices that need to work in the high-speed transmission mode of HS200 mode and HS400 mode are tuned to obtain the best sampling point, and then the delay value corresponding to the best sampling point is set for communication. In other modes, no delay value is set by default. This method can meet the needs of most eMMC devices with good PCB board routing and good material quality. However, considering the differences in production processes, PCB routing and other influencing factors, if some eMMC devices do not set the transmission delay value in HS mode or legacy mode, mainly referring to the read delay value on the cmdline (command line), it may cause the controller (usually the host controller) to be unable to normally receive the response of the eMMC device. See Figure 1a , the transmission of the rate mode switching instruction CMD6 is earlier than the clock signal CLK, and the sampling cannot be normal, and the response of the eMMC device cannot be received normally. Figure 1b , the transmission of the rate mode switching instruction CMD6 is later than the clock signal CLK, and it cannot be sampled normally, and the response of the eMMC device cannot be received normally. As a result, errors such as CRC (cyclic redundancy check) check are prone to occur during the reading process, resulting in the eMMC device being unable to switch to a higher speed working rate mode, causing problems such as failure to boot, affecting user experience, and increasing the factory defect rate.

[0044] Based on this, the embodiment of the present disclosure provides a rate mode switching method of eMMC, which is applicable to electronic devices using eMMC as storage medium, including but not limited to POS machines, mobile phones, car-related (rearview mirrors, smart cockpits), smart wearable devices, etc. The rate mode switching method is executed by a controller or processor included in the electronic device, such as a host controller on the main control chip that is connected to the eMMC for communication, and the host controller is connected to the eMMC device through a dataline (data line, data transmission line) and a cmdline to provide a clock signal and power supply for the eMMC device.

[0045] Figure 2 A flow chart of a rate mode switching method of an eMMC provided by an exemplary embodiment of the present disclosure, the rate mode switching method comprising the following steps:

[0046] Step 201: Send a first rate mode switching instruction and a clock signal to the eMMC.

[0047] Among them, the first rate mode switching instruction CMD6 is used to instruct the eMMC to switch from the current working rate mode to the target working mode, the current working rate mode of the eMMC is the HS mode or the legacy mode, and the working rate of the target working mode is greater than the rate of the current working rate mode. When the current working rate mode of the eMMC is the legacy mode, the target working mode can be the HS mode or a higher speed working mode such as the HS200 mode, the HS400 mode, the HS400ES mode. When the current working rate mode of the eMMC is the HS mode, the target working mode can be the HS200 mode, the HS400 mode, the HS400ES mode, and other working modes that are higher speed than the HS mode.

[0048] Step 202: In response to the failure of the eMMC to switch to the target working mode, determine a transmission delay value of the clock signal.

[0049] In one embodiment, the controller cannot parse the response sent by the eMMC, and determines that the eMMC fails to switch to the target working mode.

[0050] In one embodiment, the response sent by the eMMC fails to pass the CRC check, and it is determined that the eMMC fails to switch to the target working mode.

[0051] Step 203: resend the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC to synchronize the first rate mode switching instruction and the clock signal.

[0052] The transmission of the first rate mode switching instruction is synchronized with the clock signal, so that the controller can send the first rate mode switching instruction to the eMMC through the rising edge of the clock signal. After receiving the first rate mode switching instruction, the eMMC will process the instruction internally and return a response in synchronization with the clock signal to complete the CRC check, thereby achieving a successful switch of the eMMC rate mode.

[0053] In this embodiment, by setting the transmission delay value of the clock signal, it is possible to ensure that the transmission of the first rate mode switching instruction is synchronized with the clock signal as much as possible, thereby improving the success rate of switching the rate mode of the eMMC.

[0054] In one embodiment, if the eMMC successfully switches to the target working mode after the first rate mode switching instruction and the clock signal matching the transmission delay value are resent to the eMMC, it means that the transmission delay value determined in step 202 is suitable, then the step of looping to determine the transmission delay value is stopped, and the subsequent eMMC initialization process is executed. If the eMMC fails to switch to the target working mode after the first rate mode switching instruction and the clock signal matching the transmission delay value are resent to the eMMC, it means that the transmission delay value determined in step 202 is not suitable and needs to be re-determined, then return to step 202 to re-determine the transmission delay value until the eMMC successfully switches to the target working mode.

[0055] The above subsequent eMMC initialization process may include, but is not limited to: sending a SEND_EXT_CSD command to request the eMMC device to send the contents of its extended CSD register. The EXT_CSD register contains detailed configuration information of the device, and the controller further configures the eMMC device based on this information. The eMMC device enters the data transfer mode (Data Transfer Mode), and the controller starts to read and write data.

[0056] In one embodiment, an upper limit is set for the number of times the instruction is resent. When the number of times the first rate mode switching instruction is resent reaches a threshold value (upper limit), the working mode of the eMMC is still not successfully switched, indicating that the eMMC device cannot communicate normally in the current working mode (for example, HS mode), that is, no matter how the transmission delay value is set, it cannot succeed. In this case, resending the first rate mode switching instruction is stopped to reduce power consumption.

[0057] In one embodiment, after the step of resending the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, the eMMC fails to switch to the target operating mode and the number of resending reaches a threshold number, indicating that the eMMC device cannot communicate normally in the current operating mode (for example, HS mode), a second rate mode switching instruction is sent to the eMMC to instruct the eMMC to switch from the current operating rate mode to Legacy mode.

[0058] The number threshold can be set according to actual conditions. For example, the number threshold is set to N below.

[0059] In one embodiment, the step of determining the transmission delay value of the clock signal includes: dividing a clock cycle of the clock signal into N values, and determining i / N•T as the transmission delay value of resending the clock signal to the eMMC for the i-th time.

[0060] For example, when the first rate mode switching instruction is resent for the first time, 1 / N•T is determined as the transmission delay value of the clock signal. If the eMMC fails to switch to the target working mode after resending the first rate mode switching instruction and the clock signal, a second resending is performed. When the first rate mode switching instruction is resent for the second time, 2 / N•T is determined as the transmission delay value of the clock signal. If the eMMC fails to switch to the target working mode after resending the second rate mode switching instruction and the clock signal, a third resending is performed. When the first rate mode switching instruction is resent for the third time, 3 / N•T is determined as the transmission delay value of the clock signal. If the eMMC fails to switch to the target working mode after resending the second rate mode switching instruction and the clock signal, a fourth resending is performed. And so on, until the eMMC successfully switches to the target working mode, or the number of times the first rate mode switching instruction is resent reaches the number threshold.

[0061] Wherein, T represents a clock cycle of the clock signal. N can be set according to actual conditions, for example, set to 256.

[0062] In this embodiment, by dividing a clock cycle of the clock signal into N values, different transmission delay values ​​are tried in a "step-by-step" manner to obtain the response of the eMMC device until the first rate mode switching instruction can be transmitted normally and the eMMC device successfully switches to the target working mode, that is, the loop is stopped, thereby ensuring that the eMMC device can find a transmission delay value that can normally receive data on the cmdline, which can greatly improve the transmission stability of the eMMC device, avoid the device crash caused by transmission errors during the mode switching process, and improve software compatibility.

[0063] In one embodiment, the step of determining the transmission delay value of the clock signal includes: performing a binary search on a clock cycle of the clock signal to determine the transmission delay value of the clock signal.

[0064] For example, when the first rate mode switching instruction is resent for the first time, T / 2 is determined as the transmission delay value of the clock signal. If the eMMC fails to switch to the target working mode after the first rate mode switching instruction and the clock signal are resent, a second resend is performed. When the first rate mode switching instruction is resent for the second time, T / 4 and 3 / 4•T are determined as the transmission delay values ​​of the clock signal. If the eMMC fails to switch to the target working mode after the second rate mode switching instruction and the clock signal are resent, a third resend is performed. And so on, until the eMMC successfully switches to the target working mode, or the number of times the first rate mode switching instruction is resent reaches the number threshold.

[0065] In this embodiment, the transmission delay value of the clock signal is determined by binary search, which can improve the efficiency of finding an adapted transmission delay value.

[0066] Corresponding to the aforementioned eMMC rate mode switching method embodiment, the present disclosure also provides an embodiment of an eMMC rate mode switching device.

[0067] Figure 3 A schematic diagram of a module of a rate mode switching device of an eMMC provided by an exemplary embodiment of the present disclosure, the device comprising:

[0068] A sending module 31 is used to send a first rate mode switching instruction and a clock signal to the eMMC; wherein the first rate mode switching instruction instructs the eMMC to switch from a current working rate mode to a target working mode, the current working rate mode of the eMMC is HS mode or legacy mode, and the working rate of the target working mode is greater than the rate of the current working rate mode;

[0069] A determination module 32, configured to determine a transmission delay value of a clock signal in response to a failure of the eMMC to switch to the target operating mode;

[0070] The sending module 31 is further used to resend the first rate mode switching instruction and a clock signal matching the transmission delay value to the eMMC to synchronize the first rate mode switching instruction and the clock signal.

[0071] Optionally, the determining module is specifically used to:

[0072] One clock cycle of the clock signal is equally divided into N values, and i / N•T is determined as the transmission delay value of resending the clock signal to the eMMC for the i-th time.

[0073] Optionally, the determining module is specifically used to:

[0074] A binary search is performed on one clock cycle of the clock signal to determine a propagation delay value of the clock signal.

[0075] Optionally, after the sending module resends the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, it is further used to call the initialization module;

[0076] The initialization module is used to execute a subsequent eMMC initialization process in response to the eMMC successfully switching to the target working mode.

[0077] Optionally, after the sending module resends the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, it is further used to call the judgment module;

[0078] The judgment module is used to determine whether the number of times the first rate mode switching instruction is repeatedly sent reaches a number threshold in response to the eMMC failing to switch to the target working mode; and in response to the number reaching the number threshold, call the sending module to send a second rate mode switching instruction to the eMMC; the second rate mode switching instruction is used to instruct the eMMC to switch from the current working rate mode to the Legacy mode.

[0079] For the device embodiment, since it basically corresponds to the method embodiment, the relevant parts can refer to the partial description of the method embodiment. The device embodiment described above is only illustrative, wherein the units described as separate components may or may not be physically separated, and the components as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the disclosed solution.

[0080] Figure 4 This is a structural schematic diagram of an electronic device shown in an example embodiment of the present disclosure, the electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor, and when the processor executes the computer program, the rate mode switching method of the EMMC described in any of the above embodiments is implemented. Figure 4 The electronic device 40 shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0081] like Figure 4 As shown, the electronic device 40 may be in the form of a general-purpose computing device, for example, it may be a server device. The components of the electronic device 40 may include, but are not limited to: at least one processor 41, at least one memory 42, and a bus 43 connecting different system components (including the memory 42 and the processor 41).

[0082] The bus 43 includes a data bus, an address bus, and a control bus.

[0083] The memory 42 may include a volatile memory, such as a random access memory (RAM) 421 and / or a cache memory 422 , and may further include a read only memory (ROM) 423 .

[0084] The memory 42 may also include a program tool 425 (or utility) having a set (at least one) of program modules 424, such program modules 424 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0085] The processor 41 executes various functional applications and data processing by running the computer program stored in the memory 42, such as the rate mode switching method of the EMMC provided in any of the above embodiments.

[0086] The electronic device 40 can also communicate with one or more external devices 44 (e.g., keyboards, pointing devices, etc.). This communication can be performed through an input / output (I / O) interface 45. In addition, the electronic device 40 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN) and / or public network, such as the Internet) through a network adapter 46. As shown in the figure, the network adapter 46 communicates with other modules of the electronic device 40 through a bus 43. It should be understood that, although not shown in the figure, other hardware and / or software modules can be used in conjunction with the electronic device 40, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems, etc.

[0087] It should be noted that although several units / modules or sub-units / modules of the electronic device are mentioned in the above detailed description, this division is merely exemplary and not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided into multiple units / modules to be embodied.

[0088] The embodiment of the present disclosure further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the rate mode switching method of the EMMC provided in any of the above embodiments is implemented.

[0089] The readable storage medium may include but is not limited to: a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical storage device, a magnetic storage device or any suitable combination of the above.

[0090] The embodiment of the present disclosure further provides a computer program product, including a computer program, and when the computer program is executed by a processor, the rate mode switching method of the EMMC described in any one of the above items is implemented.

[0091] Among them, the program code for executing the computer program product of the present disclosure can be written in any combination of one or more programming languages, and the program code can be executed completely on the user device, partially on the user device, as an independent software package, partially on the user device and partially on a remote device, or completely on the remote device.

[0092] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A rate mode switching method for eMMC, characterized in that: The rate mode switching method comprises: Sending a first rate mode switching instruction and a clock signal to the eMMC; wherein the first rate mode switching instruction instructs the eMMC to switch from a current working rate mode to a target working mode, the current working rate mode of the eMMC is an HS mode or a legacy mode, and the working rate of the target working mode is greater than the rate of the current working rate mode; In response to the eMMC failing to switch to the target operating mode, determining a transmission delay value of a clock signal; The first rate mode switching instruction and a clock signal matching the transmission delay value are resent to the eMMC to synchronize the first rate mode switching instruction and the clock signal.

2. The rate mode switching method of eMMC according to claim 1, characterized in that, Determine the propagation delay value of the clock signal, including: One clock cycle T of the clock signal is equally divided into N values, and i / N•T is determined as the transmission delay value of resending the clock signal to the eMMC for the i-th time.

3. The rate mode switching method of eMMC according to claim 1, characterized in that, Determine the propagation delay value of the clock signal, including: A binary search is performed on one clock cycle of the clock signal to determine a propagation delay value of the clock signal.

4. The rate mode switching method of eMMC according to any one of claims 1-3, characterized in that: After the step of resending the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, the method further includes: In response to the eMMC successfully switching to the target operating mode, a subsequent eMMC initialization process is executed.

5. The rate mode switching method of eMMC according to claim 4, characterized in that: After the step of resending the first rate mode switching instruction and the clock signal matching the transmission delay value to the eMMC, the method further includes: In response to the eMMC failing to switch to the target operating mode, determining whether the number of times the first rate mode switching instruction is resent reaches a number threshold; In response to the number of times reaching the number threshold, a second rate mode switching instruction is sent to the eMMC to instruct the eMMC to switch from the current working rate mode to the Legacy mode.

6. A rate mode switching device for eMMC, characterized in that: The rate mode switching device comprises: A sending module, configured to send a first rate mode switching instruction and a clock signal to the eMMC; wherein the first rate mode switching instruction instructs the eMMC to switch from a current working rate mode to a target working mode, the current working rate mode of the eMMC is an HS mode or a legacy mode, and the working rate of the target working mode is greater than the rate of the current working rate mode; A determination module, configured to determine a transmission delay value of a clock signal in response to a failure of the eMMC to switch to the target operating mode; The sending module is further used to resend the first rate mode switching instruction and a clock signal matching the transmission delay value to the eMMC to synchronize the first rate mode switching instruction and the clock signal.

7. The rate mode switching device of eMMC according to claim 6, characterized in that: The determination module is specifically used for: One clock cycle T of the clock signal is equally divided into N values, and i / N•T is determined as the transmission delay value of resending the clock signal to the eMMC for the i-th time.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and used to run on the processor, characterized in that: When the processor executes the computer program, the rate mode switching method of the eMMC according to any one of claims 1 to 5 is implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the rate mode switching method of the eMMC according to any one of claims 1 to 5 is implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the rate mode switching method of the eMMC according to any one of claims 1 to 5 is implemented.

Images