Computer system for unmanned aerial vehicle

Abstract

The invention provides a computer system for an unmanned aerial vehicle, and relates to the technical field of unmanned aerial vehicles, the system comprises a plurality of SOC boards, a plurality of data interface control boards, a power board, a backboard and an external aviation plug interface board, each SOC board comprises a plurality of processors which are respectively used for running flight control domain software, electromechanical domain software and task domain software, the SOC boards are redundant to each other; each data interface control board is used for collecting data of a flight control sensor and performing data interaction with external equipment, and the data interface control boards are mutually redundant; the power panel is used for supplying power to the computer system; the backboard is used for distributing power output by the power board to other board cards. The SOC boards and the data interface control boards are electrically connected through the backboard. And the external aviation plug interface board is used for providing external input and output connection of other board cards. By implementing the technical scheme provided by the invention, the effects of reducing power consumption, weight and cost are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of unmanned aerial vehicles, and in particular to a computer system for unmanned aerial vehicles. Background Art

[0002] The traditional avionics system of UAVs is divided into flight control domain with flight control computer as the core, mission domain with mission management computer as the core, and electromechanical domain with electromechanical management computer as the core according to the functional domain. The above three types of computers manage the corresponding systems of UAVs respectively, and design independent computer hardware and software. The computing system of the above configuration has lagged far behind the development ideas of integrated design of modern avionics computing system, and has brought certain negative impacts on power consumption, weight and cost, which is not conducive to the capability expansion requirements of future UAV systems.

[0003] In the existing UAV computing system, each system builds its own computer hardware and develops system software. After measurement, it is found that the computing resource utilization rate of some systems is low and the computing resources are partially idle. At the same time, the computers of each system are designed and deployed separately, which leads to an increase in power consumption and weight, restricting the power consumption and weight indicators of the future improvement of the computing performance of UAVs. Summary of the invention

[0004] In order to solve the above problems, the present application provides a computer system for a drone.

[0005] In the first aspect, the present application provides a computer system for an unmanned aerial vehicle, comprising: multiple SOC boards, multiple data interface control boards, a power board, a backplane and an external flight plug-in interface board, wherein each of the multiple SOC boards contains multiple processors, which are respectively used to run flight control domain software, electromechanical domain software and mission domain software, and the multiple SOC boards serve as the main control system boards of the unmanned aerial vehicle, and each of the multiple SOC boards monitors each other and is redundant; each of the multiple data interface control boards serves as an IO control board and a sensor acquisition board, and each data interface control board is used to collect flight control sensor data and to interact with external devices for IO data, and each of the multiple data interface control boards is redundant; the power board is used to convert the input DC voltage The backplane is used to distribute the power output by the power board to other boards, wherein the other boards include each SOC board in a plurality of SOC boards and each data interface control board in a plurality of data interface control boards; the multiple SOC boards are electrically connected to each other through the backplane, the multiple data interface control boards are electrically connected to each other through the backplane, and each SOC board in the multiple SOC boards is electrically connected to each data interface control board in the multiple data interface control boards through the backplane; the external flight plug interface board is connected to the backplane through a high-density connector, the external flight plug interface board is used to provide external input and output connections for other boards, and the backplane is also used to distribute external IO signals of the external flight plug interface board to other boards.

[0006] By adopting the above technical solution, each of the multiple SOC boards contains multiple processors, which can run the flight control domain software, electromechanical domain software and mission domain software respectively, thereby improving the utilization rate of computing resources and avoiding the partial vacancy of computing resources. The mutual monitoring and mutual redundancy design between multiple SOC boards enhances the reliability and stability of the system, ensuring that it can still work normally when a single SOC board fails. Each data interface control board not only serves as an IO control board and a sensor acquisition board, but also has mutual redundancy with other data interface control boards, further improving the robustness of the system. The power board can convert the input DC voltage into a low-voltage DC voltage and distribute it to other boards through the backplane, ensuring the stable power supply of the entire system. Multiple SOC boards and data interface control boards are electrically connected through the backplane, which simplifies the wiring complexity and improves the data transmission efficiency. The external flight plug interface board is connected to the backplane through a high-density connector, providing a convenient way for other boards to input and output externally, facilitating system expansion and maintenance. In summary, the design of the computer system has greatly improved the overall performance of the drone and met the requirements for the expansion of the capabilities of the future drone system. The highly integrated design of the drone computing system has been achieved, significantly reducing power consumption, weight and cost. Through the redundant design between SOC boards, the system can continue to operate even if a component fails, improving the overall reliability and safety, and reducing the risk of system failure during the drone's mission.

[0007] Optionally, the above-mentioned computer system also includes an AI board, which serves as an artificial intelligence computing board of the computer system. Two AI acceleration modules are integrated on the AI ​​board, wherein the computing power of each AI acceleration module is 8TFLOPS / FP16 and 16TOPS / INT8, and each AI acceleration module is used to perform AI recognition on the collected image data in real time during flight. The AI ​​board is connected to each SOC board in multiple SOC boards through a network interface, and other boards also include the AI ​​board.

[0008] By adopting the above technical solutions, the two AI acceleration modules each have a powerful computing power of 8TFLOPS / FP16 and 16TOPS / INT8, which can efficiently process complex image data and improve the real-time recognition ability and decision-making efficiency of the drone during flight; the AI ​​board is connected to multiple SOC boards through a network interface, achieving efficient collaboration with other system components and ensuring the timeliness and accuracy of data processing; the powerful AI recognition capability can assist flight control, electromechanical management and task processing, reduce the need for human intervention, thereby reducing operational risks and enhancing the reliability and safety of the system. The addition of the AI ​​board has significantly improved the intelligence level of the drone.

[0009] Optionally, the target SOC board is any one of a plurality of SOC boards, and the computer system includes system software, and the system software includes flight control domain software, electromechanical domain software and mission domain software, wherein the flight control domain software, electromechanical domain software and mission domain software respectively run on corresponding CPU cores on the target SOC board, and are respectively used for flight control, electromechanical management and mission processing.

[0010] By adopting the above technical solutions, multiple SOC boards integrate the functions of the flight control domain, electromechanical domain and mission domain, reducing the demand for independent computer hardware, that is, reducing hardware redundancy, and reducing the complexity and weight of the entire system; software in different domains run on different CPU cores of the same SOC board, so that computing resources are used more efficiently and waste of computing resources is avoided; each SOC board monitors each other and is redundant, which improves the reliability and stability of the system. When a certain SOC board fails, it can quickly switch to other normal SOC boards to ensure the continuous operation of the UAV system and enhance the reliability of the entire computer system; centralized hardware design makes maintenance and upgrades simpler, and only a small number of core components need to be operated to complete the system update and optimization; the integration of multi-domain functions significantly reduces power consumption, while also reducing material and manufacturing costs, improving the economy of the system.

[0011] Optionally, the system software also includes AI software, which is used to perform AI calculations, wherein the flight control domain software is deployed on the first CPU core on the target SOC board, the electromechanical domain software is deployed on the second CPU core on the target SOC board, and the third CPU core on the target SOC board is used to run the Linux system, task domain software and AI software.

[0012] By adopting the above technical solution, the flight control domain software is deployed on the first CPU core of the target SOC board, and the electromechanical domain software is deployed on the second CPU core. This design ensures that key flight control and electromechanical management tasks have dedicated computing resources, improving the efficiency and stability of these task processing; the third CPU core runs the Linux system, task domain software and AI software, which not only supports complex task processing, but also can realize AI recognition of real-time image data, improving the intelligence level of the drone. The computer system effectively integrates the computing resources of multiple functional domains, improves the overall efficiency and resource utilization of the system, reduces hardware redundancy, reduces power consumption and weight, and meets the requirements for the expansion of future drone system capabilities.

[0013] Optionally, a channel fault logic management module is integrated in the target SOC board, and the channel fault logic management module is used to determine whether the current channel and other channels are valid according to a group of signals, wherein the current channel is used to represent the channel corresponding to the target SOC board, and other channels are used to represent the channels corresponding to other SOC boards except the target SOC board among the multiple SOC boards, the group of signals includes a CPU valid signal monitored by software, a power supply logic valid signal monitored by logic, a watchdog valid signal monitored by logic, an X channel judging the valid signal of the current channel, a Y channel judging the valid signal of the current channel, a power-on start pulse signal and a channel fault logic reset signal, and other channels include an X channel and a Y channel.

[0014] By adopting the above technical solution, a channel fault logic management module is integrated into the target SOC board, which can judge the validity of this channel (or self-channel) and other channels based on a set of signals. Specifically, the module can use multiple signal sources such as the CPU valid signal monitored by software, the power supply logic valid signal monitored by logic, and the watchdog valid signal monitored by logic to judge whether this channel and other channels are valid, so as to ensure the high reliability and stability of the system. Here, this channel refers to the channel corresponding to the target SOC board. In addition, by judging whether this channel is valid through the X channel and the Y channel, the coordination ability and fault tolerance between multiple channels are further improved, and the robustness of the entire computer system is enhanced. This design not only improves the overall reliability of the system, but also can perform self-diagnosis and recovery in time when a fault occurs, thereby ensuring the stable operation of the drone in a complex environment.

[0015] Optionally, the target SOC board is used to automatically switch to other channels when a fault is detected in the current channel, wherein the current channel is used to represent the channel corresponding to the target SOC board, other channels are used to represent channels corresponding to other SOC boards, and other SOC boards are used to represent SOC boards other than the target SOC board among multiple SOC boards.

[0016] By adopting the above technical solution, when the target SOC board detects a fault in the current channel, it can automatically switch to the channel corresponding to other SOC boards, thereby ensuring the continuous and stable operation of the system and improving the reliability of the entire UAV; this automatic switching mechanism avoids the risk of failure of the entire system due to a single SOC board failure, and the computer system can achieve high reliability and redundancy; it enhances the fault tolerance of the system and improves the adaptability and safety of the UAV in complex environments.

[0017] Optionally, data is transmitted between each of the multiple SOC boards via an LVDS interface or a PCIe interface; the target SOC board is used to identify its own ID through a target pin and determine its own priority based on its own ID, wherein the target SOC board is any one of the multiple SOC boards, and the target pin is a group of pins on the target SOC board.

[0018] By adopting the above technical solution, data transmission between multiple SOC boards can be realized through LVDS interface or PCIe interface. These two interfaces have the characteristics of high speed and low latency, which can ensure efficient and reliable data transmission between different SOC boards. At the same time, the target SOC board identifies its own ID and determines its own priority through the target pin. This mechanism can effectively manage the collaborative work of multiple SOC boards, avoid conflicts, and improve the stability and reliability of the system.

[0019] Optionally, a watchdog monitoring mechanism is provided in the target SOC board to monitor the state of the target SOC board. When it is detected that the target SOC board is in an abnormal state, the target SOC board is used to output fault information, hand over control authority, and isolate itself.

[0020] By adopting the above technical solution, the watchdog monitoring mechanism set in the target SOC board can monitor the status of the target SOC board in real time to ensure its normal operation. Once an abnormal state is detected, such as a freeze or abnormal behavior, the target SOC board will immediately output fault information to facilitate rapid location of the cause of the problem; at the same time, the target SOC board will hand over control authority in a timely manner and isolate itself to prevent the spread of faults from affecting the stability and security of the entire system. This design not only improves the reliability and fault tolerance of the system, but also shortens the fault recovery time and improves the overall performance and availability of the drone. The computer system can implement an efficient and reliable fault detection and isolation mechanism.

[0021] Optionally, the multiple SOC boards include a first SOC board, a second SOC board and a third SOC board, and the control rights between each SOC board in the multiple SOC boards are determined by a priority mechanism, wherein the priority of the first SOC board is greater than the priority of the second SOC board, and the priority of the second SOC board is greater than the priority of the third SOC board, and the multiple SOC boards constitute a triple-redundancy control system; the multiple data interface control boards include a first data interface control board and a second data interface control board, and the multiple data interface control boards constitute a dual-redundancy IO control system and a dual-redundancy sensor acquisition system.

[0022] By adopting the above technical solution, by setting up three SOC boards and allocating control rights in order of priority, it is ensured that when a certain SOC board fails, it can be quickly taken over by other SOC boards, thereby improving the reliability and stability of the system; this design not only improves flight safety, but also reduces the risk of overall system failure caused by single point failure. In addition, the two data interface control boards are mutually redundant, which enhances the reliability of data acquisition and external device communication; even if one of the data interface control boards fails, the other can still ensure normal operation, further improving the fault tolerance and anti-interference ability of the entire system.

[0023] Optionally, the above-mentioned computer system also includes a chassis, which is a 3U reinforced cooling VPX 8-slot chassis, the chassis is made of aluminum-magnesium alloy profiles, the chassis adopts integral panel splicing and the joints are designed with mortise and tenon structure, multiple SOC boards, multiple data interface control boards, power boards, backplanes and external aviation plug-in interface boards are all located in the chassis, and multiple SOC boards, multiple data interface control boards and power boards are designed with cooling plate structures.

[0024] By adopting the above technical solutions, the design of the 3U reinforced cooling VPX 8-slot chassis makes the entire system more compact, with good mechanical strength and heat dissipation performance. The use of aluminum-magnesium alloy profiles further reduces the weight of the system, and the overall panel splicing and the use of mortise and tenon structure design at the joints enhance the overall rigidity and sealing of the chassis, and improve the vibration resistance and protection level. Multiple SOC boards, data interface control boards, and power boards all adopt the cooling plate structure, which effectively solves the heat problem caused by high-density integration, ensures the stable operation of each component in a high temperature environment, and extends the service life of the system. This computer system not only realizes the high integration and redundant design of multi-domain functions, but also significantly reduces the weight, power consumption and cost of the UAV system, and improves the reliability and maintainability of the system.

[0025] In summary, one or more technical solutions provided in this application have at least the following technical effects or advantages: 1. A highly integrated design of the UAV computing system is realized, which significantly reduces power consumption, weight and cost; 2. Through the redundant design between SOC boards, even if a component fails, the system can still continue to operate, improving the overall reliability and safety, and reducing the risk of system failure during the UAV's mission execution; 3. Effectively integrate computing resources of multiple functional domains, improve the overall system performance and resource utilization, reduce hardware redundancy, power consumption and weight, and meet the requirements of future UAV system capability expansion; 4. When a fault is detected in this channel, it can automatically switch to the channel corresponding to other SOC boards to ensure the continuous and stable operation of the system. The computer system can achieve high reliability and redundancy; enhance the fault tolerance of the system and improve the adaptability and safety of the drone in complex environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a framework diagram of a computer system provided in an embodiment of the present application; Figure 2 is a framework diagram of another computer system provided in an embodiment of the present application; Figure 3 This is a diagram of the architecture of the integrated computer system of the drone provided in the embodiment of the present application; Figure 4 It is a block diagram of the composition of the UAV redundancy integrated computer system provided in the embodiment of the present application; Figure 5 It is a schematic diagram of the cross-linking relationship between boards of the drone integrated computer system provided in the embodiment of the present application; Figure 6 It is a schematic diagram of SOC board redundancy synchronization provided by an embodiment of the present application; Figure 7 It is a schematic diagram of a SOC board channel fault logic circuit provided in an embodiment of the present application; Figure 8 It is a schematic diagram of the MIO board redundancy control logic circuit provided in an embodiment of the present application; Fig. 9 This is an overall effect diagram of the chassis provided in the embodiment of the present application; Fig.10 It is a schematic diagram of the software deployment method in each domain provided in the embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to enable technicians in this field to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below in conjunction with the drawings in the embodiments of this specification. Obviously, the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0028] In the description of the embodiments of the present application, words such as "for example" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as "for example" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "for example" or "for example" is intended to present related concepts in a specific way.

[0029] In the description of the embodiments of the present application, the term "plurality" means two or more. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. The terms "include", "comprise", "have" and their variations all mean "including but not limited to", unless otherwise specifically emphasized.

[0030] The following is combined with Figure 1-Figure 10 The embodiments of the present application are described.

[0031] The present application provides a computer system for a drone, such as Figure 1 As shown, Figure 1 It is a framework diagram of a computer system provided by an embodiment of the present application, including: multiple SOC boards, multiple data interface control boards, a power board, a backplane and an external flight interface board, wherein: Each of the multiple SOC boards contains multiple processors, which are used to run the flight control domain software, the electromechanical domain software, and the mission domain software. The multiple SOC boards serve as the main control system boards of the UAV. The various SOC boards in the multiple SOC boards monitor each other and are redundant. Each of the multiple data interface control boards serves as an IO control board and a sensor acquisition board. Each data interface control board is used to collect flight control sensor data and to perform IO data interaction with external devices. Each of the multiple data interface control boards is redundant with each other. The power board is used to convert the input DC voltage into a low-voltage DC voltage to provide power to other boards in the computer system; The backplane is used to distribute the power output by the power board to other boards, wherein the other boards include each SOC board in the plurality of SOC boards and each data interface control board in the plurality of data interface control boards; The plurality of SOC boards are electrically connected to each other through a backplane, the plurality of data interface control boards are electrically connected to each other through the backplane, and each of the plurality of SOC boards is electrically connected to each of the plurality of data interface control boards through the backplane; The external aviation plug interface board is connected to the backplane through a high-density connector. The external aviation plug interface board is used to provide connections for external input and output of other boards. The backplane is also used to distribute external IO signals of the external aviation plug interface board to other boards.

[0032] In the above embodiment, each of the multiple SOC boards contains multiple processors, which can run flight control domain software, electromechanical domain software and mission domain software respectively, thereby improving the utilization rate of computing resources and avoiding the phenomenon of partial vacancy of computing resources. The mutual monitoring and mutual redundancy design between multiple SOC boards enhance the reliability and stability of the system, ensuring that it can still maintain normal operation when a single SOC board fails. Each data interface control board not only serves as an IO control board and a sensor acquisition board, but also can be redundant with other data interface control boards, further improving the robustness of the system. The power board can convert the input DC voltage into a low-voltage DC voltage and distribute it to other boards through the backplane, ensuring the stable power supply of the entire system. Multiple SOC boards and data interface control boards are electrically connected through the backplane, which simplifies the wiring complexity and improves the data transmission efficiency. The external aviation plug-in interface board is connected to the backplane through a high-density connector, providing a convenient way for other boards to input and output externally, facilitating system expansion and maintenance. In summary, the design of the computer system greatly improves the overall performance of the drone and meets the requirements for the expansion of the capabilities of the future drone system. The highly integrated design of the drone computing system has been achieved, significantly reducing power consumption, weight and cost. Through the redundant design between SOC boards, the system can continue to operate even if a component fails, improving the overall reliability and safety, and reducing the risk of system failure during the drone's mission.

[0033] The computer system of this embodiment is composed of multiple system-on-chip (SOC) boards, multiple data interface control boards, power boards, backboards, and external flight plug-in interface boards. Each component is electrically connected through the backboard to form a highly integrated computing platform. Each SOC board contains multiple processors, which are used to run the software of the flight control domain, electromechanical domain, and mission domain, respectively. This design integrates the functions of the three traditional independent computers (flight control computer, mission management computer, and electromechanical management computer) into multiple SOC boards and into a computer system, realizing unified management of hardware and software and efficient utilization of resources; the data interface control board is used as an IO control board and sensor acquisition board, responsible for collecting flight control sensor data and interacting with external devices for IO data. These boards are also designed to be redundant, which enhances the reliability and stability of the system; the power board is responsible for converting the input DC voltage into a low-voltage DC voltage to provide power for other boards; the backboard is the center of the system, responsible for distributing power, connecting various boards, and realizing data communication between boards; the external flight plug-in interface board is connected to the backboard through a high-density connector to provide the system with external input and output connections. In the related art, each functional domain uses independent computer hardware and software, resulting in low computing resource utilization and partial vacancy. In the related art, the computers of each functional domain are designed and deployed separately, which increases power consumption and weight. The computer system of this embodiment uses an integrated design to run the software of multiple functional domains on a unified SOC board, thereby improving the utilization of computing resources. Through modular design, redundant hardware is reduced, power consumption and weight are reduced, and the flight performance and endurance of the drone are improved. In addition, through redundant design, such as mutual monitoring and mutual redundancy (or mutual backup) between SOC boards, and mutual monitoring and mutual redundancy between data interface control boards, the reliability and stability of the system are improved.

[0034] In an optional embodiment, if Figure 2 As shown, the above-mentioned computer system also includes an AI board. The AI ​​board serves as an artificial intelligence computing board of the computer system. Two AI acceleration modules are integrated on the AI ​​board, wherein the computing power of each AI acceleration module is 8TFLOPS / FP16 and 16TOPS / INT8. Each AI acceleration module is used to perform AI recognition on the collected image data in real time during flight. The AI ​​board is connected to each of the multiple SOC boards through a network interface, and other boards also include the AI ​​board.

[0035] In the above embodiment, the two AI acceleration modules each have a powerful computing power of 8TFLOPS / FP16 and 16TOPS / INT8, which can efficiently process complex image data and improve the real-time recognition capability and decision-making efficiency of the drone during flight; the AI ​​board is connected to multiple SOC boards through a network interface, achieving efficient collaboration with other system components and ensuring the timeliness and accuracy of data processing; the powerful AI recognition capability can assist flight control, electromechanical management and task processing, reduce the need for human intervention, thereby reducing operational risks and enhancing the reliability and safety of the system. The addition of the AI ​​board significantly improves the intelligence level of the drone.

[0036] As the artificial intelligence computing board of the system, the AI ​​board integrates two AI acceleration modules, each with a computing power of 8TFLOPS / FP16 and 16TOPS / INT8, which means they can efficiently handle complex AI computing tasks. The AI ​​board is connected to multiple SOC boards through a network interface, so that the AI ​​processing capability can be closely integrated with the main control system of the drone. During the flight, the AI ​​board can perform AI recognition on the collected image data in real time, thereby achieving rapid perception and decision support of the environment. When the drone performs tasks, real-time performance is crucial. By integrating high-computing AI acceleration modules, the drone's ability to perform AI recognition in flight is significantly improved. The addition of the AI ​​board enables the drone to process and analyze image data in real time during flight, thereby improving the response speed and efficiency of the task. The real-time image recognition capability of the AI ​​board enables the drone to quickly identify targets and obstacles, thereby optimizing the flight path and task execution strategy, and improving the execution efficiency of the task; by processing image data in real time during flight, the drone can better understand the surrounding environment and achieve a higher level of autonomous decision-making and task planning; the addition of the AI ​​board reduces the reliance on human intervention, and the drone can independently complete tasks in more complex environments, reducing the difficulty of operation and labor costs.

[0037] The above "TFLOPS" stands for TeraFLOPS (Trillion Floating-point Operations Per Second), and "FP16" refers to the 16-bit floating-point format, so "8TFLOPS / FP16" means that the hardware device can perform 8 trillion floating-point operations per second when using 16-bit floating-point numbers for calculations. The above "TOPS" stands for Tera Operations Per Second, and "INT8" refers to the 8-bit integer format (Integer 8-bit), so "16TOPS / INT8" means that the hardware device can perform 16 trillion operations per second when using 8-bit integers for calculations.

[0038] In an optional embodiment, the target SOC board is any one of a plurality of SOC boards, and the computer system includes system software, which includes flight control domain software, electromechanical domain software and mission domain software, wherein the flight control domain software, electromechanical domain software and mission domain software respectively run on corresponding CPU cores on the target SOC board, and are respectively used for flight control, electromechanical management and mission processing.

[0039] In the above embodiment, multiple SOC boards integrate the functions of the flight control domain, the electromechanical domain, and the mission domain, reducing the demand for independent computer hardware, that is, reducing hardware redundancy, and reducing the complexity and weight of the entire system; software in different domains run on different CPU cores of the same SOC board, so that computing resources are used more efficiently and waste of computing resources is avoided; each SOC board monitors each other and is redundant, which improves the reliability and stability of the system. When a certain SOC board fails, it can quickly switch to other normal SOC boards to ensure the continuous operation of the UAV system and enhance the reliability of the entire computer system; centralized hardware design makes maintenance and upgrading easier, and only a small number of core components need to be operated to complete the system update and optimization; the integration of multi-domain functions significantly reduces power consumption, while also reducing material and manufacturing costs, and improving the economy of the system.

[0040] On a target SOC board, the flight control domain software, the electromechanical domain software and the task domain software run on different CPU cores respectively, which means that each software domain has dedicated processor resources to perform its functions, avoiding interference between multiple tasks; by assigning tasks of different domains to different CPU cores, more efficient parallel processing can be achieved, improving the response speed and efficiency of the entire system; all these software domains run on the same SOC board, rather than being scattered on multiple independent computer hardware, which simplifies the system architecture, enhances the collaboration between the domains, and improves resource utilization. This embodiment integrates the flight control domain software, the electromechanical domain software and the task domain software on different CPU cores of the target SOC board, thereby realizing centralized management and efficient utilization of resources and avoiding the problem of uneven resource allocation; in addition, the target SOC board is any one of the multiple SOC boards, that is, each of the multiple SOC boards adopts the same integrated design as the target SOC board, which not only improves resource utilization, but also improves the overall safety and reliability of the computer system through this redundant design.

[0041] In an optional embodiment, the system software also includes AI software, which is used to perform AI calculations, wherein the flight control domain software is deployed on the first CPU core on the target SOC board, the electromechanical domain software is deployed on the second CPU core on the target SOC board, and the third CPU core on the target SOC board is used to run the Linux system, task domain software and AI software.

[0042] In the above embodiment, the flight control domain software is deployed on the first CPU core of the target SOC board, and the electromechanical domain software is deployed on the second CPU core. This design ensures that key flight control and electromechanical management tasks have dedicated computing resources, improving the efficiency and stability of these task processing; the third CPU core runs the Linux system, task domain software and AI software, which not only supports complex task processing, but also can realize AI recognition of real-time image data, improving the intelligence level of the drone. In actual applications, the first CPU core and the second CPU core are small cores, and the third CPU core is a large core. The computer system effectively integrates the computing resources of multiple functional domains, improves the overall efficiency and resource utilization of the system, reduces hardware redundancy, reduces power consumption and weight, and meets the requirements for future drone system capability expansion.

[0043] In this computer system, the flight control domain software, electromechanical domain software, mission domain software and AI software are deployed on different CPU cores on the target SOC board. Specifically, the flight control domain software is deployed on the first CPU core, the electromechanical domain software is deployed on the second CPU core, and the third CPU core is used to run the Linux system, the mission domain software and the AI ​​software. By deploying the AI ​​software on the dedicated CPU core (the third CPU core) on the target SOC board, the independent and optimized utilization of AI computing resources is achieved, and the real-time performance and performance of the AI ​​algorithm are improved; by reasonably allocating CPU core resources, the parallel processing of flight control, electromechanical management, task processing and AI computing functions is achieved, and the multi-tasking processing capability of the system is improved; the dedicated CPU core and optimized resource allocation ensure the real-time and reliability of AI computing and other key tasks, and improve the overall performance and safety of the system.

[0044] In an optional embodiment, a channel fault logic management module is integrated in the target SOC board, and the channel fault logic management module is used to determine whether the current channel and other channels are valid according to a group of signals, wherein the current channel is used to represent the channel corresponding to the target SOC board, and other channels are used to represent the channels corresponding to other SOC boards except the target SOC board among the multiple SOC boards, the group of signals includes a CPU valid signal monitored by software, a power supply logic valid signal monitored by logic, a watchdog valid signal monitored by logic, an X channel judging the valid signal of the current channel, a Y channel judging the valid signal of the current channel, a power-on start pulse signal and a channel fault logic reset signal, and other channels include an X channel and a Y channel.

[0045] In the above embodiment, a channel fault logic management module is integrated into the target SOC board, which can judge the validity of the current channel (or self-channel) and other channels based on a set of signals. Specifically, the module can use multiple signal sources such as the CPU valid signal monitored by software, the power supply logic valid signal monitored by logic, and the watchdog valid signal monitored by logic to judge whether the current channel and other channels are valid, so as to ensure the high reliability and stability of the system. Here, the current channel refers to the channel corresponding to the target SOC board. In addition, by judging whether the current channel is valid through the X channel and the Y channel, the coordination ability and fault tolerance between multiple channels are further improved, and the robustness of the entire computer system is enhanced. This design not only improves the overall reliability of the system, but also can perform self-diagnosis and recovery in time when a fault occurs, thereby ensuring the stable operation of the drone in a complex environment.

[0046] The computer system integrates a channel fault logic management module in its target SOC board. The core function of this module is to monitor and judge the validity of this channel (i.e., the channel corresponding to the target SOC board) and other channels (channels corresponding to other SOC boards in the system, such as X channel and Y channel). It makes these judgments based on a set of signals, which include: a CPU valid signal monitored by software, indicating whether the CPU is operating normally; a power logic valid signal monitored by logic, indicating whether the power supply is normal; a watchdog valid signal monitored by logic, the watchdog timer is used to detect software faults, and this signal indicates whether the watchdog is operating normally; an X channel judges the validity signal of this channel, the judgment result of the X channel on the validity of this channel (i.e., the channel corresponding to the target SOC board); the judgment result of the Y channel on the validity of this channel; a power-on start pulse signal, a start signal generated when the system is powered on, used to initialize or reset the system; and a channel fault logic reset signal, used to reset the channel fault logic management module when a fault is detected.

[0047] The channel fault logic management module can monitor the channel status in real time, detect faults quickly and accurately, and significantly improve the reliability and availability of the system through timely fault detection and isolation, as well as reliable communication between channels, ensuring the stable operation of the system in various environments; each SOC board not only monitors its own health status, but also receives status information from other SOC boards to achieve mutual inspection, thus improving the overall reliability of the system. In actual applications, once a fault is detected, the system can quickly switch to a redundant path or start a backup plan, reducing downtime and the risk of data loss.

[0048] In an optional embodiment, the channel fault logic management module includes: a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a first OR gate, a second OR gate and a latch, wherein the three input ends of the first AND gate are respectively connected to the CPU valid signal monitored by software, the power supply logic valid signal monitored by logic and the watchdog valid signal monitored by logic, the three input ends of the first OR gate are respectively connected to the X channel to judge the valid signal of the current channel, the Y channel to judge the valid signal of the current channel and the power-on start pulse signal, the output end of the first AND gate and the output end of the first OR gate are respectively electrically connected to the two input ends of the second AND gate, and the output end of the second AND gate is respectively electrically connected to the two input ends of the second AND gate. The second AND gate is electrically connected to the input end of the latch, the two input ends of the second OR gate are respectively connected to the power-on start pulse signal and the channel fault logic reset signal, the output end of the second OR gate is electrically connected to the enable end of the latch, and the output end of the latch is used to output a signal for judging whether the channel is valid; the two input ends of the third AND gate are respectively connected to the output end of the latch and the software judgment X channel valid signal, the two input ends of the fourth AND gate are respectively connected to the output end of the latch and the software judgment Y channel valid signal, the output end of the third AND gate is used to output a signal for judging whether the X channel is valid, and the output end of the fourth AND gate is used to output a signal for judging whether the Y channel is valid.

[0049] In the above embodiment, the channel fault logic management module can effectively determine the validity of the current channel and other channels. Specifically: the combination of the first AND gate and the first OR gate ensures that the current channel can only be determined to be valid when the CPU valid signal, the power logic valid signal and the watchdog valid signal are all high, and at least one of the X channel judging the valid signal of the current channel, the Y channel judging the valid signal of the current channel and the power-on start pulse signal is high; the second AND gate integrates these conditions and outputs the final judgment result through the latch, so that the channel state can be correctly initialized when the system starts and remain stable during subsequent operation; the second OR gate ensures that when the power-on start pulse signal or the channel fault logic reset signal is high, the latch can be cleared or reset to avoid misjudgment. The third AND gate and the fourth AND gate are used to further confirm the validity of the X channel and the Y channel according to the output of the latch and the result of the software judgment respectively. Through accurate fault detection and fast fault response, the system can take measures quickly when a fault occurs to avoid fault propagation, thereby improving the overall reliability; accurate fault location and simple fault handling logic reduce the maintenance difficulty and cost of the system. Through the design of logic gate combinations and latches, the system can accurately determine the effectiveness of the channel under various conditions, thereby improving overall reliability. It can not only detect its own faults, but also discover other potential problems through information exchange with other channels, which helps to quickly locate the source of the fault and take measures. Even if a partial hardware or software failure occurs, the system can still keep running through redundant paths, reducing the possibility of unexpected downtime.

[0050] In an optional embodiment, the target SOC board is used to automatically switch to other channels when a fault is detected in the current channel, wherein the current channel is used to represent the channel corresponding to the target SOC board, other channels are used to represent channels corresponding to other SOC boards, and other SOC boards are used to represent SOC boards other than the target SOC board among multiple SOC boards.

[0051] In the above embodiment, when the target SOC board detects a fault in the current channel, it can automatically switch to the channel corresponding to other SOC boards, thereby ensuring the continuous and stable operation of the system and improving the reliability of the entire UAV; this automatic switching mechanism avoids the risk of failure of the entire system due to a single SOC board failure, and the computer system can achieve high reliability and redundancy; it enhances the fault tolerance of the system and improves the adaptability and safety of the UAV in complex environments.

[0052] The target SOC board of this embodiment has a built-in fault detection mechanism, which can monitor the working status of this channel in real time. Once a fault is detected in this channel, the target SOC board will decide which other channel to switch to according to the preset switching logic or strategy. The target SOC board performs a channel switching operation, disconnects the connection with this channel, and establishes a connection with other channels to ensure that the system can continue to work normally. That is, when the target SOC board detects that its corresponding channel (i.e., this channel) has a fault, it can automatically switch to the channel corresponding to other SOC boards (i.e., other channels) to continue working. The "channel" here can be a data transmission channel, a communication channel, or other functional channels, depending on the application scenario of the system, that is, the computer system has an automatic channel switching function. In actual applications, when the target SOC board detects that there is a fault in this channel, it can be automatically isolated, that is, the fault is prevented from spreading by isolating the fault channel. Through this embodiment, through the automatic channel switching function, even if a channel of a certain SOC board fails, the system can quickly switch to other channels to continue working, thereby greatly improving the reliability of the system; in a system composed of multiple SOC boards, the automatic channel switching function can ensure that even if a channel of a certain SOC board fails, the resources of other SOC boards can be fully utilized, thereby improving the resource utilization of the entire system; the automatic channel switching function reduces the need for manual intervention and reduces the maintenance cost of the system.

[0053] In an optional embodiment, data is transmitted between each of the multiple SOC boards via an LVDS interface or a PCIe interface; the target SOC board is used to identify its own ID through a target pin and determine its own priority based on its own ID, wherein the target SOC board is any one of the multiple SOC boards, and the target pin is a group of pins on the target SOC board.

[0054] In the above embodiment, data transmission between multiple SOC boards can be realized through LVDS interface or PCIe interface, which has the characteristics of high speed and low latency, and can ensure efficient and reliable data transmission between different SOC boards. At the same time, the target SOC board identifies its own ID and determines its own priority through the target pin. This mechanism can effectively manage the collaborative work of multiple SOC boards, avoid conflicts, and improve the stability and reliability of the system.

[0055] Data is transmitted between multiple SOC boards through LVDS interface or PCIe interface, both of which have the characteristics of high speed and low power consumption. LVDS (low voltage differential signal) interface transmits data through low voltage differential signal, which can realize high-speed data transmission under low power consumption and low noise. PCIe (Peripheral Component Interconnect Express) interface uses serial bus to transmit data, which has the advantages of high bandwidth and low latency. PCIe is also a computer bus standard; in addition, the target SOC board identifies its own ID through the target pin, and judges its own priority according to the ID. This design enables the system to achieve efficient data transmission and reasonable task allocation between multiple SOC boards. This embodiment improves the data transmission speed between multiple SOC boards and reduces noise interference by adopting LVDS interface or PCIe interface, thereby improving the overall performance of the system; the unique ID identification of SOC board is realized through target pin, which simplifies the configuration and management process of the system, so that the system can accurately distinguish and manage different SOC boards; by judging the priority according to the ID of SOC board, the orderly management of resource request and task execution is realized, avoiding the problems of resource conflict and low efficiency of task execution.

[0056] In an optional embodiment, a watchdog monitoring mechanism is provided in the target SOC board to monitor the status of the target SOC board. When it is detected that the target SOC board is in an abnormal state, the target SOC board is used to output fault information, hand over control authority, and isolate itself.

[0057] In the above embodiment, the watchdog monitoring mechanism set in the target SOC board can monitor the status of the target SOC board in real time to ensure its normal operation. Once an abnormal state is detected, such as a freeze or abnormal behavior, the target SOC board will immediately output fault information to facilitate rapid location of the cause of the problem; at the same time, the target SOC board will hand over control authority in a timely manner and isolate itself to prevent the spread of faults from affecting the stability and security of the entire system. This design not only improves the reliability and fault tolerance of the system, but also shortens the fault recovery time and improves the overall performance and availability of the drone. The computer system can implement an efficient and reliable fault detection and isolation mechanism.

[0058] Through the watchdog monitoring mechanism, the system can respond quickly when a SOC board fails, reducing the risk of fault propagation and shortening system downtime; the fault information output by the watchdog mechanism helps administrators quickly locate the problem, thereby accelerating the fault repair process. By handing over control authority in a timely manner and isolating the faulty SOC board, the watchdog mechanism helps maintain the overall stability and reliability of the system and reduce system-level problems caused by a single SOC board failure; the implementation of the watchdog mechanism enables system administrators to more easily monitor and maintain the status of the SOC board, thereby reducing the complexity and cost of system maintenance.

[0059] In an optional embodiment, the multiple SOC boards include a first SOC board, a second SOC board and a third SOC board, and the control rights between each SOC board in the multiple SOC boards are determined by a priority mechanism, wherein the priority of the first SOC board is greater than the priority of the second SOC board, and the priority of the second SOC board is greater than the priority of the third SOC board, and the multiple SOC boards constitute a triple-redundancy control system; the multiple data interface control boards include a first data interface control board and a second data interface control board, and the multiple data interface control boards constitute a dual-redundancy IO control system and a dual-redundancy sensor acquisition system.

[0060] In the above embodiment, by setting up three SOC boards and allocating control rights in order of priority, it is ensured that when a certain SOC board fails, it can be quickly taken over by other SOC boards, thereby improving the reliability and stability of the system; this design not only improves flight safety, but also reduces the risk of overall system failure caused by single point failure. In addition, the two data interface control boards are mutually redundant, which enhances the reliability of data acquisition and external device communication; even if one of the data interface control boards fails, the other can still ensure normal operation, further improving the fault tolerance and anti-interference ability of the entire system.

[0061] The system contains three SOC boards, namely the first SOC board, the second SOC board and the third SOC board, and the control rights are determined by the priority mechanism. Specifically, the first SOC board has the highest priority, followed by the second SOC board, and the third SOC board has the lowest priority. This priority mechanism ensures that under normal circumstances, the SOC board with the highest priority (the first SOC board) is responsible for the main control tasks, while the other SOC boards serve as backups. When the main control SOC board has a problem, the SOC board with the second highest priority (the second SOC board) will take over the control, and so on. In addition, the data interface control boards in the system include the first data interface control board and the second data interface control board, which constitute a dual-redundancy IO control system and a dual-redundancy sensor acquisition system. The dual-redundancy design means that each function has two independent implementation paths. When one path has a problem, the other path can continue to work, thereby improving the reliability and fault tolerance of the system. Through the triple-redundant control system and dual-redundant IO / sensor acquisition system, the system can maintain stable operation when encountering local faults, improving overall reliability; once a fault is detected, the system can quickly switch to a redundant path or start a backup plan to reduce downtime and the risk of data loss, which is especially important for drone applications with high real-time requirements.

[0062] In an optional embodiment, the computer system further comprises a chassis, which is a 3U reinforced, cooled VPX 8-slot chassis, which is made of aluminum-magnesium alloy profiles, and which is spliced ​​with integral panels and has a mortise and tenon structure design at the joints. Multiple SOC boards, multiple data interface control boards, a power board, a backplane and external aviation plug-in interface boards are all located in the chassis, and the multiple SOC boards, multiple data interface control boards and power boards are all cooled plate structures.

[0063] In the above embodiment, the design of the 3U reinforced cooling VPX 8-slot chassis makes the entire system more compact, with good mechanical strength and heat dissipation performance. The use of aluminum-magnesium alloy profiles further reduces the weight of the system, and the overall panel splicing and the use of mortise and tenon structure design at the joints enhance the overall rigidity and sealing of the chassis, and improve the vibration resistance and protection level. Multiple SOC boards, data interface control boards, and power boards all adopt a cooling plate structure, which effectively solves the heat problem caused by high-density integration, ensures the stable operation of each component in a high temperature environment, and extends the service life of the system. This computer system not only realizes the high integration and redundant design of multi-domain functions, but also significantly reduces the weight, power consumption and cost of the UAV system, and improves the reliability and maintainability of the system.

[0064] The chassis is designed as a 3U reinforced cooling VPX 8-slot chassis, which is made of aluminum-magnesium alloy profiles. The overall panel of the chassis is constructed by splicing, and the mortise and tenon structure design is used at the splicing to enhance stability and heat dissipation performance. In addition, multiple SOC boards, data interface control boards, power boards, backplanes, and external flight interface boards are installed inside the chassis, and these boards all use a cooling plate structure to optimize the heat dissipation effect. This is a standardized chassis design that provides 8 slots for installing boards and supports the VPX (VITA46) bus standard to ensure high-speed data transmission and signal integrity. The reinforcement design enables the chassis to withstand use in harsh environmental conditions, such as vibration and shock. The cooling design effectively removes internal heat through the heat conduction path between the chassis and the board. Aluminum-magnesium alloy has high strength, low density and good thermal conductivity, making it an ideal material for manufacturing high-performance, lightweight chassis. Overall panel splicing helps to simplify the manufacturing process of the chassis while maintaining structural integrity. The mortise and tenon structure is a traditional connection method that does not require additional fasteners. It provides a stable connection through the concave and convex fit between the panels, and also helps to dissipate heat. The cold plate is a board structure with integrated heat dissipation function. By integrating heat dissipation components such as heat sinks or heat pipes with the board, efficient heat conduction and heat dissipation are achieved.

[0065] It should be noted that the above-described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application will be described in detail below in conjunction with specific embodiments.

[0066] The embodiment of the present application provides a redundant integrated computer system for drones. The redundant integrated computer system for drones considers building a high-end intelligent computing platform based on a high-performance SOC (System on Chip) and running multi-function domain applications in parallel. The use of integrated computing equipment can simplify the complexity and quantity of drone electronic and electrical equipment.

[0067] Secondly, the system has both redundant sensor data acquisition functions and triple redundant SOC control systems, and also integrates an AI acceleration module. Its advantages are that the three SOC boards monitor each other and are redundant, and the two MIO boards (corresponding to the aforementioned multiple data interface control boards) are integrated with various flight control sensors. The two MIO boards are redundant and can obtain the optimal sensor values ​​through the redundancy management algorithm, greatly improving the reliability of flight control.

[0068] Finally, the present invention also integrates two AI acceleration modules with a computing power of up to 4 / 8 / 11TFLOPS and 8 / 16 / 22TOPS. The aircraft can perform real-time AI recognition on the collected image data during flight, broadening the application scenarios of drone computer systems.

[0069] The embodiments of the present application are described in detail below.

[0070] A redundant integrated computer system for unmanned aerial vehicles, consisting of 3 SOC processor boards (corresponding to the aforementioned multiple SOC boards), 2 MIO boards (corresponding to the aforementioned data interface control boards), 1 AI board, 1 power board, 1 external flight plug-in interface board, 1 VPX backplane (corresponding to the aforementioned backplane), 1 reinforced cooling chassis and corresponding software architecture. The redundant integrated computer system for unmanned aerial vehicles is implemented using a 3+2 architecture, and the whole machine mainly implements the following functions: (1) Aircraft management (including flight control system and electromechanical system) and mission system; (2) Triple-redundant SOC control; (3) Dual-redundancy MIO control; (4) Dual-redundant flight control sensor data acquisition and analysis; (5) AI high-performance computing; (6) High-speed CCDL (high-speed serial communication) communication function between CPUs; (7) Channel fault logic management function; (8) BIT function and wraparound detection function; (9) Timing and synchronization functions; (10) Redundancy fault isolation function; (11) Data storage; (12) RS-422 bus communication management function; (13) RS-232 bus communication management function; (14) CAN bus communication management function; (15) Discrete input and output functions; (16) Communication serial port function (RS232 / RS422 / RS485); (17)PWM output function; (18) Redundant integrated computer system software framework for unmanned aerial vehicles. DETAILED DESCRIPTION

[0071] (1) Board composition This UAV redundant integrated computer system, Figure 3This is the architecture diagram of the integrated computer system of the UAV provided in the embodiment of the present application. There are 7 3U VPX daughter boards, 1 VPX backplane, and 1 external flight plug interface board inside; the 7 3U VPX daughter boards include 3 SOC processor boards (SOC board-A, SOC board-B, SOC board-C), 2 MIO boards (MIO board-A, MIO board-B), 1 AI board, and 1 power board. The VPX daughter board and the VPX backplane are connected via 3 VPX connectors, and the VPX backplane and the external flight plug interface board are connected via 2 inter-board high-speed connectors. The block diagram of the board composition of the integrated computer system of the UAV is shown in the figure. Figure 4 shown.

[0072] (2) Board Function Introduction 1) SOC board: 3 in total, as the main control system board of the redundant integrated computer system of the UAV, it integrates the processor, memory, storage, serial port (RS232 / RS422 / RS485), network port, discrete input and output interface and other functions, and is the hardware support for the flight control algorithm, redundancy control algorithm, channel fault logic code, etc. 3 SOC boards constitute a triple redundancy system control system; 2) MIO board: 2 in total, used as the I / O control board and flight control sensor acquisition board of the drone integrated computer, using FPGA / MCU to implement corresponding functions, flight control sensor data acquisition, serial port (RS232, RS422, RS485), CANFD bus interface, PWM output interface, discrete input and output interface and other functions, which are the hardware support for I / O data interaction with external devices. 2 MIO boards constitute a dual-redundancy I / O control system and a dual-redundancy sensor acquisition system; 3) AI board: As the AI ​​computing board of the drone integrated computer, it has 2 AI acceleration modules on board, and the computing power of a single AI acceleration module is as high as: 8TFLOPS / FP16, 16TOPS / INT8. The AI ​​board communicates with the SOC board and external devices through the Ethernet interface; 4) Power board: 3U conduction-cooled VPX power supply, as the DC power control board of the drone integrated computer, converts the input DC voltage 28V into two DC power outputs of +12V / 20A and +3.3V_AUX / 2A, providing stable and reliable power supply for other components of the system; 5) VPX backplane: distributes the power output of the power board to different VPX daughter boards; distributes the external input / output signals of the external flight interface board to different VPX daughter boards; provides information channels for communication between daughter boards inside the computer; the backplane has fool-proof design for different types of daughter board slots; 6) External flight interface board: connected to the VPX backplane through two high-speed inter-board connectors, providing connection for external I / O of each board of the drone integrated computer.

[0073] (3) Cross-linking relationship between plates The three SOC boards and the two MIO boards in the redundant integrated computer system of the drone are mutually redundant. The SOC board and the MIO board are connected through the backplane. The connection relationship between the SOC board and the MIO board is as follows: Figure 5 As shown in the figure, the priority is SOC board-A>SOC board-B>SOC board-C. The SOC board and the MIO board use LVDS / PCIe to transmit data such as large data volume / high-speed signals, and use I / O signals to transmit data such as slot ID identification, fault feedback, and enable switch.

[0074] (4) SOC board redundancy synchronization and fault logic description The synchronization within this system is divided into three SOC board synchronization and SOC and MIO board synchronization. The core is the synchronization between the three SOC boards. The MIO board can use the synchronization signal after the SOC board synchronization is completed to achieve protocol frame synchronization. The SOC board redundancy synchronization is as follows Figure 6 shown.

[0075] After the SOC board is powered on, it first identifies its own ID through the pins. Then it determines its own priority based on the ID number, SOC_A>SOC_B>SOC_C. All major external interfaces in the SOC board pass through the FPGA, so the normal operation of the FPGA is a necessary condition. Secondly, the SOC board can obtain the connection status of each LVDS interface. The LVDS interface is divided into master and slave ends. The master endpoint outputs the clock and the slave endpoint receives the clock signal; the establishment of the LVDS link is initiated by the slave endpoint.

[0076] exist Figure 6 In each SOC board, LVDS1_0 and LVDS1_1 are LVDS signal groups, which are actually composed of three signals: clock, data receiving, and data sending. They are used for data communication between various boards. LVDS_IO1 and LVDS_IO2 are two control signals that assist LVDS link communication. When an LVDS communication error occurs and cannot be recovered, this signal is used to notify the other SOC board to reset the interface. For example, when SOC_A determines that an error has occurred in LVDS1_0, LVDS_IO1 is used to output a low level to notify SOC_B, and the LVDS communication modules of SOC_A and SOC_B are reset; when SOC_A determines that an error has occurred in LVDS1_1, it stops communicating and waits for SOC_C to control SOC_A's LVDS_IO2 to a low level to reset the LVDS1_1 interface processing module.

[0077] According to the priority of the SOC board, the conditions for judging the SOC control right are shown in Table 1. It is divided into the situation that both MIO_A and MIO_B are online and only one of MIO_A and MIO_B is online (whether the MIO board is online is judged by whether the corresponding LVDS is linked up).

[0078] Table 1 The status between the FPGA in the SOC board and the SOC is monitored by the watchdog. If the watchdog barks, it means that the current SOC is in an abnormal state. The FPGA of the current SOC board directly outputs fault information and hands over the control authority to isolate itself.

[0079] The channel fault logic circuit of the SOC board is as follows Figure 7 shown.

[0080] The definitions of the channel fault logic signals are as follows: 1)CPUV: The CPU monitored by the software is valid; 2) PSV: The power supply logic of the logic monitoring is valid; 3) WDV: The watchdog of logic monitoring is effective; 4)DPV_Tx / DPV_Ty: This channel determines whether the X / Y channel is valid; 5) DPV_Fx / DPV_Fy: X / Y channel determines whether this channel is valid; 6)CHV: This channel is valid; 7) SW_DPV_Tx / Ty: software determines whether the X / Y channel is valid; 8) CFL_FR: channel fault logic reset; 9)PORP: Power-on start pulse; 10) CHV_Tx and CHV_Ty are valid signals of this channel sent to X and Y channels.

[0081] (5) MIO board redundancy control logic Two MIO boards serve as the I / O control board and flight control sensor acquisition board of this system. The two MIO boards constitute a dual-redundancy I / O control system and a dual-redundancy sensor acquisition system.

[0082] The redundancy control logic circuit of the MIO board of the UAV integrated computer system is as follows Figure 8 shown.

[0083] Figure 8 The signals are defined as follows: CHV_A is SOC board-A (or SOC_A, or SOCA for short) to judge whether the MIO board is working normally. 1 means SOC_A thinks that the MIO board is working abnormally; CHV_B and CHV_C are similar; SW_A_MIO1 indicates that the MIO1 board (equivalent to the aforementioned MIO_A) monitors whether its own working status is normal, 1 indicates abnormal working, SW_A_MIO2 indicates that the MIO2 board (equivalent to the aforementioned MIO_B) monitors whether its own working status is normal, 1 indicates abnormal working; SW_B_MIO1, SW_B_MIO2, SW_C_MIO1 and SW_C_MIO2 are similar; CUT_A_MIO1 means that SOC_A needs to cut off MIO1, that is, SOC_A considers MIO1 to be faulty and needs to be isolated and stopped; When three SOCs (ie, SOC_A, SOC_B, and SOC_C) all believe that the MIO (eg, MIO1 or MIO2) is faulty, the MIO board will determine that it is a real fault and stop running.

[0084] (6) Chassis Description The chassis of this system is a 3U reinforced cooling VPX 8-slot chassis, which complies with the VITA 46.0 specification and VITA 65 OpenVPX specification and has a fully modular structure. The chassis is made of high-strength aluminum-magnesium alloy profiles, and the chassis surface is chemically oxidized; the chassis uses integral panel splicing, and the joints are designed with mortise and tenon structure; all VPX sub-boards are designed with cooling plate structure, and the chassis is designed with ventilation ducts, which has a good heat dissipation effect. The chassis effect diagram is as follows Fig. 9 shown.

[0085] The system software includes flight control domain software, electromechanical domain software, mission domain software and AI software. This architecture can fully utilize the computing power provided by high-performance SOC in UAV scenarios. During deployment, each domain software independently tests the corresponding CPU core. The specific deployment method is as follows: Fig.10 As shown in the figure, the flight control domain consists of RTOS / Agent, middleware and flight control applications. The flight control domain software is deployed on the small core core0 provided by the SOC; the electromechanical domain software is deployed on the small core core1. The large core (AP core) runs the Linux system, on which the mission system application and AI program run.

[0086] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0087] The above is only an exemplary embodiment of the present disclosure and cannot be used to limit the scope of the present disclosure. That is, any equivalent changes and modifications made according to the teachings of the present disclosure are still within the scope of the present disclosure. After considering the disclosure of the specification, those skilled in the art will easily think of other embodiments of the present disclosure.

[0088] This application is intended to cover any modifications, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field not recorded in the present disclosure.

Claims

1. A computer system for an unmanned aerial vehicle, characterized in that: include: Multiple SOC boards, multiple data interface control boards, power boards, backplanes and external flight interface boards, among which: Each of the multiple SOC boards includes multiple processors, which are respectively used to run flight control domain software, electromechanical domain software and mission domain software. The multiple SOC boards serve as the main control system board of the UAV, and the multiple SOC boards monitor each other and are redundant to each other; Each of the multiple data interface control boards serves as an IO control board and a sensor acquisition board. Each of the data interface control boards is used to collect flight control sensor data and to perform IO data interaction with external devices. Each of the multiple data interface control boards is redundant with each other. The power board is used to convert the input DC voltage into a low-voltage DC voltage to provide power to other boards of the computer system; The backplane is used to distribute the power output by the power board to the other boards, wherein the other boards include each SOC board in the plurality of SOC boards and each data interface control board in the plurality of data interface control boards; Each of the plurality of SOC boards is electrically connected to each other through the backplane, each of the plurality of data interface control boards is electrically connected to each other through the backplane, and each of the plurality of SOC boards is electrically connected to each of the plurality of data interface control boards through the backplane; The external aviation plug-in interface board is connected to the backplane via a high-density connector. The external aviation plug-in interface board is used to provide external input and output connections for the other boards and cards. The backplane is also used to distribute external IO signals of the external aviation plug-in interface board to the other boards and cards.

2. The computer system according to claim 1, characterized in that: The computer system also includes an AI board, which serves as an artificial intelligence computing board of the computer system. Two AI acceleration modules are integrated on the AI ​​board, wherein the computing power of each of the AI ​​acceleration modules is 8TFLOPS / FP16 and 16TOPS / INT8, and each of the AI ​​acceleration modules is used to perform AI recognition on the collected image data in real time during flight. The AI ​​board is connected to each of the multiple SOC boards through a network interface, and the other boards also include the AI ​​board.

3. The computer system according to claim 1, characterized in that: The target SOC board is any one of the multiple SOC boards, the computer system includes system software, the system software includes the flight control domain software, the electromechanical domain software and the mission domain software, wherein: The flight control domain software, the electromechanical domain software and the task domain software are respectively run on the corresponding CPU cores on the target SOC board, and are respectively used for flight control, electromechanical management and task processing.

4. The computer system according to claim 3, characterized in that: The system software also includes AI software, which is used to perform AI calculations, wherein: The flight control domain software is deployed on the first CPU core on the target SOC board, the electromechanical domain software is deployed on the second CPU core on the target SOC board, and the third CPU core on the target SOC board is used to run the Linux system, the task domain software and the AI ​​software.

5. The computer system according to claim 3, characterized in that: The target SOC board is integrated with a channel fault logic management module, and the channel fault logic management module is used to determine whether the current channel and other channels are valid according to a group of signals, wherein the current channel is used to indicate the channel corresponding to the target SOC board, and the other channels are used to indicate the channels corresponding to other SOC boards except the target SOC board among the multiple SOC boards, the group of signals includes a CPU valid signal monitored by software, a power supply logic valid signal monitored by logic, a watchdog valid signal monitored by logic, an X channel judging the valid signal of the current channel, a Y channel judging the valid signal of the current channel, a power-on start pulse signal and a channel fault logic reset signal, and the other channels include the X channel and the Y channel.

6. The computer system according to claim 3, characterized in that: The target SOC board is used to automatically switch to other channels when a fault is detected in the current channel, wherein the current channel is used to represent the channel corresponding to the target SOC board, the other channels are used to represent the channels corresponding to other SOC boards, and the other SOC boards are used to represent the SOC boards among the multiple SOC boards except the target SOC board.

7. The computer system according to claim 1, characterized in that: Each of the plurality of SOC boards performs data transmission via an LVDS interface or a PCIe interface; The target SOC board is used to identify its own ID through the target pins and determine its own priority according to the own ID, wherein the target SOC board is any one of the multiple SOC boards, and the target pins are a group of pins on the target SOC board.

8. The computer system according to claim 7, characterized in that: The target SOC board is provided with a watchdog monitoring mechanism for monitoring the state of the target SOC board. When it is detected that the target SOC board is in an abnormal state, the target SOC board is used to output fault information, hand over control authority, and isolate itself.

9. The computer system according to claim 1, characterized in that: The multiple SOC boards include a first SOC board, a second SOC board and a third SOC board, and the control rights among the multiple SOC boards are determined by a priority mechanism, wherein the priority of the first SOC board is greater than the priority of the second SOC board, and the priority of the second SOC board is greater than the priority of the third SOC board, and the multiple SOC boards constitute a triple-redundancy control system; The multiple data interface control boards include a first data interface control board and a second data interface control board, and the multiple data interface control boards constitute a dual-redundancy IO control system and a dual-redundancy sensor acquisition system.

10. The computer system according to any one of claims 1 to 9, characterized in that: The computer system also includes a chassis, which is a 3U reinforced cooling VPX 8-slot chassis. The chassis is made of aluminum-magnesium alloy profiles. The chassis is spliced ​​with integral panels and the joints are designed with mortise and tenon structures. The multiple SOC boards, the multiple data interface control boards, the power board, the backplane and the external flight interface board are all located in the chassis, and the multiple SOC boards, the multiple data interface control boards and the power board are all designed with a cooling plate structure.

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