Input buffer circuit and power management integrated circuit including same

Abstract

An input buffer circuit and a power management integrated circuit are provided. The input buffer circuit includes a low voltage generator, a first hysteresis buffer, and a first dual supply level shifter. The low voltage generator is connected to a first supply voltage having a first voltage level, generates a mirror current based on the first supply voltage, and generates a second supply voltage having a second voltage level less than the first voltage level. The second supply voltage is independent of a change in the first supply voltage. The first hysteresis buffer operates based on the second supply voltage and generates a first inverting reset signal having a hysteresis based on the inverting reset signal. The first dual supply level shifter operates based on a first supply voltage and a second supply voltage, and generates a second inverted reset signal by shifting a logic high level of the first inverted reset signal from a second voltage level to the first voltage level.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0163936 filed on November 23, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments generally relate to electronic devices. More particularly, example embodiments relate to an input buffer circuit and a power management integrated circuit (PMIC) including the input buffer circuit. Background Art

[0004] Various flat panel display devices have been developed to reduce weight and volume. Among the flat panel display devices, organic light emitting diode (OLED) display devices have advantages such as fast response speed and low power consumption because they display images using organic light emitting diodes that emit light based on the recombination of electrons and holes.

[0005] The OLED display device may include a display panel including a plurality of pixels arranged in a matrix form, each of the pixels including a transistor and an OLED element emitting light corresponding to a voltage applied to the OLED element.

[0006] When the battery voltage varies, an input buffer circuit in a power management integrated circuit included in the OLED display device needs to operate stably. Summary of the invention

[0007] Some example embodiments provide an input buffer circuit of a power management integrated circuit (PMIC) having a voltage level of a logic input independent of a variation in a battery voltage and having reduced power consumption.

[0008] Some example embodiments provide a PMIC including an input buffer circuit having a voltage level of a logic input independent of a variation in a battery voltage and having reduced power consumption.

[0009] According to some example embodiments, an input buffer circuit includes a low voltage generator, a first hysteresis buffer, and a first dual power supply level shifter. The low voltage generator is connected to a first power supply voltage having a first voltage level, generates a mirror current based on the first power supply voltage, and generates a second power supply voltage having a second voltage level less than the first voltage level. The second power supply voltage is independent of changes in the first power supply voltage. The first Schmitt trigger buffer operates based on the second power supply voltage and generates a first inverted reset signal with hysteresis based on the inverted reset signal. The first dual power supply level shifter operates based on the first power supply voltage and the second power supply voltage, and generates a second inverted reset signal by shifting a logic high level of the first inverted reset signal from the second voltage level to the first voltage level.

[0010] According to some example embodiments, the PMIC includes an input buffer circuit, a voltage generator, a negative voltage generator, and control logic. The input buffer circuit generates a second inverted reset signal and a second enable signal by buffering an inverted reset signal and an enable signal provided from an external host. The inverted reset signal and the enable signal correspond to a general purpose input / output (GPIO) signal. The voltage generator is activated in response to a first internal enable signal, and generates a high power supply voltage to be provided to a display panel including a plurality of pixels based on a first power supply voltage corresponding to a battery voltage. The negative voltage generator is activated in response to a second internal enable signal, and generates a low power supply voltage to be provided to the display panel based on the first power supply voltage. The control logic generates a first internal enable signal and a second internal enable signal based on a second inverted reset signal and a second enable signal. The input buffer circuit includes a low voltage generator, a first hysteresis buffer, and a first dual power supply level shifter. The low voltage generator is connected to a first power supply voltage having a first voltage level, generates a mirror current based on the first power supply voltage, and generates a second power supply voltage having a second voltage level less than the first voltage level. The second power supply voltage is independent of changes in the first power supply voltage. The hysteresis buffer operates based on the second power supply voltage and generates a first inverted reset signal with hysteresis based on the inverted reset signal. The first dual power supply level shifter operates based on the first power supply voltage and the second power supply voltage and generates a second inverted reset signal by shifting a logic high level of the first inverted reset signal from the second voltage level to the first voltage level.

[0011] According to some example embodiments, an input buffer circuit includes a low voltage generator, a hysteresis buffer, and a dual power supply level shifter. The low voltage generator is connected to a first power supply voltage having a first voltage level, generates a mirror current based on the first power supply voltage, and generates a second power supply voltage having a second voltage level less than the first voltage level. The second power supply voltage is independent of changes in the first power supply voltage. The hysteresis buffer operates based on the second power supply voltage and outputs a first inverted reset signal with hysteresis based on the inverted reset signal. The dual power supply level shifter operates based on the first power supply voltage and the second power supply voltage, and generates a second inverted reset signal by shifting a logic high level of the first inverted reset signal from the second voltage level to the first voltage level. The low voltage generator includes a plurality of n-channel metal oxide semiconductor (NMOS) transistors and a power supply transistor. The plurality of NMOS transistors are coupled in series between a first node and a ground (i.e., return) voltage, each of the plurality of NMOS transistors is diode-connected, and the power supply transistor is coupled between the first power supply voltage and the first node. The low voltage generator generates a mirror current by replicating the first current and provides the mirror current to the first node, and generates a second power supply voltage by providing a target voltage to the gate of the power supply transistor at the first node. The target voltage corresponds to the sum of the threshold voltages of the plurality of NMOS transistors.

[0012] Therefore, in the input buffer circuit and the PMIC, the low voltage generator generates a mirror current based on the battery voltage and generates a low voltage that is lower than the battery voltage and independent of changes in the battery voltage, and the dual power supply level shifter uses the battery voltage and the low voltage to shift the voltage level of the input signal. Therefore, the level of the logic high voltage and the level of the logic low voltage of the input buffer circuit are independent of the battery voltage. Therefore, even when the voltage level of the battery voltage is reduced or increased, the input buffer circuit can operate stably and can reduce power consumption by generating a mirror current based on a small current. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (when used) designate corresponding elements throughout the several views.

[0014] Figure 1 is a schematic block diagram illustrating at least a portion of a mobile device according to an example embodiment.

[0015] Figure 2 According to an example embodiment Figure 1 A schematic plan view of an organic light emitting diode (OLED) display device in a mobile device.

[0016] Figure 3 It is shown Figure 1A schematic diagram of example connections of pixels in an OLED display device is shown.

[0017] Figure 4 is a diagram showing a method of performing a Figure 3 The pixel connections are shown in a circuit diagram of an example of a pixel.

[0018] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 A schematic block diagram of at least a portion of an example of a power management integrated circuit (PMIC) in a mobile device.

[0019] Figure 6 is a diagram showing a method according to an example embodiment Figure 5 A schematic block diagram of at least a portion of an example of a PMIC.

[0020] Figure 7 is a diagram showing a method according to an example embodiment Figure 6 A schematic block diagram of an example of an input buffer circuit in a PMIC.

[0021] Fig. 8A is a diagram showing a method according to an example embodiment Figure 7 A schematic block diagram of an example of a low voltage generator in an input buffer circuit.

[0022] Figure 8B is a diagram showing a method according to an example embodiment Figure 7 A circuit diagram of an example of a low voltage generator in an input buffer circuit.

[0023] Fig.9A is a graph illustrating an example operation of a first Schmitt-trigger buffer according to example embodiments.

[0024] Fig. 9B is a diagram showing a method according to an example embodiment Figure 7 A circuit diagram of an example of an input buffer circuit of a first dual-supply level shifter.

[0025] Fig.10 is a diagram showing a method according to an example embodiment Figure 5 A schematic block diagram of a portion of a PMIC.

[0026] Fig.11 is a diagram showing a method according to an example embodiment Fig.10 A schematic block diagram of an example of a second voltage generator in a PMIC in FIG.

[0027] Fig.12 is a diagram showing a method according to an example embodiment Figure 1 A schematic block diagram of an example of a voltage generator in an OLED display device.

[0028] Fig.13 is a diagram showing a method according to an example embodiment Figure 1 A schematic block diagram of an example of a timing controller in an OLED display device.

[0029] Fig.14 is a diagram showing a method according to an example embodiment Figure 1 Schematic block diagram of an example of a scan driver circuit in an OLED display device.

[0030] Fig.15 is a diagram showing a method for performing Figure 1 The transmit driver circuit combination in Fig.14 Schematic block diagram of a scan driver circuit.

[0031] Fig.16 is a diagram showing a method according to an example embodiment Figure 1 A schematic block diagram of an emission driver circuit of an OLED display device is shown.

[0032] Fig.17 is a schematic block diagram illustrating at least a portion of an example of a display system according to example embodiments.

[0033] Fig.18 is a schematic block diagram illustrating an electronic device including an OLED display device according to example embodiments.

[0034] Fig.19 is a schematic block diagram illustrating an example of an electronic device according to an example embodiment.

[0035] Fig. 20 is a diagram showing a method for providing Fig.19 A schematic block diagram of at least a portion of a circuit configuration for transmitting power to components in an electronic device. DETAILED DESCRIPTION

[0036] Example embodiments are described more fully hereinafter with reference to the accompanying drawings.In all of the several views, the same or similar reference numerals represent the same or similar elements.

[0037] Components described in the detailed description with reference to terms "unit", "circuit", "block", "device", "component", etc. may be implemented in software, hardware, or a combination thereof. For example, software may be machine code, firmware, embedded code, and application software. For example, hardware may include circuits, electronic circuits, processors, computers, integrated circuit cores, pressure sensors, micro-electromechanical systems (MEMS), passive components, or a combination thereof.

[0038] Figure 1 is a schematic block diagram illustrating at least a portion of a mobile device according to an example embodiment.

[0039] Reference Figure 1 , the mobile device 50 may include an organic light emitting diode (OLED) display device 100 and a power management integrated circuit (PMIC) 400 .

[0040] The OLED display device 100 may include a driving circuit 105 , a display panel 110 , and a voltage generator 300 .

[0041] The driving circuit 105 and the voltage generator 300 may constitute a display driving integrated circuit.

[0042] The driving circuit 105 may include a timing controller 130 , a data driver circuit 150 , a scan driver circuit 200 , and an emission driver circuit 260 .

[0043] The timing controller 130, the data driver circuit 150, the scan driver unit circuit 200, and the emission driver circuit 260 may be electrically coupled to the display panel 110, such as but not limited to, by using a chip-on-flexible printed circuit (COF), a chip-on-glass (COG), a flexible printed circuit (FPC), etc. The term "coupled" (or "coupled" or similar terms such as "contacting", "connected", "touching", or "engaged") as may be used herein is intended to refer to a physical and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.

[0044] The display panel 110 may be electrically coupled to the scan driver circuit 200 of the driving circuit 105 through a plurality of scan line groups SLS1 to SLSn (n is an integer greater than three), may be coupled to the data driver circuit 150 through a plurality of data lines DL1 to DLm (m is an integer greater than three), and may be coupled to the emission driver circuit 260 of the driving circuit 105 through a plurality of emission control lines EL1 to ELn. In one or more embodiments, m and n may be different, but the embodiment is not limited thereto. The display panel 110 may include a plurality of pixels (PX) 111, and each pixel 111 is disposed at the intersection of each of the scan line groups SLS1 to SLSn, each of the data lines DL1 to DLm, and each of the emission control lines EL1 to ELn.

[0045] The display panel 110 may receive the high power voltage ELVDD and the low power voltage ELVSS from the PMIC 400 .

[0046] The display panel 110 may receive a first initialization voltage VINT and a second initialization voltage AINT from the voltage generator 300. The emission driver circuit 260 may receive a first operating voltage VDD, a second operating voltage VGL, and a negative voltage NVG from the voltage generator 300. In addition, the scan driver circuit 200 may receive a first operating voltage VDD, a second operating voltage VGL, and a negative voltage NVG from the voltage generator 300.

[0047] The scan driver circuit 200 may apply a plurality of scan signals to each of the pixels 111 through a plurality of scan line groups SLS1 to SLSn based on a second driving control signal DCTL2 that may be provided by the timing controller 130 .

[0048] The scan driver circuit 200 may enable at least two scan signals among the plurality of scan signals during a non-emission interval in which the pixels do not emit light, so that the scan signals partially overlap during two consecutive horizontal periods. The horizontal period corresponds to the period of the horizontal synchronization signal used by the timing controller 130.

[0049] The data driver circuit 150 may apply a data voltage to each of the pixels 111 through the plurality of data lines DL1 to DLm based on a first driving control signal DCTL1 that may be provided by the timing controller 130 .

[0050] The emission driver circuit 260 may apply an emission control signal to each of the pixels 111 through the plurality of emission control lines EL1 to ELn based on the third driving control signal DCTL3 provided by the timing controller 130. The brightness of the display panel 110 may be adjusted based on the emission control signal.

[0051] The voltage generator 300 may provide the first initialization voltage VINT and the second initialization voltage AINT to the display panel 110 in response to the power control signal PCTL that may be provided by the timing controller 130, and may provide the first operating voltage VDD, the second operating voltage VGL, and the negative voltage NVG to the emission driver circuit 260 and the scan driver circuit 200. The voltage generator 300 may change the level of the second initialization voltage AINT based on the power control signal PCTL indicating the frame rate of the image displayed in the display panel 110.

[0052] The timing controller 130 may receive input image data RGB and a control signal CTL, and may generate first to third driving control signals DCTL1 to DCTL3 and a power control signal PCLT based on the control signal CTL. The timing controller 130 may provide the first driving control signal DCTL1 to the data driver circuit 150, the second driving control signal DCTL2 to the scan driver circuit 200, the third driving control signal DCTL3 to the emission driver circuit 260, and the power control signal PCTL to the voltage generator 300. The timing controller 130 may receive input image data RGB, and arrange the input image data RGB to provide the data signal DTA to the data driver circuit 150.

[0053] The PMIC 400 may generate a first driving voltage VDDR having a positive level and a second driving voltage NAVDD having a negative level based on a battery voltage VBAT received from a battery, and may provide the first driving voltage VDDR and the second driving voltage NAVDD to the voltage generator 300 .

[0054] In addition, the PMIC 400 may generate a high power voltage ELVDD and a low power voltage ELVSS based on the battery voltage VBAT, and may provide the high power voltage ELVDD and the low power voltage ELVSS to the display panel 110 .

[0055] The PMIC 400 may include an input buffer circuit 420. The input buffer circuit 420 may generate a buffer signal by buffering the inverted reset signal RSTB, and may provide the buffer signal to an internal circuit of the PMIC 400. The input buffer circuit 420 may be configured such that the buffer signal has a voltage level of a logic input independent of changes in the battery voltage VBAT.

[0056] Figure 2 According to an example embodiment Figure 1 Schematic plan view of an OLED display device 100 in a mobile device 50.

[0057] Reference Figure 2 , the OLED display device 100 includes a substrate 10. The substrate 10 may include a display area DA and a peripheral area PA outside the display area DA (ie, surrounding the display area DA or extending around the display area DA).

[0058] A plurality of pixels (PX) 111 may be arranged in the display area DA of the substrate 10. Various wirings for transmitting (ie, transferring) electrical signals to be applied to the driving circuit 105 and the display area DA may be located in the peripheral area PA of the substrate 10.

[0059] Figure 1 The PMIC 400 in the embodiment may be disposed in the peripheral area PA.

[0060] Figure 3 It is shown Figure 1 A schematic diagram of at least a portion of example connections for pixels in an OLED display device is shown.

[0061] Figure 4 is a diagram showing a method of performing a Figure 3 An example of pixel connection of a pixel 111 is shown in a circuit diagram.

[0062] exist Figure 3 In the embodiment, the pixel 111 is electrically coupled to a first scan line group SLS1, a first data line DL1 and a first emission control line EL1, and the first scan line group SLS1 includes a first scan line SL11, a second scan line SL21, a third scan line SL31 and a fourth scan line SL41.

[0063] Reference Figure 4 , the pixel 111 may include a pixel circuit 112 and an OLED 114. The pixel circuit 112 may include a switching transistor T1, a driving transistor T2, a compensation transistor T3, a first initialization transistor T4, first and second emission transistors T5 and T6, a second initialization transistor T7, and a storage capacitor CST.

[0064] The switching transistor T1 may include a p-channel metal oxide semiconductor (PMOS) transistor having a first electrode (first source / drain) coupled to the data line DL1 to receive the data voltage SDT, a gate electrode coupled to the second scan line SL21 to receive the second scan signal GW1, and a second electrode (second source / drain) coupled to the first node N11. The driving transistor T2 may include a PMOS transistor having a first electrode coupled to the first node N11, a gate electrode coupled to the second node N12, and a second electrode coupled to the third node N13.

[0065] The compensation transistor T3 may include a PMOS transistor having a gate electrode coupled to the third scan line SL31 to receive the third scan signal GC1, a first electrode coupled to the second node N12, and a second electrode coupled to the third node N13. The first initialization transistor T4 may include a PMOS transistor having a gate electrode coupled to the first scan line SL11 to receive the first scan signal GI1, a first electrode coupled to the second node N12, and a second electrode receiving the first initialization voltage VINT.

[0066] The first emission transistor T5 may include a PMOS transistor having a first electrode coupled to the high power supply voltage ELVDD, a second electrode coupled to the first node N11, and a gate electrode coupled to the first emission control line EL1 to receive the first emission control signal EC1. The second emission transistor T6 may include a PMOS transistor having a first electrode coupled to the third node N13, a second electrode coupled to the fourth node N14, and a gate electrode coupled to the first emission control line EL1 to receive the first emission control signal EC1.

[0067] The second initialization transistor T7 may include a PMOS transistor having a gate electrode coupled to the fourth scan line SL41 to receive the fourth scan signal GB1 , a first electrode receiving the second initialization voltage AINT, and a second electrode coupled to the fourth node N14 .

[0068] The storage capacitor CST may have a first terminal coupled to the high power voltage ELVDD and a second terminal coupled to the second node N12. The OLED 114 may have an anode coupled to the fourth node N14 and a cathode coupled to the low power voltage ELVSS.

[0069] The switching transistor T1 transfers the data voltage SDT to the storage capacitor CST in response to the second scan signal GW1 , and the OLED 114 may emit light in response to the data voltage SDT stored in the storage capacitor CST to display an image.

[0070] The emission transistors T5 and T6 are turned on or off in response to the first emission control signal EC1 to supply current to the OLED 114 or to cut off (i.e., stop) the current flowing to the OLED 114. When the current flowing to the OLED 114 stops, the OLED 114 does not emit light. Therefore, the emission transistors T5 and T6 are turned on or off in response to the first emission control signal EC1 to adjust the brightness of the display panel 110.

[0071] The compensation transistor T3 may electrically connect the second node N12 and the third node N13 in response to the third scan signal GC1. That is, when an image is displayed by diode-connecting the gate electrode and the second electrode of the driving transistor T2, the compensation transistor T3 may compensate for a change in the threshold voltage of each driving transistor of each pixel 111. In the diode-connected arrangement, the PMOS transistor and the n-channel metal oxide semiconductor (NMOS) transistor are configured to have their drain terminals connected to their gates so that the gate voltage and the drain voltage of the device are equal.

[0072] The first initialization transistor T4 may transmit a first initialization voltage VINT to the second node N12 in response to the first scan signal GI1. The first initialization transistor T4 may initialize a data voltage transmitted to the driving transistor T2 during a previous frame by transmitting the initialization voltage VINT to the gate electrode of the driving transistor T2. The second initialization transistor T7 may transmit a second initialization voltage AINT to the fourth node N14 in response to the fourth scan signal GB1 to discharge the parasitic capacitance between the second emission transistor T6 and the OLED 114.

[0073] Figure 5 is a diagram showing a method according to an example embodiment Figure 1 FIG. 4 is a schematic block diagram of an example connection of a PMIC 400 in a mobile device.

[0074] Reference Figure 5 , the PMIC 400 is coupled to a first inductor 411 receiving a battery voltage VBAT at a node N21, to a second inductor 412 coupled to a ground voltage VSS at a node N22, and to a third inductor 413 receiving a battery voltage VBAT at a node N23.

[0075] The PMIC 400 may generate a high power voltage ELVDD and a first driving voltage VDDR based on the battery voltage VBAT, and may supply the high power voltage ELVDD and the first driving voltage VDDR to the display panel 110 ( Figure 1 ) provides a high power supply voltage ELVDD and supplies a voltage generator 300 ( Figure 1 ) provides a first driving voltage VDDR.

[0076] The PMIC 400 may generate a low power voltage ELVSS based on the ground voltage VSS, and may supply the low power voltage ELVSS to the display panel 110 ( Figure 1 ) provides the low power supply voltage ELVSS. The first capacitor 414 may be coupled between a node N24 connected to the PMIC 400 and a node N25 connected to the ground voltage VSS, and may store charges generated by the first driving voltage VDDR.

[0077] The PMIC 400 may generate a second driving voltage NAVDD based on the battery voltage VBAT, and may provide the second driving voltage NAVDD to the voltage generator 300 ( Figure 1 ) provides a second driving voltage NAVDD.

[0078] The second capacitor 415 may be coupled between a node N26 connected to the PMIC 400 and a node N25 connected to the ground voltage VSS, and may store charges generated by the second driving voltage NAVDD.

[0079] Figure 6 is a diagram showing a method according to an example embodiment Figure 54 is a schematic block diagram of an example of a PMIC 400.

[0080] Reference Figure 6 , the PMIC 400 may include an input buffer circuit 420, a control logic 510, an undervoltage lockout (UVLO) circuit 520, a reference voltage (BGR) generator 530, and an internal low voltage dropout (ILDO) regulator 540. The UVLO circuit 520, the BGR generator 530, and the ILDO regulator 540 may perform functions related to initial operation; that is, the output signals generated by the UVLO circuit 520, the BGR generator 530, and the ILDO regulator 540 may not be available outside the PMIC 400.

[0081] The PMIC 400 may further include an input buffer circuit 545 , a communication interface 550 , a first voltage generator 561 , a second voltage generator 570 , and a negative voltage generator 565 .

[0082] The UVLO circuit 520 may receive a battery voltage VBAT, may compare the battery voltage VBAT with a reference level (e.g., an internally generated or externally provided reference voltage), may generate a voltage level detection signal VLDS, and may provide the voltage level detection signal VLDS to the BGR generator 530 and the control logic 510, the voltage level detection signal VLDS being activated in response to the battery voltage VBAT reaching the reference level.

[0083] The BGR generator 530 may generate a reference voltage VREF based on the battery voltage VBAT in response to activation of the voltage level detection signal VLDS, and may provide the reference voltage VREF to the ILDO regulator 540 .

[0084] The ILDO regulator 540 may receive the battery voltage VBAT and may generate an internal voltage VINT based on the reference voltage VREF and the battery voltage VBAT. The ILDO regulator 540 may generate the internal voltage VINT in response to the reference voltage VREF reaching a first target level, may provide the internal voltage VINT to the control logic 510, and may provide an okay signal INT_OK to the control logic 510 in response to the reference voltage VREF reaching a second target level.

[0085] The input buffer circuit 420 can generate a second inverted reset signal RSTB2 and a second enable signal EN2 by buffering the inverted reset signal RSTB and the enable signal EN received from an external host via general purpose input / output (GPIO) pins (i.e., terminals) 403 and 404, respectively, and can provide the second inverted reset signal RSTB2 and the second enable signal EN2 to the control logic 510.

[0086] The control logic 510 can receive an internal voltage VINT, can operate based on the internal voltage VINT, can receive a voltage level detection signal VLDS and an enable signal INT_OK, can generate internal enable signals IEN11, IEN12 and IEN13 in response to activation of the voltage level detection signal VLDS and the enable signal INT_OK and activation of the second inverted reset signal RSTB2 and the second enable signal EN2, and can provide the internal enable signals IEN11, IEN12 and IEN13 to the first voltage generator 561, the second voltage generator 570 and the negative voltage generator 565, respectively.

[0087] The first voltage generator 561 may be activated based on the internal enable signal IEN11 and may generate a high power supply voltage ELVDD based on the battery voltage VBAT. The second voltage generator 570 may be activated based on the internal enable signal IEN12 and may generate a first driving voltage VDDR based on the battery voltage VBAT. The negative voltage generator 565 may be activated based on the internal enable signal IEN13 and may generate a second driving voltage NAVDD and a low power supply voltage ELVSS based on the ground voltage VSS.

[0088] The first voltage generator 561 , the second voltage generator 570 , and the negative voltage generator 565 may be coupled to a battery voltage VBAT and a ground voltage VSS.

[0089] A battery voltage VBAT may be provided to the PMIC 400 through a power terminal 401 , and a ground voltage VSS may be provided to the PMIC 400 through a ground terminal 402 .

[0090] The external host may drive a serial clock line SCL and a serial data line SDA between the external host and the PMIC 400. The external host may send an SCL signal (i.e., a clock signal) to the input buffer circuit 545 through the SCL terminal 405. The input buffer circuit 545 may provide a second SCL signal SCL2 to the communication interface 550 by buffering the SCL signal. The external host may send an SDA signal (i.e., a data signal) synchronized with the SCL signal to the input buffer circuit 545 through the SDA terminal 406. The input buffer circuit 545 may provide a second SDA signal SDA2 to the communication interface 550 by buffering the SDA signal.

[0091] The inverted reset signal RSTB, the enable signal EN, the SCL signal, and the SDA signal may correspond to the GPIO signal GPIOS. The inverted reset signal RSTB may correspond to one of the GPIO signals GPIOS, and the enable signal EN may correspond to another one of the GPIO signals GPIOS.

[0092] Figure 7 is a diagram showing a method according to an example embodiment Figure 6 4 is a schematic block diagram of an example of an input buffer circuit 420 in a PMIC 400 .

[0093] Reference Figure 7 , the input buffer circuit 420 may include a low voltage generator 430, a first Schmitt trigger buffer 460a, a second Schmitt trigger buffer 460b, a first dual power supply level shifter 470a and a second dual power supply level shifter 470b. The Schmitt trigger is a comparator circuit that incorporates hysteresis implemented by applying positive feedback to the non-inverting input of the comparator or differential amplifier. The hysteresis function of the Schmitt trigger buffers 460a, 460b provides noise immunity by preventing a transition to a new logic state until the input signal has clearly moved across the input threshold. Therefore, the first Schmitt trigger buffer 460a may be referred to as a first hysteresis buffer, and the second Schmitt trigger buffer 460b may be referred to as a second hysteresis buffer.

[0094] The low voltage generator 430 may be connected to a first power supply voltage VDDH having a first voltage level, may generate a mirror current based on the first power supply voltage VDDH, and may generate a second power supply voltage VDDL having a second voltage level less than the first voltage level. The first power supply voltage VDDH may correspond to a battery voltage VBAT. The second power supply voltage VDDL may be independent of changes in the first power supply voltage VDDH. The low voltage generator 430 may also be connected to a ground voltage VSS.

[0095] The first Schmitt trigger buffer 460a may operate based on the second power supply voltage VDDL, and may output the first inverted reset signal RSTB1 by Schmitt triggering the inverted reset signal RSTB provided as an input to the first Schmitt trigger buffer 460a. That is, the first Schmitt trigger buffer 460a may generate the first inverted reset signal RSTB1 with hysteresis based on the inverted reset signal RSTB provided as an input to the first Schmitt trigger buffer 460a.

[0096] The second Schmitt trigger buffer 460b may operate based on the second power supply voltage VDDL, and may output the first enable signal EN1 by Schmitt triggering the enable signal EN provided as an input to the second Schmitt trigger buffer 460b. That is, the second Schmitt trigger buffer 460b may generate the first enable signal EN1 with hysteresis based on the enable signal EN provided as an input to the second Schmitt trigger buffer 460b.

[0097] The first dual power level shifter 470 a may operate based on the first power voltage VDDH and the second power voltage VDDL, and may generate the second inversion reset signal RSTB2 by shifting a logic high level of the first inversion reset signal RSTB1 from the second voltage level to the first voltage level.

[0098] The second dual power level shifter 470 b may operate based on the first power voltage VDDH and the second power voltage VDDL, and may generate the second enable signal EN2 by shifting a logic high level of the first enable signal EN1 from the second voltage level to the first voltage level.

[0099] Since the first Schmitt trigger buffer 460a and the second Schmitt trigger buffer 460b operate based on the second power supply voltage VDDL which is independent of changes in the first power supply voltage VDDH, the level of the logic high voltage VIH and the level of the logic low voltage VIL of each of the first Schmitt trigger buffer 460a and the second Schmitt trigger buffer 460b can be independent of the first power supply voltage VDDH.

[0100] Input buffer circuit 545 (see Figure 6 ) can be configured with Figure 7 The configuration of the input buffer circuit 420 is substantially the same or similar.

[0101] Fig. 8A is a diagram showing a method according to an example embodiment Figure 7 4 is a schematic block diagram of an example implementation of a low voltage generator 430 in an input buffer circuit 420 of FIG.

[0102] Reference Fig. 8A , the low voltage generator 430a may include a current mirror circuit 440, a current source CS 445, a target voltage generating unit 450a, and a power transistor PT. A current mirror is a circuit configured to copy a current (input reference current) through another active device by controlling an output current in one active device, thereby keeping an output current substantially constant regardless of a load.

[0103] The current source 445 may generate a first current that sinks (ie, flows) to the ground voltage VSS. Although illustrated as an ideal current source, the current source 445 may be implemented using various known circuits for generating a constant (reference) current.

[0104] The current mirror circuit 440 may be connected to the first power supply voltage VDDH and the current source 445, may generate a mirror current Im by mirroring the first current Is, and may provide the mirror current Im to the first node N31.

[0105] The first current Is may be set to have a magnitude equal to or less than 100 mA to reduce a standby current, but the embodiment is not limited thereto. Therefore, the power consumption of the low voltage generator 430 a may be reduced.

[0106] The target voltage generating unit 450a may include a plurality of n-channel metal oxide semiconductor (NMOS) transistors M1, ..., Mr coupled in series between the first node N31 and the ground voltage VSS. Here, r is an integer greater than 2. Each of the plurality of NMOS transistors M1, ..., Mr is diode-connected, and the plurality of NMOS transistors M1, ..., Mr may operate a plurality of diodes coupled in series. That is, each of the plurality of NMOS transistors M1, ..., Mr may have a drain and a gate coupled to each other.

[0107] The power transistor PT may be an NMOS transistor, which may have a drain coupled to the first power voltage VDDH, a gate coupled to the first node N31, and a source providing the second power voltage VDDL.

[0108] Therefore, the target voltage generating unit 450a (i.e., multiple NMOS transistors M1, ..., Mr) can provide a target voltage Vr to the gate of the power transistor PT at the first node N31, which target voltage Vr corresponds to the sum of the threshold voltages of each of the multiple NMOS transistors M1, ..., Mr, and the power transistor PT connected in a source follower configuration can adjust the level of the second power supply voltage VDDL based on the target voltage Vr.

[0109] In example embodiments, the power transistor PT may correspond to a native NMOS transistor having a threshold voltage of substantially zero, and a level of the second power voltage VDDL may be the same as that of the target voltage Vr.

[0110] In example embodiments, the power transistor PT may correspond to an NMOS transistor having a non-zero threshold voltage, and the level of the second power voltage VDDL may correspond to a value obtained by subtracting the threshold voltage of the NMOS transistor from the level of the target voltage Vr.

[0111] Because each of the plurality of NMOS transistors M1, ..., Mr is diode-connected, the level of the target voltage Vr may be determined based on the number of the plurality of NMOS transistors M1, ..., Mr, or may be determined based on the size of each of the plurality of NMOS transistors M1, ..., Mr. The size of each of the plurality of NMOS transistors M1, ..., Mr may be associated with a ratio of a channel length to a channel width of each of the plurality of NMOS transistors M1, ..., Mr.

[0112] The current mirror circuit 440 may include a first p-channel metal oxide semiconductor (PMOS) transistor 441 and a second PMOS transistor 442 .

[0113] The first PMOS transistor 441 may have a source coupled to the first power supply voltage VDDH, a gate coupled to the current source 445 at the second node N32, and a drain coupled to the current source 445 at the second node N32. The second PMOS transistor 442 may have a source coupled to the first power supply voltage VDDH, a drain coupled to the first node N31, and a gate coupled to the second node N32, and may provide a mirror current Im to the first node N31.

[0114] Figure 8B is a diagram showing a method according to an example embodiment Figure 7 4 is a schematic block diagram of another example implementation of a low voltage generator 430 in an input buffer circuit 420 of FIG.

[0115] Reference Figure 8B , the low voltage generator 430b may include a current mirror circuit 440, a current source CS 445, a target voltage generating unit 450b, and a power transistor PT.

[0116] The current source 445 may generate a first current IS that sinks to a ground voltage VSS.

[0117] The current mirror circuit 440 may be connected to the first power supply voltage VDDH and the current source 445, may generate a mirror current Im by mirroring the first current Is, and may provide the mirror current Im to the first node N31.

[0118] The target voltage generating unit 450b may include a plurality of diodes D1, ..., Dr coupled between the first node N31 and the ground voltage VSS in a forward bias direction. The plurality of diodes D1, ..., Dr may be connected in series between the first node N31 and the ground voltage VSS. That is, each of the plurality of diodes D1, ..., Dr may be forward biased, wherein the cathode of one diode is connected to the anode of an adjacent diode in the series chain, and wherein the cathode of the first diode D1 may be connected to the ground voltage VSS, and the anode of the rth diode Dr may be connected to the first node N31.

[0119] The power transistor PT may be an NMOS transistor, which may have a drain coupled to the first power voltage VDDH, a gate coupled to the first node N31, and a source providing the second power voltage VDDL.

[0120] Therefore, the target voltage generating unit 450b (i.e., multiple diodes D1, ..., Dr) can provide a target voltage Vr to the gate of the power transistor PT at the first node N31, which target voltage Vr corresponds to the sum of the threshold voltages of each of the multiple diodes D1, ..., Dr, and the power transistor PT can adjust the level of the second power voltage VDDL based on the target voltage Vr.

[0121] In example embodiments, the power transistor PT may correspond to a native NMOS transistor having a threshold voltage of substantially zero, and a level of the second power voltage VDDL may be the same as that of the target voltage Vr.

[0122] In example embodiments, the power transistor PT may correspond to an NMOS transistor having a non-zero threshold voltage, and the level of the second power voltage VDDL may correspond to a value obtained by subtracting the threshold voltage of the NMOS transistor from the level of the target voltage Vr.

[0123] The level of the target voltage Vr may be determined based on the number of the plurality of diodes D1 , . . . , Dr.

[0124] The current mirror circuit 440 may include a first p-channel metal oxide semiconductor (PMOS) transistor 441 and a second PMOS transistor 442 .

[0125] The first PMOS transistor 441 may have a source coupled to the first power supply voltage VDDH, a gate coupled to the current source 445 at the second node N32, and a drain coupled to the current source 445 at the second node N32. The second PMOS transistor 442 may have a source coupled to the first power supply voltage VDDH, a drain coupled to the first node N31, and a gate coupled to the second node N32, and provide a mirror current Im to the first node N31.

[0126] Fig.9A is a graph illustrating an example operation of a first Schmitt trigger buffer according to example embodiments.

[0127] Reference Figure 7 and Fig.9A, the first Schmitt trigger buffer 460a may have a hysteresis characteristic and may output a first inverted reset signal RSTB1 by Schmitt triggering the inverted reset signal RSTB provided as an input to the first Schmitt trigger buffer 460a. Because the first Schmitt trigger buffer 460a operates based on the second power supply voltage VDDL, the level of the logic high (logic "1") voltage VIH and the level of the logic low (logic "0") voltage VIL of the first Schmitt trigger buffer 460a are independent of the first power supply voltage VDDH. In addition, even when no additional power supply voltage is provided to the first Schmitt trigger buffer 460a, the first Schmitt trigger buffer 460a may operate stably because the first Schmitt trigger buffer 460a operates based on the second power supply voltage VDDL provided from the low voltage generator 430a.

[0128] Since the level of the logic high voltage VIH and the level of the logic low voltage VIL of the first Schmitt trigger buffer 460a are independent of the first power supply voltage VDDH, even when the voltage level of the first power supply voltage VDDH decreases or increases, including Fig. 8A The low voltage generator 430a or Figure 8B The input buffer circuit 420 of the low voltage generator 430b still operates stably.

[0129] Fig. 9B is a diagram showing a method according to an example embodiment Figure 7 4 is a circuit diagram of an example of an input buffer circuit of a first dual supply level shifter 470a.

[0130] Reference Fig. 9B , the first dual-supply level shifter 470a may include an inverter 475 and a shift circuit SC.

[0131] The inverter 475 may be coupled between the second power voltage VDDL and the ground voltage VSS, and may output the first reset signal RST1 by inverting the first inverted reset signal RSTB1 .

[0132] The shift circuit SC is coupled between the first power supply voltage VDDH and the ground voltage VSS, can receive the first inverted reset signal RSTB1 and the first reset signal RST1, and can output the second inverted reset signal RSTB2 by shifting the logic high level of the first inverted reset signal RSTB1 from the second voltage level to the first voltage level.

[0133] The shift circuit SC may include a first PMOS transistor 471 , a second PMOS transistor 472 , a first NMOS transistor 473 , and a second NMOS transistor 474 .

[0134] The first PMOS transistor 471 may be coupled between the first power supply voltage VDDH and the first node N41, and may have a gate coupled to the second node N42. The second PMOS transistor 472 may be coupled between the first power supply voltage VDDH and the second node N42, and may have a gate coupled to the first node N41; that is, the first PMOS transistor 471 and the second PMOS transistor 472 may be connected in a cross-coupling configuration, which may increase the gain of the dual power supply level shifter 470a.

[0135] The first NMOS transistor 473 may be coupled between the first node N41 and the ground voltage VSS and may have a gate receiving the first inverted reset signal RSTB1. The second NMOS transistor 474 may be coupled between the second node N42 and the ground voltage VSS and may have a gate receiving the first reset signal RST1.

[0136] When the first inverted reset signal RSTB1 has a logic high level, the first NMOS transistor 473 is turned on and the first node N41 is discharged to the ground voltage VSS. In addition, the second PMOS transistor 472 is turned on based on the voltage level of the first node N41, and the voltage level of the second inverted reset signal RSTB2 is shifted to the first voltage level of the first power supply voltage VDDH.

[0137] When the first inverted reset signal RSTB1 has a logic low level, the second NMOS transistor 474 is turned on, the second node N42 is discharged to the ground voltage VSS, and the voltage level of the second inverted reset signal RSTB2 has the level of the ground voltage VSS.

[0138] Therefore, when the first inverted reset signal RSTB1 swings between the second power supply voltage VDDL and the ground voltage VSS, the second inverted reset signal RSTB2 swings between the first power supply voltage VDDH and the ground voltage VSS.

[0139] Fig.10 is a diagram showing a method according to an example embodiment Figure 5 4 is a schematic block diagram of a portion of a PMIC 400.

[0140] Reference Figure 5 , Figure 6 and Fig.10, the first voltage generator 561 may be coupled to the node N21 and may generate the high power supply voltage ELVDD based on the battery voltage VBAT stored in the inductor 411. The second voltage generator 570 may be coupled to the node N23 and may generate the first driving voltage VDDR based on the battery voltage VBAT stored in the inductor 413. The negative voltage generator 565 may be coupled to the node N22 and may generate the second driving voltage NAVDD and the low power supply voltage ELVSS based on the ground voltage VSS stored in the inductor 412.

[0141] Fig.11 is a diagram showing a method according to an example embodiment Fig.10 A schematic block diagram of an example of a second voltage generator 570 in the PMIC 400 is shown.

[0142] Reference Fig.11 The second voltage generator 570 may include a main driver 575 , a first power switch MP, a second power switch MN, an inductor L11 , a feedback circuit 580 , and a pulse width modulation (PWM) controller 585 .

[0143] The first power switch MP may be coupled between the battery voltage VBAT and the switch node SN, and may include a PMOS transistor having a source coupled to the battery voltage VBAT, a gate receiving the first drive control signal PD, and a drain coupled to the switch node SN. The second power switch MN may be coupled between the switch node SN and the ground voltage VSS. The second power switch MN may include an NMOS transistor having a drain coupled to the switch node SN, a gate receiving the second drive control signal ND, and a source coupled to the ground voltage VSS.

[0144] Energy based on the battery voltage VBAT may be stored in the inductor L11 through switching operations of the first power switch MP and the second power switch MN, and the energy stored in the inductor L11 may be provided as the first driving voltage VDDR at the output node N51 .

[0145] The PWM controller 585 may generate a PWM signal SPWM based on a feedback voltage VFB1 proportional to the first driving voltage VDDR. The PWM controller 585 may generate the PWM signal SPWM by performing PWM on the feedback voltage VFB1 provided as an input to the PWM controller 585. The PWM signal SPWM may be provided as an input to the main driver 575.

[0146] The feedback circuit 580 may generate a feedback voltage VFB1 proportional to the first driving voltage VDDR, and may provide the feedback voltage VFB1 to the PWM controller 585. The feedback circuit 580 may include voltage-dividing resistors R11 and R12 connected in series between the output node N51 and the ground voltage VSS, and the voltage-dividing resistors R11 and R12 may be connected to each other at the feedback node FN in a voltage divider configuration. For example, Fig.11 As shown, the feedback circuit 580 may generate a feedback voltage VFB1 corresponding to a ratio of resistance values ​​of the voltage-dividing resistors R11 and R12, but example embodiments are not limited thereto.

[0147] Fig.12 is a diagram showing a method according to an example embodiment Figure 1 FIG. 1 is a schematic block diagram of an example of a voltage generator 300 in the OLED display device 100 .

[0148] Reference Fig.12 , the voltage generator 300 may include a charge pump 310 and a plurality of low dropout (LDO) regulators 320a, 320b, 320c, and 320d.

[0149] The charge pump 310 may generate a negative voltage NVG based on the first driving voltage VDDR, the second driving voltage NAVDD, and the switching control signal SCS provided to the charge pump 310 .

[0150] The LDO regulator 320a may generate a first operating voltage VDD based on the first driving voltage VDDR. Each of the LDO regulators 320b, 320c, and 320d may generate a corresponding one of a first initialization voltage VINT, a second initialization voltage AVINT, and a second operating voltage VGL based on a negative voltage NVG.

[0151] The switch control signal SCS may be included in Figure 1 The power control signal PCTL in the timing controller 130 may be provided, or the timing controller 130 may provide the switching control signal SCS to the voltage generator 300.

[0152] Fig.13 is a diagram showing a method according to an example embodiment Figure 1 1 is a schematic block diagram of an example of a timing controller 130 in an OLED display device 100 .

[0153] Reference Fig.13 , the timing controller 130 may include a data analyzer 132 , a data arrangement unit 133 , and a signal generator 134 .

[0154] The data analyzer 132 may generate an arrangement control signal ARC and a scan control sequence signal SCC based on the input image data RGB. The data analyzer 132 may provide the arrangement control signal ARC to the data arrangement unit 133 and provide the scan control signal SCC to the signal generator 134.

[0155] The data analyzer 132 may analyze the grayscale level of the input image data RGB of each data line to generate an arrangement control signal ARC. The data arrangement unit 133 may rearrange the input image data RGB provided as input to the data arrangement unit 133 according to the arrangement control signal ARC to output a data signal DTA.

[0156] The signal generator 134 may generate a control signal for controlling the data driver circuit 150 ( Figure 1 ) of the first driving control signal DCTL1, controls the scanning driver circuit 200 ( Figure 1 ) and controls the emission driver circuit 260 ( Figure 1 )’s third driving control signal DCTL3.

[0157] The signal generator 134 may generate a power control signal PCTL for controlling the voltage generator 300 in response to the control signal CTL. The second driving control signal DCTL2 may include a start signal FLM (frame line mark) related to a scan mode, a plurality of initialization signals INT, and a plurality of output enable signals OE and a mode signal MS. The third driving control signal DCTL3 may include a start signal FLM, a clock signal CLK, and a mode signal MS.

[0158] Fig.14 is a diagram showing a method according to an example embodiment Figure 1 1 is a schematic block diagram of an example of a scan driver circuit 200 in an OLED display device 100.

[0159] Reference Fig.14 , the scan driver circuit 200 may include a first sub-scan driver 210 and a second sub-scan driver 230 .

[0160] The first sub-scan driver 210 can receive the initialization signal INT, the start signal FLM, the first sub-drive voltage VGH, the second sub-drive voltage VGL, the negative voltage NVG, the output enable signal OE and the mode signal MS, and can generate the first scan signal GI, the second scan signal GW and the third scan signal GC based on the initialization signal INT, the start signal FLM, the first sub-drive voltage VGH, the second sub-drive voltage VGL, the negative voltage NVG, the output enable signal OE and the mode signal MS, and can determine the scan on time of each of the first scan signal GI, the second scan signal GW and the third scan signal GC generated by the first sub-scan driver 210.

[0161] The second sub-scan driver 230 can receive the initialization signal INT, the start signal FLM, the first sub-drive voltage VGH, the second sub-drive voltage VGL, the negative voltage NVG, the output enable signal OE and the mode signal MS, and can generate the fourth scan signal GB based on the initialization signal INT, the start signal FLM, the first sub-drive voltage VGH, the second sub-drive voltage VGL, the negative voltage NVG, the output enable signal OE and the mode signal MS, and can determine the scan on time of the fourth scan signal GB.

[0162] Fig.15 is a diagram showing a method for performing Figure 1 The emission driver circuit 260 shown is a combination of Fig.14 Schematic block diagram of a scan driver circuit 200 .

[0163] exist Fig.15 In the Figure 1 Some of the plurality of stages in the first and second sub-scan drivers 210 and 230 and some of the plurality of stages in the emission driver circuit 260 are shown.

[0164] Reference Fig.15 , the first sub-scan driver 210 may include stages STG1_k, STG1_k+1, and STG1_k+2, the second sub-scan driver 230 may include stages STG2_k, STG2_k+1, and STG2_k+2, and the emission driver circuit 260 may include stages STG3_k, STG3_k+1, and STG3_k+2. Here, k is a natural number and may be one of 1 to n.

[0165] Each of the stages STG2_k, STG2_k+1, and STG2_k+2 in the second sub-scan driver 230 may generate Figure 1The fourth scanning signals GB(k), GB(k+1), and GB(k+2) associated with the corresponding pixel row of the pixel 111 in the emission driver circuit 260 may each generate a corresponding one of the fourth scanning signals GB(k), GB(k+1), and GB(k+2) associated with the corresponding pixel row of the pixel 111 in the emission driver circuit 260, and each of the stages STG3_k, STG3_k+1, and STG3_k+2 in the emission driver circuit 260 may generate a corresponding one of the fourth scanning signals GB(k), GB(k+1), and GB(k+2) associated with the corresponding pixel row of the pixel 111 in the emission driver circuit 260. Figure 1 A corresponding one of the emission control signals EC(k), EC(k+1) and EC(k+2) associated with the corresponding pixel row of pixels 111 in FIG.

[0166] The stage STG1_k in the first sub-scan driver 210 may generate a first scan signal GI(k+1) associated with the (k+1)th pixel row, a second scan signal GW(k) associated with the kth pixel row, and a third scan signal GC(k) associated with the kth pixel row.

[0167] The stage STG1_k+1 in the first sub-scanning driver 210 may generate a first scan signal GI(k+2) associated with the (k+2)th pixel row, a second scan signal GW(k+1) associated with the (k+1)th pixel row, and a third scan signal GC(k+1) associated with the (k+1)th pixel row. The stage STG1_k+2 in the first sub-scanning driver 210 may generate a first scan signal GI(k+3) associated with the (k+3)th pixel row, a second scan signal GW(k+2) associated with the (k+2)th pixel row, and a third scan signal GC(k+2) associated with the (k+2)th pixel row.

[0168] That is, the first sub-scan driver 210 may be manufactured by merging circuits related to the second scan signal GW and the third scan signal GC, or may be manufactured by merging circuits related to the first scan signal GI, the second scan signal GW, and the third scan signal GC. Therefore, the area occupied by the first sub-scan driver 210 may be reduced.

[0169] exist Fig.15 In FIG, blocks R, G, and B represent pixels displaying the corresponding colors red, green, and blue, respectively.

[0170] Fig.16 is a diagram showing a method according to an example embodiment Figure 1 1 is a schematic block diagram of an emission driver circuit 260 shown in the OLED display device 100 .

[0171] Reference Fig.16 , the emission driver circuit 260 may include a plurality of stages STG1 to STGn connected to each other successively (ie, such that an output of one stage is connected to an input of a next subsequent stage in a series configuration) to sequentially output emission control signals EC1 to ECn.

[0172] The stages STG1 to STGn are connected to the emission control lines EL1 to ELn (see Figure 1 ), and sequentially output emission control signals EC1 to ECn. The emission control signals EC1 to ECn may overlap with each other during a predetermined period.

[0173] Each of the stages STG1 to STGn receives a second operating voltage VGL and a first operating voltage VDD having a voltage level higher than that of the second operating voltage VGL. In addition, each of the stages STG1 to STGn receives a first clock signal CLK1 and a second clock signal CLK2, and one or more of the stages STG1 to STGn (e.g., the first stage STG1) receives a mode signal MS. The mode signal MS may determine the number of horizontal periods included in the non-light emitting interval. That is, the mode signal MS may determine the time interval of the non-emission interval.

[0174] Hereinafter, the emission control signals EC1 to ECn output through the emission control lines EL1 to ELn are referred to as first to nth emission control signals.

[0175] Among the stages STG1 to STGn, the first stage STG1 is driven in response to the start signal FLM. In detail, the first stage STG1 receives the first driving voltage VDD and the second driving voltage VGL, and generates the first emission control signal EC1 in response to the start signal FLM, the first clock signal CLK1, the second clock signal CLK2, and the mode signal MS. The first emission control signal EC1 is applied to the pixels in the pixel row through the first emission control line EL1.

[0176] The stages STG1 to STGn are connected to each other in succession and are sequentially driven. In detail, the current stage is connected to the output electrode of the previous stage and receives the emission control signal output from the previous stage. The current stage is driven in response to the emission control signal provided from the previous stage.

[0177] For example, the second stage STG2 may receive the first emission control signal EC1 output from the first stage STG1, and be driven in response to the first emission control signal EC1. The second stage STG2 receives the first drive voltage VDD and the second drive voltage VGL, and generates the second emission control signal EC2 in response to the first emission control signal EC1, the first clock signal CLK1 and the second clock signal CLK2. The second emission control signal EC2 is applied to the pixels in the pixel row through the second emission control line EL2. The other stages STG3 to STGn are driven in the same manner as the second stage STG2, so the details thereof are not repeated.

[0178] Fig.17 is a schematic block diagram illustrating an example of a display system according to example embodiments.

[0179] Reference Fig.17 , the display system 800 may include an application processor (AP) 810 , an OLED display device 820 , and a PMIC 860 .

[0180] The OLED display device 820 may include a driving circuit 830 , a display panel (OLED display) 840 , and a voltage generator 850 .

[0181] The voltage generator 850 may provide the initialization voltage VS to the display panel 840 in response to the power control signal PCTL from the driving circuit 830. The voltage generator 850 may generate the first driving voltage VDD, the second driving voltage VGL, and the negative voltage NVG based on the first driving voltage VDDR and the second driving voltage NAVDD, and may provide the first operating voltage VDD, the second operating voltage VGL, and the negative voltage NVG to the scan driver circuit of the driving circuit 830. The voltage generator 850 may include a plurality of LDO regulators (e.g., see FIG. 1 ) that respectively generate the first operating voltage VDD, the second operating voltage VGL, and the negative voltage NVG. Fig.12 ).

[0182] Scan driver circuit (eg, Figure 1 200) may generate a scan signal to be provided to the display panel 840 based on the first operating voltage VDD, the second operating voltage VGL, and the negative voltage NVG.

[0183] The driving circuit 830 and the voltage generator 850 may be incorporated into one integrated circuit (IC).

[0184] The PMIC 860 may generate a high power voltage ELVDD and a low power voltage ELVSS based on the battery voltage VBAT, and may provide the high power voltage ELVDD and the low power voltage ELVSS to the display panel 840. In addition, the PMIC 860 may generate a first driving voltage VDDR and a second driving voltage NAVDD based on the battery voltage VBAT, and may provide the first driving voltage VDDR and the second driving voltage NAVDD to the voltage generator 850.

[0185] The PMIC 860 may receive the inverted reset signal RSTB and the enable signal EN, and may provide a second inverted reset signal and a second enable signal to a control logic located within the PMIC 860 by buffering the inverted reset signal RSTB and the enable signal EN. The PMIC 860 may include an input buffer circuit that generates the second inverted reset signal and the second enable signal by Schmitt triggering the inverted reset signal RSTB and the enable signal EN based on a second power supply voltage that is independent of changes in the battery voltage VBAT. The input buffer circuit may adopt Figure 7 Input buffer circuit 420.

[0186] The OLED display system 800 may be a portable device such as, but not limited to, a laptop computer, a cellular phone, a smart phone, a personal computer (PC), a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a car navigation system, etc.

[0187] The application processor 810 provides the image signal RGB, the control signal CTL, and the main clock signal MCLK to the OLED display device 820 , and the driving circuit 830 provides the data DTA to the display panel 840 .

[0188] Fig.18 is a block diagram illustrating an electronic device including an OLED display device according to example embodiments.

[0189] Reference Fig.18 , the electronic device 900 includes a processor 910, a memory device 920, a storage device 930, an input / output (I / O) device 940, a PMIC 950, and an OLED display device 960. The processor 910, the memory device 920, the storage device 930, the input / output (I / O) device 940, the PMIC 950, and the OLED display device 960 may be interconnected via a communication bus or other connection arrangement. The electronic device 900 may also include a plurality of ports (not explicitly shown) for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic systems, and the like.

[0190] The processor 910 may perform various computing functions or tasks. The processor 910 may be, for example, a microprocessor, a central processing unit (CPU), etc. The processor 910 may be connected to other components via an address bus, a control bus, a data bus, etc. In addition, the processor 910 may be coupled to an expansion bus, such as a peripheral component interconnect (PCI) bus.

[0191] The memory device 920 may store data used for the operation of the electronic device 900. For example, the memory device 920 may include at least one nonvolatile memory device (such as a flash memory device) and / or at least one volatile memory device (such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.).

[0192] The storage device 930 may be, for example, a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 940 may be, for example, an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and / or an output device such as a printer, a speaker, etc. The power supply 950 may provide power for the operation of the electronic device 900. The organic light emitting display device 960 may communicate with other components via a bus or other communication links.

[0193] The OLED display device 960 may be used Figure 1 The mobile device 50 is shown. Therefore, the OLED display device 960 may include a driving circuit and a display panel, and the driving circuit may include a data driver circuit, a scan driver circuit, a voltage generator, and a PMIC.

[0194] The PMIC 950 may include an input buffer circuit. The input buffer circuit may receive an inverted reset signal and an enable signal from an external host, and provide a second inverted reset signal and a second enable signal to a control logic located inside the PMIC by buffering the inverted reset signal and the enable signal. The input buffer circuit may generate the second inverted reset signal and the second enable signal by Schmitt triggering the inverted reset signal and the enable signal based on a second power supply voltage that is independent of the variation of the battery voltage. The input buffer circuit may use Figure 7 Input buffer circuit 420.

[0195] The electronic device 900 may be a mobile electronic device including an OLED display device 960 , such as a smart phone.

[0196] Fig.19 is a block diagram illustrating an example of an electronic device according to an example embodiment.

[0197] Reference Fig.19 , the electronic device 1000 may include various electronic circuits. For example, the electronic circuits of the electronic device 1000 may include an image processing block 1100, a communication block 1200, an audio processing block 1300, a buffer memory 1400, a non-volatile memory 1500, a user interface 1600, a main processor 1800, a power management device 1900, and a charger circuit 1910.

[0198] The electronic device 1000 may be implemented with any computing device or any mobile / portable device, such as a mobile phone, a smart phone, a tablet computer, a laptop computer, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a portable multimedia player (PMP), a digital camera, a portable game console, a music player, a camera, a video player, a navigation device, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, an e-book, a virtual reality (VR) device, an augmented reality (AR) device, a robotic device, etc.

[0199] For example, the electronic device 1000 may be connected to the battery 1920, and the battery 1920 may supply power applied to the operation of the electronic device 1000. However, the present disclosure is not limited to this example. For example, the power supplied to the electronic device 1000 may be provided from a power source other than the battery 1920.

[0200] The image processing block 1100 may receive light through the lens 1110. The image sensor 1120 and the image signal processor 1130 included in the image processing block 1100 may generate image information related to an external object based on the light received from the lens 1110.

[0201] The communication block 1200 may exchange signals (i.e., transmit and / or receive signals) with an external device / system via an antenna 1210. The transceiver 1220 and the modem (modulator / demodulator) 1230 of the communication block 1200 may process signals exchanged with the external device / system according to one or more of various wired / wireless communication protocols.

[0202] The audio processing block 1300 may process sound information by using the audio signal processor 1310. The audio processing block 1300 may receive an audio input through a microphone 1320, or may output audio through a speaker 1330.

[0203] The buffer memory 1400 may store data used for the operation of the electronic device 1000. For example, the buffer memory 1400 may temporarily store data processed or to be processed by the main processor 1800. For example, the buffer memory 1400 may include a volatile memory such as a static random access memory (SRAM), a dynamic RAM (DRAM), or a synchronous DRAM (SDRAM) and / or a nonvolatile memory such as a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (ReRAM), or a ferroelectric RAM (FRAM).

[0204] The nonvolatile memory 1500 may store data regardless of whether power is supplied. For example, the nonvolatile memory 1500 may include at least one of various nonvolatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM. For example, the nonvolatile memory 1500 may include a removable memory such as a secure digital (SD) card or a solid state drive (SSD), and / or an embedded memory such as an embedded multimedia card (eMMC).

[0205] The user interface 1600 may enable communication between the user and the electronic device 1000. For example, the user interface 1600 may include an input interface for receiving an input from the user and an output interface for providing information to the user.

[0206] The main processor 1800 may control the overall operation of the components of the electronic device 1000. The main processor 1800 may perform various operations in order to operate the electronic device 1000. For example, the main processor 1800 may be implemented with an operation processing device / circuit including one or more processor cores such as a general-purpose processor, a dedicated processor, an application processor, or a microprocessor.

[0207] The power management device 1900 and the charger circuit 1910 may provide power for operating the electronic device 1000. For example, the power management device 1900 may be implemented with a plurality of PMICs 1900a, 1900b, ..., 1900h. This will be referred to as Fig. 20 Here, h may be a natural number greater than 2. The charger circuit 1910 may be configured to supply power to the battery for charging the battery 1920 ; a charging curve of the charger circuit 1910 may vary according to the characteristics of the battery 1920 .

[0208] Fig. 20 FIG. 1 shows a method for performing a Fig.19 The components in the electronic device 1000 send power-related configurations.

[0209] The power management device 1900 may supply power to the components 1100 to 1800 of the electronic device 1000 through the corresponding voltage rail (i.e., the power rail). For example, the charger circuit 1910 may charge the battery 1920 based on the power signal PWR received from outside the electronic device 1000, and the battery 1920 may provide the battery voltage VBAT to the power management device 1900 based on the charging voltage. The power management device 1900 may output power to be supplied to the components 1100 to 1600 and 1800 of the electronic device 1000 based on the battery voltage VBAT. The power management device 1900 may supply power obtained by appropriately converting the battery voltage VBAT to the components 1100 to 1600 and 1800 of the electronic device 1000. The components 1100 to 1800 may be referred to as a load system 1005.

[0210] In an example embodiment, the power management device 1900 may include a plurality of PMICs 1900a, 1900b, . . . , 1900h, each of which may supply power to at least one component of the electronic device 1000. For example, a voltage output from each PMIC may be transmitted to at least one of the image processing block 1100, the communication block 1200, the audio processing block 1300, the buffer memory 1400, the nonvolatile memory 1500, the user interface 1600 (e.g., an input / output interface such as a display device 1610 and a touch processing integrated circuit (IC) 1690), and the main processor 1800. Each component of the electronic device 1000 may operate based on the transmitted voltage.

[0211] The voltages generated from the plurality of PMICs 1900a, 1900b, ..., 1900h may be transmitted to the components 1100 to 1800 of the electronic device 1000 in a predetermined order or may be blocked in a predetermined order. To this end, the plurality of PMICs 1900a, 1900b, ..., 1900h may be synchronized with each other during a power-on sequence and a power-off sequence.

[0212] Before executing the power-on sequence, the main PMIC (one of PMIC 1900a, 1900b, ..., 1900h) may enable a first function related to a first initial operation based on the battery voltage VBAT during a standby period before generating a first output voltage based on the battery voltage VBAT, and may apply a sub-enable signal to at least one sub-PMIC (at least one sub-PMIC may correspond to PMIC 1900a, 1900b, ..., 1900h other than the main PMIC) through a first pin based on a power-on signal received from outside the electronic device 1000 after the first initial operation is completed. Each of the sub-PMICs may receive the sub-enable signal through a second pin, and may enable a second function related to a second initial operation based on the battery voltage in response to activation of the sub-enable signal. Therefore, the power management device 1900 may reduce the standby current consumed during the standby period.

[0213] Before executing the power-on sequence, the main PMIC deactivates the sub-enable signal in response to the deactivation of the power-on signal, and applies the deactivated sub-enable signal to the sub-PMIC through the first pin. Each of the sub-PMICs receives the deactivated sub-enable signal through the second pin and disables the second function. The main PMIC applies the activated sub-enable signal to the sub-PMIC, deactivates the first function after a predetermined time has passed since the activated sub-enable signal was applied to the sub-PMIC, and enters a power-off state.

[0214] According to an example embodiment, each of the plurality of PMICs 1900a, 1900b, ..., 1900h may include an input buffer circuit. The input buffer circuit may receive an inverted reset signal and an enable signal from an external host, and may provide a second inverted reset signal and a second enable signal to a control logic therein by buffering the inverted reset signal and the enable signal. The input buffer circuit may generate a second inverted reset signal and a second enable signal by Schmitt triggering the inverted reset signal and the enable signal based on a second power supply voltage that is independent of a change in a battery voltage VBAT.

[0215] The present disclosure can be applied to PMIC, SoC, and various devices and systems including PMIC and SoC, such as mobile phones, smart phones, PDAs, PMPs, digital cameras, digital televisions, set-top boxes, music players, portable game consoles, navigation devices, PCs, server computers, workstations, tablet computers, laptop computers, smart cards, printers, wearable devices, IoT devices, IoE devices, e-books, VR devices, AR devices, robotic devices, etc.

[0216] While the present disclosure has been particularly shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. An input buffer circuit, comprising: a low voltage generator connected to a first power supply voltage having a first voltage level, the low voltage generator being configured to generate a mirror current based on the first power supply voltage and being configured to generate a second power supply voltage having a second voltage level less than the first voltage level, the second power supply voltage being independent of changes in the first power supply voltage; a first hysteresis buffer configured to operate based on the second power supply voltage and configured to generate a first inverted reset signal with hysteresis based on the inverted reset signal; as well as A first dual power supply level shifter is configured to operate based on the first power supply voltage and the second power supply voltage and is configured to generate a second inverted reset signal by shifting a logic high level of the first inverted reset signal from the second voltage level to the first voltage level.

2. The input buffer circuit as claimed in claim 1, wherein: The low voltage generator comprises: a current source configured to generate a first current; a current mirror circuit connected to the first power supply voltage and the current source, configured to generate a mirror current by replicating the first current, and configured to provide the mirror current to a first node; a plurality of n-channel metal oxide semiconductor transistors coupled in series between the first node and a ground voltage, each of the plurality of n-channel metal oxide semiconductor transistors being diode-connected; and A power transistor has a drain coupled to the first power voltage, a gate coupled to the first node, and a source providing the second power voltage.

3. The input buffer circuit as claimed in claim 2, wherein: The plurality of n-channel metal oxide semiconductor transistors provide a target voltage to the gate of the power supply transistor at the first node, the target voltage corresponding to the sum of the threshold voltages of each of the plurality of n-channel metal oxide semiconductor transistors, and The power transistor is configured to adjust a level of the second power voltage based on the target voltage.

4. The input buffer circuit as claimed in claim 3, wherein: The power transistor corresponds to a native n-channel metal oxide semiconductor transistor having a zero threshold voltage, and The level of the second power supply voltage is equal to the level of the target voltage.

5. The input buffer circuit as claimed in claim 3, wherein: The power transistor corresponds to an n-channel metal oxide semiconductor transistor having a non-zero threshold voltage, and Here, the level of the second power supply voltage corresponds to a value obtained by subtracting a threshold voltage of the power supply transistor from a level of the target voltage.

6. The input buffer circuit as claimed in claim 3, wherein: A level of the target voltage is determined based on the number of the plurality of n-channel metal oxide semiconductor transistors in the low voltage generator.

7. The input buffer circuit as claimed in claim 3, wherein: A level of the target voltage is determined based on a size of each of the plurality of n-channel metal oxide semiconductor transistors in the low voltage generator.

8. The input buffer circuit as claimed in claim 2, wherein: The current mirror circuit comprises: a first p-channel metal oxide semiconductor transistor having a source coupled to the first power supply voltage, a gate coupled to the current source at a second node, and a drain coupled to the current source at the second node; and a second p-channel metal oxide semiconductor transistor having a source coupled to the first power supply voltage, a drain coupled to the first node, and a gate coupled to the second node, wherein the second p-channel metal oxide semiconductor transistor is configured to provide the mirror current to the first node.

9. The input buffer circuit of claim 1, wherein: The low voltage generator comprises: a current source configured to generate a first current; a current mirror circuit connected to the first power supply voltage and the current source, configured to generate the mirror current by replicating the first current, and configured to provide the mirror current to a first node; a plurality of diodes coupled between the first node and a ground voltage in a forward biased direction; and The power transistor has a drain coupled to the first power voltage, a gate coupled to the first node, and a source providing the second power voltage.

10. The input buffer circuit of claim 1, wherein: A level of a logic high voltage of the first hysteresis buffer and a level of a logic low voltage of the first hysteresis buffer are independent of the first power supply voltage.

11. The input buffer circuit of claim 1 , wherein: The first dual-supply level shifter comprises: an inverter coupled between the second power supply voltage and a ground voltage, the inverter being configured to output a first reset signal, the first reset signal being an inversion of the first inverted reset signal; and A shift circuit coupled between the first power supply voltage and the ground voltage, the shift circuit being configured to receive the first inverted reset signal and the first reset signal, and being configured to output the second inverted reset signal by shifting a logic high level of the first inverted reset signal from the second voltage level to the first voltage level.

12. The input buffer circuit of claim 11, wherein: The shift circuit comprises: a first p-channel metal oxide semiconductor transistor coupled between the first power supply voltage and the first node and having a gate coupled to a second node; a second p-channel metal oxide semiconductor transistor coupled between the first power supply voltage and the second node and having a gate coupled to the first node; a first n-channel metal oxide semiconductor transistor coupled between the first node and the ground voltage and having a gate receiving the first inverted reset signal; and a second n-channel metal oxide semiconductor transistor coupled between the second node and the ground voltage and having a gate receiving the first reset signal, and The shift circuit is configured to output the second inverted reset signal at the second node.

13. The input buffer circuit of claim 1 , further comprising: a second hysteresis buffer configured to operate based on the second power supply voltage and configured to generate a first enable signal with hysteresis based on an enable signal; as well as A second dual power supply level shifter is configured to operate based on the first power supply voltage and the second power supply voltage and is configured to generate a second enable signal by shifting a logic high level of the first enable signal from the second voltage level to the first voltage level.

14. The input buffer circuit of claim 13, wherein: A level of a logic high voltage of the second hysteresis buffer and a level of a logic low voltage of the second hysteresis buffer are independent of the first power supply voltage.

15. The input buffer circuit of claim 1, wherein: The first power supply voltage corresponds to a battery voltage.

16. A power management integrated circuit, comprising: an input buffer circuit configured to generate a second inverted reset signal and a second enable signal by buffering an inverted reset signal and an enable signal provided from an external host, the inverted reset signal and the enable signal corresponding to a general input / output signal; a voltage generator configured to be activated in response to a first internal enable signal and configured to generate a high power supply voltage to be provided to a display panel including a plurality of pixels based on a first power supply voltage corresponding to a battery voltage; a negative voltage generator configured to be activated in response to a second internal enable signal and configured to generate a low power supply voltage to be provided to the display panel based on the first power supply voltage; as well as a control logic configured to generate the first internal enable signal and the second internal enable signal based on the second inverted reset signal and the second enable signal, respectively, Wherein, the input buffer circuit comprises: a low voltage generator connected to the first power supply voltage having a first voltage level, the low voltage generator being configured to generate a mirror current based on the first power supply voltage and to generate a second power supply voltage having a second voltage level less than the first voltage level, the second power supply voltage being independent of changes in the first power supply voltage; a first hysteresis buffer configured to operate based on the second power supply voltage and configured to generate a first inverted reset signal with hysteresis based on the inverted reset signal; and A first dual power supply level shifter is configured to operate based on the first power supply voltage and the second power supply voltage and is configured to generate the second inverted reset signal by shifting a logic high level of the first inverted reset signal from the second voltage level to the first voltage level.

17. The power management integrated circuit of claim 16, wherein: The low voltage generator comprises: a current source configured to generate a first current; a current mirror circuit connected to the first power supply voltage and the current source, configured to generate the mirror current by replicating the first current, and configured to provide the mirror current to a first node; a plurality of n-channel metal oxide semiconductor transistors coupled in series between the first node and a ground voltage, each of the plurality of n-channel metal oxide semiconductor transistors being diode-connected; and a power supply transistor having a drain coupled to the first power supply voltage, a gate coupled to the first node, and a source providing the second power supply voltage, The level of the logic high voltage of the first hysteresis buffer and the level of the logic low voltage of the first hysteresis buffer are independent of the first power supply voltage.

18. The power management integrated circuit of claim 17, wherein: The low voltage generator is configured to provide a target voltage to the gate of the power transistor at the first node, the target voltage corresponding to the sum of threshold voltages of the plurality of n-channel metal oxide semiconductor transistors, and The power transistor is configured to adjust a level of the second power voltage based on the target voltage.

19. The power management integrated circuit of claim 16, wherein: The input buffer circuit further includes: a second hysteresis buffer configured to operate based on the second power supply voltage and configured to generate a first enable signal with hysteresis based on an enable signal corresponding to one of the universal input / output signals; and a second dual power supply level shifter configured to operate based on the first power supply voltage and the second power supply voltage and configured to generate a second enable signal by shifting a logic high level of the first enable signal from the second voltage level to the first voltage level, The level of the logic high voltage of the second hysteresis buffer and the level of the logic low voltage of the second hysteresis buffer are independent of the first power supply voltage.

20. An input buffer circuit comprising: a low voltage generator connected to a first power supply voltage having a first voltage level, the low voltage generator being configured to generate a mirror current based on the first power supply voltage and being configured to generate a second power supply voltage having a second voltage level less than the first voltage level, the second power supply voltage being independent of changes in the first power supply voltage; a hysteresis buffer configured to operate based on the second power supply voltage and configured to generate a first inverted reset signal with hysteresis based on an inverted reset signal provided to the hysteresis buffer; as well as a dual power supply level shifter configured to operate based on the first power supply voltage and the second power supply voltage and configured to generate a second inverted reset signal by shifting a logic high level of the first inverted reset signal from the second voltage level to the first voltage level, wherein the low voltage generator comprises a plurality of n-channel metal oxide semiconductor transistors and a power supply transistor, the plurality of n-channel metal oxide semiconductor transistors are coupled in series between a first node and a ground voltage, each of the plurality of n-channel metal oxide semiconductor transistors is diode-connected, and the power supply transistor is coupled between the first power supply voltage and the first node, Wherein, the low voltage generator is configured as: generating the mirror current by replicating the first current, and providing the mirror current to a first node; and The second power supply voltage is generated by providing a target voltage to a gate of the power supply transistor at the first node, the target voltage corresponding to a sum of threshold voltages of the plurality of n-channel metal oxide semiconductor transistors.

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