Host system, memory system, electronic device, operation method, and storage medium

Abstract

The embodiment of the invention provides a host system, a memory system, electronic equipment, an operation method and a storage medium. Wherein the host system includes: a host controller coupled to a memory system, the memory system including a memory device, the memory device including a plurality of regions, the plurality of regions including a first region; the host controller is configured to send a first instruction which indicates that the first area is set as a fixed area and obtains mapping information corresponding to the first area; the first area is determined according to the application program corresponding to the corresponding area.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to a host system, a memory system, an electronic device, an operation method, and a storage medium. Background Art

[0002] A memory device is a storage device used to store information in modern information technologies. As a typical non-volatile semiconductor memory, a NAND (Not-And) type memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, appropriate programming / erasing speed, and retention characteristics. Summary of the Invention

[0003] Based on this, embodiments of the present disclosure propose a host system, a memory system, an electronic device, an operation method, and a storage medium. Among them, a host system provided by an embodiment of the present disclosure includes: a host controller, the host controller is coupled to a memory system, the memory system includes a memory device, the memory device includes a plurality of regions, and the plurality of regions include a first region; the host controller is configured to: send a first instruction, the first instruction instructs to set the first region as a fixed region, and obtain mapping information corresponding to the first region; the first region is determined according to an application program corresponding to a corresponding region.

[0004] In one embodiment, the host controller is configured to: send a second instruction; the second instruction includes the mapping information; the second instruction instructs to read data of the first region according to the mapping information.

[0005] In one embodiment, the host controller is configured to: determine the first region from the plurality of regions according to attribute information of the application program.

[0006] In one embodiment, the host controller is configured to: before sending the first instruction, determine that the first region is a non-fixed region.

[0007] In one embodiment, the plurality of regions further include a second region, the first region and the second region correspond to the same application program; the first region is used to store data before the update of the same application program; the second region is used to store data after the update of the same application program; the host controller is configured to: after sending the first instruction, if the data of the same application program has been updated, send a third instruction, the third instruction instructs to set the first region as a non-fixed region, and set the second region as a fixed region.

[0008] In one embodiment, the host controller is configured to: send a fourth instruction before sending the first instruction, wherein the fourth instruction instructs to write data into the memory device.

[0009] In one implementation, the host system further includes: a host memory; the host memory is used to store the mapping information.

[0010] An embodiment of the present disclosure also provides a memory system coupled to a host system, comprising: a memory device, comprising a plurality of areas, wherein the plurality of areas include a first area; a memory controller, coupled to the memory device and configured to: receive a first instruction; in response to the first instruction, set the first area as a fixed area, and determine mapping information corresponding to the first area; the first area is determined according to an application corresponding to the corresponding area.

[0011] In one implementation, the memory controller is configured to: receive a second instruction; the second instruction includes the mapping information; and in response to the second instruction, read the data in the first area according to the mapping information.

[0012] In one embodiment, the multiple areas also include a second area, the first area and the second area correspond to the same application; the first area is used to store data of the same application before it is updated; the second area is used to store data of the same application after it is updated; the memory controller is configured to: after receiving the first instruction, if the data of the same application has been updated, receive a third instruction; in response to the third instruction, set the first area as a non-fixed area, and set the second area as a fixed area.

[0013] In one embodiment, the memory controller is configured to: receive a fourth instruction before receiving the first instruction; and write data into the memory device in response to the fourth instruction.

[0014] An embodiment of the present disclosure also provides an electronic device, comprising: a host system and a memory system coupled to the host system, wherein: the memory system comprises a memory device and a memory controller coupled to the memory device; the memory device comprises a plurality of areas; the plurality of areas comprises a first area; the host system is configured to: send a first instruction; the memory controller is configured to: receive the first instruction; in response to the first instruction, set the first area as a fixed area, and determine mapping information corresponding to the first area; the first area is determined according to an application corresponding to the corresponding area.

[0015] In one embodiment, the host system is configured to: send a second instruction, the second instruction including the mapping information; the memory controller is configured to: receive the second instruction; and in response to the second instruction, read the data of the first area according to the mapping information.

[0016] In one embodiment, the host system is configured to: after sending the first instruction, if the data of the application corresponding to the first area has been updated, send a third instruction; the memory controller is configured to: after receiving the first instruction, if the data of the application corresponding to the first area has been updated, receive the third instruction; and in response to the third instruction, set the first area as a non-fixed area, and set the second area as a fixed area; wherein the multiple areas also include the second area, the first area and the second area correspond to the same application; the first area is used to store the data of the same application before the update; the second area is used to store the data of the same application after the update.

[0017] In one embodiment, the host system is configured to: send a fourth instruction before sending the first instruction; the memory controller is configured to: receive the fourth instruction before receiving the first instruction; and write data to the memory device in response to the fourth instruction.

[0018] An embodiment of the present disclosure also provides an operating method of an electronic device, wherein a host system of the electronic device sends a first instruction; a memory system of the electronic device receives the first instruction; and in response to the first instruction, a first area of ​​a memory device in the memory system is set as a fixed area, and mapping information corresponding to the first area is determined; the first area is determined according to an application corresponding to the corresponding area; wherein the host system is coupled to the memory system; the memory system includes the memory device and a memory controller coupled to the memory device; the memory device includes multiple areas; and the multiple areas include the first area.

[0019] In one implementation, the host system sends a second instruction; the second instruction includes the mapping information; the memory controller receives the second instruction; and in response to the second instruction, reads data in the first area according to the mapping information.

[0020] In one embodiment, the operating method also includes: after sending the first instruction, if the data of the application corresponding to the first area has been updated, the host system sends a third instruction; the memory controller receives the third instruction; in response to the third instruction, the first area is set as a non-fixed area, and the second area is set as a fixed area; wherein the multiple areas also include the second area, the first area and the second area correspond to the same application; the first area is used to store the data of the same application before the update; the second area is used to store the data of the same application after the update.

[0021] In one embodiment, the method further includes: the host system sends a fourth instruction before sending the first instruction; the memory controller receives the fourth instruction before receiving the first instruction; and writing data into the memory device in response to the fourth instruction.

[0022] The embodiments of the present disclosure further provide a storage medium having executable instructions stored thereon. When the executable instructions are executed by an electronic device, the steps of the method described in the above embodiments of the present disclosure can be implemented.

[0023] In the embodiments of the present disclosure, a host system, a memory system, an electronic device, an operation method, and a storage medium are proposed. The host system includes: a host controller, the host controller is coupled to the memory system, the memory system includes a memory device, the memory device includes multiple areas, and the multiple areas include a first area; the host controller is configured to: send a first instruction, the first instruction indicates that the first area is set as a fixed area, and obtains mapping information corresponding to the first area; the first area is determined according to the application corresponding to the corresponding area. In the embodiments of the present disclosure, multiple areas of the memory system store data corresponding to different applications respectively, so that when the host system subjectively wants to obtain the mapping information of the application corresponding to the first area, it can send a first instruction to the memory device, set the first area as a fixed area, and obtain the mapping information of the application corresponding to the first area. Relatively speaking, compared with when the host system subjectively wants to obtain the mapping information of the application corresponding to the first area, the memory device blindly recommends the mapping information of the application corresponding to multiple areas to the host controller; the embodiments of the present disclosure can obtain the mapping information of the first area more accurately and more timely, improve the reading accuracy, reduce the reading time, and thus improve the reading performance of the host system and the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0025] Figure 2a A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0026] Figure 2b A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present disclosure;

[0027] Figure 3a A schematic diagram of the distribution of storage cells of a three-dimensional NAND memory according to an embodiment of the present disclosure;

[0028] Figure 3b A schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present disclosure;

[0029] Figure 4 A cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present disclosure;

[0031] Figure 6 A schematic diagram of the structure of an electronic device provided in one embodiment of the present disclosure;

[0032] Figure 7 A flowchart of all interactions involved in a process of performing a common read operation and an HPB read operation between a host system and a memory system provided by an embodiment of the present disclosure;

[0033] Figure 8 A schematic diagram of implementation flow corresponding to different read operations provided in an embodiment of the present disclosure;

[0034] Fig. 9 A schematic diagram of the structure of another electronic device provided by an embodiment of the present disclosure;

[0035] Fig.10 A schematic diagram of a correspondence between an application and a corresponding area provided in an embodiment of the present disclosure;

[0036] Fig.11 A schematic diagram of a process for reading first application data provided by an embodiment of the present disclosure;

[0037] Fig.12 A schematic diagram of a flow chart of an operating method of an electronic device provided by an embodiment of the present disclosure;

[0038] Fig.13 A schematic diagram of an interaction flow of an electronic device provided by an embodiment of the present disclosure.

[0039] In the above drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation. DETAILED DESCRIPTION

[0040] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] In the following description, a large number of specific details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0042] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0043] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0044] Spatially relative terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used here for convenience of description to describe the relationship between an element or feature shown in the figure and other elements or features. It should be understood that in addition to the orientation shown in the figure, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is turned over, then the elements or features described as "under other elements" or "under it" or "under it" will be oriented as "on" other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0045] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0046] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present disclosure, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure.

[0047] The memory device in the embodiments of the present disclosure includes but is not limited to a three-dimensional NAND memory. For ease of understanding, a three-dimensional NAND memory is taken as an example for description.

[0048] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of the present disclosure is shown. The system 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein. Figure 1As shown in , the system 100 may include a host system 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host system 108 may be a processor (e.g., a central processing unit (CPU)) or a system on a chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host system 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0049] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host system 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host system 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment solid state drive (SSD) or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0050] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host system 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0051] The memory controller 106 and the one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products. Figure 2a In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 The memory card connector 204 is coupled to the host system 108 in FIG. Figure 2b In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1 In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0052] Figure 3a A schematic diagram of the structure of a storage cell array of a three-dimensional NAND memory is given as an example. Figure 3a As shown, the memory cell array of the three-dimensional NAND memory is composed of several parallel and staggered rows of memory cell rows parallel to the gate isolation structure, every two rows of memory cell rows are separated by the gate isolation structure and the upper selection gate isolation structure, and each memory cell row includes a plurality of memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure, the first gate isolation structure divides the memory cell array into a plurality of memory blocks (Blocks), the plurality of second gate isolation structures may divide the memory blocks into a plurality of finger storage areas (Fingers), and the upper selection gate isolation structure disposed in the middle of each finger storage area may divide the finger storage area into two parts, thereby dividing the finger storage area into two memory slices. Figure 3a A storage block shown in FIG. 1 includes 6 storage slices. In actual applications, the number of storage slices in a storage block is not limited thereto.

[0053] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each individually controlled word line constitute a page. For example, Figure 3a All memory cells in each memory slice are coupled to form a page.

[0054] It should be noted that Figure 3a The number of memory cell rows between the gate isolation structure and the upper selection gate isolation structure given in the disclosure is only an exemplary demonstration and is not used to limit the number of memory cell rows contained in a finger storage area of ​​the three-dimensional NAND memory in the present disclosure. In actual applications, the number of memory cell rows contained in a finger storage area can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0055] Figure 3b 1 is a schematic circuit diagram of an exemplary memory device 300 including peripheral circuits according to some aspects of the present disclosure. The memory device 300 may be Figure 1 300 is an example of a memory device 104 in FIG. The memory device 300 may include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 is taken as an example of a three-dimensional NAND-type memory cell array, wherein the memory cell 306 is a NAND-type memory cell, and the memory cell 306 is provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons captured in the region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0056] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and can therefore store one bit of data. For example, the first storage state "0" may correspond to a first voltage range, and the second storage state "1" may correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-bit memory cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a two-bit memory cell, Double-Level Cell), three bits per cell (also referred to as a three-bit memory cell (TLC, Trinary-Level Cell)), four bits per cell (also referred to as a four-bit memory cell (QLC, Quad-Level Cell)), five bits per cell (also referred to as a five-bit memory cell (PLC, Penta-level cell)), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0057] like Figure 3bAs shown in , each memory string 308 may include a lower selection transistor (also referred to as a source side selection transistor, which includes a source selection gate BSG310) at its source terminal and an upper selection transistor (also referred to as a drain side selection transistor, which includes a drain selection gate TSG312) at its drain terminal. The source selection gate BSG310 and the drain selection gate TSG312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each storage string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having TSG312) or a deselection voltage (e.g., 0 V) ​​to a corresponding TSG312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of a transistor having BSG310) or a deselection voltage (e.g., 0 V) ​​to a corresponding BSG310 via one or more BSG lines 315.

[0058] like Figure 3b As shown in , the memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by the read and program operations. In some embodiments, in combination with the previous Figure 3a, multiple memory cells are isolated by an upper selection gate isolation structure and a gate isolation structure, and multiple memory cells between the upper selection gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, and each memory cell row is parallel to the gate isolation structure and the upper selection gate isolation structure.

[0059] refer to Figure 3a , Figure 3b , each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318, and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding selection transistor (such as the above selection transistor).

[0060] Figure 4 FIG. 3 is a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 using NAND as an example according to some aspects of the present disclosure. Figure 4 As shown, the NAND memory cell array 301 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a channel structure that vertically penetrates the gate layers 411 and the insulating layers 412, wherein the channel structure is coupled with each gate layer to form a memory cell, and the channel structure is coupled with a plurality of gate layers in the stacked structure 410 to form a memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412.

[0061] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0062] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0063] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0064] Return to reference Figure 3b , the peripheral circuit 302 may be coupled to the memory cell array 301 through the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying a voltage signal and / or a current signal to each target memory cell 306 and sensing a voltage signal and / or a current signal from each target memory cell 306 via the bit line 316, the word line 318, the source line 314, the BSG line 315, and the TSG line 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuits are shown, and the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0065] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store the program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306, and amplify the small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512, and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0066] The row decoder / word line driver 508 may be configured to be controlled by the control logic 512 and select / deselect the memory block 304 of the memory cell array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the (one or more) selected word lines 318. The voltage generator 510 may be configured to be controlled by the control logic 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory cell array 301.

[0067] The control logic 512 may be coupled to each of the other parts in the peripheral circuits described above, and is configured to control the operation of each of the other parts in the peripheral circuits. The register 514 may be coupled to the control logic 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic 512, and act as a control buffer to buffer control commands received from a host system (not shown) and relay them to the control logic 512, and to buffer status information received from the control logic 512 and relay them to the host system. The interface 516 may also be coupled to the column decoder / bit line driver 506 via the data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0068] For a NAND memory, the host system may include a host controller and a host memory. At least a portion of the entire storage area of ​​the host memory may include a HPB cache area for a host performance booster (hereinafter referred to as HPB, Host Performance Booster) function, and the HPB function may refer to a function of caching at least a portion of mapping information of a memory device in the host memory and using at least a portion of the mapping information. Figure 6 , Figure 7 , Figure 8 , a detailed description of the HPB function is given.

[0069] refer to Figure 6 , Figure 6 A schematic diagram of the structure of an electronic device is shown. Figure 6As shown, the electronic device 600 includes a host system 601 and a memory system 602; the memory system 602 is connected to the host system 601, and the host system 601 can be an electronic device such as a personal computer, a mobile terminal, etc. Among them, the host system 601 can include a host controller 603 and a host memory 604 coupled to the host controller, and the host controller 603 can be configured to send data to the memory system 602 or receive data from the memory system 602. The memory system 602 includes: a memory controller 605 and a memory device 606, the memory controller 605 is used to control the memory device 606 to perform operations such as reading, writing, and erasing, and the memory controller 605 and the memory device 606 can also be coupled in any suitable manner. The memory controller 605 can be used to control the memory system 602 as a whole. In some embodiments, the memory controller 605 may include a processor 607, a buffer 608, and a control unit 609; the processor 607 is, for example, a central processing unit (CPU), a microprocessor (MPU), etc. The memory device 606 may include multiple areas, each area includes multiple storage units, and each storage unit is used to store data.

[0070] In some embodiments, the multiple regions of the memory device can be divided into a pinned region and a non-pinned region; the mapping information corresponding to the pinned region is cached in the host memory, namely, the HPB entry (the mapping relationship between the logical address and the physical address of the storage unit in the pinned region). Based on the storage capacity of the host memory, the mapping information corresponding to the non-pinned region is stored in the memory device, namely, the L2P table of the non-pinned region. It should be noted that the pinned region is set when the logical unit number (LUN) of the memory device is configured and will not be changed. Therefore, when the LUN is configured, the memory system sends the HPB entry corresponding to the pinned region to the host system through its recommendation function, and the host system stores the HPB entry in the host memory. In some embodiments, the fixed region is generally used to store commonly used data and data corresponding to popular applications. When the host system wants to read the data corresponding to the fixed region, it can use the host controller to directly send a read command and an HPB entry to the memory system, and the memory system uses the received HPB entry to directly read the data in the fixed region and send the read data in the fixed region to the host system.

[0071] Combine the following Figure 7 , Figure 8 The normal read operation and the HPB read operation are described in detail.

[0072] refer to Figure 7 , Figure 7This is a flowchart of all interactions between a host system and a memory system during a normal read operation and an HPB read operation according to an embodiment of the present disclosure. Figure 7 , (1) is: the host system 601 sends a read instruction to the memory controller 605 (such as the processor 607) of the memory system 602 through the host controller interface, instructing to perform a read operation. The read operation can be a normal read operation or a HPB read operation.

[0073] Figure 7 In (2a), the processor 607 of the memory controller 605 retrieves and obtains the L2P table from the memory device 606, and stores the obtained L2P table in the cache 608 of the memory controller. The cache 608 may be a static random access memory (SRAM).

[0074] The L2P table is a mapping table of logical addresses and physical addresses of multiple regions in the memory device. The HPB entry is a mapping table of logical addresses and physical addresses of fixed regions in the memory device.

[0075] Figure 7 In (2b), the cache 608 sends the acquired L2P table to the processor 607.

[0076] Figure 7 In the example, (2c) is: retrieving and obtaining the HPB entry from the host memory 604.

[0077] Figure 7 In (3), the processor 607 obtains data in the storage unit corresponding to the L2P table from the memory device 606 according to the received L2P table based on the read instruction, and sends the obtained data to the host system 601 through the host controller interface.

[0078] refer to Figure 8 , Figure 8 The schematic diagram of the implementation flow corresponding to different read operations provided by the embodiment of the present disclosure is shown, wherein the common read operation can be divided into two types, such as the first read operation 801 and the second read operation 802. The HPB read operation is the third read operation 803. Figure 8 The tR shown in is the read delay.

[0079] refer to Figure 8, the interaction process and the order of the first read operation 801 are (1), (2a), (2b) and (3). Specifically, the host system 601 sends a read instruction to the processor 607 of the memory system 602; after receiving the read instruction, the processor 607 retrieves and obtains the L2P table from the memory device 606, and stores the obtained L2P table in the buffer 608 of the memory controller; then, the buffer 608 sends the L2P table to the processor 607. Next, the processor 607 obtains the data in the storage unit corresponding to the L2P table from the memory device 606 according to the received L2P table and the read instruction, and sends the obtained data to the host system 601 through the host controller interface.

[0080] refer to Figure 8 , the interaction process and the order of the second read operation 802 are (1), (2b) and (3). Specifically, the host system 601 sends a read instruction to the processor 607 of the memory system 602; when the L2P table corresponding to the read instruction is stored in the buffer 608, the processor 607 directly retrieves and obtains the L2P table from the buffer 608 after receiving the read instruction, and sends the obtained L2P table to the processor 607. Next, the processor 607 obtains the data in the storage unit corresponding to the L2P table from the memory device 606 according to the L2P table and the read instruction, and sends the obtained data to the host system 601 through the host controller interface.

[0081] refer to Figure 8 , the third read operation 803 includes the interaction process and its sequence as (2c), (1) and (3). Specifically, the host system 601 retrieves and obtains the HPB entry from the host memory 604; sends a read instruction and the HPB entry to the processor 607 of the memory system 602 through the host controller interface. After receiving the read instruction and the HPB entry, the processor 607 directly obtains the data in the storage unit corresponding to the HPB entry from the memory device 606 according to the HPB entry, and sends the obtained data to the host system 601 through the host controller interface.

[0082] It can be seen from the above three operation methods that when performing a normal read operation, after receiving the read instruction, the memory system needs to first obtain the L2P table that matches the read instruction, and then obtain the corresponding data according to the L2P table. When performing an HPB read operation, since the HPB entry has been stored in the host memory, the host system sends the HPB entry to the memory system at the same time as the read instruction. In other words, after receiving the read instruction and the HPB entry, the memory system can directly obtain the corresponding data according to the HPB entry; that is, the use of the HPB read operation can reduce the read operation process and improve the reading efficiency.

[0083] However, in the process of reading data using the HPB read operation, the area corresponding to the HPB entry is a fixed area, which is set when the LUN of the storage device is configured, and the fixed area usually stores data corresponding to popular applications (APP). In other words, the HPB entry recommended by the storage device to the host system based on the current fixed area is relatively blind, not flexible, and not accurate enough.

[0084] Based on this, a host system is provided in an embodiment of the present disclosure, wherein the host system is a part of an electronic device; Fig. 9 , Fig. 9 A schematic diagram of the composition structure of another electronic device provided in an embodiment of the present disclosure; the electronic device 900 includes: a host system 901 and a memory system 902 coupled to the host system, wherein: the host system 901 includes a host controller 903 and a host memory 904, the memory system 902 includes a memory device 906 and a memory controller 905 coupled to the memory device; the memory device 906 includes multiple areas 907; the multiple areas 907 are used to store data corresponding to all application programs. In the embodiment of the present disclosure, the multiple areas 907 include a first area 908.

[0085] In some embodiments, when the host system wants to obtain mapping information and data of the first area, the host controller is configured to: send a first instruction, the first instruction instructs to set the first area as a fixed area, and obtain mapping information corresponding to the first area.

[0086] In other words, the host system adds an instruction, such as a first instruction, which is used to instruct that the first area in the memory device is also set as a fixed area. After setting the first area as a fixed area, the memory device obtains mapping information of the first area, where the mapping information of the first area is the HPB entry corresponding to the first area. According to the instruction of the first instruction, the mapping information of the first area is recommended to the host system, and the host system stores the mapping information of the first area in the host memory. In this way, when the host wants to obtain data in the first area, the mapping information of the first area (i.e., the HPB entry corresponding to the first area) is directly sent to the memory device, and the memory device directly sends the data of the first area to the host system according to the mapping information of the first area (i.e., the HPB entry corresponding to the first area). In this way, the process of the read operation can be reduced, the read time can be saved, and the read performance can be improved.

[0087] In some embodiments, the host controller is configured to: determine the first area from the multiple areas according to the attribute information of the application. Here, the attribute information may include common use and uncommon use. That is, the host controller may indicate the division of the multiple areas according to whether the application corresponding to the data stored in the multiple areas of the memory device is common use or uncommon use. In other words, the host controller may indicate that a certain area of ​​the multiple areas of the memory device is set as the first area according to the usage of the application.

[0088] It should be noted that the application can be a native program or software module in the operating system; it can also be a native application, that is, a program that needs to be installed in the operating system to run, for example, WeChat APP; it can also be a small program that can be embedded in any APP, that is, a program that can be run only by downloading it to the browser environment. In short, the above-mentioned application can be any form of application, module or plug-in. It should be explained that the data corresponding to the application can include data interacted through the application; it can also include the data of the application itself. The data stored in the fixed area described in the embodiments of the present disclosure is data interacted through the application.

[0089] In some embodiments, the host controller is configured to: determine that the first area is a non-fixed area before sending the first instruction. It should be understood that when the first area has been set as a fixed area, when the host system wants to obtain data in the first area, it only needs to obtain the HPB entry corresponding to the first area in the host memory and send the HPB entry to the memory device, without sending the first instruction. Only when the first area is a non-fixed area can the host controller send the first instruction to the memory system, and the first instruction instructs to set the first area as a fixed area and obtain the mapping information of the first area.

[0090] In some embodiments, the host controller is further configured to: send a second instruction; the second instruction includes mapping information of the first area; and the second instruction instructs reading data of the first area according to the mapping information of the first area.

[0091] refer to Fig.10 , Fig.11 , Fig.10 A schematic diagram of the correspondence between an application and a corresponding area provided in an embodiment of the present disclosure; Fig.11A flow chart of reading first application data is provided for an embodiment of the present disclosure; wherein data of the first application APP1 is stored in RegionX~Y of the memory device, data of the second application APP2 is stored in RegionA~B of the memory device, data of the third application APP3 before update is stored in RegionC~D of the memory device, and data of the third application APP3 after update is stored in RegionE~R of the memory device.

[0092] Exemplarily, when the host system wants to obtain the interactive data of the first application APP1, the host system sends an instruction to the memory system through the host controller, instructing to set the RegionX~Y area corresponding to the first application APP1 as a fixed area. The memory system receives the instruction and adds the RegionX~Y area to the fixed area list according to the instruction, and identifies the RegionX~Y area to be activated; and activates the RegionX~Y area and sends the information of the activated RegionX~Y area to the host controller. The host controller sends an instruction again, instructing to obtain the mapping information of the RegionX~Y area, that is, the HPB entry corresponding to the RegionX~Y area; after receiving the instruction, the memory device reads the L2P table corresponding to all areas in the memory device, and sends the HPB entry corresponding to the RegionX~Y area to the host system. After receiving the HPB entry, the host system stores the HPB entry in the host memory (e.g., the HPB cache area).

[0093] Next, the host system sends a second instruction to the memory system, wherein the second instruction includes HPB entries corresponding to the RegionX-Y regions; the memory system sends the data of the RegionX-Y regions to the host controller according to the HPB entries corresponding to the RegionX-Y regions.

[0094] Similarly, when the host system wants to obtain the interactive data of the second application APP2, the host controller sends a first instruction to the memory system, instructing to set the RegionA~B area corresponding to the second application APP2 as a fixed area, and obtain the mapping information of the RegionA~B area. The host controller sends a second instruction to the memory system, the second instruction includes the mapping information of the RegionA~B area, and the second instruction instructs to read the data of the RegionA~B area. The memory system receives the second instruction, reads the data of the RegionA~B area according to the instruction of the second instruction, and sends the read data of the RegionA~B area to the host controller.

[0095] In some embodiments, referring back to Fig. 9, the plurality of regions 907 of the memory device further include a second region 909. The first region 908 and the second region 909 correspond to the same application; the first region 908 is used to store data of the same application before update; the second region is used to store data of the same application after update; the host controller is configured to: after sending the first instruction, if the data of the same application has been updated, send a third instruction, the third instruction instructing to set the first region as a non-fixed region, and to set the second region as a fixed region.

[0096] Exemplary, reference Fig.10 When the host system wants to obtain the interactive data of the third application APP3, the host controller sends a first instruction to the memory system; however, the interactive data of the third application APP3 has been updated, wherein the RegionC~D area is used to store the data of the third application APP3 before the update, and the RegionE~F area is used to store the data of the third application APP3 after the update; in this case, the host controller sends a third instruction, and the third instruction indicates that the RegionC~D area is set as a non-fixed area, and the RegionE~F area is set as a fixed area; next, after the RegionC~D area is set as a non-fixed area and the RegionE~F area is set as a fixed area, according to the instruction of the first instruction, the memory system sends the mapping information of the RegionE~F area to the host controller; the host controller sends a second instruction to the memory system, and the second instruction contains the mapping information of the RegionE~F area. The memory system reads the data of the RegionE~F area according to the mapping information of the RegionE~F area and the instruction of the second instruction, and sends the read data of the RegionE~F area to the host controller.

[0097] In this way, when the host system subjectively wants to obtain the mapping information of the application corresponding to the first area, the first instruction can be sent to the memory device, the first area can be set as a fixed area, and the mapping information of the application corresponding to the first area can be obtained. Relatively speaking, compared with the memory device blindly recommending the mapping information of the application corresponding to multiple areas to the host controller when the host system subjectively wants to obtain the mapping information of the application corresponding to the first area; the embodiment of the present disclosure can obtain the mapping information of the first area more accurately and more timely, improve the reading accuracy, reduce the reading time, and thus improve the reading performance of the host system and the memory device.

[0098] In some embodiments, the host controller is configured to: before sending the first instruction, send a fourth instruction instructing to write data into the memory device.

[0099] In other words, before fixing the first area, it is necessary to ensure that data has been written into the first area before the data in the first area can be fixed and the mapping information of the first area can be obtained; based on this, the host controller is also configured to send a fourth instruction to the memory system, instructing the memory system to write the data of the application corresponding to the first area into the first area.

[0100] Based on the above-mentioned host system, an embodiment of the present disclosure provides a memory system, which is coupled to the host system and includes: a memory device, including multiple areas, including a first area among the multiple areas; a memory controller, coupled to the memory device and configured to: receive a first instruction; in response to the first instruction, set the first area as a fixed area, and determine mapping information corresponding to the first area; the first area is determined according to an application corresponding to the corresponding area.

[0101] In some embodiments, the memory controller is configured to: receive a second instruction; the second instruction includes the mapping information; and in response to the second instruction, read the data of the first region according to the mapping information.

[0102] In some embodiments, the multiple areas also include a second area, the first area and the second area correspond to the same application; the first area is used to store data of the same application before updating; the second area is used to store data of the same application after updating; the memory controller is configured to: after receiving the first instruction, if the data of the same application has been updated, receive a third instruction; in response to the third instruction, set the first area as a non-fixed area, and set the second area as a fixed area.

[0103] In some embodiments, the memory controller is configured to: receive a fourth instruction before receiving the first instruction; and write data into the memory device in response to the fourth instruction.

[0104] Based on the above host system and memory system, an electronic device and an operating method thereof are provided in an embodiment of the present disclosure; Fig.12 , Fig.12 A schematic flow chart of an operation method of an electronic device provided in an embodiment of the present disclosure; the operation method comprises the following steps: Step S1201: a host system of the electronic device sends a first instruction. Step S1202: a memory controller of the electronic device receives the first instruction; in response to the first instruction, a first area is set as a fixed area, and mapping information corresponding to the first area is determined.

[0105] Combine the following Fig.12 and Fig.13 The interaction process of electronic devices is described in detail.

[0106] refer to Fig.13 The electronic device includes: a host system and a memory system, the memory system includes a memory device and a memory controller; the memory device includes multiple areas; the multiple areas include a first area.

[0107] In some embodiments, the operating method further includes: the host system sends a fourth instruction before sending the first instruction; the memory controller receives the fourth instruction before receiving the first instruction; and writing data into the memory device in response to the fourth instruction.

[0108] In some embodiments, the operating method also includes: after sending the first instruction and before sending the second instruction, if the data of the application corresponding to the first area has been updated, the host system sends a third instruction; the memory controller receives the third instruction; in response to the third instruction, the first area is set as a non-fixed area, and the second area is set as a fixed area; wherein the multiple areas also include the second area, the first area and the second area correspond to the same application; the first area is used to store the data of the same application before the update; the second area is used to store the data of the same application after the update.

[0109] It should be noted that after the first area is set as a non-fixed area and the second area is set as a fixed area, the mapping information of the fixed area determined by the memory controller is the mapping information of the second area. Based on this, the mapping information sent by the memory controller to the host controller is the mapping information of the second area, that is, the mapping information stored in the host memory is also the mapping information of the second area.

[0110] In some embodiments, the host system sends a second instruction; the second instruction includes the mapping information; the memory controller receives the second instruction; and in response to the second instruction, reads the data of the first area according to the mapping information.

[0111] It should be noted that if the data of the application corresponding to the first area is not updated, the second instruction indicates that the data to be read is the data of the first area; at this time, the memory controller responds to the second instruction and reads the data of the first area. If the data of the application corresponding to the first area is updated, the second instruction indicates that the data to be read is the data of the second area; at this time, the memory controller responds to the second instruction and reads the data of the second area.

[0112] An electronic device provided by an embodiment of the present disclosure includes: a host system and a memory system coupled to the host system, wherein: the memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes multiple areas; the multiple areas include a first area; the host system is configured to: send a first instruction; the memory controller is configured to: receive the first instruction; in response to the first instruction, set the first area as a fixed area, and determine mapping information corresponding to the first area; the first area is determined according to an application corresponding to the corresponding area.

[0113] In some embodiments, the host system is configured to: send a second instruction, the second instruction including the mapping information; the memory controller is configured to: receive the second instruction; and in response to the second instruction, read the data of the first area according to the mapping information.

[0114] In some embodiments, the host system is configured to: after sending the first instruction, if the data of the application corresponding to the first area has been updated, send a third instruction; the memory controller is configured to: after receiving the first instruction, if the data of the application corresponding to the first area has been updated, receive the third instruction; and in response to the third instruction, set the first area as a non-fixed area, and set the second area as a fixed area; wherein the multiple areas also include the second area, the first area and the second area correspond to the same application; the first area is used to store the data of the same application before the update; the second area is used to store the data of the same application after the update.

[0115] In some embodiments, the host system is configured to: send a fourth instruction before sending the first instruction; the memory controller is configured to: receive the fourth instruction before receiving the first instruction; and write data to the memory device in response to the fourth instruction.

[0116] In some embodiments, the memory system includes a universal flash storage device UFS or a solid state drive SSD. The memory device includes a NAND type memory.

[0117] The embodiment of the present disclosure also provides a storage medium on which executable instructions are stored.

[0118] In some specific embodiments, the storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface storage, an optical disk, or a compact disc read-only memory (CD-ROM); it can also be various devices including one or any combination of the above-mentioned memory devices.

[0119] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for use in a computing environment.

[0120] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, such as in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files storing one or more modules, subroutines, or code portions).

[0121] As an example, the executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed at multiple sites and interconnected by a communication network.

[0122] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0123] The methods disclosed in the several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The above description is only a specific implementation mode of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A host system, It is characterized in that include: a host controller coupled to a memory system, the memory system comprising a memory device, the memory device comprising a plurality of regions, the plurality of regions including a first region; The host controller is configured to: A first instruction is sent, wherein the first instruction instructs setting the first area as a fixed area and obtaining mapping information corresponding to the first area; the first area is determined according to an application corresponding to the corresponding area.

2. The host system according to claim 1, It is characterized in that The host controller is configured to: Sending a second instruction; the second instruction includes the mapping information; the second instruction instructs reading data in the first area according to the mapping information.

3. The host system according to claim 1, It is characterized in that The host controller is configured to: The first area is determined from the multiple areas according to the attribute information of the application.

4. The host system according to claim 1, It is characterized in that The host controller is configured to: Before sending the first instruction, it is determined that the first area is a non-fixed area.

5. The host system according to claim 1, It is characterized in that The multiple areas further include a second area, the first area and the second area correspond to the same application; the first area is used to store data of the same application before update; the second area is used to store data of the same application after update; The host controller is configured to: After sending the first instruction, if the data of the same application has been updated, sending a third instruction, the third instruction instructing to set the first area as a non-fixed area and to set the second area as a fixed area.

6. The host system according to claim 1, It is characterized in that The host controller is configured to: Before sending the first instruction, a fourth instruction is sent, the fourth instruction instructing to write data into the memory device.

7. The host system according to claim 1, It is characterized in that The host system further includes: a host memory; the host memory is used to store the mapping information.

8. A memory system, It is characterized in that Coupling with a host system, including: A memory device including a plurality of regions, the plurality of regions including a first region; A memory controller coupled to the memory device and configured to: receive a first instruction; In response to the first instruction, the first area is set as a fixed area, and mapping information corresponding to the first area is determined; the first area is determined according to an application corresponding to the corresponding area.

9. The memory system according to claim 8, It is characterized in that The memory controller is configured to: receiving a second instruction; the second instruction including the mapping information; In response to the second instruction, data in the first area is read according to the mapping information.

10. The memory system according to claim 8, It is characterized in that The multiple areas further include a second area, the first area and the second area correspond to the same application; the first area is used to store data of the same application before update; the second area is used to store data of the same application after update; The memory controller is configured to: After receiving the first instruction, if the data of the same application has been updated, receiving a third instruction; In response to the third instruction, the first area is set as a non-fixed area, and the second area is set as a fixed area.

11. The memory system according to claim 8, It is characterized in that The memory controller is configured to: Before receiving the first instruction, receiving a fourth instruction; In response to the fourth instruction, data is written to the memory device.

12. An electronic device, It is characterized in that include: A host system and a memory system coupled to the host system, wherein: The memory system includes a memory device and a memory controller coupled to the memory device; the memory device includes a plurality of regions; the plurality of regions includes a first region; The host system is configured to: send a first instruction; The memory controller is configured to: receive the first instruction; in response to the first instruction, set the first area as a fixed area, and determine mapping information corresponding to the first area; the first area is determined according to an application corresponding to the corresponding area.

13. The electronic device according to claim 12, It is characterized in that The host system is configured to: send a second instruction, wherein the second instruction includes the mapping information; The memory controller is configured to: receive the second instruction; and read data of the first area according to the mapping information in response to the second instruction.

14. The electronic device according to claim 12, It is characterized in that The host system is configured to: after sending the first instruction, if the data of the application corresponding to the first area has been updated, send a third instruction; The memory controller is configured to: after receiving the first instruction, if the data of the application corresponding to the first area has been updated, receive the third instruction; and in response to the third instruction, set the first area as a non-fixed area and set the second area as a fixed area; Among them, the multiple areas also include the second area, the first area and the second area correspond to the same application; the first area is used to store data of the same application before updating; the second area is used to store data of the same application after updating.

15. The electronic device according to claim 12, It is characterized in that The host system is configured to: send a fourth instruction before sending the first instruction; The memory controller is configured to: receive the fourth instruction before receiving the first instruction; and write data into the memory device in response to the fourth instruction.

16. A method for operating an electronic device, It is characterized in that The host system of the electronic device sends a first instruction; The memory system of the electronic device receives the first instruction; and in response to the first instruction, setting a first area of ​​a memory device in the memory system as a fixed area, and determining mapping information corresponding to the first area; The first area is determined according to an application corresponding to the corresponding area; The host system is coupled to the memory system; the memory system includes the memory device and a memory controller coupled to the memory device; the memory device includes a plurality of areas; the plurality of areas includes the first area.

17. The operating method according to claim 16, It is characterized in that The host system sends a second instruction; the second instruction includes the mapping information; The memory controller receives the second instruction; and in response to the second instruction, reads data in the first area according to the mapping information.

18. The operating method according to claim 17, It is characterized in that The operation method further includes: After sending the first instruction, if the data of the application corresponding to the first area has been updated, the host system sends a third instruction; The memory controller receives the third instruction; in response to the third instruction, sets the first area as a non-fixed area and sets the second area as a fixed area; Among them, the multiple areas also include the second area, the first area and the second area correspond to the same application; the first area is used to store data of the same application before updating; the second area is used to store data of the same application after updating.

19. The operating method according to claim 18, It is characterized in that The method further comprises: The host system sends a fourth instruction before sending the first instruction; The memory controller receives a fourth instruction before receiving the first instruction; and writes data into the memory device in response to the fourth instruction.

20. A storage medium, It is characterized in that The storage medium stores executable instructions, and when the executable instructions are executed by an electronic device, the steps of the method described in any one of claims 16 to 19 can be implemented.

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