Method of operating memory system and memory system

Abstract

The invention relates to a method for operating a storage system and the storage system. A method of operating a storage system including a host and a storage device is provided. According to the method, the host queries the storage device for device fill rates of storage spaces of a plurality of non-volatile memory devices in the storage device, and a storage controller controlling the plurality of non-volatile memory devices sends the calculated device fill rates to the host in response to the query, sending, by the host, a demapping command and a target logical block address to the storage device based on the calculated device fill rate, and deallocating, by the storage device, a physical block address corresponding to the target logical block address in response to the demapping command.

Description

Technical Field

[0001] The present disclosure relates to semiconductor integrated circuits, and more particularly to a memory system and an operating method thereof. Background Art

[0002] One or more semiconductor memory devices may be used in a data storage device. Examples of such data storage devices include solid-state drives (SSDs). These types of data storage devices may have various design and / or performance advantages over hard disk drives (HDDs), such as the absence of moving mechanical parts, higher data access speeds, stability, durability, and / or low power consumption. Various systems (e.g., laptops, cars, airplanes, drones, etc.) have adopted storage devices including SSDs.

[0003] When the difference between the valid data recognized by the host and the real valid data in the storage device increases, the performance of the storage system may be degraded. Summary of the invention

[0004] In general, in some aspects, the present subject matter covers a method of operating a storage system that is capable of matching valid data identified by a host with actual valid data in a storage device.

[0005] According to aspects of the present disclosure, a method for operating a storage system including a host and a storage device includes: the host queries the storage device for a device-filled-ratio of storage space of multiple non-volatile memory devices in the storage device, a storage controller that controls the multiple non-volatile memory devices sends a calculated device fill ratio to the host in response to the query, the host sends a demapping command and a target logical block address to the storage device based on the calculated device fill ratio, and the storage device deallocates a physical block address corresponding to the target logical block address in response to the demapping command.

[0006] According to aspects of the present disclosure, a method for operating a storage system including a host and a storage device includes: the storage device sending a first response to the host in response to a first request from the host to notify that an abnormal event has occurred in the storage device, the host sending a second request to the storage device for checking the abnormal event occurring in the storage device, the storage device sending a second response to the host in response to the second request, the second response including information indicating that the abnormal event is associated with a device fill rate of storage spaces of multiple non-volatile memory devices in the storage device, the host querying the storage device for the device fill rate, a storage controller controlling the multiple non-volatile memory devices sending a calculated device fill rate to the host in response to the query, and the host sending a demapping command and a target logical block address to the storage device based on the calculated device fill rate.

[0007] According to aspects of the present disclosure, a storage system includes: a storage device and a host, and the host controls the storage device by communicating with the storage device. The storage device includes multiple non-volatile memory devices and a storage controller that controls the multiple non-volatile memory devices. The storage controller sends a first response to the host in response to a first request from the host to notify that an abnormal event has occurred in the storage device, sends a second response to the host in response to a second request for checking the abnormal event, including information indicating that the abnormal event is associated with the device fill rate of the data storage space of multiple non-volatile memory devices in the storage device, calculates the device fill rate of the non-volatile memory device in response to a query associated with the device fill rate, sends the calculated device fill rate to the host, and deallocates the physical block address corresponding to the target logical block address in response to a demapping command and a target logical block address from the host.

[0008] Therefore, in some embodiments of the storage system, the host can issue a discard by checking the device fill rate of the data storage space of the storage device, or can issue a discard to secure free blocks by checking the device fill rate in response to an abnormal event alarm bit from the storage device. Therefore, the storage system can prevent the increased cost of garbage collection and can prevent the degradation of performance by preventing emergency garbage collection. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a flow chart illustrating an example of a method of operating a storage system.

[0010] Figure 1B The operation is shown in detail Figure 2 A flowchart of an example of a method of a storage system.

[0011] Figure 2 is a block diagram illustrating an example of a storage system.

[0012] Figure 3 yes Figure 2 Schematic diagram of an example of a software hierarchy of a host and a storage device in FIG.

[0013] Figure 4A shows a valid data block (e.g., a valid block) identified by the host and Figure 3 The difference between valid data blocks in the storage devices in the storage system.

[0014] Figure 4B Shows when Figure 3 The storage system in Figure 1A and Figure 1BAn example of the performance of a storage system when associating methods.

[0015] Figure 5 It is shown Figure 2 A block diagram of an example of a host in a storage system.

[0016] Figure 6 is a block diagram illustrating an example of a storage controller in the storage device in FIG. 1 .

[0017] Figure 7 Shows Figure 6 An example of a Flash Translation Layer (FTL) in a storage controller of FIG.

[0018] Figure 8 It is shown Figure 2 A block diagram of an example of a connection relationship between a storage controller in a storage device and a non-volatile memory device.

[0019] Fig. 9 It is shown Figure 8 A block diagram of an example of a non-volatile memory device in FIG.

[0020] Fig.10 It is shown Fig. 9 A block diagram of an example of a memory cell array in a non-volatile memory device.

[0021] Fig.11 It is shown Fig.10 A circuit diagram of an example of one of the memory blocks of FIG.

[0022] Fig.12 Shows Fig.11 An example of the structure of a cell string NS11 in a memory block.

[0023] Fig.13 is a diagram illustrating an example sequence of a method of operating a storage system.

[0024] Fig.14 is a diagram showing an example of a Universal Flash Storage (UFS) Protocol Information Unit (UPIU) used in a method of operating a storage system.

[0025] Fig.15 An example of the format of an inquiry request UPIU transmitted from a host to a storage device is shown.

[0026] Fig.16 Shows Fig.15 An example of a query request for UPIU's query function.

[0027] Fig.17 Shows when Fig.15 An example of transaction specific fields when a query request UPIU corresponds to a standard read / write request.

[0028] Fig.18 Shows Fig.17 An example of the read attribute opcode in .

[0029] Fig.19 An example of UFS attributes for a read request is shown.

[0030] Fig. 20 An example of the format of an inquiry response UPIU transmitted from a storage device to a host is shown.

[0031] Fig.21A Shows when Fig. 20 An example of a read attribute opcode when the query response UPIU corresponds to a standard read request.

[0032] Fig.21B An example of a UFS attribute read response is shown.

[0033] Fig.22A is a flow chart illustrating an example of a method of operating a storage system.

[0034] Fig. 22B is a flow chart illustrating an example of a method of operating a storage system.

[0035] Fig.23 yes Fig. 22B An example of a sequence of methods of operating a storage system.

[0036] Fig.24 An example of a header of a response UPIU sent from a storage device to a host is shown.

[0037] Fig.25 Shows Fig.24 An example of the format of the Device Information field in a response UPIU.

[0038] Fig.26 An example of an abnormal event control attribute included in a first query response sent from a storage device to a host is shown.

[0039] Fig. 27 An example of an abnormal event status attribute included in a first query response sent from a storage device to a host is shown.

[0040] Fig.28 Shows when Figure 3The performance of the storage system when the storage system in the embodiment executes the method of operating the storage system.

[0041] Fig.29 is a block diagram illustrating an example of a storage system.

[0042] Fig.30 is a block diagram illustrating an example of a storage device.

[0043] Fig.31 is a block diagram illustrating an example of an electronic system including a semiconductor device. DETAILED DESCRIPTION

[0044] Figure 1A is a flow chart illustrating an example of a method of operating a storage system.

[0045] Will further refer to Figure 2 The storage system 50 is used to describe the operation Figure 1A storage system method.

[0046] Reference Figure 1A and Figure 2 In a method of operating a storage system 50 including a host 100 and a storage device 200, the host 100 inquires the storage device 200 about a device fill rate of a storage space of a plurality of nonvolatile memory devices 400a-400p in the storage device 200 (operation S100). The storage space may be referred to as a data storage space of the plurality of nonvolatile memory devices 400a-400p, and the device fill rate is a ratio of the number of valid memory blocks storing valid data among a plurality of memory blocks of the plurality of nonvolatile memory devices 400a-400p.

[0047] The storage controller 300 controlling the plurality of nonvolatile memory devices 400a-400p and included in the storage device 200 sends the calculated device fill rate to the host 100 in response to the query (operation S200). The host 100 sends a demap command and a target logical block address to the storage device 200 based on the calculated device fill rate (operation S300).

[0048] The storage device 200 deallocates a physical block address corresponding to the target logical block address in response to the demap command, and transmits a response including a result of the deallocation to the host 100 (operation S400).

[0049] The host 100 and the storage device 200 may communicate with each other according to the Universal Flash Storage (UFS) standard version 3.1 announced by JEDEC on January 30, 2020.

[0050] In a conventional storage system, even when a discrepancy occurs between valid data recognized by the host 100 and actual valid data in the storage device 200, the host 100 does not query the storage device 200 for the device fill rate of the storage space. When the device fill rate recognized by the host 100 drops below a threshold, the file system in the host 100 issues a discard, and the storage device 200 starts garbage collection in response to the discard. Because the file system holds the discards without directly exporting the discards to the storage device 200, when the discards reach a predetermined number, the file system sends the discards to the storage device 200. As a result, the cost of garbage collection increases. For example, when the data storage space of the storage device 200 is full, emergency garbage collection needs to be performed, thereby degrading performance.

[0051] However, in the present storage system 50, because the host 100 can proactively issue a discard by checking the device fill rate of the data storage space of the storage device 200, the cost of garbage collection can be prevented from increasing and emergency garbage collection can be prevented.

[0052] Figure 1B The operation is shown in detail Figure 2 A flowchart of a method for storing a system. Further reference will be made to Figure 2 The storage system 50 is used to describe the operation Figure 1B storage system method.

[0053] Reference Figure 1A , Figure 1B and Figure 2 In order to query the storage device for the device fill rate of the storage space of the plurality of nonvolatile memory devices 400a-400p (operation S100), the host 100 sends a query request including a UFS attribute associated with the device fill rate of the storage space to the storage device 200 (operation S100a). In order to send the calculated device fill rate to the host 100 (operation S200), the storage controller 300 sends a query response including the calculated device fill rate to the host 100 (operation S200a).

[0054] Using a UFS Protocol Information Unit (UPIU) according to the UFS standard, a query request may be transmitted from the host 100 to the storage device 200 , and a query response may be transmitted from the storage device 200 to the host 100 .

[0055] The query request may correspond to a query request UPIU according to the UFS standard, and the host 100 may set the query function of the query request UPIU to a standard read request, and may define a UFS attribute associated with a device fill rate of a storage space by using a reserved identification number of the query request UPIU.

[0056] The query response may correspond to the query response UPIU, and the storage controller 300 may transmit the calculated device fill rate to the host 100 by using the reserved identification number of the query response UPIU.

[0057] The memory controller 300 may calculate a device fill rate based on counts of valid pages storing valid data of the plurality of nonvolatile memory devices 400 a - 400 p .

[0058] The host 100 sends a demapping command and a target logical block address to the storage device 200 based on the calculated device fill rate (operation S300).

[0059] The storage device 200 deallocates a physical block address corresponding to the target logical block address in response to the demap command, and transmits a response including a result of the deallocation to the host 100 (operation S400).

[0060] Figure 2 is a block diagram illustrating an example of a storage system.

[0061] Reference Figure 2 , the storage system 50 includes a host 100 and a storage device 200. The host 100 includes a storage interface 140. The storage device 200 may be any type of storage device.

[0062] The storage device 200 may include a storage controller 300, a plurality of non-volatile memory devices NVM1-NVMp400a-400p (where p is an integer greater than 2), a power management integrated circuit (PMIC) 270, and a host interface 240. The host interface 240 may include a signal connector 241 and a power connector 243. The storage device 200 may also include a buffer memory BM 250 implemented with a volatile memory device.

[0063] Multiple non-volatile memory devices 400a-400p can be used as storage media of the storage device 200. In some embodiments, each of the multiple non-volatile memory devices 400a-400p can include a flash memory or a vertical NAND memory device. The storage controller 300 can be coupled to the multiple non-volatile memory devices 400a-400p through multiple connection channels (channels) CH1-CHp, respectively.

[0064] The memory controller 300 may be configured to receive a request REQ from the host 100 through the signal connector 241 and communicate data DTA with the host 100. The memory controller 300 may write or read data DTA to or from the plurality of nonvolatile memory devices 400a-400p based on the request REQ.

[0065] The memory controller 300 may use the buffer memory 250 as an input / output buffer to communicate the data DTA with the host 100. In some implementations, the buffer memory 250 may include a dynamic random access memory (DRAM).

[0066] The PMIC 270 may be configured to receive a plurality of power supply voltages (e.g., external supply voltages) VES1-VESt from the host 100 through the power connector 243. For example, the power connector 243 may include a plurality of power lines P1-Pt, and the adaptive power supply circuit 500 may be configured to receive the plurality of power supply voltages VES1-VESt from the host 100 through the plurality of power lines P1-Pt, respectively. Herein, t represents a positive integer greater than 1.

[0067] The PMIC 270 may generate at least one first operating voltage VOP1 used by the memory controller 300 , at least one second operating voltage VOP2 used by the plurality of nonvolatile memory devices 400 a - 400 p , and at least one third operating voltage VOP3 used by the buffer memory 250 based on the plurality of power supply voltages VES1 -VESt.

[0068] For example, when the PMIC 270 receives all of the plurality of power supply voltages VES1-VESt from the host 100, the PMIC 270 may generate at least one first operating voltage VOP1, at least one second operating voltage VOP2, and at least one third operating voltage VOP3 using all of the plurality of power supply voltages VES1-VESt. On the other hand, when the PMIC 270 receives less than all of the plurality of power supply voltages VES1-VESt from the host 100, the PMIC 270 may generate at least one first operating voltage VOP1, at least one second operating voltage VOP2, and at least one third operating voltage VOP3 using all of a portion of the plurality of power supply voltages VES1-VESt received from the host 100.

[0069] Figure 3 yes Figure 2 Schematic diagram of an example of a software hierarchy of a host and a storage device in FIG.

[0070] Reference Figure 3The host 100 includes an application 191, a file system 192, a device driver 193, a command generator 194, a response parser 195, a data transfer manager 196, a link layer 197 and a physical layer (PHY) 198.

[0071] The device driver 193 may control the overall operation of the host 100 to control the storage device 200. The command generator 194 may generate a command to be transmitted to the storage device 200. The response parser 195 may parse or decode a response received from the storage device 200. The data transfer manager 196 may generate a packet of data to be transmitted to the storage device 200. The link layer 197 may control the data flow to the PHY 198 and perform recovery of data transmission errors. The PHY 198 may manage physical data communication with the storage device 200.

[0072] Application 191 may be an application software program executed on an operating system. For example, application 191 has been programmed to help generate, copy, and delete files. For example, application 191 may provide various services such as video applications, game applications, web browser applications, etc.

[0073] The file system 192 may manage files used by the host 100. For example, the file system 192 may manage the file name, extension, file attribute, file size, cluster information, etc. of a file accessed by a request from the host 100 or by an application executed by the host 100. The file system 192 may generate, delete, and manage data based on the file. For example, the file system 192 may be a flash-friendly file system (F2FS).

[0074] The application 191 and the file system 192 may be referred to as a high level, and the data transfer manager 196, the link layer 197, and the PHY 198 may be referred to as a low level.

[0075] The storage device 200 may include a flash translation layer (FTL) 291 , a device driver 293 , a command parser 294 , a response generator 295 , a data transfer manager 296 , a link layer 297 , and a PHY 298 .

[0076] The device driver 252 may control the overall operation of the storage device 200. The response generator 295 may generate a response to be transmitted to the host 100. The command parser 294 may parse or decode a command received from the host 100. The data transfer manager 296 may generate a packet of data to be transmitted to the host 100. The link layer 297 may control the data flow to the PHY 298 and perform recovery of data transmission errors. The PHY 298 may manage physical data communication with the host 100.

[0077] The FTL 291 may perform various functions, such as an address mapping operation, a wear-leveling operation, a garbage collection operation, and the like. The address mapping operation may be an operation of converting a logical address received from the host 100 into a physical address for actually storing data in a plurality of non-volatile memory devices 400a-400p. The wear-leveling operation may be a technique for preventing excessive degradation of a specific memory block by allowing blocks of a plurality of non-volatile memory devices 400a-400p to be used evenly. As an example, a firmware technique for balancing the erase counts of physical memory blocks may be used to implement the wear-leveling operation. The garbage collection operation may be a technique for ensuring available capacity in a plurality of non-volatile memory devices 400a-400p by erasing an existing memory block after copying valid data of the existing memory block to a new memory block.

[0078] Figure 4A shows a valid data block (e.g., a valid block) identified by the host and Figure 3 The difference between valid data blocks in the storage devices in the storage system.

[0079] When the user requests the host 100 to delete data, Figure 3 The file system 192 in the storage device 200 invalidates the data requested to be deleted and does not issue a demapping (e.g., discard) command to the storage device 200, so that there may be differences between the valid data blocks identified by the file system 192 at a specific point in time and the actual valid data blocks in the storage device 200.

[0080] Figure 4B Shows when Figure 3 The storage system in Figure 1A and Figure 1B The performance of the storage system when the associated method is used.

[0081] exist Figure 4B, a dotted line represents a device fill rate 11 indicating a ratio of valid memory blocks storing valid data among memory blocks of a plurality of nonvolatile memory devices 400a-400p of the storage device 200, and another dotted line represents a device fill rate 12 of the plurality of nonvolatile memory devices 400a-400p recognized by the host 100. The slopes of the dotted lines representing the device fill rates 11 and 12 are equal to the values ​​of the ratios. Another dotted line represents a dirty segment 13 that is invalid in the host 100 but valid in the storage device 200, another dotted line represents a free block 14 in which data is not stored in the storage device 200, and a solid line represents the performance 15 of the storage system 50, for example, the amount of mismatch between valid data and real valid data over time.

[0082] Reference Figure 4B , when the difference between the device fill rate 12 recognized by the host 100 and the actual device fill rate 11 of the storage device 200 increases and the device fill rate 12 recognized by the host 100 reaches 50%, the performance of the storage system is greatly degraded.

[0083] Figure 5 It is shown Figure 2 A block diagram of an example of a host in a storage system.

[0084] Reference Figure 5 The host 100 includes a host controller 110, a read-only memory (ROM) 120, a host memory 130, an Advanced Encryption Standard (AES) engine 135, a storage interface 150, a user interface 140, a command generator 160, and a response parser 170 connected to each other through a bus 105. The command generator 160 can be connected to Figure 3 The command generator 194 in the embodiment corresponds to the command generator 194 in the embodiment, and the response parser 170 can be connected with the command generator 194 in the embodiment. Figure 3 Corresponding to the response parser 195 in.

[0085] The bus 105 may refer to a transmission channel through which data is transmitted between the host controller 110 , the ROM 120 , the host memory 130 , the AES engine 135 , the storage interface 150 , the user interface 140 , the command generator 160 , and the response parser 170 of the host 100 .

[0086] ROM 120 may store various application programs. For example, application programs supporting storage protocols such as Advanced Technology Attachment (ATA), Small Computer System Interface (SCSI), embedded Multi Media Card (eMMC), and / or Universal Flash Storage (UFS) protocols are stored.

[0087] The host memory 130 may temporarily store data or programs. The user interface 140 may be a physical or virtual medium for exchanging information between a user and the host 100, a computer program, etc., and may include physical hardware and logical software. For example, the user interface 140 may include an input device for allowing a user to manipulate the host 100 and an output device for outputting a result of processing the user's input.

[0088] The host controller 110 may control the overall operation of the host 100. The host controller 110 may generate a command for storing data in the storage device 200 or a request (or command) for reading data from the storage device 200 by using an application stored in the ROM 120, and may transmit the request to the storage device 200 via the storage interface 150. The host controller 110 may generate a plurality of power supply voltages VES1-VESt.

[0089] The AES engine 135 may perform an encryption operation on data provided from the storage device 200 , and may perform a decryption operation on data received from the storage device 200 .

[0090] The command generator 160 may generate a command that specifies an operation to be performed in the storage device 200. The command generated by the command generator 160 may be transmitted to the storage device 200 through the storage interface 150.

[0091] The command generator 160 may generate various commands such as a read command, a write command, and an erase command. The read command may specify an operation of reading data stored in the storage device 200. The write command may specify an operation of writing data into the storage device 200. The erase command may specify an operation of physically erasing data stored in the storage device 200.

[0092] The response parser 170 may analyze the response transmitted from the storage device 200 .

[0093] Figure 6 is a block diagram illustrating an example of a storage controller in the storage device in FIG. 1 .

[0094] Reference Figure 6The storage controller 300 includes a processor 310, an error correction code (ECC) engine 320, an on-chip memory 330, an AES engine 340, a host interface 350, a ROM 355, a response generator 370, a command parser 360, and a memory interface 380 connected via a bus 305. The response generator 370 can be connected to Figure 3 The response generator 295 in the embodiment corresponds to the command parser 360, and the command parser 360 can be used with Figure 3 Corresponding to the command parser 294 in.

[0095] The processor 310 may control the overall operation of the storage controller 300. The processor 310 may control the ECC engine 320, the on-chip memory 330, the AES engine 340, the host interface 350, the ROM 355, the response generator 370, the command parser 360, and the memory interface 380. The processor 310 may include one or more cores (e.g., homogeneous multi-cores or heterogeneous multi-cores). The processor 310 may be or include, for example, at least one of a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a visual processing unit (VPU), and a neural processing unit (NPU). The processor 310 may execute various applications (e.g., a flash translation layer (FTL) 331 and firmware) loaded onto the on-chip memory 330.

[0096] The on-chip memory 330 may store various application programs that can be executed by the processor 310. The on-chip memory 330 may operate as a cache memory adjacent to the processor 310. The on-chip memory 330 may store commands, addresses, and data to be processed by the processor 310, or may store processing results of the processor 310. The on-chip memory 330 may be, for example, a storage medium or a working memory, including latches, registers, static random access memory (SRAM), dynamic random access memory (DRAM), thyristor random access memory (Thyristor Random Access Memory, TRAM), tightly coupled memory (Tightly Coupled Memory, TCM), etc.

[0097] The processor 310 may execute the FTL 331 loaded onto the on-chip memory 330. The FTL 331 may be loaded onto the on-chip memory 330 as a firmware or program stored in one of the non-volatile memory devices 400a-400p. The FTL 331 may manage the mapping between the logical address provided from the host 100 and the physical address of the non-volatile memory device 400a-400p, and may include an address mapping table manager that manages and updates the address mapping table. The FTL 331 may also perform garbage collection operations, wear leveling operations, etc., as well as the above-mentioned address mapping. The FTL 331 may be executed by the processor 310 to address one or more of the following aspects of the non-volatile memory device 400a-400p: overwrite-impossible or in-place write-impossible, the life of the memory cell, a limited number of program-erase (PE) cycles, and an erase speed slower than a write speed.

[0098] Memory cells of the nonvolatile memory devices 400a-400p may have physical characteristics that threshold voltage distribution varies due to reasons such as program elapsed time, temperature, program disturbance, read disturbance, etc. For example, data stored in the nonvolatile memory devices 400a-400p may become erroneous due to the above reasons.

[0099] The storage controller 300 may utilize various error correction techniques to correct such errors. For example, the storage controller 300 may include an ECC engine 320. The ECC engine 320 may correct errors that occur in data stored in the non-volatile memory devices 400a-400p. The ECC engine 320 may include an ECC encoder 323 and an ECC decoder 325. The ECC encoder 323 may perform an ECC encoding operation on data to be stored in the non-volatile memory devices 400a-400p. The ECC decoder 325 may perform an ECC decoding operation on data read from the non-volatile memory devices 400a-400p.

[0100] The ROM 355 may store various information necessary for the memory controller 300 to operate in firmware.

[0101] The AES engine 340 may perform at least one of an encryption operation and a decryption operation on data input to the storage controller 300 by using a symmetric key algorithm. Although not shown in detail, the AES engine 340 may include an encryption module and a decryption module. For example, the encryption module and the decryption module may be implemented as separate modules. For another example, one module capable of performing both encryption and decryption operations may be implemented in the AES engine 340.

[0102] The command parser 360 may analyze a command received from the host 100 , and may provide the analyzed command to the processor 310 .

[0103] The response generator 370 may generate a response in response to a command received from the host 100 , and may transmit the response to the host 100 through the host interface 350 .

[0104] The storage controller 300 may communicate with the host 100 through the host interface 350. For example, the host interface 350 may include Universal Serial Bus (USB), Multimedia Card (MMC), embedded MMC, Peripheral Component Interconnection (PCI), Peripheral Component Interconnection Express (PCI-express), Advanced Technology Attachment (ATA), Serial-ATA, Parallel-ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Mobile Industry Processor Interface (MIPI), Nonvolatile Memory Express (NVMe), Universal Flash Memory (UFS), etc. The storage controller 300 may communicate with the nonvolatile memory devices 400a-400p through the memory interface 380.

[0105] Figure 7 Shows Figure 6 Example of an FTL in a storage controller.

[0106] Reference Figure 7, the FTL 331 includes an input / output (I / O) interface 332 , a filled ratio calculator 335 , and a garbage collection manager 337 .

[0107] The I / O interface 332 may receive data DTA to be written and a logical address LBA of DTA in response to a write request of the host 100 , and may provide a physical address PBA corresponding to the logical address LBA to the nonvolatile memory devices 400 a - 400 p based on a mapping table stored in the on-chip memory 330 .

[0108] At least one of the nonvolatile memory devices 400 a - 400 p may perform a write operation of writing the DTA into the storage area based on the physical address PBA received from the I / O interface 332 .

[0109] The fill rate calculator 335 may receive valid page information VPI associated with the valid page count, and may calculate the fill rate FR based on the valid page information VPI. In some embodiments, the fill rate FR represents the ratio of valid pages storing data relative to available pages of the non-volatile memory device 400a-400p. The fill rate calculator 335 may provide the fill rate FR to the host 100 and the garbage collection manager 337.

[0110] The garbage collection manager 337 can generate a garbage collection trigger signal GCT and can provide the garbage collection trigger signal GCT to at least one of the non-volatile memory devices 400a-400p, so that at least one of the non-volatile memory devices 400a-400p performs garbage collection to copy data in valid pages of a source block for garbage collection among a plurality of memory blocks in each of the non-volatile memory devices 400a-400p to free pages of a destination block and erase the source block.

[0111] Figure 8 It is shown Figure 2 A block diagram of an example of a connection relationship between a storage controller in a storage device and a non-volatile memory device.

[0112] Reference Figure 8 , the memory controller 300 operates based on the first operating voltage VOP1 (eg, as a power supply voltage).

[0113] The non-volatile memory device 400a may perform an erase operation, a program operation, and / or a write operation under the control of the memory controller 300. The non-volatile memory device 400a may receive a command CMD, an address ADDR, and (user) data DTA from the memory controller 300 through an input / output line for performing such operations. In addition, the non-volatile memory device 400a may receive a control signal CTRL from the memory controller 300 through a control line, and receive power PWR1 from the memory controller 300 through a power line. In addition, the non-volatile memory device 400a may provide data DTA and a status signal RnB to the memory controller 300.

[0114] Fig. 9 It is shown Figure 8 A block diagram of an example of a non-volatile memory device in FIG.

[0115] Reference Fig. 9 The nonvolatile memory device 400 a includes a memory cell array 420 , an address decoder 450 , a page buffer circuit 430 , a data input / output (I / O) circuit 440 , a control circuit 460 , and a voltage generator 470 .

[0116] The memory cell array 420 may be coupled to the address decoder 450 through a string selection line SSL, a plurality of word lines WL, and a ground selection line GSL. In addition, the memory cell array 420 may be coupled to the page buffer circuit 430 through a plurality of bit lines BL.

[0117] The memory cell array 420 may include a plurality of memory cells coupled to a plurality of word lines WL and a plurality of bit lines BL.

[0118] In some embodiments, the memory cell array 420 may be or include a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (e.g., a vertical structure). In this case, the memory cell array 420 may include vertical cell strings oriented vertically such that at least one memory cell is located above another memory cell.

[0119] Fig.10 It is shown Fig. 9 A block diagram of an example of a memory cell array in a nonvolatile memory device.

[0120] Reference Figure 8 , the memory cell array 420 includes Fig.10The memory blocks BLK1, BLK2 to BLKz are formed by a plurality of memory blocks BLK1, BLK2 to BLKz. The memory blocks BLK1, BLK2 to BLKz extend along a first horizontal direction HD1, a second horizontal direction HD2, and a vertical direction VD. Herein, z is a natural number greater than 2. In some embodiments, the memory blocks BLK1, BLK2 to BLKz are formed by Fig. 9 The address decoder 450 selects the memory block BLK corresponding to the block address among the memory blocks BLK1, BLK2 to BLKz.

[0121] Fig.11 It is shown Fig.10 A circuit diagram of an example of one of the memory blocks.

[0122] Fig.10 The memory block BLKi may be formed in a three-dimensional structure (or a vertical structure) on the substrate SUB. For example, a plurality of memory cell strings included in the memory block BLKi may be formed in a vertical direction VD perpendicular to the substrate SUB.

[0123] Reference Fig.11 The memory block BLKi includes a plurality of cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23 and NS33 (herein, denoted as NS11 to NS33) coupled between the bit lines BL1, BL2 and BL3 and the common source line CSL. Each of the memory cell strings NS11 to NS33 includes a string selection transistor SST, a plurality of memory cells MC1, MC2, MC3, MC4, MC5, MC6, MC7 and MC8 (herein, denoted as MC1 to MC8) and a ground selection transistor GST. Fig. 9 , each of the memory cell strings NS11 to NS33 is illustrated as including eight memory cells MC1 to MC8. However, the present disclosure is not limited thereto. In some embodiments, each of the memory cell strings NS11 to NS33 may include any number of memory cells.

[0124] The string selection transistor SST may be connected to the corresponding string selection lines SSL1 to SSL3. The plurality of memory cells MC1 to MC8 may be connected to the corresponding word lines WL1 to WL8, respectively. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1 to GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0125] Word lines (eg, WL1) having the same height in the vertical direction VD may be commonly connected, and the ground selection lines GSL1 to GSL3 and the string selection lines SSL1 to SSL3 may be separated. Fig. 9 , the memory block BLKi is shown as being coupled to eight word lines WL1 to WL8 and three bit lines BL1 to BL3. However, the present disclosure is not limited thereto. In some embodiments, the memory cell array 420 may be coupled to any number of word lines and bit lines.

[0126] Fig.12 Shows Fig.11 An example of the structure of the cell string NS11 in the memory block.

[0127] Reference Fig.11 and Fig.12 , a pillar PL is provided on the substrate SUB such that the pillar PL extends in a direction perpendicular to the substrate SUB to contact the substrate SUB. Fig.10 Each of the illustrated ground selection line GSL, word lines WL1 to WL8, and string selection line SSL1 may be formed of a conductive material (eg, metal material) parallel to the substrate SUB. The pillar PL may contact the substrate SUB through the conductive material forming the string selection line SSL1, word lines WL1 to WL8, and ground selection line GSL1.

[0128] The cross-sectional view taken along line V-V' is also Fig.12 . A cross-sectional view of a first memory cell MC1 corresponding to a first word line WL1 is shown. The pillar PL may include a cylindrical body BD. An air gap AG may be defined in an inner portion of the body BD.

[0129] The body BD may include P-type silicon and may be a region where a channel will be formed. The pillar PL may also include a cylindrical tunnel insulating layer TI surrounding the body BD and a cylindrical charge trap layer CT surrounding the tunnel insulating layer TI. A blocking insulating layer BI may be provided between the first word line WL and the pillar PL. The body BD, the tunnel insulating layer TI, the charge trap layer CT, the blocking insulating layer BI and the first word line WL may constitute or be included in a charge trap type transistor formed in a direction perpendicular to the substrate SUB or the upper surface of the substrate SUB. The string selection transistor SST, the ground selection transistor GST and other memory cells may have the same structure as the first memory cell MC1.

[0130] Return to reference Fig. 9, the control circuit 460 may receive a command (signal) CMD and an address (signal) ADDR from the storage controller 300. The control circuit 460 may control an erase cycle, a program cycle, and / or a read operation of the nonvolatile memory device 400a based on the command signal CMD and the address signal ADDR. The program cycle may include a program operation and a program verification operation. The erase cycle may include an erase operation and an erase verification operation.

[0131] For example, the control circuit 460 may generate a control signal CTL for controlling the voltage generator 470, may generate a page buffer control signal PBC for controlling the page buffer circuit 430 based on the command signal CMD, may provide the control signal CTL to the voltage generator 470, and may provide the page buffer control signal PBC to the page buffer circuit 430. In addition, the control circuit 460 may generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 460 may provide the row address R_ADDR to the address decoder 450 and may provide the column address C_ADDR to the data I / O circuit 440.

[0132] The address decoder 450 may be coupled to the memory cell array 420 through the string selection line SSL, the plurality of word lines WL, and the ground selection line GSL. During a program operation or a read operation, the address decoder 450 may determine one of the plurality of word lines WL as a first word line (e.g., a selected word line) based on the row address R_ADDR, and determine the rest of the plurality of word lines WL except the first word line as unselected word lines.

[0133] The voltage generator 470 may generate a word line voltage VWL required for operation of the nonvolatile memory device 400a based on the control signal CTL. The voltage generator 470 may receive power PWR1 from the memory controller 300. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 450.

[0134] For example, during an erase operation, the voltage generator 470 may apply an erase voltage to a well of a memory block and may apply a ground voltage to the entire word line of the memory block. During an erase verification operation, the voltage generator 470 may apply an erase verification voltage to the entire word line of the memory block or sequentially apply an erase verification voltage to the word lines on a word line basis.

[0135] For example, during a program operation, the voltage generator 470 may apply a program voltage to the first word line and may apply a program pass voltage to unselected word lines. In addition, during a program verification operation, the voltage generator 470 may apply a program verification voltage to the first word line and may apply a verification pass voltage to unselected word lines.

[0136] Furthermore, during a read operation, the voltage generator 470 may apply a read voltage to a first word line, and may apply a read pass voltage to unselected word lines.

[0137] The page buffer circuit 430 may be coupled to the memory cell array 420 through a plurality of bit lines BL. The page buffer circuit 430 may include a plurality of page buffers. In some embodiments, one page buffer may be connected to one bit line. In some embodiments, one page buffer may be connected to two or more bit lines.

[0138] The page buffer circuit 430 may temporarily store data to be programmed in a selected page or data read out from a selected page.

[0139] The data I / O circuit 440 may be coupled to the page buffer circuit 430 through the data line DL. During a program operation, the data input / output circuit 440 may receive data DTA from the memory controller 300 and provide the data DTA to the page buffer circuit 430 based on the column address C_ADDR received from the control circuit 460.

[0140] During a read operation, the data I / O circuit 440 may provide the memory controller 300 with data DTA stored in the page buffer circuit 430 based on the column address C_ADDR received from the control circuit 460 .

[0141] The control circuit 460 may control the page buffer circuit 430 and the data I / O circuit 440 .

[0142] The control circuit 460 may include a status signal generator 465 , and the status signal generator 465 may generate a status signal RnB indicating whether each of a program operation, an erase operation, and a read operation is completed and / or in progress.

[0143] The memory controller 300 may determine an idle state or a busy state of each of the nonvolatile memory devices 400 a - 400 p based on the state signal RnB.

[0144] Fig.13 is a diagram illustrating an example sequence of a method of operating a storage system.

[0145] Fig.13 1 shows a query request UPIU QREQ, a query response UPIU QRSP, and a response UPIU RSP transmitted between the host 100 and the storage device 200 during an operation time interval of the storage device 200. Fig.14 etc. describe UPIU according to the UFS standard.

[0146] Reference Fig.13 , the host 100 sends a suspend entry request to the storage device 200 (operation S50), and the host 100 sends a query request QREQ including a UFS attribute associated with a device fill rate of a storage space to the storage device 200 (operation S100a).

[0147] The memory controller 300 in the memory device 200 calculates fill rates FR of the nonvolatile memory devices 400a-400p based on the valid page counts of the nonvolatile memory devices 400a-400p (operation S150), and transmits a query response QRSP including the calculated fill rates FR to the host 100 (operation S200a).

[0148] The host 100 sends a demapping command UNMAP and a target logical block address LBA to the storage device 200 based on the calculated fill rate (operation S300). The storage device 200 de-allocates a physical block address corresponding to the target logical block address LBA in response to the demapping command UNMAP (operation S350), and sends a response RSP including a result of the de-allocation to the host 100 (operation S400). Then, the host 100 and the storage device 200 enter a pause mode (operation S450).

[0149] Hereinafter, an example is described based on a system 50 in which a host 100 and a storage device 200 communicate with each other according to the UFS standard.

[0150] Fig.14 is a diagram illustrating an example of a UFS protocol information unit (UPIU) used in a method of operating a storage system.

[0151] Fig.14 The general format of the UPIU according to the UFS standard is shown. The UPIU includes multiple fields, and Fig.14Byte numbers 1 to j+3 and the names of multiple fields are shown in FIG. For example, UPIU may include fields such as transaction type, flag, LUN, task tag, IID, command set type, query function / task management. Function, response, total EHS length, device information, data segment length, transaction specific field, extra header segment (EHS) 1-extra header segment (EHS) N, header E2ECRC, data segment, data E2ECRC, etc. This description can be replaced with the description in the published UFS standard.

[0152] Using the UFS standard Fig.14 The UPIU shown may transmit a query request associated with a device fill rate of a data storage space from the host 100 to the storage device 200, and may transmit a query response including information about the device fill rate of the data storage space from the storage device 200 to the host 100.

[0153] Fig.15 An example of the format of an inquiry request UPIU transmitted from a host to a storage device is shown.

[0154] Reference Fig.15 , Fig.15 The UPIU in corresponds to the query request UPIU when the transaction type is "xx1001101b", and the query request UPIU may include fields such as flags, LUN, task tag, query function, total EHS length (00h), data segment length, transaction specific field, header E2ECRC, data segment, data E2ECRC, reserved, etc. This description may be replaced with the description in the published UFS standard.

[0155] Fig.16 Shows Fig.15 An example of a query request for UPIU's query function.

[0156] Reference Fig.16 The query function of the query request UPIU can have values ​​such as 00h, 01h, 02h-3Fh, 40-7Fh, 80h, 81h, 82h-BFh and C0h-FFh. Values ​​such as 00h, 02h-3Fh, 80h and 82h-BFh are reserved values. 01h represents a standard read request, 40-7Fh represents a vendor specific read function, 81h represents a standard write request, and C0h-FFh represents a vendor specific write function.

[0157] Fig.17 Shows when Fig.15An example of transaction-specific fields when a query request UPIU corresponds to a standard read / write request.

[0158] Reference Fig.17 ,when Fig.15 When the query request UPIU corresponds to a standard read / write request, the transaction specific fields may include fields such as the operation code OPCODE and OSF[0]-OSF[7]. The description of the operation code OPCODE and OSF[0]-OSF[7] may be replaced with the description in the published UFS standard.

[0159] Fig.18 Shows Fig.17 An example of a read attribute opcode in , and Fig.19 An example of UFS attributes for a read request is shown.

[0160] Reference Fig.18 When the operation code OPCODE corresponds to "03h", the operation code OPCODE represents a read attribute OPCODE, and the read attribute OPCODE may include an attribute identification number attribute IDN (ATTRIBUTE IDN), an index (INDEX), a selector (SELECTOR), and a reserved field.

[0161] The UFS attribute associated with the device fill rate of the data storage space may be a reserved identification number IDN defined in the UFS standard. Fig.19 As shown, the identification number IDN "80h" can define the attribute "bfilledratio" of the device fill rate of the data storage space. The attribute "bfilledratio" of the device fill rate of the data storage space can have a size of 1 byte and can be read only from the storage device 200 to the host 100, as indicated by "read-only".

[0162] exist Fig.19 In the , MDV indicates the manufacturer default value, the "D" type indicates the device-level flag, "Ind." indicates the number of valid values ​​for the index field, and "Sel." indicates the number of valid values ​​for the selector field.

[0163] The device fill ratio attribute "bfilledratio" of the data storage space can be included in the UFS standard Fig.15 The query request UPIU is in the transaction specific field and may be sent from the host 100 to the storage device 200 .

[0164] Fig. 20 An example of the format of an inquiry response UPIU transmitted from a storage device to a host is shown.

[0165] Reference Fig. 20 , the query response UPIU may include multiple fields, and the number and name that may represent each field. For example, the multiple fields may include "xx110110b", "flag", "reserved", "task tag", "query function", "query response", "total EHS length (00h)", "device information", "data segment length", "transaction specific field", "header E2ECRC (omitted if HD=0)", "data [0]", "data [1]", "data [2]", "data [3]", ..., "data [length-4]", "data [length-3]", "data [length-2]", "data [length-1]", "data E2ECRC (omitted if HD=0)", etc.

[0166] Can be used Fig. 20 Field FLD1 in defines the UFS attributes of the read response.

[0167] Fig.21A Shows when Fig. 20 An example of a read attribute opcode when the query response UPIU corresponds to a standard read request, and Fig.21B An example of a UFS attribute read response is shown.

[0168] Reference Fig.21A , when the operation code OPCODE corresponds to "03h", the operation code OPCODE indicates a read attribute operation code.

[0169] The UFS attribute associated with the calculated device fill rate of the data storage space may be a reserved identification number IDN defined in the UFS standard. Fig.21B As shown, the identification number IDN of "80h" may define the attribute "bfilledratio" of the device fill ratio of the calculated data storage space. For example, "00h" may represent 0% of the device fill ratio, "01h" may represent 10% of the device fill ratio, "02h-09h" may represent 20%-90% of the device fill ratio, respectively, and "0Ah" may represent 100% of the device fill ratio.

[0170] The attribute “bfilledratio” of the device fill ratio of the data storage space may have a size of 1 byte and may be read only from the storage device 200 to the host 100 , as indicated by “read-only”.

[0171] The device fill ratio attribute "bfilledratio" of the data storage space can be included in the UFS standard Fig. 20 The query response UPIU is in the transaction specific field and may be sent from the storage device 200 to the host 100 .

[0172] Fig.22A is a flow chart illustrating an example of a method of operating a storage system.

[0173] Will further refer to Figure 2 The storage system 50 is described Fig.22A A method of operating a storage system.

[0174] Reference Figure 2 and Fig.22A , the storage device 200 sends a first response notifying that an abnormal event has occurred in the storage device 200 to the host 100 in response to the first request from the host 100 (operation S510). The host 100 sends a second request for checking the abnormal event occurring in the storage device 200 to the storage device 200 (operation S520). The storage device 200 sends a second response including information indicating that the abnormal event is associated with a device fill rate of a data storage space of a plurality of nonvolatile memory devices 400a-400p in the storage device 200 to the host 100 in response to the second request (operation S530).

[0175] The host 100 queries the storage device 200 for device fill rates of the plurality of nonvolatile memory devices 400a-400p in the storage device 200 (operation S540). The storage controller 300, which controls the plurality of nonvolatile memory devices 400a-400p and is included in the storage device 200, transmits the calculated device fill rates to the host 100 in response to the query (operation S550).

[0176] The host 100 sends a demapping command and a target logical block address to the storage device 200 based on the calculated device fill rate (operation S560). The storage device 200 deallocates the physical block address corresponding to the target logical block address in response to the demapping command, and sends a response including the result of the deallocation to the host 100. For example, the host 100 may be configured to send a demapping command and a target logical block address to the storage device 200 when the difference between the actual device fill rate 11 of the storage device 200 (e.g., the calculated device fill rate) and the device fill rate 12 recognized by the host 100 (e.g., the device fill rate recognized by the file system) exceeds a threshold value (e.g., greater than a reference value).

[0177] Fig. 22B is a flow chart illustrating a method of operating a storage system, and Fig.23 yes Fig. 22B An example of a sequence of methods of operating a storage system.

[0178] Will further refer to Figure 2 The storage system 50 is described Fig. 22B Method of operating a storage system and Fig.23sequence.

[0179] Fig.23 Request REQ1, responses RSP1 and RSP2, query requests UPI1, QREQ1, QREQ2 and QREQ3, and query responses UPI1, QRSP1, QRSP2 and QRSP3 transmitted between the host 100 and the storage device 200 during the operation time interval of the storage device 200 are shown. Fig.24 etc. describe UPIU according to the UFS standard.

[0180] Reference Fig. 22B and Fig.23 , the host 100 sends a first request REQ1 to the storage device 200 (operation S610). The storage device 200 sends a first response RSP1 notifying that an abnormal event has occurred in the storage device 200 to the host 100 in response to the first request REQ1 (operation S620). The host 100 sends a first query request QREQ1 for checking the abnormal event occurring in the storage device 200 to the storage device 200 (operation S630). The storage device 200 sends a first query response QRSP1 including information indicating that the abnormal event is associated with a device fill rate of a data storage space of a plurality of non-volatile memory devices 400a-400p in the storage device 200 to the host in response to the first query request QREQ1 (operation S640).

[0181] The host 100 transmits a second query request QREQ2 for disabling an abnormal event occurring in the storage device 200 to the storage device 200 (operation S650). The storage device 200 transmits a second query response QRSP2 notifying that the abnormal event has been disabled to the host 100 in response to the second query request QREQ2 (operation S660).

[0182] The host 100 transmits a third query request QREQ3 including an inquiry about device fill rates of the plurality of nonvolatile memory devices 400 a - 400 p in the storage device 200 (operation S670 ).

[0183] The storage controller 300 that controls multiple nonvolatile memory devices 400a-400p in the storage device 200 calculates the fill rate FR of the nonvolatile memory devices 400a-400p based on the valid page counts of the nonvolatile memory devices 400a-400p (operation S675), and sends a third query response QRSP3 including attributes of the calculated fill rate FR to the host 100 (operation S680).

[0184] The host 100 sends a demapping command UNMAP and a target logical block address LBA based on the calculated fill rate to the storage device 200 (operation S690). The storage device 200 de-allocates a physical block address corresponding to the target logical block address LBA in response to the demapping command UNMAP (operation S695), and sends a second response RSP2 including a result of the de-allocation to the host 100 (operation S710).

[0185] Fig.24 shows an example of a header of a response UPIU sent from a storage device to a host, and Fig.25 Shows Fig.24 An example of the format of the Device Information field in a response UPIU.

[0186] Reference Fig.24 and 25 , the first bit B[0] in the device information field FLD2 is an abnormal event alarm bit, through which the storage device 200 can notify the host 100 that an abnormal event has occurred in the storage device 200, and the first bit B[0] has been used. When the first bit B[0] in the device information field FLD2 is "1", the host 100 sends a UPIU to the storage device 200 for checking the abnormal event occurring in the storage device 200.

[0187] The second to eighth bits B[1:7] in the device information field FLD2 are reserved bits.

[0188] Fig.26 An example of an abnormal event control attribute included in a first query response sent from a storage device to a host is shown.

[0189] Reference Fig.26 According to the UFS standard, the exception event control attribute wExceptionEventControl may have an identification number IDN of "0Dh", may have a size of 2 bytes, may be read from the storage device 200 to the host 100, and may be volatile.

[0190] The exception event control attribute wExceptionEventControl may include bits B[0], B[1], B[2], B[3], B[4], B[5], and B[6], and each of the bits B[0], B[1], B[2], B[3], B[4], B[5], and B[6] may indicate whether each of a plurality of events DYNCAP_EVENT_EN, SYSPOOL_EVENT_EN, URGENT_BKOPS_EN, TOO_HIGH_TEMP_EN, TOO_LOW_TEMP_EN, WRITEBOOSTER_EVENT_EN, and PERFORMANCE_THROTTLING_EN is enabled. The exception event control attribute wExceptionEventControl may also include bits B[7]-B

[15] reserved in the UFS standard. The storage controller 300 may notify the non-volatile memory device 400a that the exception event is associated with a device fill rate (e.g., DEVICE_FULL_FILLED) indicating that the device is fully filled in storage space by using one of the reserved bits B[7]-B

[15] (e.g., B[7]) of the exception event control attribute wExceptionEventControl of the query response UPIU.

[0191] Descriptions about a plurality of events DYNCAP_EVENT_EN, SYSPOOL_EVENT_EN, URGENT_BKOPS_EN, TOO_HIGH_TEMP_EN, TOO_LOW_TEMP_EN, WRITEBOOSTER_EVENT_EN, and PERFORMANCE_THROTTLING_EN may be replaced with descriptions in the published UFS standard.

[0192] Fig. 27 An example of an abnormal event status attribute included in a first query response sent from a storage device to a host is shown.

[0193] Reference Fig. 27 According to the UFS standard, the exception event status attribute wExceptionEventStatus may have an identification number IDN of "0Eh", may have a size of 2 bytes, may be read from the storage device 200 to the host 100, and may be volatile.

[0194] The exception event status attribute wExceptionEventStatus may include bits B[0], B[1], B[2], B[3], B[4], B[5], and B[6], and each of the bits B[0], B[1], B[2], B[3], B[4], B[5], and B[6] may indicate whether each of a plurality of events DYNCAP_NEEDED, SYSPOOL_EXHAUSTED, URGENT_BKOPS, TOO_HIGH_TEMP, TOO_LOW_TEMP, WRITEBOOSTER_FLUSH_NEEDED, or PERFORMANCE_THROTTLING has occurred. The exception event status attribute wExceptionEventStatus may also include bits B[7]-B

[15] reserved in the UFS standard. The storage controller 300 may notify that the exception event is associated with the device fill rate DEVICE_FULL_FILLED of the storage space by using one (eg, B[7]) of the reserved bits B[7]-B

[15] of the exception event status attribute wExceptionEventStatus of the query response UPIU.

[0195] Descriptions about a plurality of events DYNCAP_NEEDED, SYSPOOL_EXHAUSTED, URGENT_BKOPS, TOO_HIGH_TEMP, TOO_LOW_TEMP, WRITEBOOSTER_FLUSH_NEEDED, and PERFORMANCE_THROTTLING may be replaced with descriptions in the published UFS standard.

[0196] Fig.28 Shows when Figure 3 The performance of the storage system when the storage system in the embodiment executes the method of operating the storage system.

[0197] exist Fig.28 , a dotted line represents a device fill rate 21 indicating a ratio of valid memory blocks storing valid data among memory blocks of a plurality of nonvolatile memory devices 400a-400p of the storage device 200, another dotted line represents a device fill rate 22 of the plurality of nonvolatile memory devices 400a-400p recognized by the host 100. The slopes of the dotted lines representing the device fill rates 11 and 12 are equal to the values ​​of the ratios. Another dotted line represents a dirty segment 23 that is invalid in the host 100 but valid in the storage device 200, another dotted line represents a free block 24 in which data is not stored in the storage device 200, and a solid line represents the performance 25 of the storage system 50.

[0198] Reference Fig.28, when the difference between the device fill rate 22 recognized by the host 100 and the actual device fill rate 21 of the storage device 200 increases, the performance 25 of the storage system may be degraded. Since the host queries the storage device 200 for the device fill rate and sends a demapping command and a target logical block address to the storage device 200 based on the calculated device fill rate to protect the free blocks, the reduced performance of the storage system may not be degraded. Alternatively, the storage device 200 may change the device fill rate to protect the free blocks so that the difference between the device fill rate 22 recognized by the host 100 and the actual device fill rate 21 of the storage device 200 is reduced. As the free blocks increase, the dirty segments decrease, and the performance is maintained in the regional ROI.

[0199] Figure 1A methods, Figure 1B methods, Fig.22A Methods and Fig. 22B The method can be Figure 2 The storage system 50 is executed.

[0200] Therefore, the storage controller 300 in the storage device 200 sends a first response to the host 100 in response to a first request from the host 100 to notify that an abnormal event has occurred in the storage device 200, sends a second response to the host 100 in response to a second request for checking the abnormal event, including information indicating that the abnormal event is associated with the device fill rate of the data storage space of multiple non-volatile memory devices 400a-400p in the storage device 200, calculates the device fill rate of the non-volatile memory devices 400a-400p in response to a query associated with the device fill rate, sends the calculated device fill rate to the host 100, and de-allocates the physical block address corresponding to the target logical block address in response to a demapping command and the target logical block address from the host 100, and protects the free block.

[0201] Therefore, in the storage system 50, the host 100 can issue a discard by checking the device fill rate of the data storage space of the storage device 200, or can issue a discard to protect free blocks by checking the device fill rate in response to an abnormal event alarm bit from the storage device 200. Therefore, the storage system 50 can prevent the increased cost of garbage collection, and can prevent the degradation of performance by preventing emergency garbage collection.

[0202] Fig.29 is a block diagram illustrating an example of a storage system.

[0203] Reference Fig.29 , the storage system 700 includes a UFS host 710 and a UFS storage device 740 .

[0204] The UFS host 710 may include a storage interface circuit 720 , and the UFS storage device 740 may include a host interface circuit 750 .

[0205] exist Fig.29 In the embodiment, the storage interface circuit 720 and the host interface circuit 750 may be referred to as a first interface circuit and a second interface circuit, respectively, and may include a physical layer M-PHY and UniPro corresponding to an interface protocol recommended by the Mobile Industry Processor Interface (MIPI) Alliance. The physical layer M-PHY of the first interface circuit 720 may include a pair of lines for transmitting a differential input signal pair DIN_t and DIN_c, a pair of lines for transmitting a differential output signal pair DOUT_t and DOUT_c, and a line for transmitting a reference clock signal REF_CLK. The physical layer M-PHY of the first interface circuit 720 may include a transmitter 731 and a receiver 732.

[0206] The physical layer M-PHY of the first interface circuit 720 may transmit a signal to the second interface circuit 750 through the output terminals DOUT_t and DOUT_c. The output terminals DOUT_t and DOUT_c may be connected to the transmitter 731 and may constitute a transmission channel M-TX of the first interface circuit 720. For example, the signal transmitted through the output terminals DOUT_t and DOUT_c may be a pair of differential signals. That is, the signal transmitted through the output terminal DOUT_c may be complementary to the signal transmitted through the output terminal DOUT_t.

[0207] The physical layer M-PHY of the first interface circuit 720 may receive a signal from the second interface circuit 750 through the input terminals DIN_t and DIN_c. The input terminals DIN_t and DIN_c may be connected to the receiver 732 and may constitute a receiving channel M-RX of the first interface circuit 720. For example, the signal received through the input terminals DIN_t and DIN_c may be a pair of differential signals. That is, the signal received through the input terminal DIN_c may be complementary to the signal received through the input terminal DIN_t.

[0208] The output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c can be controlled to be in one of various states in accordance with a given protocol. For example, each of the output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c can be controlled to be in a positive state, a negative state, a ground state, or a floating state.

[0209] When the level (e.g., voltage level) of the output signal of the first output terminal DOUT_t is higher than the level of the output signal of the second output terminal DOUT_c, the output terminals DOUT_t and DOUT_c may be in a positive state. When the level of the output signal of the first output terminal DOUT_t is lower than the level of the output signal of the second output terminal DOUT_c, the output terminals DOUT_t and DOUT_c may be in a negative state. When the first output terminal DOUT_t and the second output terminal DOUT_c are floating, the output terminals DOUT_t and DOUT_c may be in a floating state DIF-Q. When the levels of the first output terminal DOUT_t and the second output terminal DOUT_c are equal, the output terminals DOUT_t and DOUT_c may be in a base state.

[0210] When the level of the input signal of the first input terminal DIN_t is higher than the level of the input signal of the second input terminal DIN_c, the input terminals DIN_t and DIN_c may be in a positive state. When the level of the input signal of the first input terminal DIN_t is lower than the level of the input signal of the second input terminal DIN_c, the input terminals DIN_t and DIN_c may be in a negative state. When the first input terminal DIN_t and the second input terminal DIN_c are connected to the terminals of the base state, the input terminals DIN_t and DIN_c may be in a base state. When the first input terminal DIN_t and the second input terminal DIN_c are floating, the input terminals DIN_t and DIN_c may be in a floating state.

[0211] The second interface circuit 750 may include input terminals DIN_t and DIN_c, output terminals DOUT_t and DOUT_c, and a clock terminal REF_CLK.

[0212] The output terminals DOUT_t and DOUT_c of the second interface circuit 750 may correspond to the input terminals DIN_t and DIN_c of the first interface circuit 720 , and the input terminals DIN_t and DIN_c of the second interface circuit 750 may correspond to the output terminals DOUT_t and DOUT_c of the first interface circuit 720 .

[0213] The physical layer M-PHY of the second interface circuit 750 may receive signals through input terminals DIN_t and DIN_c, and may transmit signals through output terminals DOUT_t and DOUT_c. The physical layer M-PHY of the second interface circuit 750 may include a receiver 761 and a transmitter 763.

[0214] As in the above description given with reference to the first interface circuit 720 , the output terminals DOUT_t and DOUT_c and the input terminals DIN_t and DIN_c of the second interface circuit 750 may be controlled to a positive state, a negative state, a ground state, or a floating state.

[0215] Meanwhile, the physical layer M-PHY of the second interface circuit may be a reference clock detector (not shown) according to the MIPI M-PHY specification. The reference clock detector may detect a change between an idle mode and an active mode of the UFS storage device 740.

[0216] When the UFS storage device 740 does not perform any operation, the UFS storage device 740 may be in a first idle mode or a second idle mode. When the UFS storage device 740 is in the first idle mode or the second idle mode, the first interface circuit 720 may not transmit the reference clock REF_CLK to the second interface circuit 750. When the UFS storage device 740 switches from the first idle mode and / or the second idle mode to the active mode, the input terminals DIN_t and DIN_c of the second interface circuit 750 may switch from a floating state to a negative state. When the UFS storage device 740 switches from the first idle mode and / or the second idle mode to the active mode, the first interface circuit 720 may resume the transmission of the reference clock REF_CLK to the second interface circuit 750.

[0217] In some embodiments, when the UFS storage device 740 is in the second idle mode, the reference clock detector may generate a trigger signal for allowing the UFS storage device 740 to enter the active mode based on toggling of the reference clock REF_CLK.

[0218] Fig.30 is a block diagram illustrating an example of a storage device.

[0219] Reference Fig.30 , the storage device 800 includes a storage controller 810 and a storage media 820. The storage device 800 may support a plurality of channels CH1, CH2, . . . , CHp (hereinafter referred to as CH1 to CHp), and the storage media 820 may be connected to the storage controller 810 through the plurality of channels CH1 to CHp.

[0220] The storage medium 820 may include a plurality of nonvolatile memory devices NVM11, NVM12, ..., NVM1s, NVM21, NVM22, ..., NVM2s, NVMp1, NVMp2, ..., NVMps. For example, the nonvolatile memory devices NVM11 to NVMps may correspond to the nonvolatile memory devices 400a-400p in FIG. 1. Each of the nonvolatile memory devices NVM11 to NVMps may be connected to one of the plurality of channels CH1 to CHp in a manner corresponding thereto. For example, the nonvolatile memory devices NVM11 to NVM1s may be connected to the first channel CH1 in manners W11, W12, ..., W1s, the nonvolatile memory devices NVM21 to NVM2s may be connected to the second channel CH2 in manners W21, W22, ..., W2s, and the nonvolatile memory devices NVMp1 to NVMps may be connected to the pth channel CHp in manners Wp1, Wp2, ..., Wps. In some embodiments, each of the nonvolatile memory devices NVM11 to NVMps may be implemented as any memory unit that may be operated according to a separate command from the memory controller 810. For example, each of the nonvolatile memory devices NVM11 to NVMps may be implemented as a chip or a die, but examples are not limited thereto.

[0221] The storage controller 810 may send and receive signals to and from the storage medium 820 through a plurality of channels CH1 to CHp. Figure 2 For example, the storage controller 810 may send commands CMDa, CMDb, ..., CMDp, addresses ADDRa, ADDRb, ..., ADDRp, and data DTAa, DTAb, ..., DTAp to the storage medium 820 through channels CH1 to CHp, or may receive DTAa to DTAp from the storage medium 820.

[0222] The memory controller 810 may select one of the nonvolatile memories NVM11 to NVMps connected to each of the channels CH1 to CHp by using a corresponding one of the channels CH1 to CHp, and may transmit and receive signals to and from the selected nonvolatile memory device.

[0223] The storage controller 810 may send and receive signals to and from the storage medium 820 in parallel through different channels.

[0224] The storage controller 810 may communicate with an external host according to the UFS standard. A query request may be sent from the host to the storage controller 810 using the UPIU according to the UFS standard, and a query response may be sent from the storage controller 810 to the host.

[0225] The query request may correspond to a query request UPIU according to the UFS standard, and the host may set the query function of the query request UPIU to a standard read request, and may define a UFS attribute associated with a device fill rate of a storage space by using a reserved identification number of the query request UPIU.

[0226] The query response may correspond to the query response UPIU, and the storage controller 810 may transmit the calculated device fill rate to the host by using the reserved identification number of the query response UPIU.

[0227] Fig.31 is a block diagram illustrating an example of an electronic system including a semiconductor device.

[0228] Reference Fig.31 , the electronic system 3000 includes a semiconductor device 3100 and a controller 3200 electrically connected to the semiconductor device 3100. The electronic system 3000 may be a storage device including one or more semiconductor devices 3100 or an electronic device including a storage device. For example, the electronic system 3000 may be a solid state drive (SSD) device, a universal serial bus (USB), a computing system, a medical device, or a communication device that may include one or more semiconductor devices 3100.

[0229] The semiconductor device 3100 may be a nonvolatile memory device, for example, Figures 9 to 12 The semiconductor device 3100 may include a first structure 3100F and a second structure 3100S on the first structure 3100F. The first structure 3100F may be a peripheral circuit structure including a decoder circuit 3110, a page buffer circuit 3120, and a logic circuit 3130. The second structure 3100S may be a memory cell structure including a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a (memory) cell string CSTR between the bit line BL and the common source line CSL.

[0230] In the second structure 3100S, each of the memory cell strings CSTR may include lower transistors LT1 and LT2 adjacent to a common source line CSL, upper transistors UT1 and UT2 adjacent to a bit line BL, and a plurality of memory cell transistors MCT between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. The number of the lower transistors LT1 and LT2 and the number of the upper transistors UT1 and UT2 may be varied.

[0231] In some embodiments, the upper transistors UT1 and UT2 may include string selection transistors, and the lower transistors LT1 and LT2 may include ground selection transistors. The lower gate lines LL1 and LL2 may be gate electrodes of the lower transistors LT1 and LT2, respectively. The word lines WL may be gate electrodes of the memory cell transistors MCT, respectively, and the upper gate lines UL1 and UL2 may be gate electrodes of the upper transistors UT1 and UT2, respectively.

[0232] In some embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground selection transistor LT2 that may be connected in series to each other. The upper transistors UT1 and UT2 may include a string selection transistor UT1 and an upper erase control transistor UT2. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 may be used in an erase operation to erase data stored in the memory cell transistor MCT through a gate induced drain leakage (GIDL) phenomenon.

[0233] The common source line CSL, the first and second lower gate lines LL1 and LL2, the word lines WL, and the first and second upper gate lines UL1 and UL2 may be electrically connected to the decoder circuit 3110 through a first connection wiring 3115 extending from the first structure 3100F to the second structure 3110S. The bit line BL may be electrically connected to the page buffer circuit 3120 through a second connection wiring 3125 extending from the first structure 3100F to the second structure 3100S.

[0234] In the first structure 3100F, the decoder circuit 3110 and the page buffer circuit 3120 may perform a control operation on at least one selected memory cell transistor among a plurality of memory cell transistors MCT. The decoder circuit 3110 and the page buffer circuit 3120 may be controlled by a logic circuit 3130. The semiconductor device 3100 may communicate with the controller 3200 through an input / output pad 3101 electrically connected to the logic circuit 3130. The input / output pad 3101 may be electrically connected to the logic circuit 3130 through an input / output connection wiring 3135 in the first structure 3100F and extending to the second structure 3100S.

[0235] The controller 3200 may include a processor 3210 , a NAND controller 3220 , and a host interface 3230 . The electronic system 3000 may include a plurality of semiconductor devices 3100 , and in this case, the controller 3200 may control the plurality of semiconductor devices 3100 .

[0236] The processor 3210 may control the operation of the electronic system 3000 including the controller 3200. The processor 3210 may be operated by firmware and may control the NAND controller 3220 to access the semiconductor device 3100. The NAND controller 3220 may include a NAND interface 3221 for communicating with the semiconductor device 3100. Through the NAND interface 3221, a control command for controlling the semiconductor device 3100, data to be written into the memory cell transistor MCT of the semiconductor device 3100, data to be read from the memory cell transistor MCT of the semiconductor device 3100, etc. may be transmitted. The host interface 3230 may provide communication between the electronic system 3000 and an external host. When a control command is received from an external host through the host interface 3230, the processor 3210 may control the semiconductor device 3100 in response to the control command.

[0237] The present disclosure can be applied to various electronic devices including storage devices. For example, example embodiments can be applied to systems such as memory cards, solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash storage (UFS), mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, navigation systems, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-books, virtual reality (VR) devices, augmented reality (AR) devices, server systems, automotive driving systems, etc.

[0238] Although the present disclosure contains many specific implementation details, these should not be interpreted as limiting the scope of the claimed protection. Certain features described in the context of separate embodiments in the present disclosure may also be implemented in combination in a single embodiment. On the contrary, the various features described in the context of a single embodiment may also be implemented in multiple embodiments individually or in any suitable sub-combination. In addition, although the features may be described above as working in certain combinations, one or more features from the combination may be deleted from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0239] The foregoing is illustrative of example embodiments and should not be construed as limiting thereof. Although a few example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without materially departing from the present disclosure.

Claims

1. A method for operating a storage system including a host and a storage device, the method comprising: The host queries the storage device for a device filling rate of storage spaces of a plurality of non-volatile memory devices in the storage device; sending, by a storage controller in the storage device, the calculated device fill rate to the host in response to the query, wherein the storage controller is configured to control the plurality of non-volatile memory devices; Sending, by the host, a demapping command and a target logical block address to the storage device based on the calculated device fill rate; and A physical block address corresponding to the target logical block address is de-allocated by the storage device in response to the de-map command.

2. The method according to claim 1, wherein: The host and the storage device are configured to communicate with each other according to the Universal Flash Storage (UFS) standard.

3. The method according to claim 1, wherein: Querying the equipment fill rate includes: sending, by the host, a query request including a universal flash storage (UFS) attribute associated with the device fill rate of the storage space, and The sending of the calculated device fill rate to the host includes the storage controller sending a query response including the calculated device fill rate to the host.

4. The method according to claim 3, wherein: The query request is sent from the host to the storage device using a UFS protocol information unit (UPIU) according to a UFS standard, and the query response is sent from the storage device to the host using the UPIU according to the UFS standard.

5. The method according to claim 3, wherein: The query request corresponds to a query request UFS protocol information unit UPIU according to the UFS standard, and wherein the host is configured to: Setting the query function of the query request UPIU to a standard read request; and defining the UFS attribute associated with the device fill rate of the storage space by using a reserved identification number of the query request UPIU, wherein the query response corresponds to the query response UPIU, and Wherein, the storage controller is configured to send the calculated device fill rate to the host by using a reserved identification number of the query response UPIU.

6. The method according to claim 3, wherein: The memory controller is configured to calculate the device fill rate based on a count of valid pages of the plurality of non-volatile memory devices, and wherein the valid pages store valid data.

7. The method according to claim 1, wherein: The host is configured to query the storage device for the device fill rate after sending a suspend entry command to the storage device, and The host is configured to send the demapping command and the target logical block address to the storage device when a difference between the calculated device fill rate and the device fill rate identified by the file system of the host is greater than a reference value.

8. The method according to claim 1, further comprising: After deallocating the physical block addresses, the host causes the storage device to enter a suspend mode when a difference between the calculated device fill rate and a device fill rate recognized by a file system of the host is greater than a reference value.

9. A method of operating a storage system comprising a host and a storage device, the method comprising: In response to a first request from the host, the storage device sends a first response, wherein the first response notifies the host that an abnormal event has occurred in the storage device; The host sends a second request to the storage device to check the abnormal event occurring in the storage device; In response to the second request, the storage device sends a second response to the host, the second response including information indicating that the abnormal event is associated with a device fill rate of storage space of a plurality of non-volatile memory devices in the storage device; The host queries the storage device for the device fill rate; sending, by a storage controller in the storage device in response to the query, a calculated device fill rate to the host; and The host sends a demapping command and a target logical block address to the storage device based on the calculated device fill rate, The storage controller is configured to control the plurality of non-volatile memory devices.

10. The method according to claim 9, wherein: The host and the storage device are configured to communicate with each other according to the Universal Flash Storage (UFS) standard.

11. The method according to claim 10, wherein: The first response corresponds to a response UFS protocol information unit UPIU according to the UFS standard, The storage controller is configured to notify the host of the abnormal event by setting the abnormal event alarm bit to a first value, and Wherein, the abnormal event alarm bit is included in the device information field of the response UPIU.

12. The method according to claim 10, wherein: The second response corresponds to a query response UFS protocol information unit UPIU according to the UFS standard, and The storage controller is configured to notify the host that the abnormal event is associated with the device fill rate of the storage space by using one of the reserved bits of the abnormal event control attribute of the query response UPIU.

13. The method according to claim 12, wherein: The storage controller is configured to notify the host that the abnormal event is associated with the device fill rate of the storage space by: allocating one of the reserved bits of the exception event control attribute of the query response UPIU to indicate that the storage device is fully filled; and The one bit is set to a first value.

14. The method according to claim 10, wherein: The second response corresponds to a query response UFS protocol information unit UPIU according to the UFS standard, and The storage controller is configured to notify the host that the abnormal event is associated with the device fill rate of the storage space by using one of the reserved bits of the abnormal event status attribute of the query response UPIU.

15. The method according to claim 14, wherein: The storage controller is configured to notify the host that the abnormal event is associated with the device fill rate of the storage space by: allocating one of the reserved bits of the abnormal event status attribute of the query response UPIU to indicate that the storage device is fully filled; and The one bit is set to a first value.

16. The method according to claim 10, wherein: Querying the equipment fill rate includes: transmitting, by the host, a query request including a universal flash storage (UFS) attribute associated with the device fill rate of the storage space, and The sending of the calculated device fill rate to the host includes the storage controller sending a query response including the calculated device fill rate to the host.

17. The method according to claim 16, wherein: The query request corresponds to a query request UFS protocol information unit UPIU according to the UFS standard, and wherein the host is configured to: Setting the query function of the query request UPIU to a standard read request; and defining the UFS attribute associated with the device fill rate of the storage space by using a reserved identification number of the query request UPIU, wherein the query response corresponds to the query response UPIU, and Wherein, the storage controller is configured to send the calculated device fill rate to the host by using a reserved identification number of the query response UPIU.

18. The method of claim 9, further comprising deallocating, by the storage device in response to the demap command, a physical block address corresponding to the target logical block address.

19. A storage system comprising: A storage device comprising a plurality of non-volatile memory devices and a storage controller configured to control the plurality of non-volatile memory devices; and a host configured to control the storage device by communicating with the storage device, Wherein, the storage controller is configured as: sending a first response in response to a first request from the host, the first response notifying the host that an abnormal event has occurred in the storage device; sending a second response to the host in response to a second request for checking the abnormal event, the second response including information indicating that the abnormal event is associated with a device fill rate of data storage space of the plurality of non-volatile memory devices in the storage device; calculating the device fill rate in response to a query associated with the device fill rate; sending the calculated device fill rate to the host; and A physical block address corresponding to a target logical block address is de-allocated in response to a de-mapping command and a target logical block address from the host.

20. The storage system according to claim 19, in, The host and the storage device are configured to communicate with each other according to the Universal Flash Storage (UFS) standard, The first response corresponds to a response UFS protocol information unit UPIU according to the UFS standard, wherein the storage controller is configured to notify the host of the occurrence of the abnormal event by setting an abnormal event alarm bit to a first value, the abnormal event alarm bit being included in the device information field of the response UPIU, wherein the second response corresponds to a query response UPIU according to the UFS standard, and The storage controller is configured to notify the host that the abnormal event is associated with the device fill rate of the storage space by using one of the reserved bits of the abnormal event control attribute of the query response UPIU.

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