Memory controller, storage device, and operation method of memory controller

Abstract

A memory controller, a memory device, and an operating method of the memory controller are provided. The memory device includes: a memory device including a plurality of dies; and a memory controller receiving at least one command from a host and transmitting the at least one command to the memory device, in which the memory controller stores the commands received from the host in a queue, and when there is a command occupying the same die among the commands stored in the queue, the memory controller transmits the commands to the memory device. The memory controller changes an order in which the commands are transferred to the memory device.

Description

Technical Field

[0001] The present disclosure relates to memory devices, and more particularly to memory devices that reduce power consumption by controlling the order of commands transmitted to the memory devices, thereby achieving improved performance. Background Art

[0002] Storage devices such as solid state drives (SSDs), non-volatile express memory (NVMe), embedded multimedia cards (eMMCs), and UFS are widely used. Summary of the invention

[0003] The storage device may transmit commands received from the host device to the memory device. The storage device may generate a scheduler to schedule the commands. However, when a non-volatile memory device is used in a mobile device such as a cellular phone, peak power issues may occur.

[0004] The present disclosure provides a storage device and a memory controller of the storage device, wherein the storage device has improved performance by controlling the order of transmitting commands to the memory device based on whether there are commands occupying the same die among at least one command stored in a queue. The disclosed scheduler can meet power constraints and improve the performance of the storage device.

[0005] In general, in some aspects, a storage device including a memory device that communicates with a host includes: a plurality of dies and a memory controller, the memory controller being configured to receive at least one command from the host and transmit at least one command to the memory device, wherein the memory controller stores the commands received from the host in a queue, and when there are commands occupying the same die among the commands stored in the queue, the memory controller changes the order in which the commands are transmitted to the memory device.

[0006] In general, in some other aspects, a memory controller includes: a queue controller configured to determine whether to store a command received from a host in a queue based on a queue depth; a scheduler configured to generate a scheduler for providing commands to a memory device including a plurality of dies based on whether there are overlapping dies among a plurality of dies respectively occupied by the commands stored in the queue and whether the commands are stored in the queue; and a power counter configured to compare a total power amount of the memory device with a limited power amount of the memory device and generate a power comparison result, wherein the scheduler transmits at least one of the commands to the memory device according to the scheduler based on the power comparison result.

[0007] In general, in some other aspects, a method of operating a memory controller includes: receiving at least one command from a host; determining whether to store at least one command in a queue; generating a scheduler for providing commands to a memory device based on whether the command is stored in the queue and whether there are overlapping dies among a plurality of dies respectively occupied by the commands stored in the queue; and transmitting at least one of the commands to the memory device according to the scheduler. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an example of a host storage system.

[0009] Figure 2 is a block diagram illustrating an example of a host storage system including a host and a storage device.

[0010] Figure 3 is a diagram illustrating an example of a memory device.

[0011] Figure 4 is a block diagram illustrating an example of a memory controller.

[0012] Figure 5A is a diagram illustrating an example of a queue controller.

[0013] Figure 5B is a diagram illustrating an example of a queue controller.

[0014] Figure 6 is a diagram showing an example of the operation of a scheduler.

[0015] Figure 7 is a diagram showing an example of the operation of the scheduler according to the command type.

[0016] Fig. 8A is a diagram showing an example of a power counter.

[0017] Figure 8B is a diagram showing an example of a power counter.

[0018] Fig. 9 is a flowchart illustrating an example of an operating method of a memory controller.

[0019] Fig.10 is a flow chart illustrating an example of a method in which a memory controller determines whether to store a command in a queue.

[0020] Fig.11 is a flowchart illustrating an example of a method in which a memory controller generates a scheduler. and Fig.12 An example of a system using a storage device is shown.

[0021] Like reference numerals are used for like components in the drawings, and redundant descriptions thereof are omitted. DETAILED DESCRIPTION

[0022] Figure 1 is a block diagram showing an example of the host storage system 1 .

[0023] refer to Figure 1 , the host storage system 1 includes a host 20 and a storage device 10. In addition, the storage device 10 includes a memory controller 100 and a memory device 200.

[0024] The host 20 may transmit various types of commands CMD corresponding to a user request to the storage device 10. Therefore, the storage device 10 may perform an operation corresponding to the command CMD. In addition, in this specification, a command may be used to represent a work request or an instruction.

[0025] The storage device 10 may communicate with the host 20. The storage device 10 may communicate with the host 20 through various interfaces. As an example, the storage device 10 may communicate with the host 20 through various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), eMMC, Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), NVMe.

[0026] The storage device 10 may include a non-volatile memory device, such as a flash memory. In some implementations, the storage device 10 may be implemented as a memory built into or removable from an electronic device. For example, the storage device 10 may be implemented in various forms, such as an embedded UFS memory device, an eMMC, a solid state drive (SSD), a UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, a memory stick, etc.

[0027] The memory controller 100 may control the overall operation of the memory device 10. The memory controller 100 may also be referred to as a controller, a device controller, or a memory controller.

[0028] When power is supplied from the outside to the memory device 10, the memory controller 100 may run firmware. When the memory device 200 is a flash memory device, the firmware may include a host interface layer (HIL), a flash translation layer (FTL), and a flash interface layer (FIL).

[0029] The memory controller 100 may control the memory device 200 to perform a memory operation (e.g., a programming operation, a writing operation, etc.) in response to a command CMD of the host 20. The memory controller 100 may receive the command CMD from the host 20 and provide the command CMD to the memory device 200. During a writing operation, the memory controller 100 may provide a writing command (or a programming command), a physical address, and data to the memory device 200. During a reading operation, the memory controller 100 may provide a reading command and a physical address to the memory device 200.

[0030] As an example, the memory controller 100 may transmit commands, addresses, and data generated by the memory controller 100 to the memory device 200 regardless of the command CMD provided from the host 20. For example, the memory controller 100 may generate commands, addresses, and data for performing background operations and provide the commands, addresses, and data to the memory device 200. The background operation may be, for example, wear leveling, read reclaim, or garbage collection.

[0031] The memory controller 100 may receive at least one command CMD from the host 20 and transmit the at least one command CMD to the memory device 200. Transmitting the command CMD to the memory device 200 by the memory controller 100 may include transmitting a request or command generated by the memory controller 100 corresponding to the command CMD.

[0032] The memory controller 100 may store the command CMD received from the host 20 in a queue. As an example, the memory controller 100 may store a plurality of command CMDs in the queue. The queue may temporarily store the command CMD received from the host 20. As an example, the queue may be a command queue. The memory controller 100 may transmit the command CMD stored in the queue to a die of the memory device 200. The memory controller 100 may generate a scheduler to transmit the command CMD to the memory device 200 and transmit the command CMD to the dies corresponding to the command CMD respectively according to the generated scheduler.

[0033] In some implementations, the memory controller 100 may control the order in which the commands CMD are transmitted to the memory device 200 based on whether there are commands CMDs occupying the same die among the commands CMDs stored in the queue. That is, the memory controller 100 may generate a scheduler for providing the commands CMD to the memory device 200 based on whether there are commands CMDs occupying the same die among the commands CMDs stored in the queue. The memory device 200 may rearrange the order in which the commands CMD are transmitted based on whether there are commands CMDs occupying the same die.

[0034] The die occupied by the command CMD may refer to the die of the memory device 200 on which the command CMD will perform a memory operation. The memory controller 100 may determine the die occupied by the command CMD through the command CMD information. As an example, the memory controller 100 may determine the die occupied by each command CMD based on the logical page number (LPN) of each command CMD.

[0035] Among the command CMDs, the command CMD occupying the same die may refer to the command CMD occupying overlapping die among the die of the memory device 200 respectively occupied by the command CMDs stored in the queue. As an example, a first read command, a second read command, and a third read command are stored in the queue, the first read command occupies the first die, the second read command occupies the second die, and the third read command occupies the first die. The first read command and the third read command may be command CMDs occupying the same first die.

[0036] In some implementations, when there are command CMDs occupying the same die among the multiple command CMDs stored in the queue, the memory controller 100 may change the order in which the command CMDs are transmitted to the memory device 200 so that the command CMDs occupying the same die are in a continuous order. When there are command CMDs occupying the same die among the multiple command CMDs stored in the queue, but not all command CMDs stored in the queue occupy the same die, the memory controller 100 may generate a scheduler so that the command CMDs occupying the same die are in a continuous order.

[0037] As an example, a first read command, a second read command, and a third read command are stored in a queue, the first read command occupies the first die, the second read command occupies the second die, and the third read command occupies the first die. The memory controller 100 may generate a scheduler so that the first read command and the third read command are in a continuous order. The memory controller 100 may transmit the first read command, the third read command, and the second read command to the memory device 200 in such an order.

[0038] In some implementations, the memory device 200 may be a non-volatile memory device. For example, the non-volatile memory device may include a NAND flash memory device. When the memory device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. A 3D memory array may be a circuit associated with an array of memory cells or the operation of a memory cell having an active region disposed on a silicon substrate, the 3D memory array being formed as a monolith on a substrate or a monolith on at least one physical level of a circuit formed in a substrate. The term "monolith" means that the layers constituting each level of the array are stacked directly on top of the layers of each lower level of the array.

[0039] In some implementations, a 3D memory array may include vertical NAND strings arranged in a vertical direction such that at least one memory cell is located on top of another memory cell.At least one memory cell may include a charge trapping layer.

[0040] However, the present disclosure is not limited thereto, and the memory device 200 may include other types of memory. For example, the memory device 200 may include a nonvolatile memory, and the nonvolatile memory may include various types of memory, such as a magnetic random access memory (MRAM), a spin transfer torque MRAM, a conductive bridge RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive RAM, a nanotube RAM, a polymer RAM (PoRAM), a nano floating gate memory (NFGM), a holographic memory, a molecular electronic memory, or an insulated resistance change memory. Hereinafter, the memory device 200 is assumed to be a NAND flash memory device.

[0041] In some implementations, the memory device 200 may include multiple dies (e.g., Figure 3 In the embodiment of the present invention, a first die 211 and a second die 212 are provided in the embodiment of the present invention, each die may include a plurality of planes. Each plane may include a plurality of memory blocks (memory blocks may also be referred to as blocks). Each memory block may include a plurality of pages, and each of the plurality of pages may include a plurality of memory cells sharing a word line. As an example, a block may be an erase unit, and a page may be a write and read unit. Figure 3 The structure of the memory device 200 is described in detail.

[0042] Figure 2 2 is a block diagram showing a host storage system 1 including a host 20 and a storage device 10. Figure 2 The storage device 10, the memory controller 100 and the memory device 200 correspond to Figure 1The memory device 10, the memory controller 100 and the memory device 200 are described herein, so a redundant description thereof is omitted.

[0043] refer to Figure 2 , the host storage system 1 includes a storage device 10 and a host 20, and the storage device 10 may include a memory controller 100 and a memory device 200. In addition, the host 20 may include a host controller 21 and a host memory 22. The host memory 22 may act as a buffer memory for temporarily storing data to be transmitted to or from the storage device 10.

[0044] In some implementations, the host controller 21 and the host memory 22 may be implemented as separate semiconductor chips. Alternatively, in some implementations, the host controller 21 and the host memory 22 may be integrated on the same semiconductor chip. As an example, the host controller 21 may be one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 22 may be an embedded memory provided in the application processor, or may be a non-volatile memory or a memory module located outside the application processor.

[0045] The memory controller 100 may include a processor 110, a scheduler 120, a host interface 130, a buffer memory 140, and a memory interface 150, which may communicate with each other through a bus 160. The processor 110 may include a CPU or a microprocessor, and may control the overall operation of the memory controller 100. In some implementations, the processor 110 may be implemented as a multi-core processor, such as a dual-core processor or a quad-core processor.

[0046] The memory controller 100 may receive a command CMD provided from the host 20 and may access the memory device 200 in response to the command CMD.

[0047] The host interface 130 may transmit and receive data packets to and from the host 20. The data packets transmitted from the host 20 to the host interface 130 may include a command CMD or data to be written to the memory device 200, and the data packets transmitted from the host interface 130 to the host 20 may include a response to a command CMD or data read from the memory device 200. The host interface 130 may receive various types of command CMDs and data regarding the command CMDs.

[0048] The memory interface 150 may transmit data to be written to the memory device 200 or receive data read from the memory device 200. This memory interface 150 may be implemented to comply with a standard protocol, such as Toggle or Open NAND Flash Interface (ONFI). The command CMD may be transmitted to the memory device 200 through the memory interface 150. As an example, the command CMD may be transmitted to the memory device 200 as a data packet.

[0049] In some implementations, the memory controller 100 may further include a packet manager, an error correction code (ECC) engine, and an advanced encryption standard (AES) engine. The packet manager may generate a packet according to a protocol of an interface negotiated with the host 20, or parse various information from a packet received from the host 20.

[0050] The ECC engine may perform an error detection and correction function on the read data read from the memory device 200. In detail, the ECC engine may generate parity bits of the write data to be stored in the memory device 200, and the parity bits generated in this manner are stored together with the write data in the memory device 200. When reading data from the memory device 200, the ECC engine may correct errors in the read data using the parity bits read from the memory device 200 together with the read data, and may output the error-corrected read data.

[0051] The AES engine may perform at least one of an encryption operation and a decryption operation on data input to the memory controller 100 using a symmetric key algorithm.

[0052] The scheduler 120 may transfer the command CMD received from the host 20 to the memory device 200. The scheduler 120 may transfer the command CMD stored in the queue to the die of the memory device 200. The scheduler 120 may generate a scheduler to transfer the command CMD to the memory device 200, and transfer the command CMD to the die corresponding to each command CMD according to the generated scheduler.

[0053] In some implementations, the scheduler 120 may control the order in which the commands CMD are transmitted to the memory device 200 based on whether there are commands CMD occupying the same die among the commands CMD stored in the queue. The memory controller 100 may generate a scheduler based on whether there are overlapping dies among the dies occupied by each command in the commands CMD stored in the queue.

[0054] In some implementations, when there are command CMDs occupying the same die among the command CMDs stored in the queue, the scheduler 120 may change the order in which the command CMDs are transmitted to the memory device 200 so that the command CMDs occupying the same die are in a continuous order. The scheduler 120 may transmit the command CMDs to the memory device 200 according to a scheduler that sets the command CMDs occupying overlapping die to be in a continuous order. When there are command CMDs occupying the same die among the plurality of command CMDs stored in the queue, but not all the command CMDs stored in the queue are command CMDs occupying the same die, the scheduler 120 may generate a scheduler so that the command CMDs occupying the same die are in a continuous order.

[0055] In some implementations, the scheduler 120 may generate a scheduler based on whether the command CMD is stored in the queue. When the command CMD is stored in the queue, the scheduler 120 may generate a scheduler so that the command CMDs occupying the same die among the command CMDs stored in the queue are in a continuous order, and the command CMDs may be transmitted to the memory device 200 according to the scheduler. If the command CMD is not stored in the queue, the scheduler 120 may determine not to generate a scheduler, for example, to bypass the generation of a scheduler. If the command CMD is not stored in the queue, the scheduler 120 does not generate a scheduler that takes into account commands occupying the same die, for example, to bypass the generation of a scheduler.

[0056] In some implementations, the scheduler 120 may transmit at least one of the commands CMD to the memory device 200 according to the scheduler based on the power comparison result. The power comparison result may be a comparison result of the total power amount of the memory device 200 and the limited power amount of the memory device 200.

[0057] If the total power amount of the memory device 200 is less than the limited power amount of the memory device 200, the scheduler 120 may transmit at least one of the commands CMD to the memory device 200 according to the scheduler. If the total power amount of the memory device 200 is less than the limited power amount of the memory device 200, the scheduler 120 may transmit the commands occupying the same die to the memory device 200 in a continuous order.

[0058] If the total power amount of the memory device 200 is greater than or equal to the limit power amount of the memory device 200, the scheduler 120 may stop transmitting the command CMD to the memory device 200. The scheduler 120 may stop transmitting at least one of the commands CMD stored in the queue to the memory device 200 according to the scheduler.

[0059] The buffer memory 140 may temporarily store data to be written to the memory device 200 or data to be read from the memory device 200. The buffer memory 140 may be provided within the memory controller 100 or may be located outside the memory controller 100. For example, the memory controller 100 may further include a buffer memory manager or a buffer memory interface for communicating with the buffer memory 140.

[0060] Figure 3 is a diagram illustrating an example of a memory device 200 .

[0061] refer to Figure 3 , the memory device 200 includes a package 210. Although Figure 3 The memory device 200 in FIG. 2 is illustrated as including one package 210 , but the memory device 200 is not limited thereto, and the memory device 200 may include a plurality of packages.

[0062] The package 210 may include a plurality of dies. The package 210 may include a first die 211 and a second die 212. Each of the first die 211 and the second die 212 may include a plurality of planes. Figure 3 It is shown that one package 210 includes two of the first die 211 and the second die 212 , but the package 210 is not limited thereto, and the package 210 may include various numbers of dies. For example, the package 210 may include four dies.

[0063] In addition, each of the first die 211 and the second die 212 may include various numbers of planes. Planes belonging to the same die (the first die 211 or the second die 212) may perform the same type of operation at the same time, and each of the first die 211 and the second die 212 may independently perform NAND operations at the same time. Figure 1 The command received by the host 20 in the embodiment of the present invention may include information about the first die 211 and the second die 212 occupied by the corresponding command. The first die 211 and the second die 212 occupied by the command may refer to the first die 211 and the second die 212 of the memory device 200 on which the command will perform a memory operation. For example, the die occupied by each of the first command and the second command may be the first die 211.

[0064] Figure 4 is a block diagram showing an example of the memory controller 100. Figure 4 The memory controller 100 and the scheduler 120 correspond to Figure 2 The memory controller 100 and the scheduler 120 are described below, so redundant descriptions thereof are omitted.

[0065] refer to Figure 4, the memory controller 100 includes a scheduler 120, a queue controller 170, and a power counter 180. The scheduler 120 can send data from a host (e.g., Figure 2 The host 20) transmits the command CMD received to the memory device 200. The scheduler 120 may generate a scheduler for transmitting the command CMD to the memory device 200 and transmit the command CMD to the dies corresponding to the command CMD respectively according to the generated scheduler.

[0066] In some implementations, the scheduler 120 may generate a scheduler to transmit the command CMDs that occupy overlapping dies among the multiple dies occupied by each command CMD in a continuous order. If there are command CMDs that occupy the same die among the command CMDs, the scheduler 120 may transmit the command CMDs that occupy the same die in a continuous order. As an example, a first command, a second command, and a third command are transmitted from the host, the first command occupies the second die, the second command occupies the first die, and the third command occupies the second die. Because the first command and the third command occupy the second die, the scheduler 120 may generate a scheduler that transmits the first command and the third command to the memory device 200 in a continuous order. The scheduler 120 may transmit the first command, the third command, and the second command to the memory device 200 in the listed order.

[0067] When there are command CMDs occupying the same die among the plurality of command CMDs stored in the queue, but not all command CMDs stored in the queue are command CMDs occupying the same die, the scheduler 120 may generate a scheduler such that the command CMDs occupying the same die are in a continuous order.

[0068] When the die occupied by each of the commands in the command CMD is the same, the scheduler 120 does not generate a scheduler that takes into account the commands occupying the same die. As an example, a first command, a second command, and a third command are transmitted from the host, and each of the first command, the second command, and the third command occupies the first die. Because the die occupied by each of the first command, the second command, and the third command is the same, the scheduler 120 does not generate a scheduler that takes into account the die.

[0069] When there is no command occupying the same die among the commands CMD, the scheduler 120 does not generate a scheduler that takes into account the commands occupying the same die. As an example, the first command, the second command, and the third command are transmitted from the host, and the first command, the second command, and the third command occupy the first die, the second die, and the third die, respectively. Because the dies occupied by the first command, the second command, and the third command are different, the scheduler 120 can determine not to generate a scheduler that takes into account the commands occupying the same die. As an example, the scheduler 120 can transmit the commands CMD to the memory device 200 in the order in which the commands CMD are transmitted to the memory controller 100. However, the present disclosure is not limited to this.

[0070] In some implementations, the scheduler 120 may generate a scheduler based on the die status information drI. The scheduler 120 may receive the die status information drI from the die. The die status information drI may be a signal indicating a ready state of a die included in the memory device 200, and may include status information of a plane included in the die. The scheduler 120 may receive a busy signal when the die is performing a separate operation and receive a ready signal when the die is not performing a separate operation. The die status information drI may include a busy signal and a ready signal.

[0071] When receiving the die status information drI of the ready signal, the scheduler 120 may generate a scheduler that transmits the commands CMD that occupy the overlapping die among the die respectively occupied by the commands CMD in a continuous order. As an example, the first command occupies the second die, the second command occupies the first die, the third command occupies the second die, and the scheduler 120 receives the ready signal of the second die. The scheduler 120 may generate a scheduler that transmits the first command and the third command to the memory device 200 in a continuous order. The scheduler 120 may transmit the first command, the third command, and the second command to the memory device 200 in the listed order. However, the inventive concept is not limited to the above examples.

[0072] When receiving the die status information drI of the busy signal, the scheduler 120 does not generate a scheduler considering the same die. As an example, upon receiving the die status information drI of the busy signal, the scheduler 120 may queue the command CMD transmitted from the host. The scheduler 120 may generate a scheduler when the die is ready and receives a ready signal.

[0073] The memory controller 100 may determine whether to store at least one command CMD received from the host in the queue. The queue controller 170 may determine whether to store the command CMD in the queue. In some implementations, the queue controller 170 may determine whether to store the command CMD in the queue based on the queue depth. The queue depth may indicate the number of commands CMD received from the host during a specific time period. The queue controller 170 may obtain information about the queue depth based on the command CMD received from the host.

[0074] In some implementations, if the queue depth of the command CMD is greater than or equal to a threshold depth, the queue controller 170 may store the command CMD in the queue. A queue depth greater than or equal to the threshold depth may correspond to a first queue depth. When the queue depth of the command CMD corresponds to the first queue depth, the queue controller 170 may store the command CMD in the queue.

[0075] As an example, the first queue depth may be a relatively high queue depth. That is, when the queue depth of the command CMD corresponds to a high queue depth, the queue controller 170 may queue the command CMD. In some implementations, a threshold depth may be pre-set in the storage device.

[0076] In some implementations, if the queue depth of the command CMD is less than the threshold depth, the queue controller 170 does not store the command CMD in the queue. The queue depth less than the threshold depth may correspond to the second queue depth. When the queue depth of the command CMD corresponds to the second queue depth, the queue controller 170 does not store the command CMD in the queue. As an example, the second queue depth may be a relatively low queue depth. That is, when the queue depth of the command CMD corresponds to a low queue depth, the queue controller 170 does not queue the command CMD. The queuing process of the command CMD may be omitted, and the command CMD may be transmitted to the memory device 200.

[0077] The power counter 180 may calculate the total power amount of the memory device 200. The total power amount of the memory device 200 may refer to the power amount currently consumed by the memory device 200. The power counter 180 may calculate the total power amount based on at least one of the type of command CMD executed by the memory device 200, the number of command CMDs, and the power amount consumed when one command CMD is executed. For example, if a memory operation corresponding to the command CMD currently executed in the memory device is added, the total power amount currently consumed by the memory device 200 may increase. When the memory operation corresponding to the command CMD executed in the memory device is completed, the total power amount may decrease.

[0078] The power counter 180 can compare the total power amount with the limit power amount and generate a power comparison result. The limit power amount can refer to the maximum power amount that the memory device 200 can consume while satisfying the reliability and stability of the memory device 200. The limit power amount can be a preset value. The power counter 180 can compare whether the total power amount is greater than or equal to the limit power amount or less than the limit power amount.

[0079] In some implementations, the scheduler 120 may generate a scheduler based on whether the command CMD is stored in the queue. When the command CMD is stored in the queue, the scheduler 120 may generate a scheduler by taking the same die into consideration. When the queue depth of the command CMD corresponds to the first queue depth, the scheduler 120 may generate a scheduler based on whether there are commands occupying the same die among the commands CMD stored in the queue.

[0080] The commands CMD are stored in the queue, and when there are commands CMD occupying the same die among the commands CMD stored in the queue, the scheduler 120 may generate a scheduler so that the commands occupying the same die are in a continuous order. The scheduler 120 may change the order in which the commands CMD are transmitted to the memory device 200 so that the commands occupying the same die are in a continuous order.

[0081] If the command CMD is not stored in the queue, the scheduler 120 does not generate a scheduler that takes into account commands occupying the same die. In some implementations, when the command CMD is not stored in the queue, the scheduler 120 may transmit the command CMD directly to the memory device 200. As an example, when the command CMD is not stored in the queue, the scheduler 120 does not change the order in which the command CMD is transmitted to the memory device 200.

[0082] In some implementations, the scheduler 120 may transmit at least one of the commands CMD to the memory device 200 according to a scheduler based on the power comparison result. For example, the scheduler 120 may receive the power comparison result from the power counter 180 and transmit the command CMD to the memory device 200 based on the power comparison result.

[0083] When the power comparison result indicates that the total power amount is less than the limited power amount of the memory device 200, the scheduler 120 may transmit the command CMD to the memory device 200 according to the generated scheduler. If the total power amount of the memory device 200 is less than the limited power amount, the scheduler 120 may transmit the commands CMD occupying the same die to the memory device 200 in a continuous order.

[0084] If the power comparison result indicates that the total power amount of the memory device 200 is greater than or equal to the limit power amount, the scheduler 120 does not transmit the command CMD to the memory device 200 according to the generated scheduler. For example, when the total power amount is greater than or equal to the limit power amount, the scheduler 120 may wait until the total power amount is less than the limit power amount before transmitting the command CMD to the memory device 200.

[0085] In some implementations, the scheduler 120 may control the order in which the commands CMD are transmitted to the memory device 200 based on the power comparison result. If the total power amount is less than the limit power amount, the scheduler 120 may control the order in which the commands CMD are transmitted based on whether there are commands CMDs occupying the same die among the commands CMDs stored in the queue.

[0086] If there are commands occupying the same die among the commands stored in the queue, the memory controller 100 may change the command transmission order so that the commands occupying the same die are in a continuous order, thereby improving the performance of the memory device.

[0087] Figure 5A is a diagram showing an example of a queue controller. In detail, Figure 5A A case is shown where the command CMD is stored in the queue 171 and the queue depth corresponds to the first queue depth. Descriptions substantially the same as those given above are omitted.

[0088] The queue controller 170 may determine whether to store the command CMD in the queue 171. In some implementations, the queue controller 170 may determine whether to store the command CMD in the queue based on the queue depth. The queue controller 170 may receive queue depth information qdi, and determine whether to store the command CMD in the queue based on the queue depth information qdi. However, the present disclosure is not limited thereto, and the queue controller 170 may obtain information about the queue depth based on the command CMD received from the host.

[0089] In some implementations, if the queue depth of the command CMD is greater than or equal to a threshold depth, the queue controller 170 may store the command CMD in the queue 171. When the queue depth of the command CMD corresponds to the first queue depth, the queue controller 170 may store the command CMD in the queue 171. The queue controller 170 may queue the command CMD. For example, the queue controller 170 may store the first command CMD1, the second command CMD2, and the third command CMD3 in the queue 171.

[0090] As an example, when the command CMD is stored in the queue 171, the queue controller 170 may generate a queuing signal qs. The queuing signal qs may refer to a signal indicating whether the command CMD is stored in the queue 171. The queue controller 170 may transmit the queuing signal qs to a scheduler (e.g., Figure 4 For example, the queue controller 170 may transmit the first level queuing signal qs to the scheduler. However, the present disclosure is not limited thereto. The scheduler may generate a scheduler based on the queuing signal qs by taking into account commands occupying the same die.

[0091] Figure 5B 1 is a diagram showing the queue controller 170. In detail, Figure 5B This refers to a case where the command CMD is not stored in the queue 171 and the queue depth corresponds to the second queue depth. Descriptions substantially the same as those given above are omitted.

[0092] In some implementations, if the queue depth of the command CMD is less than the threshold depth, the queue controller 170 does not store the command CMD in the queue 171. If the queue depth of the command CMD corresponds to the second queue depth, the queue controller 170 does not store the command CMD in the queue 171. The queuing process of the command CMD may be omitted, and the command CMD may be transmitted to the memory device.

[0093] As an example, the queue controller 170 may generate a queuing signal qs when the command CMD is not stored in the queue 171. The queuing signal qs indicating that the command CMD is not stored in the queue 171 may be at a different level from the queuing signal indicating that the command CMD is stored in the queue 171. For example, the queue controller 170 may transmit the second level queuing signal qs to the scheduler. However, the present disclosure is not limited thereto. The queue controller 170 may be implemented so that the queuing signal qs is not generated when the command CMD is not stored in the queue 171.

[0094] When the queue depth corresponds to a relatively low queue depth, commands are not stored in the queue and may be transmitted to the memory device, thereby reducing latency in processing commands received from the host.

[0095] Figure 6 1 is a diagram showing an example of the operation of the scheduler 120. In detail, Figure 6 FIG. 1 shows a case where the memory controller 100 receives a read command. Figure 6 In the process, the command CMD is stored in the queue 171. Descriptions substantially the same as those given above are omitted.

[0096] refer to Figure 6, the memory controller 100 may receive a command CMD from the host. As an example, each command CMD may be a single plane command occupying one plane. The command CMD may include a first read command RCMD_p18, a second read command RCMD_p23, a third read command RCMD_p41, and a fourth read command RCMD_p45. The memory controller 100 may receive the first read command RCMD_p18, the second read command RCMD_p23, the third read command RCMD_p41, and the fourth read command RCMD_p45 in the order listed.

[0097] First, second, third, and fourth read commands RCMD_p18, RCMD_p23, RCMD_p41, and RCMD_p45 may be stored in the queue 171. Although the memory controller 100 is described as receiving four read commands, this is only for convenience of description, and the memory controller 100 may receive various numbers of commands CMD.

[0098] The memory device 200 includes a first die 211 and a second die 212. The first die 211 may include a first plane Pl1, a second plane Pl2, a third plane Pl3, and a fourth plane Pl4. The first plane Pl1 may include page 0, page 8, page 16, page 24, page 32, and page 40. Similarly, each of the second plane Pl2, the third plane Pl3, and the fourth plane Pl4 may include Figure 6 The multiple pages shown in .

[0099] The second die 212 may include a fifth plane P15, a sixth plane P16, a seventh plane P17, and an eighth plane P18. The fifth plane P15 may include pages 4, 12, 20, 28, 36, and 44. Similarly, each of the sixth plane P16, the seventh plane P17, and the eighth plane P18 may include Figure 6 The multiple pages shown in .

[0100] The scheduler 120 may control the order in which the commands CMD are transmitted to the memory device 200 based on whether there are commands occupying the same die among the commands CMD stored in the queue 171. The scheduler 120 may determine whether there are commands CMD occupying the same die among the commands CMD stored in the queue 171.

[0101] The first read command RCMD_p18 may perform a memory operation on page 18, and the first read command RCMD_p18 may occupy the first die 211. The second read command RCMD_p23 may perform a memory operation on page 23 and may occupy the second die 212. The third read command RCMD_p41 may perform a memory operation on page 41 and may occupy the first die 211. The fourth read command RCMD_p45 may perform a memory operation on page 45 and may occupy the second die 212. Because the first read command RCMD_p18 and the third read command RCMD_p41 occupy the first die 211, the scheduler 120 may determine that the first read command and the third read command occupy the same die, and because the second read command RCMD_p23 and the fourth read command RCMD_p45 occupy the second die 212, the scheduler 120 may determine that the second read command and the fourth read command occupy the same die.

[0102] If there are commands CMDs occupying the same die among the commands CMDs stored in the queue 171, and not all the commands CMDs stored in the queue 171 occupy the same die, the scheduler 120 may change the order in which the commands CMDs are transmitted to the memory device 200 so that the commands CMDs are in a continuous order. Because the first read command RCMD_p18 and the third read command RCMD_p41 occupy the same first die 211, the first read command RCMD_p18 and the third read command RCMD_p41 may be transmitted to the memory device 200 in a continuous order.

[0103] As an example, the scheduler 120 may transmit the first read command RCMD_p18, the third read command RCMD_p41, the second read command RCMD_p23, and the fourth read command RCMD_p45 in the listed order to the memory device 200. The memory controller 100 may control the command transmission order so that the commands occupying the same die are in a continuous order, so that the instantaneous power consumption rate of the memory device can be reduced and the performance of the memory device can be improved.

[0104] Figure 7 1 is a diagram showing an example of the operation of the scheduler 120 according to the command type. In detail, Figure 7 FIG. 1 shows a case where the memory controller 100 receives a read command and a write command. Figure 7 In the example of FIG. 1 , command CMD is stored in queue 171. Figure 6 Descriptions given that are substantially the same are omitted.

[0105] refer to Figure 7, the command CMD may include a first read command RCMD_p18, a second write command WCMD_p11, a third read command RCMD_p41, and a fourth read command RCMD_p45. The memory controller 100 may receive the first read command RCMD_p18, the second write command WCMD_p11, the third read command RCMD_p41, and the fourth read command RCMD_p45 in the listed order. The first read command RCMD_p18, the second write command WCMD_p11, the third read command RCMD_p41, and the fourth read command RCMD_p45 may be stored in the queue 171.

[0106] The scheduler 120 may control the order in which the commands CMD are transmitted to the memory device 200 based on whether there are commands occupying the same die among the commands CMD stored in the queue 171. The scheduler 120 may determine whether there are commands CMD occupying the same die among the commands CMD stored in the queue 171. The scheduler 120 may determine that the first read command RCMD_p18, the second write command WCMD_p11, and the third read command RCMD_p41 occupy the first die 211.

[0107] In some implementations, the scheduler 120 may change the order in which the commands CMD are transmitted to the memory device 200 so that the commands CMD occupying the same die have the same command type in a continuous order. The command type may include a read command, a write command, etc. The first read command RCMD_p18, the second write command WCMD_p11, and the third read command RCMD_p41 occupy the same first die 211, but the second write command WCMD_p11 is a write command, and the command type of the second write command WCMD_p11 may be different from the command type of the first read command RCMD_p18 and the third read command RCMD_p41.

[0108] The scheduler 120 may transmit the first read command RCMD_p18 and the third read command RCMD_p41 having the same command type in a consecutive order to the memory device 200. As an example, the scheduler 120 may transmit the first read command RCMD_p18, the third read command RCMD_p41, the second write command WCMD_p11, and the fourth read command RCMD_p45 to the memory device 200 in the listed order.

[0109] Fig. 8A is a diagram showing an example of the power counter 180. Descriptions substantially the same as those given above are omitted.

[0110] The power counter 180 may calculate the total power amount TP of the memory device 200. The total power amount TP of the memory device 200 may refer to the power amount currently consumed by the memory device 200. The power counter 180 may calculate the total power amount TP of the memory device 200 based on the power information pi. The power information pi may include the type of command CMD, the number of command CMDs, and the amount of power consumed by the memory device 200 when one command CMD is executed. In some implementations, the power counter 180 may calculate the total power amount TP of the memory device 200 based on at least one of the type of command CMD executed in the memory device 200, the number of command CMDs, and the amount of power consumed when one command CMD is executed. For example, the power counter 180 may calculate the total power amount TP of the memory device 200 by multiplying the number of command CMDs by the amount of power consumed when each command CMD is executed according to the type of the command CMD.

[0111] The power counter 180 may compare the total power amount TP with the limited power amount LP and generate a power comparison result pr. The limited power amount LP may refer to the maximum power amount that the memory device 200 may consume while satisfying the reliability and stability of the memory device 200. The limited power amount LP may be a preset value. The power counter 180 may compare whether the total power amount TP is greater than or equal to the limited power amount LP, or compare whether the total power amount is less than the limited power amount LP.

[0112] The power counter 180 may transmit the power comparison result pr to the scheduler 120. When the total power amount TP is less than the limit power amount LP, the power comparison result pr may include a signal indicating the corresponding fact. For example, the power comparison result pr may include a first signal. When the total power amount TP is greater than or equal to the limit power amount LP, the power comparison result pr may include a signal indicating the corresponding fact. For example, the power comparison result pr may include a second signal.

[0113] The scheduler 120 may transmit the commands CMD to the memory device 200 based on the total power amount TP. The scheduler 120 may transmit at least one of the commands CMD to the memory device 200 according to a scheduler based on the power comparison result pr. In some implementations, when the power comparison result pr indicates that the total power amount TP of the memory device 200 is less than the limit power amount LP, the scheduler 120 may transmit the commands CMD to the memory device 200 according to a scheduler generated by taking into account commands occupying the same die. If the total power amount TP of the memory device 200 is less than the limit power amount LP, the scheduler 120 may transmit the commands CMD occupying the same die to the memory device 200 in a consecutive order.

[0114] As an example, even if the scheduler 120 fails to generate a schedule considering commands occupying the same die, the scheduler 120 does not follow the schedule based on the power comparison result pr and transmits the command CMD to the memory device 200 .

[0115] In some implementations, the scheduler 120 may control the order in which the commands CMD are transmitted to the memory device 200 based on the power comparison result pr. If the total power amount TP is less than the limit power amount LP, the scheduler 120 may generate a scheduler by considering commands occupying the same die.

[0116] When the command CMD is transmitted to the memory device 200, the total power amount TP of the memory device 200 may increase. When a memory operation corresponding to each command CMD executed in the memory device 200 is completed, the total power amount TP of the memory device may decrease.

[0117] Figure 8B is a diagram showing the power counter 180 . Figure 8B 2 shows a case where the command CMD is not transmitted to the memory device 200. Fig. 8A Descriptions given that are substantially the same are omitted.

[0118] The scheduler 120 may transmit the command CMD to the memory device 200 based on the total power amount TP of the memory device 200. In some implementations, when the power comparison result pr indicates that the total power amount TP of the memory device 200 is greater than or equal to the limit power amount LP of the memory device 200, the scheduler 120 may stop transmitting the command CMD to the memory device 200 according to a scheduler generated by taking into account commands occupying the same die. For example, when the total power amount TP of the memory device 200 is greater than or equal to the limit power amount LP, the scheduler 120 may wait until the total power amount TP is less than the limit power amount LP before transmitting the command CMD to the memory device 200.

[0119] In some implementations, the scheduler 120 may control the order in which the commands CMD are transmitted to the memory device 200 based on the power comparison result pr. When the total power amount TP is greater than or equal to the limit power amount LP, the scheduler 120 does not control the order in which the commands are transmitted based on whether there are commands CMD occupying the same die among the commands CMD stored in the queue. That is, when the total power amount TP is greater than or equal to the limit power amount LP, the scheduler 120 does not generate a scheduler that takes into account commands occupying the same die.

[0120] Fig. 9 is a flowchart showing an example of an operation method of a memory controller. Descriptions substantially the same as those given above are omitted.

[0121] In operation S910, the memory controller may receive at least one command. The memory controller may receive the command from a host.

[0122] In operation S920, the memory controller may determine whether to store the command in the queue. In some implementations, the memory controller may determine whether to store the command in the queue based on the queue depth. The queue depth may indicate the number of commands received from the host during a specific time period.

[0123] In operation S930, the memory controller may generate a scheduler based on whether the plurality of commands are stored in the queue and whether there are overlapping dies among the plurality of dies respectively occupied by the commands stored in the queue. When the commands are stored in the queue, the memory controller may generate a scheduler based on whether there are overlapping dies among the dies respectively occupied by the commands stored in the queue.

[0124] In some implementations, the memory controller may control the order in which commands are transmitted to the memory device based on whether there are commands occupying the same die among the commands stored in the queue. The memory controller may generate a scheduler based on whether there are overlapping dies among the dies respectively occupied by the commands stored in the queue. Controlling the order may include changing the order and not changing the order.

[0125] In some implementations, if there are commands occupying the same die among the plurality of commands stored in the queue, the memory controller may change the order in which the commands are transmitted to the memory device so that the commands occupying the same die are in a continuous order. If there are commands occupying the same die among the plurality of commands stored in the queue, but not all commands stored in the queue are commands occupying the same die, the memory controller may generate a scheduler so that the commands occupying the same die are in a continuous order.

[0126] In operation S940, the memory controller may transmit at least one of the at least one command to the memory device according to a scheduler. The memory controller may transmit the command to the memory device according to a scheduler that sets commands occupying overlapping dies in a sequential order.

[0127] In some implementations, the memory controller may transmit at least one of the commands to the memory device according to a scheduler based on a power comparison result. The power comparison result may be a comparison result between a total power amount of the memory device and a limited power amount of the memory device.

[0128] Fig.10 is a flow chart illustrating an example of a method in which a memory controller determines whether to store a command in a queue. Fig.10 The operations can be included in Fig. 9 In operation S920. In detail, Fig.10 It is shown Figure 4 Flow chart of the operating method of the queue controller 170.

[0129] In operation S1010, the memory controller may receive queue depth information. The memory controller may determine whether to store a command in a queue based on the queue depth information. The queue depth may indicate the number of commands received from the host during a specific time period. The memory controller may obtain the queue depth information based on the command received from the host.

[0130] In operation S1020, the memory controller may determine whether the queue depth is greater than or equal to a threshold depth. If the queue depth is greater than or equal to the threshold depth, the memory controller may perform operation S1030, and if the queue depth is less than the threshold depth, the memory controller may perform operation S1040. In some implementations, the threshold depth may be pre-set in the storage device.

[0131] In operation S1030, if the queue depth of the command is equal to or greater than the threshold depth, the memory controller may store the command in the queue. Once the command is stored in the queue, the memory controller may generate a scheduler by taking into account commands occupying the same die.

[0132] In operation S1040, if the queue depth of the command is less than the threshold depth, the memory controller does not store the command in the queue. The queuing process of the command may be omitted, and the command may be transmitted to the memory device.

[0133] Fig.11 is a flowchart showing an example of a method for a memory controller to generate a scheduler. Fig.11 The operation in Fig. 9 Operations S930 and S940 in the Fig.11 In the READY state, the commands are stored in a queue. The memory controller can receive die status information in the READY state.

[0134] In operation S1110, the memory controller may determine whether there are overlapping dies among the dies respectively occupied by the commands stored in the queue, and whether all the commands occupy the same die. For example, a first read command, a second read command, and a third read command are stored in the queue, the first read command occupies the first die, the second read command occupies the second die, and the third read command occupies the first die. The first die may correspond to a die occupied by the first read command and the third read command overlapping. If there are overlapping dies among the dies respectively occupied by the commands stored in the queue, the memory controller may perform operation S1120, and if there are no overlapping dies, the memory controller may perform operation S1130.

[0135] In operation S1120, if there are commands occupying the same die among the commands stored in the queue, but not all commands stored in the queue are commands occupying the same die, the memory controller may generate a scheduler so that the commands occupying the same die are in a continuous order. If all commands stored in the queue do not occupy the same die, the memory controller may generate a scheduler that sets the commands occupying overlapping die in a continuous order. For example, because the first read command and the third read command occupy the first die, the memory controller may generate a scheduler that sets the first read command and the third read command in a continuous order.

[0136] In operation S1130 , the memory controller does not generate a scheduler that sets commands occupying overlapping dies in a sequential order.

[0137] In operation S1140, the memory controller may determine whether the total power amount is less than the limited power amount. The total power amount of the memory device may refer to the power amount currently consumed by the memory device. The limited power amount may refer to the maximum power amount that the memory device can consume while satisfying the reliability and stability of the memory device. The limited power amount may be a preset value. The memory controller may calculate the total power amount of the memory device based on the power information.

[0138] In operation S1150, when the total power amount of the memory device is less than the limit power amount, the memory controller may transmit the command to the memory device. When operation S1120 is performed, if the total power amount of the memory device is less than the limit power amount, the memory controller may transmit the command to the memory device according to a scheduler that sets the commands occupying overlapping dies in a continuous order. That is, if the total power amount of the memory device is less than the limit power amount, the memory controller may transmit the command to the memory device according to the scheduler generated in operation S1120.

[0139] If the total power amount of the memory device is less than the limit power amount, the memory controller may transmit the commands occupying the overlapping dies to the memory device in a continuous order. As an example, because the first read command and the third read command occupy the first die, the memory controller may transmit the first command, the third command, and the second command to the memory device in the listed order.

[0140] When performing operation S1130, because the memory controller does not generate a scheduler that sets the commands occupying overlapping dies in a continuous order, if the total power amount of the memory device is less than the limit power amount, the memory controller may transmit the commands to the memory device without following the scheduler. For example, the memory controller may transmit the commands to the memory device in the order in which the commands are received from the host.

[0141] If the total power amount of the memory device is greater than or equal to the limit power amount, the memory controller may perform operation S1110 again. If the total power amount of the memory device is greater than or equal to the limit power amount, the memory controller may regenerate the scheduler.

[0142] Fig.12 An example of a system 1000 using a storage device is shown. Fig.12 The system 1000 may be a mobile system, such as a mobile phone, a smart phone, a tablet personal computer, a wearable device, a medical device, or an Internet of Things (IoT) device. However, Fig.12 The system 1000 is not limited to a mobile system, but may include a personal computer, a laptop computer, a server, a media player, or an automotive device such as a navigation device.

[0143] refer to Fig.12 , system 1000 includes a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b, and may further include one or more of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0144] The main processor 1100 may control the overall operation of the system 1000, and in detail, control the operations of other components forming the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

[0145] The main processor 1100 may include one or more CPU cores 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some implementations, the main processor 1100 may also include an accelerator 1130, which is a dedicated circuit for high-speed data calculations such as artificial intelligence (AI) data calculations. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may also be implemented as a separate chip physically independent of other components of the main processor 1100.

[0146] Memories 1200a and 1200b may be used as main memory devices of system 1000 and may include volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or resistive random access memory (RRAM). Memories 1200a and 1200b may also be implemented in the same package as main processor 1100.

[0147] The storage devices 1300a and 1300b may function as nonvolatile storage devices that store data regardless of whether power is supplied or not, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b, and nonvolatile memories (NVM) 1320a and 1320b that store data under the control of the storage controllers 1310a and 1310b. The nonvolatile memories 1320a and 1320b may include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) vertical NAND (V-NAND) structure, but may also include other types of nonvolatile memories such as PRAM and / or RRAM. The above reference Figures 1 to 11 The storage device described (for example, Figure 1 The storage device 10) can be applied to Fig.12 Storage devices 1300a and 1300b in.

[0148] The storage devices 1300a and 1300b may be included in the system 1000 in a state physically separated from the main processor 1100, or may be implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may have a form such as a solid-state device (SSD) or a memory card, and may be detachably coupled to other components of the system 1000 through an interface, such as a connection interface 1480 to be described below. Such storage devices 1300a and 1300b may be devices to which a standard protocol (such as UFS, eMMC, or NVMe) is applied, but are not limited thereto.

[0149] The image capture device 1410 may capture still images or moving images, and may be a camera, a video camera, and / or a webcam. The user input device 1420 may receive various types of data input from a user of the system 1000, and may include a touch pad, a keypad, a keyboard, a mouse, and / or a microphone, etc. The sensor 1430 may detect various types of physical quantities that may be obtained from the outside of the system 1000, and convert the sensed physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, an illumination sensor, a position sensor, an acceleration sensor, a biosensor, and / or a gyroscope sensor.

[0150] The communication device 1440 may transmit and receive signals to and from other devices outside the system 1000 according to various communication protocols. The communication device 1440 may be implemented to include an antenna, a transceiver, and / or a modem. The display 1450 and the speaker 1460 may serve as output devices that output visual information and auditory information to a user of the system 1000, respectively. The power supply device 1470 may appropriately convert power supplied from a battery (not shown) built into the system 1000 and / or an external power source, and supply power to each component of the system 1000.

[0151] The connection interface 1480 may provide a connection between the system 1000 and an external device connected to the system 1000, and may exchange data with the system 1000. The connection interface 1480 may be implemented by various interface methods, such as an Advanced Technology Attachment (ATA) device, Serial ATA (SATA), external SATA (e-SATA), SCSI, Serial Attached SCSI (SAS), PCI, PCI Express (PCIe), NVMe, IEEE 1394, USB, SD card, MMC, eMMC, UFS, embedded Universal Flash (eUFS), CF card interface, etc.

[0152] Although the present disclosure includes many specific implementation details, these should not be interpreted as limiting the scope of the claimed protection. Certain features described in the context of separate implementations in the present disclosure may also be implemented in combination in a single implementation. On the contrary, various features described in the context of a single implementation may also be implemented in multiple implementations individually or in any suitable sub-combination. In addition, although features may be described as working in certain combinations, one or more features from the combination may be removed from the combination in some cases, and the combination may be directed to a sub-combination or a variation of the sub-combination.

[0153] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, the storage device communicating with a host, the storage device comprising: a memory device comprising a plurality of dies; as well as a memory controller configured to receive at least one command from the host and transmit the at least one command to the memory device, The memory controller is further configured to store commands received from the host in a queue, and The memory controller is further configured to: when a first group of commands among the commands stored in the queue occupy a same die, change the order in which the commands stored in the queue are transmitted to the memory device.

2. The storage device according to claim 1, wherein: The memory controller is further configured to, when the first set of commands occupy the same die, change the order in which the commands are transmitted to the memory device so that the commands occupying the same die are in a sequential order.

3. The storage device according to claim 2, wherein: The memory controller is further configured to change the order so that commands of the same command type among the commands occupying the same die are in a consecutive order.

4. The storage device according to claim 1, wherein: The memory controller is further configured to determine whether to store the at least one command received from the host in the queue based on a queue depth.

5. The storage device according to claim 4, wherein: The memory controller is further configured to, in response to a queue depth of the at least one command corresponding to a first queue depth, store the command in the queue and change an order of the commands stored in the queue.

6. The storage device according to claim 5, wherein: The memory controller is further configured to, in response to a queue depth of the at least one command corresponding to a second queue depth that is less than the first queue depth, transmit the at least one command directly to the memory device.

7. The storage device according to claim 1, wherein: The memory controller is further configured to calculate a total power amount of the memory device and transmit the commands stored in the queue to the memory device in a changed order based on the total power amount of the memory device.

8. The storage device according to claim 7, wherein: The memory controller is further configured to, in response to the total power amount of the memory device being less than a limited power amount of the memory device, transmit at least one of the commands stored in the queue to the memory device in the changed order.

9. The storage device according to claim 1, wherein: The memory controller is further configured to compare a total power amount of the memory device with a limited power amount of the memory device, and change the order in response to the presence of commands occupying the same die among the commands stored in the queue according to the comparison result.

10. The storage device according to claim 1, wherein: The memory controller is further configured to receive die status information from the memory device and to change the order based on the die status information.

11. A memory controller, the memory controller comprising: a queue controller configured to determine whether to store a command received from a host in a queue based on a queue depth; a scheduler configured to generate a scheduler for providing the command to a memory device including the plurality of dies based on whether there are overlapping dies among the plurality of dies respectively occupied by the commands stored in the queue and whether the command is stored in the queue; as well as a power counter configured to compare a total power amount of the memory device with a limited power amount of the memory device and generate a power comparison result, The scheduler is further configured to transmit at least one of the commands to the memory device according to the scheduling procedure based on the power comparison result.

12. The memory controller according to claim 11, wherein: The scheduler is configured to place the commands occupying overlapping die in a sequential order in response to the commands being provided to the memory device.

13. The memory controller according to claim 11, wherein: The queue controller is further configured to store the command received from the host in the queue in response to the queue depth of the command received from the host being greater than or equal to a threshold depth, and The scheduler is further configured to generate the scheduler based on whether there are overlapping dies.

14. The memory controller according to claim 11, wherein: The queue controller is further configured to not perform storing the command received from the host in the queue in response to the queue depth of the command received from the host being less than a threshold depth.

15. The memory controller according to claim 11, wherein: The power counter calculates the total amount of power based on a type of commands executed by the memory device and a number of commands executed by the memory device.

16. The memory controller according to claim 11, wherein: The scheduler is further configured to: when the power comparison result is that the total power amount is less than the limit power amount, transmit at least one of the commands stored in the queue according to the scheduling procedure.

17. The memory controller according to claim 11, wherein: The scheduler is further configured to, in response to the power comparison result being that the total power amount is greater than or equal to the limit power amount, stop transmitting at least one of the commands stored in the queue to the memory device according to the scheduler.

18. The memory controller according to claim 11, wherein: The scheduler is further configured to: in response to the power comparison result being that the total power amount is greater than or equal to the limit power amount, regenerate the scheduler.

19. A method for operating a memory controller, the method comprising: receiving at least one command from a host; determining whether to store the at least one command in a queue; generating a scheduler for providing the command to a memory device based on whether the command is stored in the queue and whether there are overlapping dies among a plurality of dies respectively occupied by the commands stored in the queue; as well as At least one of the commands is transmitted to the memory device according to the scheduler.

20. The operating method according to claim 19, wherein: The scheduler is configured to place the commands occupying overlapping die in a sequential order in response to the commands being provided to the memory device.

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