FPGA-based multi-channel low-pass filtering operation resource optimization method
By optimizing the multi-channel low-pass filtering algorithm in FPGA, transfer filter coefficient operation and using multiplication rotation algorithm, the problem of limited FPGA operation resources is solved, and efficient multi-channel low-pass filtering is realized, meeting the current loop operation requirements of six-axis drive-control integrated.
Patent Information
- Application Number
- CN202510083707.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-20
- Publication Date
- 2025-05-23
AI Technical Summary
In the integrated drive and control technology, FPGA is difficult to meet the needs of multi-channel low-pass filtering due to limited computing resources, resulting in limited current loop computing.
By optimizing multi-channel low-pass filtering algorithms, including transferring the filter coefficients to the ARM side, simplifying the FPGA's computing tasks, and reducing the FPGA's computing resources through multiplication and data amplification and reduction.
It realizes efficient multi-channel low-pass filtering operation in limited FPGA computing resources, significantly reducing the use of computing resources, and meeting the current loop computing requirements of six-axis drive-control integrated.
Smart Images
Figure CN120029583A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated drive and control technology, and in particular to a method for optimizing computing resources of multi-channel low-pass filtering based on FPGA. Background Art
[0002] As far as the inventors know, in the field of integrated drive and control technology, in order to integrate multi-motor servo control and robot control into a system framework, Zynq7020 can be selected as the main control chip, which includes a processor system and a programmable logic system, integrating the ARM dual-core cortex-A9 processor and the Xilinx7 series FPGA architecture. Therefore, Zynq7020 has huge advantages in energy consumption, performance, cost and compatibility as a main control MCU for integrated drive and control. Therefore, one chip can control multiple motors. ARM has powerful floating-point computing capabilities and is good at handling complex mathematical operations and data processing. It is usually used to control the position loop and speed loop of servo control. FPGA has high-speed response capabilities due to its parallel computing characteristics, and is usually used for servo current loop control and protection signal monitoring.
[0003] Taking the six-axis integrated drive control as an example, the FPGA needs to be responsible for the current loop operation of the six axes. Each axis needs to collect the current of the U phase and the W phase to perform the current loop operation, and the current sampling is easily affected by environmental factors such as temperature and magnetic field, which causes the current sampling to be interfered and burred. In order to solve the problem of current interference and burrs, a low-pass filter is usually added to each current sample. Therefore, each motor requires two low-pass filters. Based on this calculation, six motors require twelve low-pass filters. However, FPGA does not have a large number of DSP resources, cannot perform a large number of mathematical operations, and often cannot meet the use requirements of the current loop. Summary of the invention
[0004] The problem to be solved by the present invention is to provide a computing resource optimization method for multi-channel low-pass filtering based on FPGA. By using the resource optimization method, the use of computing resources for multi-channel low-pass filtering can be greatly reduced.
[0005] To solve the above problems, the present invention provides a method for optimizing computing resources of multi-channel low-pass filtering based on FPGA. To achieve the above objectives, the technical solution adopted by the present invention to solve the technical problems is:
[0006] A method for optimizing computing resources of multi-channel low-pass filtering based on FPGA, comprising:
[0007] The transfer function of RC low-pass filter is:
[0008] in is the model constant, fhz is the low-pass filter cutoff frequency;
[0009] After discretization, we get
[0010] Where dt is the time period constant, is the filter coefficient;
[0011] Among them, formula A is simplified to transfer some calculation tasks; and / or the alpha data in formula A is first enlarged and then reduced to eliminate floating-point operations; and / or formula A is subjected to a multiplication round-robin operation algorithm to separate the multiplication operation into a common algorithm block.
[0012] As a further improvement of the present invention, the calculation of the alpha filter coefficient is transferred to the ARM side, and the FPGA is only responsible for the iterative calculation of the cycle, so the low-pass filter calculation formula is simplified to Formula B:
[0013] y(t)=alpha*(x(t)-y(t-1))+y(t-1).
[0014] As a further improvement of the present invention, the alpha filter coefficient is scaled by a factorial of 2 when it is calculated on the ARM side.
[0015] As a further improvement of the present invention, the alpha filter coefficient is first amplified by 2 N times, FPGA
[0016] After calculating formula B, reduce the result by 2 N times, and the value range of N is 20 to 26.
[0017] As a further improvement of the present invention, the alpha data is first amplified and then reduced to eliminate the floating point operation formula:
[0018] y(t)=(alpha*(x(t)-y(t-1))+y(t-1)<<23)>>23.
[0019] As a further improvement of the present invention, the algorithm block expression of the multiplication round sequence algorithm is:
[0020] y_temp=alpha*(xy).
[0021] As a further improvement of the present invention, formula D sets a state machine, starts the state machine accumulation at the beginning of the cycle, and when the state machine is an even number, the channel data is calculated by the algorithm block. When the state machine state is an odd number, the algorithm block outputs the calculation result to complete the subsequent iterative calculation.
[0022] As a further improvement of the present invention, Formula A is modeled on a 24-bit wide RC low-pass filter.
[0023] The beneficial technical effect of the computing resource optimization method of the FPGA-based multi-channel low-pass filtering of the present application is: using the resource optimization method of the present invention can greatly reduce the use of computing resources for multi-channel low-pass filtering. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0025] Figure 1 is a code block diagram of an embodiment of the present invention;
[0026] Figure 2 It is a code block diagram of an implementation mode of the present invention. DETAILED DESCRIPTION
[0027] The present invention is further described in detail below in conjunction with specific embodiments:
[0028] In order to achieve the purpose of the present invention, the purpose of the present invention is to provide a computing resource optimization method for multi-channel low-pass filtering based on FPGA based on a 24-bit wide RC low-pass filter model in view of the shortcomings of the prior art.
[0029] The transfer function of RC low-pass filter is:
[0030] in is the model constant, and fhz is the low-pass filter cutoff frequency.
[0031] After discretization, we get
[0032] Where dt is the time period constant, is the filter coefficient.
[0033] Optimization method 1: Simplify the formula and transfer some calculation tasks.
[0034] Among them, (Formula A) contains multiple division and multiplication operations, and the alpha filter coefficient is just a constant calculation. There is no requirement for the calculation speed and calculation cycle. Therefore, in order to reduce the calculation task of FPGA, the calculation of alpha filter coefficient is transferred to ARM side, and FPGA is only responsible for the iterative calculation of the cycle. Therefore, the low-pass filter calculation formula is simplified to (Formula B).
[0035] y(t)=alpha*(x(t)-y(t-1))+y(t-1)(Formula B)
[0036] The simplified calculation formula only includes one multiplication operation, one subtraction operation and one addition operation, which greatly reduces the calculation pressure of FPGA.
[0037] Optimization method 2: Enlarge the data first and then reduce it to eliminate floating-point operations.
[0038] The alpha filter coefficient is a floating point type with a value less than 1. However, the FPGA cannot handle floating point operations. The 2 factorial scaling method is used, taking the 23rd power as an example. Therefore, when calculating on the ARM side, the alpha filter coefficient is first scaled by 2. 23 After the FPGA finishes the calculation (Formula B), it reduces the result by 2 23
[0039] The scaling method of 2 factorial can avoid division operation. For details, see (Formula C). y(t)=(alpha*(x(t)-y(t-1))+y(t-1)<<23)>>23(Formula C)
[0040] According to the code diagram of optimization method 1 and optimization method 2, Figure 1 shown.
[0041] Figure 1 An operation is performed in each enable cycle.
[0042] The resources occupied after compilation are shown in the following table:
[0043]
[0044] Optimization method three: multiplication round-order operation method.
[0045] In order to reduce the occupation of DSP resources, the multiplication operation is separated into a common algorithm block, and its algorithm block expression is y_temp = alpha*(xy) (Formula D). In order to enable all channels to perform operations in turn without conflict, a state machine is set, and the state machine accumulation is started at the beginning of the cycle. When the state machine is an even number, the channel data is calculated by the algorithm block. When the state machine state is an odd number, the algorithm block outputs the calculation result to complete the subsequent iterative calculation. Its code block diagram is as follows Figure 2 shown.
[0046] The resources occupied after compilation are shown in the following table:
[0047]
[0048] The beneficial effect of adopting the above technical solution is: the 24-bit 12-channel low-pass filtering algorithm performs the calculation task transfer, so that the 24-bit 12-channel low-pass filtering only needs to occupy 588 logic resources and 24 calculation resources, and then the round-robin operation algorithm is used to reduce the occupation of FPGA calculation resources, and after optimization, 868 logic resources and 2 calculation resources are occupied. Using the resource optimization method of the present invention, the use of calculation resources for multi-channel low-pass filtering can be greatly reduced.
[0049] The above embodiments are only for illustrating the technical concept and features of the present invention, and their purpose is to enable people familiar with this technology to understand the content of the present invention and implement it. They cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be included in the protection scope of the present invention.
Claims
1. A method for optimizing computing resources of multi-channel low-pass filtering based on FPGA, characterized in that: include: The transfer function of RC low-pass filter is: in is the model constant, fhz is the low-pass filter cutoff frequency; After discretization, we get Where dt is the time period constant, is the filter coefficient; Wherein, formula simplification is performed on the formula A to transfer some calculation tasks; and / or The alpha data in the formula A is first enlarged and then reduced to eliminate floating point operations; and / or The formula A performs a multiplication round-robin algorithm, and separates the multiplication operation into a common algorithm block.
2. The method for optimizing computing resources of multi-channel low-pass filtering based on FPGA according to claim 1, characterized in that: The calculation of the alpha filter coefficient is transferred to the ARM side, and the FPGA is only responsible for the iterative calculation of the cycle, so the low-pass filter calculation formula is simplified to formula B: y(t)=alpha*(x(t)-y(t-1))+y(t-1). (Formula B) 3. The method for optimizing computing resources of multi-channel low-pass filtering based on FPGA according to claim 1, characterized in that: The alpha filter coefficients are scaled by the factorial of 2 when calculated on the ARM side.
4. The method for optimizing computing resources of multi-channel low-pass filtering based on FPGA according to claim 3, characterized in that: First, enlarge the alpha filter coefficient by 2 N After FPGA finishes calculating formula B, it reduces the result by 2 N times, and the range of N is 20 to 26.
5. The method for optimizing computing resources of multi-channel low-pass filtering based on FPGA according to claim 4, characterized in that: The alpha data is first enlarged and then reduced to eliminate floating point operations. The formula is: y(t)=(alpha*(x(t)-y(t-1))+y(t-1)<<23)>>23. (Formula C) 6. The method for optimizing computing resources of multi-channel low-pass filtering based on FPGA according to claim 1, characterized in that: The algorithm block expression of the multiplication round sequence algorithm is: y_temp=alpha*(xy). (Formula D) 7. The method for optimizing computing resources of multi-channel low-pass filtering based on FPGA according to claim 6, characterized in that: The formula D sets a state machine, starts the state machine accumulation at the beginning of the cycle, and when the state machine is an even number, the channel data is calculated by the algorithm block. When the state machine state is an odd number, the algorithm block outputs the calculation result to complete the subsequent iterative calculation.
8. The method for optimizing computing resources of multi-channel low-pass filtering based on FPGA according to claim 1, characterized in that: Formula A is modeled with a 24-bit wide RC low-pass filter.