Cyclic jump direction prediction and update system

Abstract

The invention relates to the technical field of computers, in particular to a cyclic jump direction predicting and updating system. The loop jump direction predicting and updating system at least comprises an instruction fetching unit, a branch processing operation unit and a processing unit which are in signal connection with one another, and the instruction fetching unit is used for obtaining a corresponding instruction code from a pre-configured register according to an instruction fetching address and sending the instruction code to the processing unit; the instruction fetching address is sent to the branch processing operation unit; the branch processing operation unit is used for predicting a cyclic branch jump direction according to the instruction fetching address and a pre-configured branch jump mode historical index table, and outputting a target jump prediction direction; and the processing unit is used for updating the prediction parameters of the branch processing operation unit according to the instruction code and the target jump prediction direction. The invention provides a cyclic jump direction predicting and updating system with higher accuracy.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular, to a loop jump direction prediction and updating system. Background Art

[0002] Branch prediction requires predicting the jump direction and jump address of the jump instruction. The prediction of the jump direction is usually divided into static prediction and dynamic prediction. Dynamic prediction of jump direction is generally applied to complex processors and is generally implemented using a saturation counter.

[0003] The most widely used saturation counter is the "2-bit saturating counter" as a branch "direction" dynamic predictor. The 2-bit saturating counter uses a 2-bit saturating counter to mark the historical state for each branch instruction, such as a conditional jump instruction. When a jump is encountered, the counter is incremented by 1, and when a non-jump is encountered, the counter is decremented by 1. Finally, the prediction is made based on the value of the counter. Figure 1 As shown in Figure 1, there are four mapping methods for jump direction prediction: strongly not taken, weakly not taken, weakly taken, and strongly taken. The corresponding prediction state machines are as follows: Figure 1 As shown: when the current state is "strongly no jump required" or "weakly no jump required", the direction of the instruction is predicted to be "no jump required (not taken)"; when the current state is "weakly required jump" or "strongly required jump (strongly taken)", the direction of the instruction is predicted to be "required jump (taken)".

[0004] For loop bodies, this commonly used branching technique has a flaw: when the number of loops in the loop body is greater than the number of bits in the branch jump history, it is impossible to correctly predict the last jump out of the loop body. Take the following instruction flow as an example:

[0005] 8000000:li a1,0

[0006] 8000002:li s1,100

[0007] 8000004:addi a1,a1,1

[0008] 8000008:bne a1,s1,80000004

[0009] 800000a:lhu t0,0(a1)

[0010] For the loop instruction flow above, instruction 80000004 needs to be executed 100 times to meet the condition of exiting the loop body. The first 99 times instruction 80000008 are all jumps, and the 100th time does not jump. For only 10 historical bits, the history from the 10th to the 100th is 10'b11_1111_1111, so the index is always the same jump result, and it becomes a strong jump state after 3 times at most. Therefore, when the jump instruction 80000008 is executed for the 100th time, the jump must be predicted incorrectly. Therefore, for a loop body with a particularly large number of loops, the last jump out of the loop body must be wrong.

[0011] Therefore, the accuracy of loop body branch jump direction prediction is currently low. Summary of the invention

[0012] In order to solve the above technical problems, a loop jump direction prediction and update system is provided in an embodiment of the present application.

[0013] In a first aspect of an embodiment of the present application, a loop jump direction prediction and update system is provided, which is used to predict the branch jump direction of a predicted loop body, and the loop jump direction prediction and update system at least includes an instruction fetch unit, a branch processing operation unit, and a processing unit that are signal-connected to each other, wherein:

[0014] The instruction fetch unit is used to obtain a corresponding instruction code from a pre-configured register according to an instruction fetch address, and send the instruction code to the processing unit, and send the instruction fetch address to the branch processing operation unit;

[0015] The branch processing operation unit is used to predict the loop branch jump direction according to the instruction fetch address and the pre-configured branch jump mode history index table, and output the target jump prediction direction; wherein the branch jump mode history index table at least includes the historical loop branch jump direction corresponding to the historical instruction fetch address of each instruction code;

[0016] The processing unit is used to update the prediction parameters of the branch processing operation unit according to the instruction code and the target jump prediction direction.

[0017] In an optional embodiment of the present application, the branch processing operation unit at least includes:

[0018] A branch jump prediction module, the branch jump prediction module is respectively connected to the instruction fetch unit and the processing unit by signal, the branch jump prediction module is used to determine an initial jump prediction direction from the pre-configured branch jump mode history index table according to the instruction fetch address;

[0019] A loop predictor, wherein the loop predictor is respectively connected to the instruction fetch unit, the processing unit signal and the branch jump prediction module signal, and the loop predictor is used to correct the initial jump prediction direction when the instruction fetch address reaches a preset condition, and output the corrected target jump prediction direction.

[0020] In an optional embodiment of the present application, the processing unit at least includes:

[0021] A decoding module, the decoding module is connected to the instruction fetch unit signal, and the decoding module is used to parse the instruction code to obtain the instruction execution type of the instruction code;

[0022] A branch execution module, wherein the branch execution module is respectively connected to the decoding module, the branch jump prediction module and the loop predictor signal, and the branch execution module is used to update the loop predictor according to the instruction execution type and the target jump prediction direction.

[0023] In an optional embodiment of the present application, the loop predictor includes multiple entry modules, each of which is used to store and maintain different branch jump parameters in the loop jump process, and the branch execution module is used to update the branch jump parameters in each of the entry modules in the loop predictor according to the instruction execution type and the target jump prediction direction.

[0024] In an optional embodiment of the present application, the different branch jump parameters at least include:

[0025] At least one of the fetch address hash value, the jump confidence value, the age value of the fetch address hash value, the number of jump loops, and the preset total number of loops.

[0026] In an optional embodiment of the present application, the loop predictor is used to correct the initial jump prediction direction and output the corrected target jump prediction direction when the instruction fetch address reaches a preset condition, including:

[0027] The loop predictor is used to perform hash calculation on at least two preset bit intervals of the instruction fetch address to obtain a loop address hash value;

[0028] The loop address hash value is compared with the instruction fetch address hash value in the entry module, and the target jump prediction direction after the initial jump prediction direction is corrected is determined according to the comparison result.

[0029] In an optional embodiment of the present application, comparing the loop address hash value with the instruction fetch address hash value in the entry module, and determining the target jump prediction direction after the initial jump prediction direction is corrected according to the comparison result, includes:

[0030] If the loop address hash value matches the instruction fetch address hash value in the entry module, then increasing the jump confidence value by a preset confidence value;

[0031] If the loop address hash value does not match the instruction fetch address hash value in the entry module, reducing the jump confidence value by the preset confidence value;

[0032] If the current jump confidence value reaches a preset maximum value, the current initial jump prediction direction is determined as the target jump prediction direction.

[0033] In an optional embodiment of the present application, the loop predictor is further used to:

[0034] If the loop address hash value does not match the instruction fetch address hash value in the entry module, reducing the age value of the instruction fetch address hash value by a preset age value to obtain the age value of the current instruction fetch address hash value;

[0035] If the age value of the current instruction fetch address hash value is 0, the age value of the instruction fetch address hash value in the entry module is replaced with the current instruction fetch address hash value.

[0036] In an optional embodiment of the present application, the branch jump prediction module includes at least a plurality of two-bit saturated counters, and the plurality of two-bit saturated counters are used to configure the branch jump pattern history index table.

[0037] In an optional embodiment of the present application, the branch processing operation unit and / or the processing unit is also used to determine that a jump cycle is completed if the number of jump cycles is equal to the preset total number of cycles, and output the target jump prediction direction of the current cycle of the predicted loop body.

[0038] The loop jump direction prediction and update system provided in the embodiment of the present application is used to predict the branch jump direction of the predicted loop body, the instruction fetch unit is used to obtain the corresponding instruction code from the pre-configured register according to the instruction fetch address, and send the instruction code to the processing unit, and send the instruction fetch address to the branch processing operation unit; the branch processing operation unit is used to predict the loop branch jump direction according to the instruction fetch address and the pre-configured branch jump mode history index table, and output the target jump prediction direction; wherein the branch jump mode history index table at least contains the historical loop branch jump direction corresponding to the historical instruction fetch address of each instruction code; the processing unit is used to update the prediction parameters of the branch processing operation unit according to the instruction code and the target jump prediction direction. By updating the prediction parameters in the branch processing operation unit, the dynamic iterative update of the branch processing operation unit is realized, and the subsequent prediction accuracy of the branch processing operation unit is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0040] Figure 1 It is a schematic diagram of loop jump logic in the prior art;

[0041] Figure 2 A schematic diagram of the structure of a loop jump direction prediction and update system provided in an embodiment of the present application;

[0042] Figure 3 A schematic diagram of the structure of a loop jump direction prediction and update system provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of a branch jump pattern history index table in a loop jump direction prediction and update system provided in an embodiment of the present application.

[0044] Among them: 10, loop jump direction prediction and update system; 100, instruction fetch unit; 200, branch processing operation unit; 210, branch jump prediction module; 220, loop predictor; 300, processing unit; 310, decoding module; 320, branch execution module; 400, register. DETAILED DESCRIPTION

[0045] In the process of implementing the present application, the applicant discovered that the accuracy of current loop body branch jump direction prediction is low.

[0046] In view of the above problems, an embodiment of the present application provides a loop jump direction prediction and update system. To make the purpose, technical solution and advantages of the present application clearer, the following further details the loop jump direction prediction and update system of the present application through embodiments and in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0047] The serial numbers assigned to the components in this document, such as "first", "second", etc., are only used to distinguish the described objects and do not have any sequential or technical meaning. The "connection" and "coupling" mentioned in the present application, unless otherwise specified, both include direct and indirect connection (coupling). In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application.

[0048] In the present application, unless otherwise clearly specified and limited, the first feature being "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature being "above", "over" and "on top of" the second feature may be that the first feature is directly above or obliquely above the second feature, or simply means that the first feature has a higher horizontal height than the second feature. The first feature being "below", "beneath" and "underneath" the second feature may be that the first feature is directly below or obliquely below the second feature, or simply means that the first feature has a lower horizontal height than the second feature.

[0049] Branch prediction needs to predict the jump direction and jump address of the jump instruction. The prediction of the jump direction is usually divided into two types: static prediction and dynamic prediction. Dynamic prediction of the jump direction is generally applied to complex processors and is generally implemented using a saturating counter.

[0050] The most widely used saturating counter at present is the "two-bit saturating counter (2-bit saturating counter)" as the branch "direction" dynamic predictor. The two-bit saturating counter will use the two-bit saturating counter to mark the historical state for each branch instruction, such as a conditional jump instruction. When a jump occurs, the counter is incremented by 1, and when a non-jump occurs, the counter is decremented by 1; finally, the prediction is made according to the value of the counter. For example Figure 1As shown in Figure 1, there are four mapping methods for jump direction prediction: strongly not taken, weakly not taken, weakly taken, and strongly taken. The corresponding prediction state machines are as follows: Figure 1 As shown: when the current state is "strongly no jump required" or "weakly no jump required", the direction of the instruction is predicted to be "no jump required (not taken)"; when the current state is "weakly required jump" or "strongly required jump (strongly taken)", the direction of the instruction is predicted to be "required jump (taken)".

[0051] For loop bodies, this commonly used branching technique has a flaw: when the number of loops in the loop body is greater than the number of bits in the branch jump history, it is impossible to correctly predict the last jump out of the loop body. Take the following instruction flow as an example:

[0052] 8000000:li a1,0

[0053] 8000002:li s1,100

[0054] 8000004:addi a1,a1,1

[0055] 8000008:bne a1,s1,80000004

[0056] 800000a:lhu t0,0(a1)

[0057] For the loop instruction flow above, instruction 80000004 needs to be executed 100 times to meet the condition of exiting the loop body. The first 99 times instruction 80000008 are all jumps, and the 100th time does not jump. For only 10 historical bits, the history from the 10th to the 100th is 10'b11_1111_1111, so the index is always the same jump result, and it becomes a strong jump state after 3 times at most. Therefore, when the jump instruction 80000008 is executed for the 100th time, the jump must be predicted incorrectly. Therefore, for a loop body with a particularly large number of loops, the last jump out of the loop body must be wrong.

[0058] Therefore, the accuracy of loop body branch jump direction prediction is currently low.

[0059] See also Figure 2, an embodiment of the present application provides a loop jump direction prediction and update system 10 for predicting the branch jump direction of a predicted loop body. The loop jump direction prediction and update system 10 at least includes an instruction fetch unit 100, a branch processing operation unit 200, and a processing unit 300 that are connected by signals to each other, where:

[0060] The instruction fetch unit 100 is configured to obtain a corresponding instruction code from a pre-configured register 400 according to the instruction fetch address, send the instruction code to the processing unit 300, and send the instruction fetch address to the branch processing operation unit 200;

[0061] The number of the registers 400 may be one, and different instruction codes are stored in different positions of the register 400. The number of the registers 400 may also be multiple, and different instruction codes are stored in different registers 400. The corresponding instruction fetch address may be the label of the register 400 and the specific position in the register 400.

[0062] The branch processing operation unit 200 is configured to predict the loop branch jump direction according to the instruction fetch address and a pre-configured branch jump mode history index table, and output a target jump prediction direction; wherein, the branch jump mode history index table at least includes the historical loop branch jump directions corresponding to the historical instruction fetch addresses of each instruction code;

[0063] The target jump prediction direction includes at least two types: jump and no jump; wherein, in some optional embodiments, the jump can be further refined into: weakly need to jump and strongly need to jump; the no jump can be further refined into: strongly do not need to jump and weakly do not need to jump, which are not specifically limited in the embodiments of the present application.

[0064] The branch jump mode history index table is a table for storing branch instruction history information, such as a PHT (pattern history table), which is mainly used to improve the accuracy of branch prediction, thereby optimizing the performance of the processor. The branch jump mode history index table stores and records the jump execution history of each branch instruction to help the loop predictor 220 more accurately judge the jump direction and target address of the branch instruction.

[0065] During the indexing process, the branch jump history (for example, 0110 in the following Figure 4 means that the first bit does not jump, the second bit jumps, the third bit jumps, and the fourth bit does not jump,) can be used as the index of the address PHT. As shown in the following Figure 4 If it is assumed that n bits are used to record the history of the register, then 2 to the nth power of table entries can be indexed. Determine whether it is a strong jump or no jump according to the low bits, and finally correct the state machine of the two-bit protection register 400 according to the prediction result.

[0066] The processing unit 300 is configured to update the prediction parameters of the branch processing operation unit 200 according to the instruction code and the target jump prediction direction.

[0067] The prediction parameter can be any parameter related to branch jump in the branch processing operation unit 200, such as prediction model parameters, specific information of the branch jump pattern history index table, etc., which will not be enumerated here.

[0068] The loop jump direction prediction and update system 10 provided by the embodiment of the present application is used to predict the branch jump direction of the predicted loop body. The instruction fetch unit 100 is configured to obtain the corresponding instruction code from the pre-configured register 400 according to the instruction fetch address, send the instruction code to the processing unit 300, and send the instruction fetch address to the branch processing operation unit 200; the branch processing operation unit 200 is configured to predict the loop branch jump direction according to the instruction fetch address and the pre-configured branch jump pattern history index table, and output the target jump prediction direction; wherein, the branch jump pattern history index table at least includes the historical loop branch jump directions corresponding to the historical instruction fetch addresses of each instruction code; the processing unit 300 is configured to update the prediction parameters of the branch processing operation unit 200 according to the instruction code and the target jump prediction direction. By updating the prediction parameters in the branch processing operation unit 200, the dynamic iterative update of the branch processing operation unit is realized, and the subsequent prediction accuracy of the branch processing operation unit 200 is further improved.

[0069] Please refer to Figure 3 , in an optional embodiment of the present application, the branch processing operation unit 200 at least includes: a branch jump prediction module 210 and a loop predictor 220, wherein:

[0070] The branch jump prediction module 210 is respectively connected to the instruction fetch unit 100 and the processing unit 300 in a signal connection. The branch jump prediction module 210 is configured to determine the initial jump prediction direction from the pre-configured branch jump pattern history index table according to the instruction fetch address;

[0071] The loop predictor 220 is respectively connected to the instruction fetch unit 100, the processing unit 300 and the branch jump prediction module 210 in a signal connection. The loop predictor 220 is configured to correct the initial jump prediction direction when the instruction fetch address reaches a preset condition, and output the corrected target jump prediction direction.

[0072] The instruction fetch address includes a high-order address and a low-order address, wherein the low-order address includes bits from the 1st bit to the nth bit in the instruction fetch address, and the high-order address includes bits from the nth bit to the maximum bit of the PC value in the instruction fetch address, where n is a value between 1 and the maximum bit of the PC value; the branch jump mode history index table is indexed by the instruction fetch address, for example Figure 4 The low-order address (0110) can be used to index the entry of the branch jump mode history index table to obtain an initial jump prediction direction that represents the historical jump direction result.

[0073] When the instruction fetch unit 100 fetches the instruction code from the register 400, it sends the instruction fetch address (e.g., 8000000 in the above loop instruction) to the branch jump prediction module 210 and the loop predictor 220. After obtaining the instruction code, the branch jump prediction module 210 determines whether the instruction code is a jump instruction and whether a jump is required (i.e., determines the initial jump prediction direction).

[0074] The loop predictor 220 predicts whether the instruction code is a loop jump. Only when the branch jump prediction module 210 predicts that the current instruction code is a conditional jump and the loop predictor 220 predicts that the current instruction is a loop jump, the loop predictor 220 reverses the branch jump prediction direction, that is, reverses the jump to no jump, and reverses the no jump to a jump, to obtain the reversed jump prediction direction, that is, the corrected target jump prediction direction.

[0075] In an actual loop, for a for loop, there will be a large number of predictions of no jumps in the early stage of the loop, and in the final judgment of a jump, then there will definitely be a prediction error, and the loop predictor 220 solves this problem very well. At the same time, the loop detector can still make good predictions for the case of a small number of for loops, not just for large loops, so the accuracy of loop jump prediction can be greatly improved. The above-mentioned branch jump prediction module 210 and loop predictor 220 determine whether the instruction code really jumps, and whether the initial jump prediction direction is correct, and correct the initial jump prediction direction when the initial jump prediction direction is wrong, and obtain the correct target jump prediction direction, which can help the next jump direction prediction to make a more accurate prediction result.

[0076] See also Figure 3 In an optional embodiment of the present application, the processing unit 300 at least includes: a decoding module 310 and a branch execution module 320, wherein:

[0077] The decoding module 310 is connected to the instruction fetching unit 100 by signal, and the decoding module 310 is used to parse the instruction code to obtain the instruction execution type of the instruction code;

[0078] The instruction execution type at least includes: whether it is a jump instruction, etc. Taking the instruction code 8000008 in the above loop instruction code as an example, the instruction fetch unit 100 fetches the instruction 8000008, and then sends it to the decoding unit, which parses the instruction code 8000008 and determines that the instruction code 8000008 is a jump instruction.

[0079] The branch execution module 320 is signal-connected to the decoding module 310 , the branch jump prediction module 210 and the loop predictor 220 , respectively. The branch execution module 320 is used to update the loop predictor 220 according to the instruction execution type and the target jump prediction direction.

[0080] In an optional embodiment of the present application, the loop predictor 220 includes multiple entry modules, each of which is used to store and maintain different branch jump parameters in the loop jump process, and the branch execution module 320 is used to update the branch jump parameters in each of the entry modules in the loop predictor 220 according to the instruction execution type and the target jump prediction direction.

[0081] The branch jump prediction module 210 obtains an initial jump prediction direction, i.e., jump or not jump, and then determines whether the prediction looper hits. If the hit is wrong, i.e., the target jump prediction direction is different from the initial jump prediction direction, i.e., the prediction is incorrect, the branch execution module 320 will update both the branch jump prediction and the loop predictor 220. The embodiment of the present application gives priority to updating the loop predictor 220, thereby helping to make a more accurate prediction result for the next jump direction prediction.

[0082] In an optional embodiment of the present application, the different branch jump parameters include at least one of the following Table 1: the instruction address hash value Tag, the jump confidence value Conf, the age value Age of the instruction address hash value, the number of jump cycles S-cnt, and the preset total number of cycles P-cnt.

[0083] Table 1

[0084] Tags Conf Age P_cnt S_cnt

[0085] Instruction address hash value Tag: The Tag value stores the hash value of the pc. For example, if the Tag is 9 bits, the values ​​of the two intervals of 9-1 bits and 18-10 bits of the instruction address are hashed to obtain a 9-bit hash value. Then, it is determined whether this hash value is equal to the instruction address hash value Tag value. If they are equal, it means that the predictor hits (that is, the initial jump prediction direction and the target jump prediction direction are the same). Every time the loop predictor 220 is entered, it is necessary to check whether the instruction address hash value Tag value matches the current loop address hash value. The instruction address hash value Tag and the age value Age of the instruction address hash value constitute the life cycle of a single loop predictor 220.

[0086] Jump confidence value Conf: If the instruction address hash value Tag matches the current loop address hash value, then the jump confidence value Conf will be determined. The jump confidence value Conf indicates the confidence level of the current loop address hash value. The jump confidence value Conf will increase by 1 for each successful completion of the loop jump into the loop predictor 220. However, only when the jump confidence value Conf reaches the maximum value (for example, two bits, the maximum value is 311), the loop prediction result (i.e., the target jump prediction direction) can be adopted.

[0087] Age value of the instruction address hash value: used to record the age of the instruction address hash value Tag. When the instruction address hash value Tag does not match the current cycle address hash value, the instruction address hash value Tag is reduced by 1. When the instruction address hash value Tag is 0, the instruction address hash value Tag can be replaced by the current cycle address hash value.

[0088] Jump loop count S-cnt: refers to the loop count of the loop predictor 220, which is incremented by 1 each time the loop is executed. When the loop predictor 220 is first entered and the loop ends, the value of S-cnt can be updated to the preset total loop count P-cnt.

[0089] The preset total number of loops P-cnt refers to the total number of loops set by the loop predictor 220. When the previously set value of the preset total number of loops P-cnt is equal to the value of the jump loop number S-cnt, the loop predictor 220 considers that a loop is completed.

[0090] In an optional embodiment of the present application, the loop predictor 220 is used to correct the initial jump prediction direction and output the corrected target jump prediction direction when the instruction fetch address reaches a preset condition, including:

[0091] The loop predictor 220 is used to perform hash calculation on at least two preset bit intervals of the instruction fetch address to obtain a loop address hash value;

[0092] The loop address hash value is compared with the instruction fetch address hash value in the entry module, and the target jump prediction direction after the initial jump prediction direction is corrected is determined according to the comparison result.

[0093] In an optional embodiment of the present application, comparing the loop address hash value with the instruction fetch address hash value in the entry module, and determining the target jump prediction direction after the initial jump prediction direction is corrected according to the comparison result, includes:

[0094] If the loop address hash value matches the instruction fetch address hash value in the entry module, then increasing the jump confidence value by a preset confidence value;

[0095] If the loop address hash value does not match the instruction fetch address hash value in the entry module, reducing the jump confidence value by the preset confidence value;

[0096] If the current jump confidence value reaches a preset maximum value, the current initial jump prediction direction is determined as the target jump prediction direction.

[0097] In an optional embodiment of the present application, the loop predictor 220 is further configured to:

[0098] If the loop address hash value does not match the instruction fetch address hash value in the entry module, reducing the age value of the instruction fetch address hash value by a preset age value to obtain the age value of the current instruction fetch address hash value;

[0099] If the age value of the current instruction fetch address hash value is 0, the age value of the instruction fetch address hash value in the entry module is replaced with the current instruction fetch address hash value.

[0100] The above updating method has been described in detail in the above embodiments through the entry modules and the corresponding branch jump parameters, and will not be repeated here.

[0101] In an optional embodiment of the present application, the branch jump prediction module 210 includes at least a plurality of two-bit saturated counters, and the plurality of two-bit saturated counters are used to configure the branch jump pattern history index table.

[0102] In an optional embodiment of the present application, the branch processing operation unit 200 and / or the processing unit 300 is also used to determine that a jump cycle is completed if the number of jump cycles is equal to the preset total number of cycles, and output the target jump prediction direction of the current cycle of the predicted loop body.

[0103] It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0104] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0105] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A loop jump direction prediction and update system, characterized in that: Used to predict the branch jump direction of the predicted loop body, the loop jump direction prediction and update system at least includes an instruction fetch unit, a branch processing operation unit and a processing unit that are signal-connected to each other, wherein: The instruction fetch unit is used to obtain a corresponding instruction code from a pre-configured register according to an instruction fetch address, and send the instruction code to the processing unit, and send the instruction fetch address to the branch processing operation unit; The branch processing operation unit is used to predict the loop branch jump direction according to the instruction fetch address and the pre-configured branch jump mode history index table, and output the target jump prediction direction; wherein the branch jump mode history index table at least includes the historical loop branch jump direction corresponding to the historical instruction fetch address of each instruction code; The processing unit is used to update the prediction parameters of the branch processing operation unit according to the instruction code and the target jump prediction direction.

2. The loop jump direction prediction and updating system according to claim 1, characterized in that: The branch processing operation unit at least includes: A branch jump prediction module, the branch jump prediction module is respectively connected to the instruction fetch unit and the processing unit by signal, the branch jump prediction module is used to determine an initial jump prediction direction from the pre-configured branch jump mode history index table according to the instruction fetch address; A loop predictor, wherein the loop predictor is respectively connected to the instruction fetch unit, the processing unit signal and the branch jump prediction module signal, and the loop predictor is used to correct the initial jump prediction direction when the instruction fetch address reaches a preset condition, and output the corrected target jump prediction direction.

3. The loop jump direction prediction and updating system according to claim 2, characterized in that: The processing unit at least comprises: A decoding module, the decoding module is connected to the instruction fetch unit signal, and the decoding module is used to parse the instruction code to obtain the instruction execution type of the instruction code; A branch execution module, wherein the branch execution module is respectively connected to the decoding module, the branch jump prediction module and the loop predictor signal, and the branch execution module is used to update the loop predictor according to the instruction execution type and the target jump prediction direction.

4. The loop jump direction prediction and updating system according to claim 3, characterized in that: The loop predictor includes multiple entry modules, each of which is used to store and maintain different branch jump parameters in the loop jump process, and the branch execution module is used to update the branch jump parameters in each of the entry modules in the loop predictor according to the instruction execution type and the target jump prediction direction.

5. The loop jump direction prediction and updating system according to claim 4, characterized in that: The different branch jump parameters at least include: At least one of the following: a hash value of the instruction address, a jump confidence value, an age value of the hash value of the instruction address, the number of jump cycles, and a preset total number of cycles.

6. The loop jump direction prediction and updating system according to claim 5, characterized in that: The loop predictor is used to correct the initial jump prediction direction when the instruction fetch address reaches a preset condition, and output a corrected target jump prediction direction, including: The loop predictor is used to perform hash calculation on at least two preset bit intervals of the instruction fetch address to obtain a loop address hash value; The loop address hash value is compared with the instruction fetch address hash value in the entry module, and the target jump prediction direction after the initial jump prediction direction is corrected is determined according to the comparison result.

7. The loop jump direction prediction and updating system according to claim 6, characterized in that: The step of comparing the loop address hash value with the instruction fetch address hash value in the entry module, and determining the target jump prediction direction after the initial jump prediction direction is corrected according to the comparison result, comprises: If the loop address hash value matches the instruction fetch address hash value in the entry module, then increasing the jump confidence value by a preset confidence value; If the loop address hash value does not match the instruction fetch address hash value in the entry module, reducing the jump confidence value by the preset confidence value; If the current jump confidence value reaches a preset maximum value, the current initial jump prediction direction is determined as the target jump prediction direction.

8. The loop jump direction prediction and updating system according to claim 6, characterized in that: The loop predictor is also used to If the loop address hash value does not match the instruction fetch address hash value in the entry module, reducing the age value of the instruction fetch address hash value by a preset age value to obtain the age value of the current instruction fetch address hash value; If the age value of the current instruction fetch address hash value is 0, the age value of the instruction fetch address hash value in the entry module is replaced with the current instruction fetch address hash value.

9. The loop jump direction prediction and updating system according to claim 2, characterized in that: The branch jump prediction module includes at least a plurality of two-bit saturation counters, and the plurality of two-bit saturation counters are used to configure the branch jump mode history index table.

10. The loop jump direction prediction and updating system according to claim 5, characterized in that: The branch processing operation unit and / or the processing unit is also used to determine that a jump cycle is completed if the jump cycle number is equal to the preset total cycle number, and output the target jump prediction direction of the current cycle of the prediction loop body.

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