Time division multiplexing multi-core DSP program guiding and updating method

Abstract

The invention discloses a time division multiplexing multi-core DSP (Digital Signal Processor) program guiding and updating method and an FPGA (Field Programmable Gate Array) end, which are used for performing program guiding and updating control on a multi-core DSP; at the multi-core DSP end, under the guidance control of the FPGA, each DSP core firstly performs primary guidance by utilizing a bootstrap function after the DSP is reset, moves a secondary guidance program from a BOOT space of the DSP core to an SRAM (Static Random Access Memory) in the DSP core, and reads an application program of the DSP core from a FLASH and moves the application program to the SRAM to operate by operating the secondary guidance program, so that secondary guidance is completed; and after the secondary guidance of the main DSP is completed, executing an application program of the main DSP, establishing a communication mechanism with external equipment to realize a handshake function, receiving an instruction sent by the external equipment, cooperating with FPGA update control, and performing program update on a DSP core needing program update according to instruction requirements. According to the method, multi-core DSP program guiding can be achieved only through one FLASH chip, the layout area can be remarkably reduced, the cost is reduced, and meanwhile guiding of each core is independent and does not affect one another.

Description

Technical Field

[0001] The invention relates to the field of embedded systems, in particular to a time-division multiplexed multi-core DSP program booting and updating method. Background Art

[0002] Digital Signal Processor (DSP) has the advantages of high-speed input and output, high computing accuracy, and strong real-time performance. However, the peripheral resources of DSP are limited and not suitable for parallel computing. Therefore, FPGA chips are often configured on the periphery of DSP to expand the peripheral interface of DSP and handle parallel computing. At the same time, in order to solidify the DSP program and realize automatic program operation after power-on, the system integrates non-volatile storage chip FLASH to store DSP programs and related data. However, with the rapid development of science and technology, information processing systems have put forward higher requirements for computing speed, data throughput, high integration, and small size. Limited by physical limits, power consumption and heat dissipation, manufacturing costs, etc., the benefits of improving the performance of single-core DSP are very small. Therefore, DSP designers expand from single-core to multi-core to meet the needs of current applications, but it still brings considerable challenges to board size and cost control.

[0003] The common DSP program boot method is to configure a non-volatile memory on the periphery of the DSP. After the DSP is reset, the DSP boot loader is used to automatically move the program in the memory to the internal storage space of the DSP and execute it to achieve a one-time boot. However, the length of the one-time boot program is fixed and limited, which often cannot meet the application requirements. Therefore, the function of the secondary boot program is embedded in the one-time boot program to move more program data and finally achieve the boot of the DSP. The paper "Flash Burning and BootLoad Program Design Based on TMS320C6713", the paper "Design and Implementation of Boot Loading Method of TMS320VC33", and the paper "Boot Program Design Technology of TMS320C671X Series DSP" all use this method to achieve program boot of single-core DSP. This method can be extended to program boot of multi-core DSP. It is necessary to configure a non-volatile memory for each DSP core, which has the disadvantages of high cost, large board size, and high power consumption.

[0004] The paper "Design of a Real-time Radar Signal Processing Platform Based on Multi-core DSP" discloses a multi-core DSP program boot method, which adopts a multi-mode boot loading and multi-core startup boot loading scheme. Specifically, a multi-mode startup module is added to the program of the DSP master core, the program entry address of the DSP slave core is assigned to the corresponding register of the slave core, and the master core sends an IPC interrupt to the slave core to wake up the slave core to achieve booting. Although this method can realize multi-core DSP program booting and updating through one FLASH, if the master core fails to boot, other slave cores cannot complete the booting.

[0005] The invention patent "A method for implementing a bootstrap method for a multi-core DSP processor without memory" discloses a method for booting a multi-core DSP program, which implements the multi-core bootstrap function through the EMFI port. Specifically, the program data is received through the external serial port and stored in the SDRAM on the FPGA board, and the secondary bootstrap program is written to the address of DSP core 0. After sending a reset signal, core 0 jumps to the secondary bootstrap program to complete the booting. Then DSP core 0 reads the programs of other cores through EMIF and saves them to the memory of each core respectively. Finally, a signal is sent to each core to implement the program booting of each core. Although this method implements the booting of multi-core DSP programs, the DSP program needs to be injected externally, and self-booting cannot be achieved at power-on. In addition, when an abnormality occurs in core 0, other cores cannot complete the booting. Summary of the invention

[0006] The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to provide a time-division multiplexed multi-core DSP program booting and updating method, to realize sequential booting of the multi-core DSP through FPGA control of the reset signal of the multi-core DSP and access control of FLASH, and to realize booting of the multi-core DSP with only one FLASH chip; to allow the main DSP to enter the program update process by designing a handshake mechanism, and to perform FLASH address offset control in accordance with the read-write control requirements of the main DSP, thereby realizing program update solidification of the multi-core DSP.

[0007] The technical solution of the present invention is: a time-division multiplexed multi-core DSP program boot and update method, comprising:

[0008] Connect the EMIF bus and reset signal of the multi-core DSP to the FPGA, connect the FPGA to a FLASH, and connect to external devices through the external data interface of the FPGA;

[0009] The program of the multi-core DSP is solidified in FLASH in a predetermined order, wherein the program includes a secondary boot program and an application program; one DSP core in the multi-core DSP is selected as the master DSP, and the rest are slave DSPs, and the master DSP communicates with external devices through the EMIF bus and the external data interface of the FPGA;

[0010] On the FPGA side, program guidance and update control of the multi-core DSP are achieved by controlling the reset signal of the multi-core DSP and access to FLASH;

[0011] On the multi-core DSP side, under the FPGA boot control, each DSP core uses the boot function after the DSP is reset to boot once, move the secondary boot program from the BOOT space of the DSP core to the SRAM in the DSP core, run the secondary boot program, read the application program of the DSP core from the FLASH and move it to the SRAM for running, and complete the secondary boot; after the secondary boot of the main DSP is completed, the application program of the main DSP is executed, and the handshake function is realized by establishing a communication mechanism with the external device, and the instruction sent by the external device is received. After the handshake is successful, the program update process is entered, and the FPGA update control is coordinated to update the program of the DSP core that needs to be updated according to the instruction requirements; after the secondary boot of the slave DSP is completed, the application program of the slave DSP is executed.

[0012] Furthermore, the FPGA side implements access control to FLASH by running the boot update control program, and performs program boot and update control on the multi-core DSP;

[0013] The multi-core DSP includes n DSP cores, x represents the xth DSP core, x=1, 2, 3, ..., n, DSP core 1 is the master DSP, DSP core 2 to DSP core n are slave DSPs;

[0014] The boot update control program includes the following steps:

[0015] (F1) The boot register ADD_BOOT_x of the master DSP and the slave DSP is set to invalid, indicating that the corresponding DSP core has not been successfully booted;

[0016] (F2) Set the main DSP program update register ADD_UPDATA to 0, indicating that no DSP core needs to update the program;

[0017] (F3) Initialize external data interface;

[0018] (F4) Reset and maintain all DSP cores through the reset signal pin;

[0019] (F5) Program guide control of the main DSP:

[0020] (F5.1) Connect the EMIF bus of DSP core 1 to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core 1 stored in FLASH;

[0021] (F5.2) Cancel the reset of DSP core 1 and start the timer at the same time;

[0022] (F5.3) Read the value of DSP core 1 boot register ADD_BOOT_1. If the value is invalid, go to step (F5.4), otherwise go to step (F6);

[0023] (F5.4) Read the timer value. If the timer value is greater than the set threshold, go to step (F6), otherwise go to step (F5.3);

[0024] (F6) Program the slave DSP in the specified order:

[0025] (F6.1) Initialize the count k to 2;

[0026] (F6.2) Connect the EMIF bus of DSP core k to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core k stored in FLASH;

[0027] (F6.3) Cancel the reset of DSP core k and start the timer at the same time;

[0028] (F6.4) Read the value of DSP core k boot register ADD_BOOT_k. If the value is invalid, go to step (F6.5), otherwise go to step (F 6.6);

[0029] (F6.5) Read the timer value. If the timer value is greater than the set threshold, go to step (F 6.6), otherwise go to step (F6.4);

[0030] (F6.6) count k plus 1;

[0031] (F6.7) Determine whether all DSP cores are reset, if yes, go to step (F7), otherwise go to step (F6.2);

[0032] (F7) judging whether each DSP core is successfully started according to the start register value of each DSP core, and feeding back the judgment result through the external data interface;

[0033] (F8) Control the DSP program update:

[0034] (F8.1) Read the value of register ADD_UPDATA. If the value is equal to the DSP core number x, go to step (F8.2), otherwise go to step (F8.1);

[0035] (F8.2) Connect the EMIF bus of DSP core x to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core x stored in FLASH;

[0036] (F8.3) Set the value in register ADD_UPDATA to 0 and proceed to step (F8.1).

[0037] Furthermore, when canceling the reset of DSP core x in step (F5.2) or step (F6.3) of the multi-core DSP program boot and update control program, the DSP side performs a primary boot and a secondary boot, including the following steps:

[0038] (D1) Transfer the secondary boot program from the starting address of the BOOT space to SRAM via the EMIF bus;

[0039] (D2) Run the DSP secondary boot program:

[0040] (D2.1) Set the integer variable ptrA to 0, set the integer variable add1A to the starting address where the program runs, and set the integer variable add2A to the starting address where the application program of DSP core x is stored in FLASH;

[0041] (D2.2) Assign the value at address (add1A + ptrA) to the value at address (add2A + ptrA);

[0042] (D2.3) Increment ptrA by 1;

[0043] (D2.4) Determine whether ptrA is greater than the length of the space where the application program of DSP core x is stored in FLASH. If so, proceed to step (D3); otherwise, proceed to step (D2.2);

[0044] (D3) Jump the program according to the entry address of the application program of DSP core x and run the application program of DSP core x.

[0045] Furthermore, the application program of the main DSP includes the following steps:

[0046] (Z1) Set the value of the startup register ADD_BOOT_1 of DSP core 1 to valid, indicating that the boot of DSP core 1 is successful;

[0047] (Z 2) Start the timer;

[0048] (Z 3) If a handshake command sent by an external device is received, proceed to step (Z 6); otherwise, proceed to step (Z 4);

[0049] (2-4) If the timer count is greater than the set threshold, proceed to step (Z 5);

[0050] (Z5) Execute the target function program of DSP core 1 and end;

[0051] (Z6) Feedback handshake success to the external device via the external data interface;

[0052] (Z7) determining whether the core x program update instruction and the program data to be updated sent by the external device are received, if yes, proceeding to step (Z8), otherwise proceeding to step (Z7);

[0053] (Z8) Set the program update register ADD_UPDATA to x;

[0054] (Z9) Set the integer variable ptrB to 0, the integer variable add1B to the first address of the program data to be updated, and the integer variable add2B to the first address of the application program of DSP core x stored in FLASH;

[0055] (Z10) Determine whether the value of the program update register ADD_UPDATA is 0, if yes, go to step (Z11), otherwise go to step (Z8);

[0056] (Z11) writing the program data to be updated into the address space where the application program of DSP core x is stored in FLASH in address sequence;

[0057] (Z11.1) Assign the value at address (add2B+ptrB) to the value at address (add1 B+ptrB);

[0058] (Z11.2)ptrB increases by 1;

[0059] (Z11.3) Determine whether ptrB is greater than the space length of the program data to be updated. If so, proceed to step (Z12); otherwise, proceed to step (Z11.1);

[0060] (Z12) Feedback that the application program of DSP core x is successfully updated is given through the external data interface.

[0061] Further, from the DSP application, the following steps are included:

[0062] (C1) Set the value of the boot register ADD_BOOT_x of DSP core x to be valid, indicating that DSP core x is successfully booted, x=2, 3, ..., n;

[0063] (C2) Execute the target function program of DSP core x.

[0064] Furthermore, the target function program refers to the function program decomposed into the DSP core to complete the final function of the system, and the target function programs for different purposes are different.

[0065] The present invention also provides a computer program product, which implements the steps of the above method when executed by a processor.

[0066] The advantages of the present invention compared with the prior art are:

[0067] Traditional multi-core DSP program booting requires the support of multiple FLASH chips, that is, the number of FLASH chips is equal to the number of DSP cores. The present invention only needs one FLASH chip to realize multi-core DSP program booting, which can significantly reduce the board area and reduce the cost. At the same time, the booting of each core is relatively independent, and there is no situation where the failure of the main core to boot will cause the failure of other cores to boot. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] Figure 1 It is a main circuit relationship diagram involved in the method of the present invention;

[0069] Figure 2 This is an example diagram of the solidification of the multi-core DSP program of the present invention in FLASH;

[0070] Figure 3 It is a flowchart of the boot and update control program of the FPGA end of the present invention;

[0071] Figure 4 It is the whole flow chart of guiding the DSP of the present invention;

[0072] Figure 5 It is a secondary boot program flow chart of the DSP of the present invention;

[0073] Figure 6 It is the application flow chart of the main DSP of the present invention;

[0074] Figure 7 This is a flow chart of the application program from DSP of the present invention. DETAILED DESCRIPTION

[0075] In order to better understand the technical solution of the present invention, the specific implementation mode of the present invention is described in detail below with reference to the accompanying drawings.

[0076] The main circuit relationships involved in this method are as follows Figure 1 As shown in the figure, the EMIF bus and reset signal of the multi-core DSP are connected to the FPGA, the data bus, address bus and read / write control signal of a FLASH are connected to the FPGA, and the external device is connected to the FPGA through the external data interface; the secondary boot program and application program of the multi-core DSP are solidified in the FLASH according to certain rules, such as the example stored in the order of DSP core number as shown in the figure. Figure 2 As shown; one of the DSP cores is selected as the master DSP, and the rest are slave DSPs. The master DSP communicates with external devices through the EMIF bus and the external data interface control program of the FPGA (the external data interface can be selected according to the hardware resource situation, without special requirements).

[0077] On the FPGA side, the program guidance and update control of the multi-core DSP are realized by controlling the reset signal of the multi-core DSP and the access control of the FLASH, such as Figure 3 As shown;

[0078] On the multi-core DSP side, under the control of FPGA boot, each DSP core uses the boot function after DSP reset to boot once, move the secondary boot program from the BOOT space of the DSP core to the SRAM in the DSP core, run the secondary boot program, read the application of the DSP core from FLASH and move it to SRAM to run, and complete the secondary boot. The whole boot process of DSP is as follows: Figure 4 As shown, the secondary boot process is as follows Figure 5 As shown in the figure; after the secondary boot of the main DSP is completed, the application program of the main DSP is executed, and the handshake function is realized by establishing a communication mechanism with the external device, and the instruction sent by the external device is received. After the handshake is successful, the program update process is entered, and the FPGA update control is coordinated to update the DSP core that needs to be updated according to the instruction requirements, such as Figure 6 As shown; after the secondary boot from the DSP is completed, the application from the DSP is executed, such as Figure 7 shown.

[0079] Specifically, the FPGA side implements access control to the FLASH by running the boot update control program, and performs program boot and update control on the multi-core DSP.

[0080] Boot the update control program, the specific implementation method is as follows:

[0081] (1) Set the boot register ADD_BOOT_x of the master DSP and slave DSP and set it to invalid, indicating that the corresponding DSP has not been successfully booted

[0082] (2) Set the main DSP program update register ADD_UPDATA to 0, indicating that no DSP core needs to update the program;

[0083] (3) Initialize the external interface (the external interface can achieve interactive communication, no special requirements);

[0084] (4) Reset and hold all DSP cores through the reset signal pin. The hold time cannot be less than the minimum time for the DSP reset signal to be determined to be valid.

[0085] (5) Program booting of the main DSP (DSP core 1);

[0086] (5.1) Connect the EMIF bus of DSP core 1 to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core 1 stored in FLASH;

[0087] (5.2) Cancel the reset of DSP core 1 and start the timer;

[0088] (5.3) Read the value of DSP core 1 boot register ADD_BOOT_1. If the value is invalid, go to step (5.4), otherwise go to step (6);

[0089] (5.4) Read the timer value. If the timer value is greater than the set threshold, go to step (6), otherwise go to step (5.3);

[0090] (6) The slave DSPs are guided by the program in a predetermined order (here the order of increasing core numbers is used for illustration);

[0091] (6.1) The count k is initialized to 2;

[0092] (6.2) Connect the EMIF bus of DSP core k to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core k stored in FLASH;

[0093] (6.3) Cancel the reset of DSP core k and start the timer at the same time;

[0094] (6.4) Read the value of DSP core k boot register ADD_BOOT_k. If the value is invalid, go to step (6.5), otherwise go to step (6.6);

[0095] (6.5) Read the timer value. If the timer value is greater than the set threshold, go to step (6.6), otherwise go to step (6.4);

[0096] (6.6) count k plus 1;

[0097] (6.7) If all DSP cores cancel reset, go to step (7), otherwise go to step (6.2);

[0098] (7) Based on the startup register values ​​of each core, determine whether the startup of each core is successful (the startup register value corresponding to the successfully started DSP core is valid), and feedback the result through the external interface;

[0099] (8) Read and write control of FLASH according to the program update register value of the main DSP;

[0100] (8.1) Read the value of register ADD_UPDATA as an integer. If the value is equal to the number x of the DSP core (x = 1, 2, 3, ..., n), go to step (8.2), otherwise go to step (8.1);

[0101] (8.2) Connect the EMIF bus of DSP core x to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core x stored in FLASH;

[0102] (8.3) Set the integer value in register ADD_UPDATA to 0 and go to step (8.1).

[0103] When the reset of DSP core x is canceled in step (5.2) or step (6.3) of the multi-core DSP program boot and update control program, the DSP end performs primary boot and secondary boot. Through the primary boot, the secondary boot program is moved from the BOOT space of the DSP core to the SRAM in the DSP core. By running the secondary boot program, the application program of the DSP core is read from the FLASH and moved to the SRAM for running, completing the secondary boot. The specific implementation method is as follows:

[0104] (1) Move 1K data from the starting address of the DSP's BOOT space to SRAM through the EMIF bus and run it (i.e., offset the access address according to the first address of core x in FLASH storage through FPGA);

[0105] (2) Run the secondary boot program of DSP;

[0106] (2.1) The integer variable ptrA is set to 0, the integer variable add1A is set to the first address where the program is running, and the integer variable add2A is set to the first address where the application of DSP core x (x=1, 2, 3, ..., n) is stored in FLASH;

[0107] (2.2) The value at address (add1A+ptrA) is assigned to the value at address (add2A+ptrA);

[0108] (2.3)ptrA is equal to ptrA plus 1;

[0109] (2.4) If ptrA is greater than the length of the space where the application of DSP core x is stored in FLASH, go to step (3), otherwise go to step (2.2);

[0110] (3) Jump the program according to the application entry address of DSP core x and run the application of DSP core x.

[0111] The application of the main DSP implements the handshake function by establishing a communication mechanism with the external device, receives the instructions sent by the external device, and enters the program update process after the handshake is successful. It cooperates with the FPGA update control to update the DSP core that needs to be updated according to the instruction requirements. The specific implementation method is as follows:

[0112] (1) The value of the boot register ADD_BOOT_1 of DSP core 1 is set to valid, indicating that DSP core 1 boots successfully;

[0113] (2) Start the timer;

[0114] (3) If a handshake command is received from an external device, proceed to step (6); otherwise, proceed to step (4);

[0115] (4) If the timer count is greater than the set threshold, proceed to step (5);

[0116] (5) Execute according to the target function program of DSP core 1 (the target function refers to the function decomposed to the DSP core to complete the final function of the system, and the target function program for different purposes is different);

[0117] (6) Feedback the handshake success to the external device through the external interface;

[0118] (7) If a core x (x=1, 2, 3, ..., n) program update instruction and program data to be updated are received from an external device, then go to step (8); otherwise, go to step (7);

[0119] (8) The program updates the register ADD_UPDATA to x;

[0120] (9) The integer variable ptrB is set to 0, the integer variable add1B is set to the first address where the program data to be updated is stored, and the integer variable add2B is set to the first address where the application program of DSP core x (x=1, 2, 3, ..., n) is stored in the FLASH;

[0121] (10) If the value of the program update register ADD_UPDATA is 0, go to step (11), otherwise go to step (8);

[0122] (11) Write the program data to be updated into the address space of the application program of DSP core x (x=1, 2, 3, ..., n) stored in FLASH in the order of addresses;

[0123] (11.1) The value at address (add2B+ptrB) is assigned to the value at address (add1 B+ptrB);

[0124] (11.2)ptrB is equal to ptrB plus 1;

[0125] (11.3) If ptrB is larger than the space length of the program data to be updated, go to step (12), otherwise go to step (11.1);

[0126] (12) Feedback is given through the external interface that the application program of DSP core x (x=1, 2, 3, ..., n) has been successfully updated.

[0127] From the DSP application, you only need to set the start register to be valid before the target function program is executed. The specific implementation method is as follows:

[0128] (1) The value of the boot register ADD_BOOT_x of DSP core x (x=2, 3, ..., n) is set to valid, indicating that the DSP core x is successfully booted;

[0129] (2) Execute according to the target function program of DSP core x (the target function program refers to the function program decomposed to the DSP core to complete the final function of the system, and the target function program for different purposes is different).

[0130] It is to be understood that the present invention is described by way of embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and embodiments that can fall within the scope of the claims of this application all fall within the scope protected by the present invention.

[0131] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A time-division multiplexed multi-core DSP program boot and update method, characterized in that: include: Connect the EMIF bus and reset signal of the multi-core DSP to the FPGA, connect the FPGA to a FLASH, and connect to external devices through the external data interface of the FPGA; Solidify the multi-core DSP program in FLASH according to a predetermined sequence, wherein the program includes a secondary boot program and an application program; One DSP core in the multi-core DSP is selected as the master DSP, and the rest are slave DSPs. The master DSP communicates with external devices through the EMIF bus and the external data interface of the FPGA; On the FPGA side, program guidance and update control of the multi-core DSP are achieved by controlling the reset signal of the multi-core DSP and access to FLASH; On the multi-core DSP side, under the FPGA boot control, each DSP core uses the boot function after the DSP is reset to boot once, move the secondary boot program from the BOOT space of the DSP core to the SRAM in the DSP core, run the secondary boot program, read the application program of the DSP core from the FLASH and move it to the SRAM for running, and complete the secondary boot; after the secondary boot of the main DSP is completed, the application program of the main DSP is executed, and the handshake function is realized by establishing a communication mechanism with the external device, and the instruction sent by the external device is received. After the handshake is successful, the program update process is entered, and the FPGA update control is coordinated to update the program of the DSP core that needs to be updated according to the instruction requirements; after the secondary boot of the slave DSP is completed, the application program of the slave DSP is executed.

2. The time-division multiplexed multi-core DSP program booting and updating method according to claim 1, characterized in that: The FPGA side implements access control to FLASH by running the boot update control program, and performs program boot and update control on the multi-core DSP; The multi-core DSP includes n DSP cores, x represents the xth DSP core, x=1, 2, 3, ..., n, DSP core 1 is the master DSP, DSP core 2 to DSP core n are slave DSPs; The boot update control program includes the following steps: (F1) The boot register ADD_BOOT_x of the master DSP and the slave DSP is set to invalid, indicating that the corresponding DSP core has not been successfully booted; (F2) Set the main DSP program update register ADD_UPDATA to 0, indicating that no DSP core needs to update the program; (F3) Initialize external data interface; (F4) Reset and maintain all DSP cores through the reset signal pin; (F5) Program guide control of the main DSP: (F5.1) Connect the EMIF bus of DSP core 1 to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core 1 stored in FLASH; (F5.2) Cancel the reset of DSP core 1 and start the timer at the same time; (F5.3) Read the value of DSP core 1 boot register ADD_BOOT_1. If the value is invalid, go to step (F5.4), otherwise go to step (F6); (F5.4) Read the timer value. If the timer value is greater than the set threshold, go to step (F6), otherwise go to step (F5.3); (F6) Program the slave DSP in the specified order: (F6.1) Initialize the count k to 2; (F6.2) Connect the EMIF bus of DSP core k to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core k stored in FLASH; (F6.3) Cancel the reset of DSP core k and start the timer at the same time; (F6.4) Read the value of DSP core k boot register ADD_BOOT_k. If the value is invalid, go to step (F6.5), otherwise go to step (F 6.6); (F6.5) Read the timer value. If the timer value is greater than the set threshold, go to step (F 6.6), otherwise go to step (F6.4); (F6.6) count k plus 1; (F6.7) Determine whether all DSP cores are reset, if yes, go to step (F7), otherwise go to step (F6.2); (F7) judging whether each DSP core is successfully started according to the start register value of each DSP core, and feeding back the judgment result through the external data interface; (F8) Control the DSP program update: (F8.1) Read the value of register ADD_UPDATA. If the value is equal to the DSP core number x, go to step (F8.2), otherwise go to step (F8.1); (F8.2) Connect the EMIF bus of DSP core x to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the first address of the program of DSP core x stored in FLASH; (F8.3) Set the value in register ADD_UPDATA to 0 and go to step (F8.1).

3. The time-division multiplexed multi-core DSP program booting and updating method according to claim 2 is characterized in that: When the reset of DSP core x is canceled in step (F5.2) or step (F6.3) of booting and updating the control program on the FPGA side, the DSP side performs a primary boot and a secondary boot, including the following steps: (D1) Move the secondary boot program from the starting address of the BOOT space to SRAM through the EMIF bus; (D2) Run the DSP secondary boot program: (D2.1) Set the integer variable ptrA to 0, the integer variable add1A to the first address where the program is running, and the integer variable add2A to the first address where the application of DSP core x is stored in FLASH; (D2.2) Assign the value at address (add1A+ptrA) to the value at address (add2A+ptrA); (D2.3)ptrA increases by 1; (D2.4) Determine whether ptrA is greater than the length of the space where the application of DSP core x is stored in FLASH. If yes, proceed to step (D3), otherwise proceed to step (D2.2); (D3) Jump the program according to the application entry address of DSP core x and run the application of DSP core x.

4. The time-division multiplexed multi-core DSP program booting and updating method according to claim 3 is characterized in that: The main DSP application includes the following steps: (Z1) Set the value of the boot register ADD_BOOT_1 of DSP core 1 to valid, indicating that DSP core 1 boots successfully; (Z 2) Start the timer; (Z 3) If a handshake command is received from an external device, proceed to step (Z 6), otherwise proceed to step (Z 4); (2-4) If the timer count is greater than the set threshold, go to step (Z 5); (Z5) Execute the target function program of DSP core 1 and end; (Z6) Feedback handshake success to the external device through the external data interface; (Z7) determining whether the core x program update instruction and the program data to be updated sent by the external device are received, if yes, proceeding to step (Z8), otherwise proceeding to step (Z7); (Z8) Set the program update register ADD_UPDATA to x; (Z9) Set the integer variable ptrB to 0, the integer variable add1B to the first address of the program data to be updated, and the integer variable add2B to the first address of the application program of DSP core x stored in FLASH; (Z10) Determine whether the value of the program update register ADD_UPDATA is 0, if yes, go to step (Z11), otherwise go to step (Z8); (Z11) writing the program data to be updated into the address space where the application program of DSP core x is stored in FLASH in address sequence; (Z11.1) Assign the value at address (add2B+ptrB) to the value at address (add1 B+ptrB); (Z11.2)ptrB increases by 1; (Z11.3) Determine whether ptrB is greater than the space length of the program data to be updated. If so, proceed to step (Z12); otherwise, proceed to step (Z11.1); (Z12) Feedback that the application program of DSP core x is successfully updated is given through the external data interface.

5. The time-division multiplexed multi-core DSP program booting and updating method according to claim 1, characterized in that: From the DSP application, the following steps are included: (C1) Set the value of the boot register ADD_BOOT_x of DSP core x to be valid, indicating that DSP core x is successfully booted, x=2, 3, ..., n; (C2) Execute the target function program of DSP core x.

6. The time-division multiplexed multi-core DSP program booting and updating method according to claim 5, characterized in that: The target function program refers to the function program decomposed into the DSP core to complete the final function of the system, and the target function program for different purposes is different.

7. A computer program product, characterized in that: When the computer program product is executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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