A time division multiplexed multi-core DSP program booting and updating method

Abstract

The application discloses a kind of time division multiplexing multi-core DSP program guiding and updating method, FPGA end, program guiding and updating control are carried out to multi-core DSP;Multi-core DSP end, under the guidance control of FPGA, first guiding is carried out using the bootstrap function after the reset of each DSP core, and the secondary boot program is moved from the BOOT space of the DSP core to the SRAM in the DSP core, and the application program of the DSP core is read from the FLASH and moved to the SRAM for running by running the secondary boot program, to complete secondary boot;After the secondary boot of main DSP is completed, the application program of main DSP is executed, handshake function is realized by establishing communication mechanism with external device, receives the instruction sent by external device, cooperates with FPGA update control, and the DSP core needing program updating is updated according to the instruction requirement.The application can realize multi-core DSP program guiding by only needing 1 piece of FLASH chip, can significantly reduce the area of layout, reduce cost, and the guiding of each core is independent and does not exist mutual influence.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded systems, in particular to a time division multiplexing multi-core DSP program booting and updating method. BACKGROUND

[0002] Digital signal processor (DSP) has the advantages of high-speed input and output, high operation precision, strong real-time performance, etc. However, the peripheral resources of DSP are limited, and it is not suitable for parallel operation. Therefore, an FPGA chip is often configured in the periphery of DSP to expand the peripheral interface of DSP and process parallel operation. Meanwhile, in order to solidify the program of DSP and realize automatic program running after power-on, a non-volatile storage chip FLASH is integrated in the system to store the DSP program and related data. However, with the rapid development of science and technology, the information processing system has put forward higher requirements on operation speed, data throughput, high integration, small size, etc. Limited by physical limits, power consumption and heat dissipation, manufacturing cost, etc., the performance improvement of single-core DSP has little benefit. Therefore, DSP designers expand from single core to multi-core to meet the current application requirements, but this still brings great challenges to board size and cost control.

[0003] A common DSP program booting method is to configure a non-volatile memory in the periphery of DSP. After the reset of DSP, the program in the memory is automatically moved to the internal storage space of DSP by the boot loader of DSP and executed to realize one-time booting. However, the length of one-time booting program is fixed and limited, which often cannot meet the application requirements. Therefore, a secondary booting program is embedded in the one-time booting program to move more program data, and finally the booting of DSP is realized. The papers "Flash Programming and BootLoader Design Based on TMS320C6713", "Design and Implementation of Boot Loading Method for TMS320VC33", and "Design Technology of Boot Program for TMS320C671X Series DSP" all use this method to realize the program booting of single-core DSP. This method can be extended to the program booting of multi-core DSP, which needs to configure a non-volatile memory for each DSP core, and has the disadvantages of high cost, large board size, high power consumption, etc.

[0004] A multi-core DSP program booting method is disclosed in the paper "Design of Real-Time Radar Signal Processing Platform Based on Multi-core DSP". The method adopts a multi-mode boot loading and multi-core boot loading scheme. Specifically, a multi-mode start module is added to the program of the main core of DSP, the program entry address of the slave core is assigned to the corresponding register of the slave core, and the slave core is awakened to realize booting by sending an IPC interrupt from the main core to the slave core. Although this method can realize the program booting and updating of multi-core DSP by using one FLASH, if the booting of the main core fails, the booting of other slave cores cannot be completed.

[0005] The invention patent "A Method for Booting a Multi-Core DSP Processor Without Memory" discloses a method for booting a multi-core DSP program, which implements multi-core booting functionality through the EMIF port. Specifically, it receives program data via an external serial port and stores it in the SDRAM on the FPGA board. A secondary boot program is written to the address of DSP core 0. After sending a reset signal, core 0 jumps to the secondary boot program to complete the boot process. Then, DSP core 0 reads the programs of other cores through the EMIF and saves them to their respective memory. Finally, signals are sent to each core to boot its program. While this method achieves multi-core DSP program booting, the DSP program requires external injection, making power-on self-booting impossible. Furthermore, if core 0 malfunctions, the other cores cannot complete the boot process. Summary of the Invention

[0006] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a time-division multiplexed method for multi-core DSP program booting and updating. By controlling the reset signal of the multi-core DSP and the access control of FLASH through FPGA, the sequential booting of the multi-core DSP can be realized, so that only one FLASH chip is needed to boot the multi-core DSP. By designing a handshake mechanism to allow the main DSP to enter the program update process, the FPGA cooperates with the read and write control requirements of the main DSP to perform FLASH address offset control, thereby realizing the program update and solidification of the multi-core DSP.

[0007] The technical solution of this invention is: a time-division multiplexed multi-core DSP program booting and updating method, comprising:

[0008] Connect the EMIF bus and reset signal of the multi-core DSP to the FPGA, connect the FPGA to a FLASH chip, and connect the FPGA to external devices through the FPGA's external data interface.

[0009] The program of the multi-core DSP is stored in FLASH in a predetermined order. The program includes a secondary boot program and an application program. One DSP core in the multi-core DSP is selected as the master DSP and the rest are slave DSPs. The master DSP communicates with external devices through the EMIF bus and the external data interface of the FPGA.

[0010] On the FPGA side, the program booting and update control of the multi-core DSP is realized by controlling the reset signal of the multi-core DSP and the access control of FLASH.

[0011] At the multi-core DSP end, under the guidance of the FPGA, each DSP core uses the self-boot function after the DSP reset to first perform a boot, move the secondary boot program from the BOOT space of the DSP core to the SRAM in the DSP core, run the secondary boot program, read the application program of the DSP core from the FLASH and move it to the SRAM for running, and complete the secondary boot; after the secondary boot of the master DSP is completed, the application program of the master DSP is executed, the handshake function is realized by establishing a communication mechanism with an external device, instructions sent by the external device are received, after the handshake is successful, the program update flow is entered, the program update of the DSP core that needs to be updated is performed according to the instruction requirement in cooperation with the FPGA update control; after the secondary boot of the slave DSP is completed, the application program of the slave DSP is executed.

[0012] Further, the FPGA end realizes access control to the FLASH, program boot and update control of the multi-core DSP by running the boot update control program;

[0013] The multi-core DSP includes n DSP cores, x represents the xth DSP core, x = 1, 2, 3,..., n, the DSP core 1 is a master DSP, and the DSP core 2 to the DSP core n are slave DSPs;

[0014] The boot update control program includes the following steps:

[0015] (F1) setting the start register ADD_BOOT_x of the master DSP and the slave DSP to be invalid, representing that the corresponding DSP core is not successfully booted;

[0016] (F2) setting the program update register ADD_UPDATA of the master DSP to be 0, representing that no DSP core needs to update the program;

[0017] (F3) initializing an external data interface;

[0018] (F4) resetting and maintaining all DSP cores through a reset signal pin;

[0019] (F5) performing program boot control on the master DSP:

[0020] (F5.1) connecting the EMIF bus of the DSP core 1 with the data bus, the address bus and the read-write control signal of the FLASH, and offsetting the address bus to the first address of the program of the DSP core 1 stored in the FLASH;

[0021] (F5.2) canceling the reset of the DSP core 1 and starting a timer;

[0022] (F5.3) read the value of the boot register ADD_BOOT_1 of the DSP core 1, if the value is invalid, go to step (F5.4), otherwise go to step (F6);

[0023] (F5.4) read the timer value, if the timer value is greater than a set threshold, go to step (F6), otherwise go to step (F5.3);

[0024] (F6) program booting from the DSP in a predetermined order:

[0025] (F6.1) initialize the counter k as 2;

[0026] (F6.2) connect the EMIF bus of the DSP core k with the data bus, address bus and read-write control signal of the FLASH, and shift the address bus to the first address of the program of the DSP core k stored in the FLASH;

[0027] (F6.3) cancel the reset of the DSP core k, and start the timer;

[0028] (F6.4) read the value of the boot register ADD_BOOT_k of the DSP core k, if the value is invalid, go to step (F6.5), otherwise go to step (F6.6);

[0029] (F6.5) read the timer value, if the timer value is greater than a set threshold, go to step (F6.6), otherwise go to step (F6.4);

[0030] (F6.6) increase the counter k by 1;

[0031] (F6.7) determine whether all DSP cores are reset, if yes, go to step (F7), otherwise go to step (F6.2);

[0032] (F7) determine whether the boot of each DSP core is successful according to the value of the boot register of each DSP core, and feed back the determination result through the external data interface;

[0033] (F8) program updating control of the DSP:

[0034] (F8.1) read the value of the register ADD_UPDATA, if the value is equal to the number x of the DSP core, go to step (F8.2), otherwise go to step (F8.1);

[0035] (F8.2) connect the EMIF bus of the DSP core x with the data bus, address bus and read-write control signal of the FLASH, and shift the address bus to the first address of the program of the DSP core x stored in the FLASH;

[0036] (F8.3) Set the value in register ADD_UPDATA to 0, and go to step (F8.1).

[0037] Further, when the reset of the DSP core x is cancelled in step (F5.2) or step (F6.3) of the multi-core DSP program booting and updating control procedure, the DSP side carries out the primary booting and the secondary booting, including the following steps:

[0038] (D1) Moving the secondary booting program from the starting address of the BOOT space to the SRAM through the EMIF bus;

[0039] (D2) Running the DSP secondary booting program:

[0040] (D2.1) Setting the integer variable ptrA to 0, the integer variable add1A to the first address of the program running storage, and the integer variable add2A to the first address of the application program of the DSP core x stored in the FLASH;

[0041] (D2.2) Assigning the value in the address (add1A+ptrA) to the value in the address (add2A+ptrA);

[0042] (D2.3) Adding 1 to ptrA;

[0043] (D2.4) Judging whether ptrA is greater than the space length of the application program of the DSP core x stored in the FLASH. If yes, go to step (D3), otherwise go to step (D2.2);

[0044] (D3) Jumping the program according to the application program entry address of the DSP core x, and running the application program of the DSP core x.

[0045] Further, the application program of the main DSP includes the following steps:

[0046] (Z1) Setting the value of the start register ADD_BOOT_1 of the DSP core 1 to valid, representing that the booting of the DSP core 1 is successful;

[0047] (Z2) Starting the timer;

[0048] (Z3) If the handshake instruction sent by the external device is received, go to step (Z6), otherwise go to step (Z4);

[0049] (2-4) If the timer count is greater than the set threshold value, go to step (Z5);

[0050] (Z5) Executing the target function program of the DSP core 1, and ending;

[0051] (Z6) Feeding back the handshake success to the external device through the external data interface;

[0052] (Z7) judging whether the program update instruction and the program data to be updated sent by the external device are received, if yes, entering step (Z8), otherwise, entering step (Z7);

[0053] (Z8) setting the program update register ADD_UPDATA as x;

[0054] (Z9) setting the integer variable ptrB as 0, the integer variable add1 B as the first address of the program data to be updated, and the integer variable add2B as the first address of the application program of the DSP core x stored in the FLASH;

[0055] (Z10) judging whether the value of the program update register ADD_UPDATA is 0, if yes, entering step (Z11), otherwise, entering step (Z8);

[0056] (Z11) writing the program data to be updated into the address space of the application program of the DSP core x in the FLASH in the address order;

[0057] (Z11.1) setting the value in the address (add2B+ptrB) as the value in the address (add1 B+ptrB);

[0058] (Z11.2) adding 1 to ptrB;

[0059] (Z11.3) judging whether ptrB is greater than the space length of the program data to be updated, if yes, entering step (Z12), otherwise, entering step (Z11.1);

[0060] (Z12) feeding back the success of the application program update of the DSP core x through the external data interface.

[0061] Further, the application program of the DSP includes the following steps:

[0062] (C1) setting the value of the start register ADD_BOOT_x of the DSP core x as valid, representing the booting of the DSP core x is successful, x=2, 3, …, n;

[0063] (C2) executing the target function program of the DSP core x.

[0064] Further, the target function program refers to the function program of the DSP core decomposed from the final function of the system, and the target function programs are different for different purposes.

[0065] The application further provides a computer program product, which, when executed by a processor, realizes the steps of the above method.

[0066] Compared with the prior art, the present application has the advantages of:

[0067] The conventional multi-core DSP program guiding needs multiple FLASH chips, that is, the number of FLASH chips is equal to the number of DSP cores, and the present application only needs one FLASH chip to realize the multi-core DSP program guiding, which can significantly reduce the layout area and cost, and the guiding of each core is relatively independent, and the guiding failure of the main core does not lead to the guiding failure of other cores. BRIEF DESCRIPTION OF DRAWINGS

[0068] Figure 1 The main circuit relationship involved in the method of the present application is shown in the figure.

[0069] Figure 2 The solidification example of the multi-core DSP program in the FLASH of the present application is shown in the figure.

[0070] Figure 3 The guiding and updating control program flowchart of the FPGA end of the present application is shown in the figure.

[0071] Figure 4 The guiding full flowchart of the DSP of the present application is shown in the figure.

[0072] Figure 5 The secondary guiding program flowchart of the DSP of the present application is shown in the figure.

[0073] Figure 6 The application program flowchart of the main DSP of the present application is shown in the figure.

[0074] Figure 7 The application program flowchart of the slave DSP of the present application is shown in the figure. DETAILED DESCRIPTION

[0075] In order to better understand the technical scheme of the present application, the specific embodiments of the present application will be specifically described below with reference to the accompanying drawings.

[0076] The main circuit relationship involved in the method of the present application is shown in the figure. Figure 1 As shown in the figure, the EMIF bus and the reset signal of the multi-core DSP are connected with the FPGA, the data bus, the address bus and the read-write control signal of one FLASH are connected with the FPGA, and the external device is connected with the FPGA through the external data interface; the secondary guiding program and the application program of the multi-core DSP are solidified in the FLASH according to certain rules, for example, the example of storage according to the DSP core number sequence is shown in the figure. Figure 2 As shown in the figure; one of the DSP cores is selected as the main DSP, and the others are slave DSPs, the main DSP controls the program communication with the external device through the EMIF bus and the external data interface of the FPGA (the external data interface can be selected according to the hardware resource situation, without special requirements).

[0077] The FPGA end controls the reset signal of the multi-core DSP and accesses the FLASH to realize program booting and updating control of the multi-core DSP, as shown in Figure 3

[0078] The multi-core DSP end, under the booting control of the FPGA, uses the self-boosting function of the DSP after reset to perform booting for the first time, moves the second booting program from the BOOT space of the DSP core to the SRAM in the DSP core, reads the application program of the DSP core from the FLASH and moves it to the SRAM for running by running the second booting program, completes the second booting, and the whole booting flow of the DSP is as shown in Figure 4 , and the flow of the second booting program is as shown in Figure 5 . After the second booting of the master DSP is completed, the application program of the master DSP is executed to realize the handshake function by establishing a communication mechanism with the external device, receives the instruction sent by the external device, and enters the program updating flow after the handshake is successful, cooperates with the FPGA updating control, and updates the program of the DSP core that needs to be updated according to the instruction, as shown in Figure 6 . After the second booting of the slave DSP is completed, the application program of the slave DSP is executed, as shown in Figure 7 .

[0079] Specifically, the FPGA end realizes access control of the FLASH by running the booting and updating control program, and realizes program booting and updating control of the multi-core DSP.

[0080] The booting and updating control program realizes the specific mode as follows:

[0081] (1) Set the start register ADD_BOOT_x of the master DSP and the slave DSP to be invalid, which represents that the corresponding DSP does not boot successfully

[0082] (2) Set the program updating register ADD_UPDATA of the master DSP to be 0, which represents that no DSP core needs to update the program;

[0083] (3) Initialize the external interface (the external interface can realize interactive communication, and has no special requirements);

[0084] (4) Reset all DSP cores through the reset signal pin and keep, and the keeping time cannot be less than the minimum time of the DSP reset signal determination validity;

[0085] (5) Program booting of the master DSP (DSP core 1);

[0086] ​(5.1) connect the EMIF bus of DSP core 1 with the data bus, address bus and read-write control signal of FLASH, and shift the address bus to the first address of the program of DSP core 1 stored in FLASH;

[0087] (5.2) cancel the reset of DSP core 1, and start the timer at the same time;

[0088] (5.3) read the value of the start-up register ADD_BOOT_1 of DSP core 1, if the value is invalid, go to step (5.4), otherwise go to step (6);

[0089] (5.4) read the value of the timer, if the value of the timer is greater than the set threshold, go to step (6), otherwise go to step (5.3);

[0090] (6) boot the program from the DSP according to the predetermined order (here, the order of increasing core number is used to describe);

[0091] (6.1) initialize the counter k as 2;

[0092] (6.2) connect the EMIF bus of DSP core k with the data bus, address bus and read-write control signal of FLASH, and shift the address bus to the first address of the program of DSP core k stored in FLASH;

[0093] (6.3) cancel the reset of DSP core k, and start the timer at the same time;

[0094] (6.4) read the value of the start-up register ADD_BOOT_k of DSP core k, if the value is invalid, go to step (6.5), otherwise go to step (6.6);

[0095] (6.5) read the value of the timer, if the value of the timer is greater than the set threshold, go to step (6.6), otherwise go to step (6.4);

[0096] (6.6) increase the counter k by 1;

[0097] (6.7) if all DSP cores are reset, go to step (7), otherwise go to step (6.2);

[0098] (7) integrate the values of the start-up registers of all cores, judge whether the start-up of each core is successful (the value of the start-up register of the DSP core whose start-up is successful is valid), and feed back the result through the external interface;

[0099] (8) control the reading and writing of FLASH according to the program update register value of the master DSP;

[0100] (8.1) read the value of the register ADD_UPDATA, if the value is equal to the number x of the DSP core (x = 1, 2, 3,..., n), go to step (8.2), otherwise go to step (8.1);

[0101] (8.2) connect the EMIF bus of the DSP core x with the data bus, address bus and read-write control signal of the FLASH, and shift the address bus to the first address of the program of the DSP core x stored in the FLASH;

[0102] (8.3) set the integer value in the register ADD_UPDATA to 0, and go to step (8.1).

[0103] When the reset of the DSP core x is cancelled in step (5.2) or step (6.3) of the multi-core DSP program booting and updating control program, the DSP side carries out primary booting and secondary booting, through the primary booting, the secondary booting program is moved from the BOOT space of the DSP core to the SRAM in the DSP core, through running the secondary booting program, the application program of the DSP core is read from the FLASH and moved to the SRAM for running, the secondary booting is completed, and the specific mode is as follows:

[0104] (1) move 1K size data from the starting address of the BOOT space of the DSP to the SRAM and run (i.e. through the FPGA, the access address is shifted according to the first address of the FLASH storage of the core x);

[0105] (2) run the secondary booting program of the DSP;

[0106] (2.1) set the integer variable ptrA to 0, set the integer variable add1A to the first address of the program running storage, and set the integer variable add2A to the first address of the application program of the DSP core x (x = 1, 2, 3,..., n) stored in the FLASH;

[0107] (2.2) assign the value in the address (add1A + ptrA) to the value in the address (add2A + ptrA);

[0108] (2.3) set ptrA equal to ptrA plus 1;

[0109] (2.4) if ptrA is greater than the space length of the application program of the DSP core x stored in the FLASH, go to step (3), otherwise go to step (2.2);

[0110] (3) jump the program according to the application program entry address of the DSP core x, and run the application program of the DSP core x.

[0111] The application program of the main DSP realizes the handshake function by establishing a communication mechanism with the external device, receives the instruction sent by the external device, and after the handshake is successful, enters the program updating flow, cooperates with the FPGA updating control, and updates the program of the DSP core required to be updated according to the instruction requirement, and realizes the specific mode as follows:

[0112] (1) The value of the start register ADD_BOOT_1 of the DSP core 1 is set, which represents that the booting of the DSP core 1 is successful;

[0113] (2) Start the timer;

[0114] (3) If the handshake instruction sent by the external device is received, step (6) is entered, otherwise step (4) is entered;

[0115] (4) If the timer count is greater than the set threshold value, step (5) is entered;

[0116] (5) Execute the target function program of the DSP core 1 (the target function program is the function of the DSP core decomposed to the system final function, and the target function program is different for different purposes);

[0117] (6) Feedback the handshake success to the external device through the external interface;

[0118] (7) If the program updating instruction of the core x (x=1, 2, 3, …, n) and the program data to be updated sent by the external device are received, step (8) is entered, otherwise step (7) is entered;

[0119] (8) The program updating register ADD_UPDATA is set to x;

[0120] (9) The integer variable ptrB is set to 0, the integer variable add1 B is set to the first address of the program data to be updated, and the integer variable add2B is set to the first address of the application program of the DSP core x (x=1, 2, 3, …, n) in the FLASH;

[0121] (10) If the value of the program updating register ADD_UPDATA is 0, step (11) is entered, otherwise step (8) is entered;

[0122] (11) The program data to be updated is written into the address space of the application program of the DSP core x (x=1, 2, 3, …, n) in the FLASH in the address order;

[0123] (11.1) The value in the address (add2B+ptrB) is assigned to the value in the address (add1 B+ptrB);

[0124] (11.2) ptrB is equal to ptrB plus 1;

[0125] (11.3) If ptrB is greater than the space length of the program data to be updated, go to step (12), otherwise go to step (11.1);

[0126] (12) Feedback the application program update success of the DSP core x (x = 1, 2, 3, …, n) to the external interface.

[0127] From the application program of the DSP, only the start register is set to be valid before the target function program is executed, and the specific mode is as follows:

[0128] (1) The start register ADD_BOOT_x of the DSP core x (x = 2, 3, …, n) is set to be valid, which represents the booting success of the DSP core x;

[0129] (2) Execute the target function program of the DSP core x (the target function program refers to the function program of the DSP core which is decomposed to complete the final function of the system, and the target function program is different for different purposes).

[0130] It can be understood that the present application is described through the embodiments, and those skilled in the art know that various changes or equivalent replacements can be made to the features and embodiments without departing from the spirit and scope of the present application. In addition, the features and embodiments can be modified to adapt to specific conditions under the guidance of the present application without departing from the spirit and scope of the present application. Therefore, the present application is not limited by the specific embodiments disclosed herein, and the embodiments falling within the scope of the claims of the present application all belong to the scope of protection of the present application.

[0131] The contents not described in detail in the specification of the present application are the known technology of those skilled in the art.

Claims

1. A time-division multiplexed multi-core DSP program booting and updating method, characterized in that, include: Connect the EMIF bus and reset signal of the multi-core DSP to the FPGA, connect the FPGA to a FLASH chip, and connect the FPGA to external devices through the FPGA's external data interface. The program of the multi-core DSP is stored in FLASH in a predetermined order, and the program includes a secondary boot program and an application program; One DSP core in the multi-core DSP is selected as the master DSP, and the rest are slave DSPs. The master DSP communicates with external devices through the EMIF bus and the external data interface of the FPGA. The FPGA controls the multi-core DSP by controlling the reset signal and accessing the FLASH memory, thereby enabling program booting and update control of the multi-core DSP. Under the FPGA boot control, each DSP core utilizes its bootstrap function after DSP reset to perform an initial boot, moving the secondary boot program from its BOOT space to its SRAM. By running the secondary boot program, the DSP core's application program is read from FLASH and moved to SRAM for execution, completing the secondary boot. After the main DSP's secondary boot is complete, its application program is executed. A communication mechanism is established with external devices to achieve a handshake function, receiving instructions from external devices. After a successful handshake, the program update process begins, cooperating with FPGA update control to update the programs of DSP cores requiring updates according to the instructions. After the secondary boot of the slave DSP is complete, its application program is executed.

2. The time-division multiplexing multi-core DSP program booting and updating method according to claim 1, characterized in that: A multi-core DSP consists of n DSP cores, where x represents the x-th DSP core, and x = 1, 2, 3, ..., n. DSP core 1 is the master DSP, and DSP cores 2 to n are slave DSPs. The FPGA controls access to the FLASH memory and performs program booting and update control for the multi-core DSP by running a boot update control program, including the following steps: (F1) Invalidates the ADD_BOOT_x boot register of the master DSP and slave DSP, indicating that the corresponding DSP core has failed to boot. (F2) Sets the main DSP's program update register ADD_UPDATA to 0, indicating that no DSP core needs to update its program; (F3) Initialize the external data interface; (F4) Resets and holds all DSP cores via the reset signal pin; (F5) Perform program guidance and control on the main DSP: (F5.1) Connect the EMIF bus of DSP core 1 to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the starting address of the program of DSP core 1 stored in FLASH; (F5.2) Cancel the reset of DSP core 1 and start the timer simultaneously; (F5.3) Read the value of ADD_BOOT_1 in the DSP core 1 boot register. If the value is invalid, proceed to step (F5.4); otherwise, proceed to step (F6). (F5.4) Read the timer value. If the timer value is greater than the set threshold, proceed to step (F6); otherwise, proceed to step (F5.3). (F6) Boot the DSP program in a predetermined order: (F6.1) Initialize the counter k to 2; (F6.2) Connect the EMIF bus of DSP core k to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the starting address of the program of DSP core k stored in FLASH; (F6.3) Cancel the reset of DSP core k and start the timer simultaneously; (F6.4) Read the value of ADD_BOOT_k in the DSP core k boot register. If the value is invalid, proceed to step (F6.5); otherwise, proceed to step (F6.6). (F6.5) Read the timer value. If the timer value is greater than the set threshold, proceed to step (F6.6); otherwise, proceed to step (F6.4). (F6.6) Increment the counter k by 1; (F6.7) Determine whether all DSP cores have canceled the reset. If yes, proceed to step (F7); otherwise, proceed to step (F6.2). (F7) Determine whether each core has started successfully based on the value of its startup register, and feed back the result through an external data interface. (F8) Control program updates for multi-core DSPs: (F8.1) Read the value of register ADD_UPDATA. If the value is equal to the DSP core number x, proceed to step (F8.2); otherwise, proceed to step (F8.1). (F8.2) Connect the EMIF bus of DSP core x to the data bus, address bus and read / write control signal of FLASH, and offset the address bus to the starting address of the program of DSP core x stored in FLASH; (F8.3) Set the value in the ADD_UPDATA register to 0 and proceed to step (F8.1).

3. The time-division multiplexing multi-core DSP program booting and updating method according to claim 2, characterized in that: When the reset of DSP core x is cancelled in step (F5.2) or step (F6.3) of the FPGA-side boot and update control program, the DSP-side performs a first boot and a second boot, including the following steps: (D1) Move the secondary boot program from the starting address of the BOOT space to SRAM via the EMIF bus; (D2) Run the DSP secondary boot program: (D2.1) Set integer variable ptrA to 0, integer variable add1A to the starting address where the program is stored, and integer variable add2A to the starting address where the application program of DSP core x is stored in FLASH. (D2.2) Assign the value at address (add1A+ptrA) to the value at address (add2A+ptrA); (D2.3)ptrA plus 1; (D2.4) Determine whether ptrA is greater than the space length of the application program stored in FLASH on the DSP core x. If yes, proceed to step (D3); otherwise, proceed to step (D2.2). (D3) Jump to the program according to the application entry address of DSP core x and run the application of DSP core x.

4. The time-division multiplexing multi-core DSP program booting and updating method according to claim 3, characterized in that: The application program executing the main DSP establishes a communication mechanism with external devices to perform a handshake function, receives instructions from the external devices, and enters the program update process after a successful handshake. In coordination with the FPGA update control, it updates the program of the DSP cores that require updates according to the instructions, including the following steps: (Z1) Sets the value of ADD_BOOT_1 in the boot register of DSP core 1 to valid, indicating that DSP core 1 has successfully booted; (Z 2) Start the timer; (Z 3) If a handshake command is received from an external device, proceed to step (Z6); otherwise, proceed to step (Z4). (Z4) If the timer count is greater than the set threshold, proceed to step (Z5); (Z5) Execute the target function program of DSP core 1, and end; (Z6) Successful handshake is reported to the external device via the external data interface; (Z7) Determine whether the DSP core x program update instruction and the program data to be updated have been received from the external device. If yes, proceed to step (Z8); otherwise, proceed to step (Z7). (Z8) Set the program update register ADD_UPDATA to x; (Z9) Set integer variable ptrB to 0, integer variable add1B to the starting address of the program data to be updated, and integer variable add2B to the starting address of the DSP core x application program stored in FLASH. (Z10) Determine whether the value of the program update register ADD_UPDATA is 0. If yes, proceed to step (Z11); otherwise, proceed to step (Z8). (Z11) Write the program data to be updated into the address space of the DSP core x application in FLASH according to the address order; (Z11.1) Assigns the value at address (add2B+ptrB) to the value at address (add1B+ptrB); (Z11.2)ptrB plus 1; (Z11.3) Determine whether ptrB is greater than the space length of the program data to be updated. If yes, proceed to step (Z12); otherwise, proceed to step (Z11.1). (Z12) Feedback from the external data interface indicates that the application update of DSP core x was successful.

5. The time-division multiplexing multi-core DSP program booting and updating method according to claim 1, characterized in that: Executing the application from the DSP includes the following steps: (C1) Set the value of ADD_BOOT_x in the boot register of DSP core x to valid, which means that DSP core x has successfully booted. x = 2, 3, ..., n; (C2) Execute the target function program of DSP core x.

6. The time-division multiplexing multi-core DSP program booting and updating method according to claim 5, characterized in that: The target function program refers to the function program that is decomposed to the DSP core to complete the final function of the system. The target function program is different for different purposes.

7. A computer program product, characterized in that: When the computer program product is executed by a processor, it implements the steps of the method as described in any one of claims 1 to 6.

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