BIOS parameter debugging method, program product, electronic equipment and storage medium

Abstract

The invention discloses a BIOS parameter debugging method, a program product, electronic equipment and a storage medium, and relates to the technical field of BIOS tuning, the BIOS parameter debugging method comprises the following steps: respectively inputting each group of candidate BIOS parameter combinations into a hybrid model; obtaining at least one of a CPU utilization rate sub-score, a memory bandwidth sub-score, a delay sub-score and a power consumption sub-score corresponding to each group of candidate BIOS parameter combinations output when the hybrid model runs in the target business scene; and based on the CPU utilization rate sub-score, the memory bandwidth sub-score, the delay sub-score and the power consumption sub-score, determining a target BIOS parameter combination corresponding to the target business scene from each group of candidate BIOS parameter combinations. According to the BIOS parameter debugging method, the synergistic effect between hardware is comprehensively considered, and the technical effects of relatively high tuning efficiency, relatively good tuning effect and dynamic tuning capability are achieved.

Description

Technical Field

[0001] The present application relates to the technical field of BIOS tuning, and in particular to a BIOS parameter debugging method, a program product, an electronic device and a storage medium. Background Art

[0002] With the development of cloud computing and data centers, server performance tuning has become the key to improving the utilization of computing resources. One of the core means of current server performance tuning is to optimize hardware behavior by adjusting BIOS parameters. In related technologies, BIOS parameters are mainly adjusted by manual experience tuning. For example, for two different loads, AI training and database transactions, the BIOS configuration needs to be manually switched, which is inefficient and prone to errors, and the tuning effect is poor; and it is difficult to cope with complex and changing load environments. Summary of the invention

[0003] The present application provides a BIOS parameter debugging method, a program product, an electronic device and a storage medium, so as to at least solve the problems of low efficiency and poor tuning effect in the related art.

[0004] The present application provides a BIOS parameter debugging method, including: Inputting each group of candidate BIOS parameter combinations into a hybrid model, respectively, wherein the hybrid model includes: at least two of a CPU load model, a memory load model, and a GPU load model pre-built for simulating server operation; Obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each group of the candidate BIOS parameter combinations output by the hybrid model running in the target business scenario; Based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score, a target BIOS parameter combination corresponding to the target business scenario is determined from each group of the candidate BIOS parameter combinations.

[0005] The present application also provides a computer program product, comprising: A first processing module, configured to input each group of candidate BIOS parameter combinations into a hybrid model, wherein the hybrid model includes at least two of a pre-built CPU load model, a memory load model, and a GPU load model; A second processing module is used to obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each group of the candidate BIOS parameter combinations output by the hybrid model running in the target business scenario; The third processing module is used to determine a target BIOS parameter combination corresponding to the target business scenario from each group of the candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score.

[0006] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any one of the above-mentioned BIOS parameter debugging methods when executing the computer program.

[0007] The present application also provides a computer-readable storage medium, in which a computer program is stored, wherein when the computer program is executed by a processor, the steps of any of the above-mentioned BIOS parameter debugging methods are implemented.

[0008] Through the present application, different candidate BIOS parameter combinations are respectively input into a hybrid model that can simulate hardware collaborative efficiency and dynamic load characteristics. The hybrid model simulates the sub-scores of performance indicators such as CPU utilization, memory bandwidth, latency, and power consumption corresponding to the server under different BIOS parameter combinations in the target business scenario, so as to obtain the target BIOS parameter combination based on these sub-scores. Therefore, the technical problems of low efficiency and poor tuning effect can be solved, and the technical effect of responding to load fluctuations, comprehensively considering the synergy between various hardware, and having high tuning efficiency, good tuning effect and dynamic tuning capability can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0010] Figure 1 One of the flow charts of a BIOS parameter debugging method provided in an embodiment of the present application; Figure 2 A second flowchart of a BIOS parameter debugging method provided in an embodiment of the present application; Figure 3 A third flowchart of a BIOS parameter debugging method provided in an embodiment of the present application; Figure 4 A fourth flowchart of a BIOS parameter debugging method provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a computer program product provided in an embodiment of the present application; Figure 6A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0012] It should be noted that, in the description of this application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0013] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0014] In conjunction with the specific application environment architecture or the specific hardware architecture on which the execution of the BIOS parameter debugging method depends, the specific application environment architecture or the specific hardware architecture is described herein.

[0015] like Figure 2 As shown, the execution device of the BIOS parameter debugging method of the present application includes: a device main program, a test device, a database and a server. Among them, the device main program is used to schedule data and various models, the test device is responsible for calculating data acquisition and execution tasks; the database is used for data storage and parameter storage.

[0016] The overall architecture of the BIOS parameter debugging method of the present application includes: a BIOS data acquisition layer, a BIOS parameter modeling, a load generation layer, a performance dynamic evaluation and modeling layer, and a dynamic performance adjustment layer.

[0017] Among them, the main program obtains the Map String and configuration path of BIOS options in batches through the SCE tool, supports atomic setting and checksum verification of parameter groups, builds a BIOS parameter library based on I, II, and III rule bases, and obtains multiple sets of candidate BIOS parameter combinations.

[0018] Atomic configuration of BIOS options is achieved through the SCELNX_64 tool, supporting transactional operations of configuration groups (all successful or rollback to the last stable state).

[0019] After starting the GPU bandwidth test (nvqual tool) based on the priority policy, superimpose the CPU / memory stress model (stress-ng, stressapptest) to simulate the resource contention in real business scenarios and run the hybrid model.

[0020] Real-time monitoring of CPU IPC, memory bandwidth, GPU memory utilization, and machine power consumption, with millisecond-level sampling.

[0021] A state-action space model is constructed. The state vector includes the BIOS configuration code and the real-time score value. The action space is the BIOS option adjustment instruction (such as HyperThreading: 0→1). A performance and BIOS parameter evaluation model is constructed to determine the target BIOS parameter combination corresponding to the target business scenario from multiple sets of candidate BIOS parameter combinations based on the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score.

[0022] During the application process, BIOS parameters are dynamically adjusted according to business needs to ensure a balance between server performance and resources.

[0023] The specific implementation method will be described in detail below.

[0024] The embodiment of the present application provides a BIOS parameter debugging method, and the method is described in detail in conjunction with the execution flow of the BIOS parameter debugging method.

[0025] like Figure 1 As shown, the BIOS parameter debugging method includes: step 110, step 120 and step 130.

[0026] Step 110, input each group of candidate BIOS parameter combinations into the hybrid model respectively; In this step, BIOS (Basic Input / Output System) parameters are configuration options used to configure hardware and system behavior when the computer starts, including but not limited to: startup settings, CPU and overclocking, memory, storage, power management, security, and monitoring parameter categories.

[0027] The candidate BIOS parameter combination is a combination of state values ​​of one or more adjustable BIOS parameters, and different candidate BIOS parameter combinations correspond to different BIOS parameters and / or different state values ​​of BIOS parameters.

[0028] The hybrid model is established for each component and link of the server. It can simulate the hardware coordination efficiency, hardware resource competition and dynamic load characteristics during the operation of the server. It includes simulation models, algorithm models, data acquisition models and other types of models.

[0029] The hybrid model may include: at least two of a pre-built CPU load model, a memory load model, and a GPU load model for simulating server operation.

[0030] The CPU load model is a model used to simulate CPU load, the memory load model is a model used to simulate memory load, and the GPU load model is a model used to simulate GPU load.

[0031] In some embodiments, the hybrid model may also include other types of load models, such as a graphics card load model and a PCIe link load model, etc. During operation, the load models dynamically collaborate with each other.

[0032] The BIOS parameter combination is used to configure the hybrid model so that the hybrid model can simulate the operation of the server under the corresponding BIOS parameter configuration and output the corresponding performance indicators. It is understandable that the performance indicators output by the hybrid model operation may also be different due to different candidate adjustable parameters input to the hybrid model.

[0033] Step 120: Obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each group of candidate BIOS parameter combinations output by the hybrid model running in the target business scenario; In this step, the target business scenario can be any business scenario, such as the current business scenario, or can be based on user customization. For each business scenario, the corresponding BIOS parameter debugging method is similar, and the following takes a business scenario as an example for explanation.

[0034] CPU utilization, memory bandwidth, latency, and power consumption are performance indicators used to evaluate server performance and computing power. The sub-scores are the quantitative scores of each performance indicator. The higher the sub-score, the better the corresponding performance indicator.

[0035] Different combinations of candidate BIOS parameters may result in different server performance and computing power after configuration.

[0036] In some embodiments, the performance indicators may also include other indicators, such as graphics card related indicators, etc., which may be based on user-defined settings and are not limited in this application.

[0037] In the actual execution process, the hybrid model can run according to the given BIOS parameters, such as obtaining the BIOS option combination and BIOS option path of the BIOS parameter library, obtaining the Map String of the BIOS option, and building a parameter relationship map. To configure the BIOS option, multiple transactions are established through the thread pool, and each transaction sets the option values ​​of the BIOS options in batches through the SCE. The BIOS parameter path is traversed on the control machine side, and after setting the parameter path of each BIOS, the server is restarted to make the BIOS parameters take effect. At the same time, the hybrid model of the server is started. During this process, performance indicators are dynamically collected, including but not limited to CPU utilization, memory bandwidth, latency, power consumption and other performance indicators, and converted into scores to obtain corresponding sub-scores.

[0038] Step 130: Determine a target BIOS parameter combination corresponding to the target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score.

[0039] In this step, the target BIOS parameter combination is a screened BIOS parameter combination that can best match the server performance of the server with the requirements in the target business scenario, and may include one or more candidate BIOS parameter combinations.

[0040] For example, the server performance computing power value corresponding to each set of candidate BIOS parameter combinations can be obtained by summing the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score, and then a set of candidate BIOS parameter combinations with the highest server performance computing power value can be selected as the target BIOS parameter combination.

[0041] For the sub-scores not obtained in step 120 , a value of 0 may be assigned to them for calculation in step 130 .

[0042] During the research and development process, the inventors found that in the related technologies, there are mainly the following BIOS tuning methods: 1) Manual BIOS tuning, where the administrator sets BIOS parameters based on experience (such as turning off hyperthreading and enabling Turbo Boost), and verifies the effect through performance testing tools. This method relies on manual experience and cannot cover complex parameter combinations (such as a server BIOS option with more than 500 items and a combination space of 10^100); and the tuning cycle is long and cannot respond to load fluctuations in real time. 2) Static performance testing tools, using tools such as Prime95 (CPU stress test) and FIO (storage IO test) to test the performance of each component separately. This method only tests a single component and ignores the hardware synergy effect (such as CPU cache contention leading to a decrease in memory bandwidth); and lacks business scenario simulation capabilities (such as mixed computing and IO load). 3) Threshold-based monitoring alarms, setting fixed thresholds (such as CPU utilization > 90% triggers an alarm), and manual intervention tuning; this method requires passive response, and only triggers correction after performance degradation, with a high risk of business jitter; and cannot predict potential bottlenecks (such as future performance degradation caused by an increase in the bit error rate of the PCIe link).

[0043] In the present application, a hybrid model capable of simulating hardware collaborative efficiency and dynamic load characteristics is pre-constructed, and multiple groups of candidate BIOS parameter combinations corresponding to different BIOS parameter combination forms are respectively input into the hybrid model. The hybrid model simulates the operation status under the hardware collaborative efficiency and dynamic load characteristics in the target business scenario, and obtains the server performance computing power value corresponding to the server under different BIOS parameter combination forms, so as to screen one or more groups of candidate BIOS parameter combinations that can make the server performance reach a higher level in the target business scenario according to the server performance computing power value, and realize BIOS parameter tuning. The dynamic tuning capability is combined with the dynamic load model and the real-time performance score, and the synergy between the hardware can be comprehensively considered, such as the CPU cache contention leading to the decrease of memory bandwidth and other problems, so as to realize the rapid location of cross-component resource conflicts, reduce invalid configuration paths, and obtain the target BIOS parameter combination that is most suitable for the current business scenario. It is suitable for complex and changeable load environments and has a good tuning effect. In addition, the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score corresponding to each group of candidate BIOS parameter combinations output by the hybrid model can be used to quantitatively evaluate the server performance computing power. It can also combine multi-dimensional performance indicators for comprehensive evaluation to achieve coordinated optimization of energy efficiency and performance. For example, it can consider the natural contradiction between high-performance modes (such as CPU Turbo Boost) and energy-saving strategies (such as C-state), dynamically balance instantaneous computing power requirements and long-term energy consumption costs, and predict the optimal BIOS parameter combination through reinforcement learning algorithms, thereby reducing the traditional manual traversal tuning time and improving tuning efficiency and tuning effects.

[0044] According to the BIOS parameter debugging method provided in the embodiment of the present application, different candidate BIOS parameter combinations are respectively input into a hybrid model that can simulate hardware synergy efficiency and dynamic load characteristics. The hybrid model simulates the sub-scores of performance indicators such as CPU utilization, memory bandwidth, latency, and power consumption corresponding to the server under different BIOS parameter combinations in the target business scenario, so as to obtain the target BIOS parameter combination based on these sub-scores. The method can respond to load fluctuations, comprehensively consider the synergy between various hardware, and has higher tuning efficiency, better tuning effect and dynamic tuning capability.

[0045] In some embodiments, step 130 may include: According to the weight sequence, the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score are weighted and summed to obtain the server performance computing power score corresponding to each group of candidate BIOS parameter combinations; Based on the server performance computing power score, a target BIOS parameter combination is determined from each group of candidate BIOS parameter combinations.

[0046] In this embodiment, the server performance computing power score is used to characterize the server performance computing power. The higher the score, the higher the computing power value.

[0047] The weight sequence is a sequence consisting of weights corresponding to various performance indicators such as CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score.

[0048] The weight sequence can be based on user-defined or initial weights. For example, the weight sequence can be set to: CPU utilization (CPU_IPC): 0.4; memory bandwidth (Mem_BW): 0.3; latency (Latency): 0.2; power consumption (Power): 0.1.

[0049] In the actual execution process, the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, power consumption sub-score, etc. can be weighted and summed based on the weight sequence to obtain the server performance computing power score.

[0050] For each set of candidate BIOS parameter combinations, a server performance computing power score can be calculated, and a set of candidate BIOS parameter combinations with the highest scores among these server performance computing power scores is determined as the target BIOS parameter combination.

[0051] According to the BIOS parameter debugging method provided in the embodiment of the present application, by dynamically collecting performance indicators and converting them into sub-scores, weighted scoring is used to obtain a server performance computing power score to quantify the performance of the server under different BIOS parameter combinations, thereby achieving better tuning precision and accuracy.

[0052] In some embodiments, the weight sequence can be determined using the Analytic Hierarchy Process (AHP).

[0053] In this embodiment, the Analytic Hierarchy Process (AHP) constructs a hierarchical structure, pairwise comparison judgment matrices, calculates weights, and performs consistency tests.

[0054] During actual execution, a weighted evaluation function can be constructed based on the AHP to calculate the server performance computing power value. For example, the server performance computing power score Score can be calculated through the following formula: Score = 0.4 * CPU utilization sub-score + 0.3 * memory bandwidth sub-score + 0.2 * latency sub-score + 0.1 * power consumption sub-score.

[0055] According to the BIOS parameter debugging method provided by the embodiments of the present application, by constructing a multi-dimensional performance scoring model using the AHP, screening the target BIOS parameter combination based on comprehensive CPU IPC, memory bandwidth, latency, and power consumption indicators, and realizing BIOS parameter optimization, the energy efficiency fluctuation can be reduced and the optimization effect can be improved.

[0056] In some embodiments, the weight sequence can be adjusted based on the target business requirements of the target business scenario.

[0057] In this embodiment, the target business requirements can be the requirements for server performance in the target business scenario. It can be understood that for different business scenarios, the emphasis on server computing, latency, and other performance requirements may be different. Based on the emphasis of the target business requirements, the initial weight sequence corresponding to the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score can be adjusted.

[0058] In some embodiments, when the target business requirements emphasize computing, increase the weight corresponding to the CPU utilization sub-score in the weight sequence; When the target business requirements emphasize latency, increase the weight corresponding to the latency sub-score in the weight sequence.

[0059] For example, if the target business requirements emphasize computing more, the weight sequence can be adjusted to: [0.4, 0.3, 0.2, 0.1]; If the target business requirements emphasize latency more, the weight sequence can be adjusted to: [0.2, 0.2, 0.5, 0.1].

[0060] According to the BIOS parameter debugging method provided in the embodiment of the present application, the weight sequence is dynamically adjusted through the target business needs, and various performance indicators of the server computing power can be monitored according to the business type to achieve adaptive scoring, thereby screening out the target BIOS parameter combination that best matches the current business scenario, which is suitable for complex and changeable business scenarios.

[0061] In some embodiments, parameter combinations can also be predicted based on the PPO algorithm, and the state-action space can be modeled to calculate the server performance computing power scores corresponding to each group of candidate BIOS parameter combinations.

[0062] Among them, the state is the current BIOS configuration code (binary vector) + real-time performance score (Score); the action is used to adjust the value of the specified BIOS option (such as HyperThreading: 0→1).

[0063] Use PyTorch to build a 3-layer MLP, input a state vector, and output an action probability distribution. Execute the strategy in parallel on multiple servers to accelerate convergence. Record the candidate BIOS parameter combinations corresponding to the high server performance computing power scores of the top number of targets (Top-N), and output the corresponding relationship between the candidate BIOS parameter combinations and server performance computing power.

[0064] In order to facilitate the automatic matching of the target BIOS parameter combination corresponding to the business scenario according to the actual business scenario in the subsequent application process, such as TurboBoost=Enabled in the HPC scenario and SR-IOV=Enable in the virtualization scenario.

[0065] In some embodiments, inputting each set of candidate BIOS parameter combinations into the hybrid model may include: The hybrid model is configured based on each group of candidate BIOS parameter combinations. When the GPU load model is activated to a stable state, at least one of the CPU load model and the memory load model is dynamically injected in combination with the target business scenario to run the hybrid model.

[0066] In this embodiment, whether a steady state is reached can be determined according to the size of the processor (SM) utilization. If the SM utilization is greater than or equal to a preset threshold, such as SM utilization ≥ 85% or SM utilization ≥ 90%, it is considered that a steady state is reached.

[0067] During the actual execution process, the GPU load model can be activated to a stable state based on the simulation of hardware resource competition, and allocated in advance according to the load size, thread size, and CPU utilization. Then the CPU load model or memory load model can be dynamically injected for concurrency control, thereby avoiding the situation where the GPU cannot be executed due to CPU priority startup, thereby improving the stability of server operation.

[0068] Then, the BIOS option combination (i.e., candidate BIOS parameter combination) and BIOS option path of the BIOS parameter library are obtained, the Map String of the BIOS option is obtained, and a parameter relationship map is constructed. To configure the BIOS option, multiple transactions are established through the thread pool, and each transaction sets the option values ​​of the BIOS options in batches through the SCE. The BIOS parameter path is traversed in a loop on the control machine side, and after setting the parameter path of each BIOS, the server is restarted to make the BIOS parameters effective. At the same time, the hybrid dynamic model of the server is started. During this process, performance indicators such as CPU utilization, memory bandwidth, latency, and power consumption are dynamically collected. By weighted calculation of the sub-scores corresponding to each performance indicator, the server computing power performance under each set of BIOS parameter combination configurations is quantitatively evaluated.

[0069] According to the BIOS parameter debugging method provided in the embodiment of the present application, by hybrid dynamic load model and adopting priority-driven hybrid load superposition strategy, it is possible to support rapid adaptation of heterogeneous computing power scenarios and improve business performance.

[0070] In some embodiments, after inputting each set of candidate BIOS parameter combinations into the hybrid model, the method may further include: In the event that any parameter setting in the candidate BIOS parameter combination fails, the control hybrid model is restored to the last stable state.

[0071] In this embodiment, a failure rollback mechanism may be set. If any setting in the parameter group fails, it will automatically recover to the last stable state. The execution instruction is: SCELNX_64 / i / ms HyperThreading / qv 0x00.

[0072] According to the BIOS parameter debugging method provided in the embodiment of the present application, by setting an atomic rollback mechanism, it can ensure that the BIOS configuration automatically recovers to a stable state when it fails, thereby improving the reliability of the system.

[0073] In some embodiments, the CPU load model may be constructed based on the following steps: constructing a dynamic power-aware model for executing workloads; Simulate mixed load scenarios and construct business scenario simulation models; A CPU load model is obtained based on at least one of a dynamic power consumption awareness model and a business scenario simulation model.

[0074] In this embodiment, the CPU load model may include: one or more of a dynamic power consumption awareness model and a business scenario simulation model. In actual application, a corresponding model may be selected according to a target business scenario.

[0075] For the construction of a dynamic power consumption awareness model, the Intel PTU tool can be used to perform real-time TDP calibration. The execution load is: ptu-ct 1-t 172800-log-logname ptu_stress–csv. Combined with the RAPL interface, the thermal power consumption TDP is monitored in real time (accuracy ±2%).

[0076] For the construction of business scenario simulation models, you can use stress-ng to simulate mixed load scenarios. The execution strategy is: input according to the ratio of business state thread / kernel state thread = 3 / 1, stress-ng -c [business state thread] -i [kernel state thread] -t48H [duration].

[0077] In some embodiments, the memory load model may be constructed based on the following steps: Perform full memory channel scan and build a joint bandwidth-delay model based on the collected correctable error rate; Adopting adaptive thread control strategy, constructing dynamic pressure regulation algorithm model; A memory load model is obtained based on at least one of a bandwidth-delay joint model and a dynamic pressure regulation algorithm model.

[0078] In this embodiment, the memory load model may include: one or more of a bandwidth-delay joint model and a dynamic pressure adjustment algorithm model. In actual application, a corresponding model may be selected according to a target business scenario.

[0079] To build a joint bandwidth-delay model, you can use stressapptest to scan the entire memory channel, collect the correctable error rate through the Error Detection and Correction (EDAC) module, and build a reliability model stressapptest -M [value] -s [time] to obtain the joint bandwidth-delay model.

[0080] For the construction of the dynamic pressure regulation algorithm model, an adaptive thread control strategy can be used to set the dynamic pressure regulation algorithm. For example, when the actual pressure is < 90% of the target value, stress-ng --vm 16 [working threads; if the reserved pressure cannot be reached, the number of threads needs to be increased appropriately] vm-bytes 90% [load size] -t 48H [duration] is used to obtain the PSI indicator through / proc / pressure / memory and dynamically maintain the 90% load threshold.

[0081] In some embodiments, Nvqual depth test can be executed, / nvqual --test [duration] --index <0~num-1> --loops n command to perform bandwidth performance test, collect memory bandwidth and SM, etc., perform memory bandwidth bottleneck detection, and build a GPU load model.

[0082] According to the BIOS parameter debugging method provided in the embodiment of the present application, by constructing multiple load models to simulate the synergistic effect between various hardware, dynamically respond to load fluctuations, such as considering the difference between burst traffic and steady-state load, as well as delay fluctuations or power consumption mutations in high-concurrency scenarios, thereby improving the tuning effect.

[0083] The following describes a method for obtaining a candidate BIOS parameter combination.

[0084] In some embodiments, before step 110, the method may further include: According to the correlation between the BIOS parameters, the BIOS parameters are classified to obtain multiple parameter sets; Based on a combination mechanism corresponding to a target class parameter set among the multiple classes of parameters, the state values ​​of the parameters in the target class parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set; The sub-BIOS parameter combinations corresponding to the various parameter sets are combined to obtain multiple groups of candidate BIOS parameter combinations.

[0085] In this embodiment, the association relationship is used to characterize whether there is a correlation between different categories of BIOS parameters, etc., which can be obtained by analyzing the correlation between server hardware components (CPU, memory, PCIe device) and BIOS options. For example, the BIOS parameters can be divided into two categories: irrelevant and related, or the BIOS parameters can be divided into multiple categories such as mutually exclusive or non-mutually exclusive, or can be divided into more categories, which can be divided according to needs, and this application does not limit it here.

[0086] In the actual execution process, the BIOS configuration file can be exported through the SCE tool, and the BIOS option field can be accurately located based on the Map String feature matching algorithm to obtain the current BIOS default parameters (BIOS Default Values) and BIOS adjustable options (BIOS Options). A BIOS option structured data table is constructed, including BIOS basic parameters and associations; then the BIOS parameters are classified based on the associations.

[0087] After the BIOS parameters are divided, for different major categories, a combination mechanism adapted to the major category is adopted to combine the state values ​​of the BIOS parameters of each subcategory under the major category to obtain multiple groups of candidate sub-BIOS parameter combinations.

[0088] Then, the candidate sub-BIOS parameter combinations corresponding to each major category are arranged and combined to obtain multiple groups of candidate BIOS parameter combinations.

[0089] During the research and development process, the inventors also discovered that in the related technology, the traditional method of manually traversing BIOS parameters is time-consuming and difficult to enumerate all possibilities. Especially when multiple parameter dependencies are involved (such as the linkage adjustment of CPU hyperthreading and memory timing), the combination space grows exponentially, resulting in low tuning efficiency.

[0090] According to the BIOS parameter debugging method provided in the embodiment of the present application, the BIOS parameters are graded according to the association relationship between the BIOS parameters, and the BIOS parameters are combined based on the combination mechanism corresponding to each level to obtain multiple groups of candidate BIOS parameter combinations. This can reduce the traditional manual traversal tuning time and cover as many BIOS combination methods as possible, thereby improving the feasibility of each group of candidate BIOS parameter combinations, thereby improving the subsequent tuning efficiency.

[0091] In some embodiments, BIOS parameters are classified according to associations between BIOS parameters to obtain multiple parameter sets, which may include: According to the association relationship between the BIOS parameters, the BIOS parameters are divided into an unrelated parameter set, a related parameter set or a mutually exclusive parameter set.

[0092] In this embodiment, there is no dependency between the various BIOS options included in the irrelevant parameter set, such as Turbo Boost and NUMA Configuration.

[0093] Among the BIOS parameters included in the related class parameter set, there is an association relationship between at least two BIOS options, such as a tree relationship.

[0094] Among the BIOS parameters included in the mutually exclusive parameter set, there is a mutually exclusive relationship between at least two BIOS options, such as the virtualization technology conflicts with a specific energy-saving mode, and C-States and Hyper-Threading cannot be disabled at the same time.

[0095] In the actual implementation process, the BIOS options can be divided into Level I (i.e., irrelevant parameter sets), Level II (i.e., related parameter sets), and Level III (i.e., mutually exclusive parameter sets) based on the hierarchical principle shown in Table 1, and a hierarchical BIOS parameter relationship library is constructed to calculate the BIOS parameter library.

[0096] Table 1

[0097] According to the BIOS parameter debugging method provided in the embodiment of the present application, by dividing the BIOS parameters into unrelated parameter sets, related parameter sets or mutually exclusive parameter sets, multiple parameter dependencies can be considered, and the risk of system startup failure or performance abnormality caused by logical mutual exclusion between BIOS parameters can be reduced, parameter configuration conflicts and stability risks can be reduced, and the subsequent parameter tuning effect can be further improved, thereby improving the stability of the system.

[0098] The following describes the construction methods of candidate sub-BIOS parameter combinations corresponding to different class sets.

[0099] In some embodiments, based on a combination mechanism corresponding to a target class parameter set in multiple classes of parameters, the state values ​​of the parameters in the target class parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set, which may include: When the target parameter set is an irrelevant parameter set, the state values ​​of different parameters in the irrelevant parameter set are arranged and combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0100] In this embodiment, in the level I model corresponding to the irrelevant parameter set, since there is no dependency between the various BIOS options, the number of candidate sub-BIOS parameter combinations N can be calculated as: the product of the total number of BIOS Options of each option, as shown in Table 2.

[0101] Table 2

[0102] The total number of candidate sub-BIOS parameter combinations is obtained: N=i=1∏kOptionCounti (k is the total number of level I options), and the BIOS parameters included in each combination and the state values ​​corresponding to the parameters are obtained; an example is shown in Table 3: Table 3

[0103] In some embodiments, based on a combination mechanism corresponding to a target class parameter set in multiple classes of parameters, the state values ​​of the parameters in the target class parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set, which may include: When the target class parameter set is a related class parameter set, a parameter combination path is constructed according to the dependency relationship of each parameter, and the state values ​​of the parameters corresponding to the same combination path are combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0104] In this embodiment, since there is a tree relationship between the BIOS parameters in the level II model corresponding to the related class parameter set, all paths of the tree structure can be calculated by a recursive algorithm, such as Figure 3 shown.

[0105] After obtaining each path, traverse each path to obtain the total number M of level II model BIOS option combinations and a list of combination paths. Each combination path corresponds to a candidate sub-BIOS parameter combination, and the BIOS parameters included in each combination and the state values ​​corresponding to the parameters are obtained.

[0106] In some embodiments, traversing each path to obtain the total number M of level II model BIOS option combinations and a list of combination paths may include: If the current node has child nodes, add one to the total number of combinations M and record the combination path; If the current node does not have a child node, jump to the next node.

[0107] like Figure 4 As shown, in the actual execution process, the initial value of the total number of combinations M can be set to 0 first, and then check whether the node is empty. If it is not empty, add the node to the path and check whether the current node has a child node; if there is no child node, jump to the next node and continue to check whether the next node has a child node; if there is a child node, add one to the total number of combinations M and record the combination path.

[0108] In some embodiments, based on a combination mechanism corresponding to a target class parameter set in multiple classes of parameters, the state values ​​of the parameters in the target class parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set, which may include: In the case where the target class parameter set is a mutually exclusive class parameter set, the parameters in the mutually exclusive class parameter set having a relatively mutually exclusive relationship are divided into the same mutually exclusive group, and the state values ​​of the parameters corresponding to the same mutually exclusive group are obtained; The state values ​​corresponding to the mutually exclusive groups are combined to obtain at least one group of candidate sub-BIOS parameter combinations.

[0109] In this embodiment, there is a mutually exclusive relationship between the BIOS parameters in the level III model corresponding to the mutually exclusive parameter set, and the BIOS options of the level III model can be grouped according to the mutually exclusive relationship between the BIOS options.

[0110] The grouping rules are as follows: Divide mutually exclusive BIOS parameters into independent mutually exclusive groups (a total of X groups, where X is a positive integer).

[0111] In each group, the maximum number of optional values ​​Y (i.e. the maximum number of adjustable state values) is taken as the number of valid combinations of the group.

[0112] The total number of combinations is as follows: XY=i=1∏xOptionCounti(i=max(GroupOptions1,GroupOptions2,...,GroupOptionsX)); wherein XY is the total number of candidate sub-BIOS parameter combinations finally obtained; an example is shown in Table 4.

[0113] Table 4

[0114] After obtaining the candidate sub-BIOS parameter combinations corresponding to the major categories, the candidate sub-BIOS parameter combinations corresponding to the major categories may be combined to obtain multiple groups of candidate BIOS parameter combinations.

[0115] In some embodiments, after step 130, the method may further include: Control server operation based on target BIOS parameter combinations and obtain real-time performance indicator data; When a change in the target business scenario is detected and it is determined based on the real-time performance indicator data that the server performance has degraded, the target BIOS parameter combination is adjusted based on the changed target business scenario.

[0116] In this embodiment, Figure 2 An overall logic control block diagram of the method of the present application is illustrated. In actual application, if a target BIOS parameter combination under a target business scenario is predicted in advance and the server is configured and operated based on the target BIOS parameter combination, various performance indicators of the server computing power can be monitored according to the business type and business information; if the performance is too low, the BIOS parameters are dynamically adjusted according to the current business scenario in a manner such as steps 110 to 130 to perform performance tuning, thereby achieving real-time tuning.

[0117] According to the BIOS parameter debugging method provided in the embodiment of the present application, by providing a closed-loop feedback mechanism of real-time load, it is possible to dynamically switch the BIOS configuration mode according to business pressure, realize dynamic BIOS voltage regulation, and be better used in complex and changeable business scenarios.

[0118] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method.

[0119] like Figure 5 As shown, an embodiment of the present application further provides a computer program product, including: a first processing module 510 , a second processing module 520 and a third processing module 530 .

[0120] A first processing module 510 is used to input each group of candidate BIOS parameter combinations into a hybrid model, where the hybrid model includes: at least two of a pre-built CPU load model, a memory load model, and a GPU load model; The second processing module 520 is used to obtain at least one of the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score and the power consumption sub-score corresponding to each group of candidate BIOS parameter combinations output by the hybrid model running in the target business scenario; The third processing module 530 is used to determine a target BIOS parameter combination corresponding to the target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score.

[0121] According to the computer program product provided in the embodiment of the present application, different candidate BIOS parameter combinations are respectively input into a hybrid model that can simulate hardware collaborative efficiency and dynamic load characteristics. The hybrid model simulates the sub-scores of performance indicators such as CPU utilization, memory bandwidth, latency, and power consumption corresponding to the server under different BIOS parameter combinations in the target business scenario, so as to obtain the target BIOS parameter combination based on these sub-scores. The method can respond to load fluctuations, comprehensively consider the synergy between various hardware, and has high tuning efficiency, good tuning effect and dynamic tuning capability.

[0122] In some embodiments, the third processing module 530 may also be used to: According to the weight sequence, the CPU utilization sub-score, memory bandwidth sub-score, latency sub-score, and power consumption sub-score are weighted and summed to obtain the server performance computing power score corresponding to each group of candidate BIOS parameter combinations; Based on the server performance computing power score, a target BIOS parameter combination is determined from each group of candidate BIOS parameter combinations.

[0123] In some embodiments, the third processing module 530 may also be used to determine a weight sequence using a hierarchical analysis method.

[0124] In some embodiments, the first processing module 510 may also be used to: When the GPU load model is activated to a stable state, at least one of the CPU load model and the memory load model is dynamically injected in combination with the target business scenario to run the hybrid model; Each set of candidate BIOS parameter combinations is input into the hybrid model respectively.

[0125] In some embodiments, the computer program product may further include a fourth processing module configured to: After each group of candidate BIOS parameter combinations is input into the hybrid model, in the event that any parameter setting in the candidate BIOS parameter combination fails, the hybrid model is controlled to recover to the last stable state.

[0126] In some embodiments, the computer program product may further include a fifth processing module configured to: constructing a dynamic power-aware model for executing workloads; Simulate mixed load scenarios and construct business scenario simulation models; A CPU load model is obtained based on at least one of a dynamic power consumption awareness model and a business scenario simulation model.

[0127] In some embodiments, the computer program product may further include a sixth processing module, configured to: Perform full memory channel scan and build a joint bandwidth-delay model based on the collected correctable error rate; Adopting adaptive thread control strategy, constructing dynamic pressure regulation algorithm model; A memory load model is obtained based on at least one of a bandwidth-delay joint model and a dynamic pressure regulation algorithm model.

[0128] In some embodiments, the computer program product may further include a seventh processing module, configured to: Before inputting each group of candidate BIOS parameter combinations into the hybrid model, the BIOS parameters are classified according to the correlation between the BIOS parameters to obtain multiple parameter sets; Based on a combination mechanism corresponding to a target class parameter set among the multiple classes of parameters, the state values ​​of the parameters in the target class parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set; The sub-BIOS parameter combinations corresponding to the various parameter sets are combined to obtain multiple groups of candidate BIOS parameter combinations.

[0129] In some embodiments, the seventh processing module may also be used to: According to the association relationship between the BIOS parameters, the BIOS parameters are divided into an unrelated parameter set, a related parameter set or a mutually exclusive parameter set.

[0130] In some embodiments, the seventh processing module may also be used to: When the target parameter set is an irrelevant parameter set, the state values ​​of different parameters in the irrelevant parameter set are arranged and combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0131] In some embodiments, the seventh processing module may also be used to: When the target class parameter set is a related class parameter set, a parameter combination path is constructed according to the dependency relationship of each parameter, and the state values ​​of the parameters corresponding to the same combination path are combined to obtain at least one set of candidate sub-BIOS parameter combinations.

[0132] In some embodiments, the seventh processing module may also be used to: In the case where the target class parameter set is a mutually exclusive class parameter set, the parameters in the mutually exclusive class parameter set having a relatively mutually exclusive relationship are divided into the same mutually exclusive group, and the state values ​​of the parameters corresponding to the same mutually exclusive group are obtained; The state values ​​corresponding to the mutually exclusive groups are combined to obtain at least one group of candidate sub-BIOS parameter combinations.

[0133] In some embodiments, the computer program product may further include an eighth processing module configured to: After determining a target BIOS parameter combination corresponding to a target business scenario from each group of candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score, the server operation is controlled based on the target BIOS parameter combination, and real-time performance indicator data is obtained; When a change in the target business scenario is detected and it is determined based on the real-time performance indicator data that the server performance has degraded, the target BIOS parameter combination is adjusted based on the changed target business scenario.

[0134] For the description of the features in the embodiments corresponding to the computer program product, reference may be made to the relevant description of the embodiments corresponding to the BIOS parameter debugging method, which will not be described in detail here.

[0135] like Figure 6 As shown, an embodiment of the present application further provides an electronic device 600, including a memory 602 and a processor 601, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above-mentioned BIOS parameter debugging method embodiments.

[0136] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above-mentioned BIOS parameter debugging method embodiments when running.

[0137] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0138] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps in any one of the above-mentioned BIOS parameter debugging method embodiments are implemented.

[0139] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the steps in any of the above-mentioned BIOS parameter debugging method embodiments are implemented.

[0140] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0141] The above is a detailed introduction to a BIOS parameter debugging method provided by the present application. The principles and implementation methods of the present application are described in detail using specific examples herein, and the description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications may be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A BIOS parameter debugging method, characterized in that: include: Inputting each group of candidate BIOS parameter combinations into a hybrid model, respectively, wherein the hybrid model includes: at least two of a CPU load model, a memory load model, and a GPU load model pre-built for simulating server operation; Obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each group of the candidate BIOS parameter combinations output by the hybrid model running in the target business scenario; Based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score, a target BIOS parameter combination corresponding to the target business scenario is determined from each group of the candidate BIOS parameter combinations.

2. The BIOS parameter debugging method according to claim 1, characterized in that: The determining a target BIOS parameter combination from each group of the candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score includes: According to the weight sequence, weighted summation is performed on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score to obtain a server performance computing power score corresponding to each group of candidate BIOS parameter combinations; Based on the server performance computing power score, the target BIOS parameter combination is determined from each group of candidate BIOS parameter combinations.

3. The BIOS parameter debugging method according to claim 2, characterized in that: The weight sequence is determined by using the hierarchical analysis method.

4. The BIOS parameter debugging method according to any one of claims 1 to 3, characterized in that: The step of inputting each set of candidate BIOS parameter combinations into the hybrid model comprises: The hybrid model is configured respectively based on each group of candidate BIOS parameter combinations. When the GPU load model is activated to a stable state, at least one of the CPU load model and the memory load model is dynamically injected in combination with the target business scenario to run the hybrid model.

5. The BIOS parameter debugging method according to any one of claims 1 to 3, characterized in that: After inputting each group of candidate BIOS parameter combinations into the hybrid model respectively, the method further includes: In the event that any parameter in the candidate BIOS parameter combination fails to be set, the hybrid model is controlled to recover to a previous stable state.

6. The BIOS parameter debugging method according to any one of claims 1 to 3, characterized in that: The CPU load model is constructed based on the following steps: constructing a dynamic power-aware model for executing workloads; Simulate mixed load scenarios and construct business scenario simulation models; The CPU load model is obtained based on at least one of the dynamic power consumption awareness model and the business scenario simulation model.

7. The BIOS parameter debugging method according to any one of claims 1 to 3, characterized in that: The memory load model is constructed based on the following steps: Perform full memory channel scan and build a joint bandwidth-delay model based on the collected correctable error rate; Adopting adaptive thread control strategy, constructing dynamic pressure regulation algorithm model; The memory load model is obtained based on at least one of the bandwidth-delay joint model and the dynamic pressure adjustment algorithm model.

8. The BIOS parameter debugging method according to any one of claims 1 to 3, characterized in that: Before inputting each group of candidate BIOS parameter combinations into the hybrid model, the method further includes: According to the correlation between the BIOS parameters, the BIOS parameters are classified to obtain multiple parameter sets; Based on a combination mechanism corresponding to a target class parameter set among the multiple classes of parameters, the state values ​​of the parameters in the target class parameter set are combined to obtain at least one set of candidate sub-BIOS parameter combinations corresponding to the target class parameter set; The sub-BIOS parameter combinations corresponding to the various parameter sets are combined to obtain multiple groups of candidate BIOS parameter combinations.

9. The BIOS parameter debugging method according to claim 8, characterized in that: The BIOS parameters are classified according to the association relationship between the BIOS parameters to obtain multiple parameter sets, including: According to the association relationship between the BIOS parameters, the BIOS parameters are divided into an irrelevant parameter set, a related parameter set or a mutually exclusive parameter set.

10. The BIOS parameter debugging method according to claim 8, characterized in that: The combining mechanism corresponding to the target class parameter set in the multiple types of parameters, combining the state values ​​of the parameters in the target class parameter set to obtain at least one group of candidate sub-BIOS parameter combinations corresponding to the target class parameter set, includes: In the case that the target parameter set is an irrelevant parameter set, the state values ​​of different parameters in the irrelevant parameter set are arranged and combined to obtain the at least one set of candidate sub-BIOS parameter combinations.

11. The BIOS parameter debugging method according to claim 8, characterized in that: The combining mechanism corresponding to the target class parameter set in the multiple types of parameters, combining the state values ​​of the parameters in the target class parameter set to obtain at least one group of candidate sub-BIOS parameter combinations corresponding to the target class parameter set, includes: In the case that the target class parameter set is a related class parameter set, a parameter combination path is constructed according to the dependency relationship of each parameter, and the state values ​​of the parameters corresponding to the same combination path are combined to obtain the at least one group of candidate sub-BIOS parameter combinations.

12. The BIOS parameter debugging method according to claim 8, characterized in that: The combining mechanism corresponding to the target class parameter set in the multiple types of parameters, combining the state values ​​of the parameters in the target class parameter set to obtain at least one group of candidate sub-BIOS parameter combinations corresponding to the target class parameter set, includes: In the case where the target class parameter set is a mutually exclusive class parameter set, the parameters in the mutually exclusive class parameter set having a relatively mutually exclusive relationship are divided into the same mutually exclusive group, and the state values ​​of the parameters corresponding to the same mutually exclusive group are obtained; The state values ​​corresponding to the mutually exclusive groups are combined to obtain the at least one group of candidate sub-BIOS parameter combinations.

13. The BIOS parameter debugging method according to any one of claims 1 to 3, characterized in that: After determining the target BIOS parameter combination corresponding to the target business scenario from each group of the candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score, the method further includes: Controlling server operation based on the target BIOS parameter combination and obtaining real-time performance indicator data; When a change in the target business scenario is detected and it is determined based on the real-time performance indicator data that the server performance has degraded, the target BIOS parameter combination is adjusted based on the changed target business scenario.

14. A computer program product, characterized in that include: A first processing module, configured to input each group of candidate BIOS parameter combinations into a hybrid model, wherein the hybrid model includes at least two of a pre-built CPU load model, a memory load model, and a GPU load model; A second processing module is used to obtain at least one of a CPU utilization sub-score, a memory bandwidth sub-score, a latency sub-score, and a power consumption sub-score corresponding to each group of the candidate BIOS parameter combinations output by the hybrid model running in the target business scenario; The third processing module is used to determine a target BIOS parameter combination corresponding to the target business scenario from each group of the candidate BIOS parameter combinations based on the CPU utilization sub-score, the memory bandwidth sub-score, the latency sub-score, and the power consumption sub-score.

15. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the BIOS parameter debugging method according to any one of claims 1 to 13 when executing the computer program.

16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the BIOS parameter debugging method according to any one of claims 1 to 13.

Images