Memory error detection method and device, equipment, medium and product

Abstract

The invention relates to the technical field of computers, and discloses a memory error detection method and device, equipment, a medium and a product, and the memory error detection method comprises the following steps: obtaining an intermediate representation of a target compiled code, and analyzing the intermediate representation to obtain a current memory access operation; obtaining a memory area corresponding to the current memory access operation, and performing static analysis on the current memory access operation based on the memory area to obtain first memory error information; when the memory area corresponding to the current memory access operation is not obtained, dynamically analyzing the current memory access operation to obtain second memory error information; and performing memory access error processing based on the first memory error information or the second memory error information. According to the method, comprehensive detection and positioning of memory errors in the compiling stage are ensured, a user can be helped to quickly find and repair memory problems, and software development efficiency and code quality are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a memory error detection method, device, equipment, medium and product. Background Art

[0002] As the complexity of software development continues to increase, memory management errors have become one of the main issues affecting system stability and security. Common memory errors include memory leaks, buffer overflows, illegal memory accesses, etc. These errors can not only cause software crashes, but may even threaten hardware security.

[0003] Due to the limitations of memory checking tools, memory problems cannot be quickly discovered and repaired during the software development process, which in turn affects software development efficiency and code quality, and makes it difficult to ensure hardware security. Summary of the invention

[0004] In view of this, the present invention provides a memory error detection method, device, equipment, medium and product to solve the problem that memory problems cannot be quickly discovered and repaired during the software development process, which affects software development efficiency and code quality and makes it difficult to ensure hardware security.

[0005] In a first aspect, the present invention provides a memory error detection method, the method comprising:

[0006] Get the intermediate representation of the target compiled code, analyze the intermediate representation, and get the current memory access operation;

[0007] Acquire a memory area corresponding to a current memory access operation, and perform static analysis on the current memory access operation based on the memory area to obtain first memory error information;

[0008] When the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain second memory error information;

[0009] Memory access error processing is performed based on the first memory error information or the second memory error information.

[0010] A memory error detection method provided in this embodiment obtains a current memory access operation by analyzing an intermediate representation of a target compiled code, performs static analysis on the current memory access operation based on a memory area, obtains first memory error information, and when a memory area corresponding to the current memory access operation is not obtained, performs dynamic analysis on the current memory access operation to obtain second memory error information, and performs memory access error processing based on the first memory error information or the second memory error information; by performing static and dynamic analysis on memory access operations during multi-threaded compilation, comprehensive detection and positioning of memory errors in the compilation stage is guaranteed, which can help users quickly discover and repair memory problems, significantly improve software development efficiency and code quality, and assist users in carrying out high-quality software engineering.

[0011] In an optional implementation, obtaining a memory area corresponding to a current memory access operation, and performing a static analysis on the current memory access operation based on the memory area to obtain first memory error information includes:

[0012] Perform dependency analysis on the current memory access operation to obtain the memory area corresponding to the current memory access operation;

[0013] The memory access operation information corresponding to the current memory access operation is compared with the memory information corresponding to the memory area, and the first memory error information is determined based on the comparison result.

[0014] A memory error detection method provided in this embodiment determines first memory error information by comparing memory access operation information corresponding to the current memory access operation with memory information corresponding to the memory area, thereby achieving accurate detection of memory access operation errors with memory definitions in the compilation stage, and can help users quickly discover and repair memory problems.

[0015] In an optional implementation, when the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain second memory error information, including:

[0016] Divide the compiled multi-thread memory space corresponding to the target compiled code into a main memory space and multiple shadow memory spaces, and map the main memory space to the multiple shadow memory spaces;

[0017] Get the detection code and perform detection code stubs on the shadow memory space;

[0018] The target compiled code after the detection code is inserted is run to detect the memory error and obtain the second memory error information.

[0019] A memory error detection method provided in this embodiment divides the compiled multi-threaded memory space into a main memory space and multiple shadow memory spaces, maps the main memory space to the multiple shadow memory spaces, and inserts detection code into the shadow memory spaces, and then runs the target compiled code after the detection code is inserted to detect memory errors. This can ensure that there is enough shadow memory space for memory checking and that each thread can perform independent checks without conflict.

[0020] In an optional implementation, the compiled multi-thread memory space corresponding to the target compiled code is divided into a main memory space and multiple shadow memory spaces, and the main memory space is mapped to the multiple shadow memory spaces, including:

[0021] Divide the compiled multi-thread memory space into a common memory space and an original shadow memory space;

[0022] The public memory space is divided into a main memory space and an independent shadow memory space, and the independent shadow memory space is used to store multi-thread memory access information;

[0023] Establish multiple shadow memory spaces based on the original shadow memory space and the independent shadow memory space;

[0024] Map the main memory space into multiple shadow memory spaces.

[0025] A memory error detection method provided in this embodiment divides the common memory space into a main memory space and an independent shadow memory space for storing multi-threaded memory access information, and then establishes multiple shadow memory spaces, and maps the main memory space to the multiple shadow memory spaces, thereby storing the memory access information of all threads in the main memory space while ensuring that the access to each thread does not conflict with each other.

[0026] In an optional implementation, obtaining detection code and performing detection code stubbing on the shadow memory space includes:

[0027] Obtain the thread number corresponding to the current memory access operation, and determine the shadow memory address of each thread based on the thread number of the current thread;

[0028] The detection code is inserted based on the shadow memory address of each thread to obtain the target compiled code after the detection code is inserted.

[0029] A memory error detection method provided in this embodiment determines the shadow memory address of each thread by the thread number of the current thread, ensures that there is enough space for shadow memory for memory checking, and performs detection code insertion according to the shadow memory address of each thread during the compilation phase, thereby achieving accurate positioning detection of memory errors and improving the work efficiency of writing high-quality code.

[0030] In an optional implementation, performing memory access error processing based on the first memory error information or the second memory error information includes:

[0031] marking the first memory error information or the second memory error information with an error type;

[0032] If the error type corresponding to the first memory error information or the second memory error information is an alarm type, a warning message is generated and recorded in the software running code;

[0033] If the error type corresponding to the first memory error information or the second memory error information is an interrupt type, the code compilation process or the software running code execution process is interrupted.

[0034] A memory error detection method provided in this embodiment can immediately interrupt code compilation or software operation when a code execution error that may threaten hardware safety is detected, thereby preventing serious accidents from occurring and ensuring hardware safety.

[0035] In a second aspect, the present invention provides a memory error detection device, which includes:

[0036] The acquisition module is used to obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation;

[0037] A static analysis module, used for acquiring a memory area corresponding to a current memory access operation, and performing a static analysis on the current memory access operation based on the memory area to obtain first memory error information;

[0038] A dynamic analysis module, used for dynamically analyzing the current memory access operation to obtain second memory error information when the memory area corresponding to the current memory access operation is not obtained;

[0039] The memory access error processing module is used to perform memory access error processing based on the first memory error information or the second memory error information.

[0040] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to thereby execute a memory error detection method of the first aspect or any corresponding embodiment thereof.

[0041] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute a memory error detection method according to the first aspect or any corresponding embodiment thereof.

[0042] In a fifth aspect, the present invention provides a computer program product, comprising computer instructions for causing a computer to execute a memory error detection method according to the first aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0044] Figure 1 is a flow chart of a memory error detection method according to an embodiment of the present invention;

[0045] Figure 2 is a flow chart of another memory error detection method according to an embodiment of the present invention;

[0046] Figure 3 is a flow chart of another memory error detection method according to an embodiment of the present invention;

[0047] Figure 4 is a flow chart of another memory error detection method according to an embodiment of the present invention;

[0048] Figure 5 is a schematic diagram of a process of performing memory error detection by using a static + dynamic analysis method according to an embodiment of the present invention;

[0049] Figure 6 is a structural block diagram of a memory error detection device according to an embodiment of the present invention;

[0050] Figure 7 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0052] During software development, memory management errors are one of the important issues that affect system stability and security. Among them, the many-core architecture places higher demands on memory checking tools. In the many-core architecture, each core group can be regarded as an independent thread. The multi-threaded programming model can better utilize all threads to provide program performance. Each independent thread can access both its own independent memory space and the public memory space. There may be certain errors in the memory access process. How to set up a mechanism to simultaneously check the memory access errors of multiple threads at different levels of memory is also a problem that memory checking tools need to solve.

[0053] Memory checking tools and methods can be divided into the following categories:

[0054] (1) Static analysis tools:

[0055] Static analysis tools detect memory errors during the compilation phase by analyzing source code. Related static analysis tools include LLVM (Low Level Virtual Machine, compiler)'s Clang Static Analyzer (a static code analysis tool) and Coverity (a static analysis software). These tools can detect potential memory leaks, out-of-bounds access, and other problems before code execution. However, the disadvantage of static analysis tools is that they rely on the static characteristics of the code and cannot detect problems that occur dynamically at runtime.

[0056] (2) Dynamic analysis tools:

[0057] Dynamic analysis tools monitor and detect memory errors while the program is running. Valgrind is a widely used dynamic analysis tool that can detect memory leaks, illegal memory accesses, and other problems. Another dynamic analysis tool is AddressSanitizer (a fast memory error detection tool) that monitors memory operations by inserting instrumentation code. Although dynamic analysis tools are able to catch runtime errors, they usually introduce additional runtime overhead that affects program performance.

[0058] (3) Hardware-supported memory check:

[0059] Some advanced hardware platforms provide built-in memory error detection mechanisms. For example, MPX (Memory Protection Extensions) technology detects and prevents memory out-of-bounds accesses through hardware support. However, such technologies require hardware support and may be limited by hardware compatibility in actual applications.

[0060] (4) Protection at the operating system level:

[0061] The operating system also provides some memory protection mechanisms, such as preventing illegal memory access through memory paging and virtual memory technology. However, operating system-level protection is usually unable to detect and repair memory errors in applications in a fine-grained manner.

[0062] In summary, there is no technology that can apply memory checking to the many-core architecture. Due to the special hardware characteristics of the many-core architecture, such as the small independent memory space of the threads cannot be used to store memory access information, the public memory space is large but is accessed simultaneously, etc., it is difficult to ensure that the memory access errors of each thread in the multi-threaded programming model can be accurately checked.

[0063] To solve the above technical problems, an embodiment of the present invention provides a memory error detection method, which assists users in locating code errors when performing multi-threaded programming, improves the work efficiency of writing high-quality code, and assists users in carrying out high-quality software engineering. When a code running error that may threaten hardware security is detected, the tool can forcibly interrupt the software operation, thereby ensuring hardware security.

[0064] The embodiment of the present invention provides a memory error detection method. It should be noted that the execution subject of the memory error detection method provided by the embodiment of the present invention can be a memory error detection device. The memory error detection device can be implemented as part or all of an electronic device through software, hardware, or a combination of software and hardware. The electronic device can be a server or a terminal. The server in the embodiment of the present application can be a single server or a server cluster composed of multiple servers. The terminal in the embodiment of the present application can be a smart phone, a personal computer, a tablet computer, a wearable device, an intelligent robot, and other intelligent hardware devices. In the following method embodiments, the execution subject is an electronic device as an example for explanation.

[0065] According to an embodiment of the present invention, a memory error detection method embodiment is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0066] In this embodiment, a memory error detection method is provided, which can be used in the above electronic device. Figure 1 is a flow chart of a memory error detection method according to an embodiment of the present invention. Figure 1 As shown, the process includes the following steps:

[0067] Step S101, obtaining an intermediate representation of the target compiled code, analyzing the intermediate representation, and obtaining a current memory access operation.

[0068] Specifically, during the compilation phase, the intermediate representation (IR) of the target compiled code is analyzed to obtain the current memory access operation (such as memory allocation, release, reading, writing, etc.).

[0069] Step S102, obtaining a memory area corresponding to a current memory access operation, and performing a static analysis on the current memory access operation based on the memory area to obtain first memory error information.

[0070] Specifically, memory error information includes out-of-bounds (OOB) memory access, access to unallocated memory, memory leak, multiple release, stack overflow, and other information.

[0071] Furthermore, static analysis of the current memory access operation is performed to identify illegal memory operations in the compilation stage as much as possible, and the relevant information corresponding to the illegal memory operation is used as the first memory error information, and the first memory error information is processed as a memory access error; for memory operations identified as legal, other memory operations are continued to be analyzed.

[0072] Step S103: When the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain second memory error information.

[0073] Specifically, if the definition of a memory cannot be obtained, the current memory access operation is dynamically analyzed; for example, there is a memory access operation in function A that reads a certain address addr, but addr is a parameter of A, and this parameter will only be passed in during execution, and then dynamic analysis is performed.

[0074] Furthermore, for memory access operations whose legality cannot be analyzed at the compile stage, dynamic analysis is performed using shadow memory technology and compile-time instrumentation methods.

[0075] Step S104: performing memory access error processing based on the first memory error information or the second memory error information.

[0076] A memory error detection method provided in this embodiment obtains a current memory access operation by analyzing an intermediate representation of a target compiled code, performs static analysis on the current memory access operation based on a memory area, obtains first memory error information, and when a memory area corresponding to the current memory access operation is not obtained, performs dynamic analysis on the current memory access operation to obtain second memory error information, and performs memory access error processing based on the first memory error information or the second memory error information; by performing static and dynamic analysis on memory access operations during multi-threaded compilation, comprehensive detection and positioning of memory errors in the compilation stage is guaranteed, which can help users quickly discover and repair memory problems, significantly improve software development efficiency and code quality, and assist users in carrying out high-quality software engineering.

[0077] In this embodiment, a memory error detection method is provided which can be used in the above electronic device. Figure 2 is a flow chart of a memory error detection method according to an embodiment of the present invention. Figure 2 As shown, the process includes the following steps:

[0078] Step S201, obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation. Figure 1 Step S101 of the illustrated embodiment will not be described in detail here.

[0079] Step S202, obtaining a memory area corresponding to a current memory access operation, and performing a static analysis on the current memory access operation based on the memory area to obtain first memory error information.

[0080] Specifically, the above step S202 includes:

[0081] Step S2021, performing dependency analysis on the current memory access operation to obtain a memory area corresponding to the current memory access operation.

[0082] Specifically, the compiler is used to find the source operation that the current memory access operation depends on, and then obtain the memory area corresponding to the current memory access operation; for example, the current memory access operation is to read a memory address, and the compiler searches for the defined memory area according to the memory address, and then obtains various parameters during the definition.

[0083] Furthermore, general compilation techniques such as single IR analysis, alias analysis (AA), and define-use (DU) analysis may be used to find the memory area of ​​the current memory access operation.

[0084] Step S2022: Compare the memory access operation information corresponding to the current memory access operation with the memory information corresponding to the memory area, and determine the first memory error information based on the comparison result.

[0085] Specifically, for a certain memory access operation, obtain relevant information of the current memory access operation (the size of the memory access, whether it is an allocation / release behavior, etc.), and the memory information corresponding to the memory area (whether it is allocated / released memory, the defined memory size, whether it is initialized, etc.), and compare the above two pieces of information. If the two match, it is determined that the current memory access operation is a legal operation. Otherwise, the current memory access operation is an illegal operation.

[0086] Step S203: When the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain the second memory error information. Figure 1 Step S103 of the illustrated embodiment will not be described in detail here.

[0087] Step S204: Perform memory access error processing based on the first memory error information or the second memory error information. Figure 1 Step S104 of the illustrated embodiment will not be described in detail here.

[0088] A memory error detection method provided in this embodiment determines first memory error information by comparing memory access operation information corresponding to the current memory access operation with memory information corresponding to the memory area, thereby achieving accurate detection of memory access operation errors with memory definitions in the compilation stage, and can help users quickly discover and repair memory problems.

[0089] In this embodiment, a memory error detection method is provided, which can be used in the above electronic device. Figure 3 is a flow chart of a memory error detection method according to an embodiment of the present invention. Figure 3 As shown, the process includes the following steps:

[0090] Step S301, obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation. Figure 2 Step S201 of the illustrated embodiment will not be described in detail here.

[0091] Step S302, obtaining a memory area corresponding to the current memory access operation, and performing static analysis on the current memory access operation based on the memory area to obtain first memory error information. Figure 2 Step S202 of the illustrated embodiment will not be described in detail here.

[0092] Step S303: When the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain second memory error information.

[0093] Specifically, the above step S303 includes:

[0094] Step S3031, dividing the compiled multi-thread memory space corresponding to the target compiled code into a main memory space and multiple shadow memory spaces, and mapping the main memory space to the multiple shadow memory spaces.

[0095] Specifically, shadow memory technology allocates an additional memory area for each monitored memory address, called the "shadow memory area". Shadow memory records and maintains status information corresponding to the actual memory, which may include whether it has been initialized or is accessible. Each time the memory is accessed (read or written), the shadow memory will perform synchronization operations. For example, when accessing an actual memory address, the shadow memory will synchronously update or query the corresponding status information. Shadow memory is created at compile time, and will generate binary with normal code, and will be dynamically read and written at runtime.

[0096] In some optional implementations, the above step S3031 includes:

[0097] Step a1, dividing the compiled multi-thread memory space into a common memory space and an original shadow memory space.

[0098] Specifically, the public memory space belongs to the program process and is used by the program process. The original shadow memory space is used to store the metadata required for detecting memory errors. That is, the original shadow memory stores metadata that can reflect normal memory status information, while the normal memory stores the data that the program really needs.

[0099] Step a2: divide the public memory space into a main memory space and an independent shadow memory space, where the independent shadow memory space is used to store multi-thread memory access information.

[0100] Specifically, since the independent memory space of a single thread is small, it is impossible to open up additional space to store the huge memory access information. Therefore, the memory access information corresponding to multiple threads can only be stored in the public memory space. However, another problem is that the public memory space can be accessed by multiple threads at the same time. It is necessary to ensure that each thread can access the memory space that does not conflict with each other. Therefore, a shadow memory space (i.e., an independent shadow memory space) is reserved on the public memory space to store the memory access information of all threads.

[0101] Furthermore, the independent shadow memory space is evenly divided into the number of threads, and each thread can only access the corresponding memory space. The calculation formula for the total memory space size of the independent shadow memory space is as follows:

[0102] shadowMemorySize=threadNum*threadShadowMemorySize

[0103] Among them, shadowMemorySize is the total memory space size of the independent shadow memory space, threadNum is the total number of fixed threads of the hardware, and threadShadowMemorySize is the shadow memory space size required by each thread.

[0104] Step a3: establishing multiple shadow memory spaces based on the original shadow memory space and the independent shadow memory space.

[0105] Step a4, mapping the main memory space to multiple shadow memory spaces.

[0106] Step S3032, obtaining detection code, and performing detection code stubbing on the shadow memory space.

[0107] Specifically, the compile-time instrumentation method is a method of inserting additional code into a program during the compilation process, with the aim of monitoring, analyzing and optimizing the program. This method is different from the dynamic instrumentation technology because the instrumentation is performed during the compilation phase of the program, rather than when the program is running, that is, additional detection code is inserted before the memory access operation, including collecting relevant information about the memory access operation, memory access detection and error handling.

[0108] In some optional implementations, the above step S3032 includes:

[0109] Step b1, obtaining the thread number corresponding to the current memory access operation, and determining the shadow memory address of each thread based on the thread number of the current thread.

[0110] Specifically, the thread number of the current thread is obtained during the compilation period, and the shadow memory address threadShadowMemoryAddress of each thread is calculated as follows:

[0111] threadShadowMemoryAddress

[0112] =threadID*threadShadowMemorySize+shadowMemoryAddress

[0113] Among them, threadID is the thread number of the current thread, threadShadowMemorySize is the size of the shadow memory space required by each thread, and shadowMemoryAddress is the starting address of the total shadow memory, which needs to be dynamically obtained at runtime.

[0114] Step b2, performing detection code stubbing based on the shadow memory address of each thread to obtain the target compiled code after the detection code stubbing.

[0115] Specifically, all code locations such as assignments and copies in the program are identified, and detection code is inserted to update the metadata of the target object.

[0116] Step S3033, running the target compiled code after the detection code is inserted, detecting the memory error, and obtaining the second memory error information.

[0117] Specifically, the detection code and the original code are compiled into a binary file together, and the detection code and the original code are executed in sequence during the runtime phase. A memory access detection method is used before the memory access operation is performed, and the detection result is passed to the user after memory access error processing.

[0118] Step S304: Perform memory access error processing based on the first memory error information or the second memory error information. Figure 2 Step S204 of the illustrated embodiment will not be described in detail here.

[0119] A memory error detection method provided in this embodiment divides the compiled multi-threaded memory space into a main memory space and multiple shadow memory spaces, maps the main memory space to the multiple shadow memory spaces, and inserts detection code into the shadow memory spaces, and then runs the target compiled code after the detection code is inserted to detect memory errors. This can ensure that there is enough shadow memory space for memory checking and that each thread can perform independent checks without conflict.

[0120] In this embodiment, a memory error detection method is provided, which can be used in the above electronic device. Figure 4 is a flow chart of a memory error detection method according to an embodiment of the present invention. Figure 4 As shown, the process includes the following steps:

[0121] Step S401, obtain the intermediate representation of the target compiled code, analyze the intermediate representation, and obtain the current memory access operation. Figure 3 Step S301 of the illustrated embodiment will not be described in detail here.

[0122] Step S402, obtaining a memory area corresponding to the current memory access operation, and performing static analysis on the current memory access operation based on the memory area to obtain first memory error information. Figure 3 Step S302 of the illustrated embodiment will not be described in detail here.

[0123] Step S403: When the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain the second memory error information. Figure 3 Step S303 of the illustrated embodiment will not be described in detail here.

[0124] Step S404: performing memory access error processing based on the first memory error information or the second memory error information.

[0125] Specifically, the above step S404 includes:

[0126] Step S4041: Mark the first memory error information or the second memory error information with an error type.

[0127] Specifically, memory errors can be marked as warnings and aborts.

[0128] Furthermore, the specific distinction between error types is based on different hardware architectures, and a relatively loose strategy is adopted as much as possible to avoid causing more code development troubles to users; among them, for software errors that may threaten hardware boards, such as causing hardware crashes and requiring a restart, it takes several hours to restart the machine and recover, and the above-mentioned memory errors require interruption, and this type of memory error is marked as an interrupt type; for some types of memory access out of bounds that may cause calculation errors, only the memory access error is output to the user, and the user decides how to deal with it, whether to modify or retain it, and this type of memory error is marked as an alarm type; in the software, it will be distinguished based on the specific address value of the memory access. Addresses within a certain range or zero address access will cause hardware errors, and addresses within a certain range will not have adverse effects.

[0129] Step S4042: if the error type corresponding to the first memory error information or the second memory error information is an alarm type, a warning message is generated and recorded in the software running code.

[0130] Specifically, for relatively minor memory errors such as alarms, a warning message is generated, which is recorded in a log or printed to a command line to alert developers to the problem.

[0131] Step S4043: if the error type corresponding to the first memory error information or the second memory error information is an interruption type, the code compilation process or the software running code execution process is interrupted.

[0132] Specifically, for interrupt-type memory errors, the compilation process or code execution is forcibly interrupted to avoid hardware downtime.

[0133] A memory error detection method provided in this embodiment can immediately interrupt code compilation or software operation when a code execution error that may threaten hardware safety is detected, thereby preventing serious accidents from occurring and ensuring hardware safety.

[0134] The following describes the specific steps of a memory error detection method through a specific embodiment.

[0135] Embodiment 1:

[0136] On a domestic chip with a multi-core architecture, the memory detection tool was implemented based on a self-developed compiler for a multi-threaded programming model. After a large number of code test case experiments, many test case writing errors were identified, such as Figure 5 As shown in the figure, the memory detection tool adopts static + dynamic analysis method. The memory detection steps include:

[0137] During the compilation phase, the intermediate representation of the code is analyzed, and during this process, all memory access operations (such as memory allocation, release, reading, writing, etc.) are identified.

[0138] Through static analysis of memory access operations, illegal memory operations are identified as much as possible during the compilation phase. For memory access operations identified as legal, other memory access operations will continue to be analyzed; for memory operations identified as illegal, the results will be handled with errors.

[0139] For memory access operations that cannot be identified during static analysis, a dynamic inspection method is used, and the instrumentation technology is used to detect them at runtime, and error handling is performed on the results.

[0140] In the above-mentioned embodiment 1, for codes that are difficult to locate, the user can use the memory detection tool to efficiently locate some memory access errors and solve the problems after repairing them; in addition, for the processing of different threads, the memory access error information of the erroneous thread can also be accurately identified; if an unallocated empty address is accessed, the hardware will be restarted and restored after several hours; after using this tool, this type of memory access error will be identified before execution and the program will be interrupted to prevent hardware crashes; in summary, it can be seen that the tool has relatively effective user development efficiency improvement and hardware protection functions.

[0141] In this embodiment, a memory error detection device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0142] This embodiment provides a memory error detection device, such as Figure 6 As shown, including:

[0143] An acquisition module 601 is used to acquire an intermediate representation of a target compiled code, analyze the intermediate representation, and obtain a current memory access operation;

[0144] A static analysis module 602 is used to obtain a memory area corresponding to a current memory access operation, and to perform a static analysis on the current memory access operation based on the memory area to obtain first memory error information;

[0145] The dynamic analysis module 603 is used to dynamically analyze the current memory access operation to obtain second memory error information when the memory area corresponding to the current memory access operation is not obtained;

[0146] The memory access error processing module 604 is used to perform memory access error processing based on the first memory error information or the second memory error information.

[0147] In some optional implementations, the static analysis module 602 includes:

[0148] A dependency analysis unit, used to perform dependency analysis on the current memory access operation to obtain a memory area corresponding to the current memory access operation;

[0149] The comparison unit is used to compare the memory access operation information corresponding to the current memory access operation with the memory information corresponding to the memory area, and determine the first memory error information based on the comparison result.

[0150] In some optional implementations, the dynamic analysis module 603 includes:

[0151] A partitioning unit, used for partitioning a compiled multi-thread memory space corresponding to a target compiled code into a main memory space and multiple shadow memory spaces, and mapping the main memory space to the multiple shadow memory spaces;

[0152] The instrumentation unit is used to obtain the detection code and perform instrumentation on the shadow memory space;

[0153] The detection unit is used to run the target compiled code after the detection code is inserted, detect the memory error, and obtain the second memory error information.

[0154] In some optional implementations, the dividing unit includes:

[0155] A first partitioning subunit is used to partition the compiled multi-thread memory space into a common memory space and an original shadow memory space;

[0156] A second division subunit is used to divide the public memory space into a main memory space and an independent shadow memory space, wherein the independent shadow memory space is used to store multi-thread memory access information;

[0157] Establishing a subunit for establishing multiple shadow memory spaces based on the original shadow memory space and the independent shadow memory space;

[0158] The mapping subunit is used to map the main memory space into multiple shadow memory spaces.

[0159] In some optional implementations, the plugging unit includes:

[0160] A determination subunit is used to obtain a thread number corresponding to a current memory access operation, and determine a shadow memory address of each thread based on the thread number of the current thread;

[0161] The instrumentation subunit is used to perform instrumentation of the detection code based on the shadow memory address of each thread to obtain the target compiled code after the instrumentation of the detection code.

[0162] In some optional implementations, the memory access error handling module 604 includes:

[0163] A marking unit, used for marking the first memory error information or the second memory error information with an error type;

[0164] an alarm unit, configured to generate a warning message if the error type corresponding to the first memory error information or the second memory error information is an alarm type, and record the warning message into the software running code;

[0165] The interrupt unit is used to interrupt the code compilation process or the software running code execution process if the error type corresponding to the first memory error information or the second memory error information is an interrupt type.

[0166] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0167] A memory error detection device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0168] The embodiment of the present invention also provides a computer device having the above Figure 6 A memory error detection device is shown.

[0169] See also Figure 7 , Figure 7 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Figure 7As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0170] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0171] The memory 20 stores instructions executable by at least one processor 10, so that the at least one processor 10 executes the method shown in the above embodiment.

[0172] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0173] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0174] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0175] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0176] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0177] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0178] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A memory error detection method, characterized in that: The method comprises: Obtaining an intermediate representation of the target compiled code, analyzing the intermediate representation, and obtaining a current memory access operation; Acquire a memory area corresponding to the current memory access operation, and perform static analysis on the current memory access operation based on the memory area to obtain first memory error information; When the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain second memory error information; Memory access error processing is performed based on the first memory error information or the second memory error information.

2. The method according to claim 1, characterized in that The acquiring the memory area corresponding to the current memory access operation, and performing static analysis on the current memory access operation based on the memory area to obtain first memory error information includes: Performing dependency analysis on the current memory access operation to obtain a memory area corresponding to the current memory access operation; The memory access operation information corresponding to the current memory access operation is compared with the memory information corresponding to the memory area, and the first memory error information is determined based on the comparison result.

3. The method according to claim 1, characterized in that When the memory area corresponding to the current memory access operation is not obtained, the current memory access operation is dynamically analyzed to obtain second memory error information, including: Dividing the compiled multi-thread memory space corresponding to the target compiled code into a main memory space and multiple shadow memory spaces, and mapping the main memory space to the multiple shadow memory spaces; Obtain detection code, and perform detection code stubbing on the shadow memory space; The target compiled code after the detection code is inserted is run to detect the memory error and obtain the second memory error information.

4. The method according to claim 3, characterized in that The step of dividing the compiled multi-thread memory space corresponding to the target compiled code into a main memory space and multiple shadow memory spaces, and mapping the main memory space to the multiple shadow memory spaces includes: Dividing the compiled multi-thread memory space into a common memory space and an original shadow memory space; Dividing the public memory space into a main memory space and an independent shadow memory space, wherein the independent shadow memory space is used to store multi-thread memory access information; Establishing the multiple shadow memory spaces based on the original shadow memory space and the independent shadow memory space; The main memory space is mapped into the multiple shadow memory spaces.

5. The method according to claim 3, characterized in that: The obtaining of the detection code and performing detection code instrumentation on the shadow memory space includes: Obtaining a thread number corresponding to the current memory access operation, and determining a shadow memory address of each thread based on the thread number of the current thread; Detection code stubbing is performed based on the shadow memory address of each thread to obtain the target compiled code after the detection code stubbing is performed.

6. The method according to claim 1, characterized in that The performing memory access error processing based on the first memory error information or the second memory error information includes: marking the first memory error information or the second memory error information with an error type; If the error type corresponding to the first memory error information or the second memory error information is an alarm type, a warning message is generated, and the warning message is recorded in the software running code; If the error type corresponding to the first memory error information or the second memory error information is an interrupt type, the code compilation process or the software running code execution process is interrupted.

7. A memory error detection device, characterized in that: The device comprises: An acquisition module is used to acquire an intermediate representation of the target compiled code, analyze the intermediate representation, and obtain a current memory access operation; A static analysis module, used for acquiring a memory area corresponding to the current memory access operation, and performing a static analysis on the current memory access operation based on the memory area to obtain first memory error information; A dynamic analysis module, configured to dynamically analyze the current memory access operation to obtain second memory error information when a memory area corresponding to the current memory access operation is not obtained; A memory access error processing module is used to perform memory access error processing based on the first memory error information or the second memory error information.

8. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the memory error detection method according to any one of claims 1 to 6 by executing the computer instructions.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the memory error detection method according to any one of claims 1 to 6.

10. A computer program product, characterized in that The method comprises computer instructions, wherein the computer instructions are used to cause a computer to execute the memory error detection method according to any one of claims 1 to 6.

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