Parallel communication data processing method and device

Abstract

The invention provides a parallel communication data processing method and device, and the method comprises the steps: enabling a user to store to-be-transmitted effective data in a transmission data storage unit, and enabling the transmission data storage unit to transmit the effective data to an internal DMA control unit according to the configuration of the user, the internal DMA control unit generates a first time sequence for reading and operating the sending data storage unit, carries valid data from the sending data storage unit to the internal DMA control unit through the DMA channel based on the first time sequence, and carries the valid data to the channel cache FIFO unit, and the channel cache FIFO unit carries the valid data to the channel cache FIFO unit according to the valid data. I channel data and Q channel data are obtained through the I channel and the Q channel, data interleaving processing is carried out on the I channel data and the Q channel data so as to transmit effective data to the sending control unit, and the sending control unit determines a target sending protocol mode according to the sending protocol mode and transmits the effective data to external equipment based on the target sending protocol mode.

Description

Technical Field

[0001] The present application relates to the field of communication technology, and in particular to a parallel communication data processing method and device. Background Art

[0002] Microcomputer system, also known as microcomputer system, microcomputer system, is an important part of modern computing technology. With the production and development of microprocessors and microcomputers, microcomputer system has gradually become an important tool in the field of information technology. From the initial 4-bit microprocessor to the current 64-bit or even higher performance processor, microcomputer system has experienced rapid development. In microcomputer system, data exchange and processing are often involved.

[0003] At present, there is a universal programmable parallel I / O interface, which is widely used in almost all series of microcomputer systems. The programmable parallel I / O interface has three data ports with latches or buffers, which can exchange data with peripherals in parallel. Among them, the data bus buffer and read-write control logic realize the writing of the transmitted data and the reading of the received data.

[0004] However, the existing technology requires three 8-bit data ports for communication with peripherals, namely, the PA port, the PB port, and the PC port. The PA port, the PB port, and the PC port can only transmit their own data independently, which greatly wastes I / O resources and the utilization rate of the transmission channel is also low. Moreover, each time data is transmitted, it is necessary to continuously write and send data, which makes the CPU overhead large and leads to low data transmission efficiency. Summary of the invention

[0005] In view of this, the purpose of the present application is to provide a parallel communication data processing method and device, which performs parallel data processing through four units including a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiver control unit. Through the data interleaving processing of the I / O channel, the data of two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, which saves I / O resources and improves the utilization rate of the transmission channel; at the same time, through the internal DMA control unit, the CPU overhead can be minimized during high-speed data transmission, thereby improving the data transmission efficiency.

[0006] In a first aspect, an embodiment of the present application provides a parallel communication data processing method, which is applied to a parallel communication data processing device, wherein the parallel communication data processing device includes a data storage unit, an internal DMA control unit, a channel cache FIFO unit, and a transceiver control unit; the data storage unit includes a send data storage unit and a receive data storage unit; the transceiver control unit includes a send control unit and a receive control unit; the parallel communication data processing device has a data receiving mode and a data sending mode; the method includes:

[0007] In the data transmission mode, the user stores the valid data to be transmitted in the transmission data storage unit, and the transmission data storage unit transmits the valid data to the internal DMA control unit according to a preset user configuration; the user configuration includes a DMA configuration;

[0008] The internal DMA control unit generates a first timing for reading the transmission data storage unit, and based on the first timing, the valid data is transferred from the transmission data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and the valid data is transferred to the channel buffer FIFO unit; wherein the channel buffer FIFO unit includes an I channel and a Q channel;

[0009] The channel buffer FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit;

[0010] The sending control unit determines a corresponding target sending protocol mode according to a preset sending protocol mode, and transmits the valid data to an external device based on the target sending protocol mode; wherein the sending protocol mode includes a single edge mode and a double edge mode.

[0011] In a possible implementation, the method further includes:

[0012] In the data receiving mode, the receiving control unit determines a corresponding target sending protocol mode according to the sending protocol mode, and transmits the received valid data to the channel buffer FIFO unit based on the target sending protocol mode;

[0013] The channel buffer FIFO unit performs deinterleaving processing on the valid data, transmits the processed valid data to the corresponding I channel and Q channel respectively, and transmits the valid data to the internal DMA control unit through the I / Q channel;

[0014] The internal DMA control unit receives the data of the I channel and the Q channel, generates a second timing required for the write operation of the received data storage unit, and moves the data of the I channel and the Q channel to the received data storage unit based on the second timing;

[0015] The received data storage unit receives the data of the I channel and the Q channel of the internal DMA control unit and stores the data into the corresponding address space.

[0016] In a possible implementation, the transmit data storage unit and the receive data storage unit are dual-port RAMs, wherein the left port supports the access protocol of the AHB bus and supports 32-bit mode access; the right port supports the three-bus protocol for accessing the RAM interface and supports 8-bit mode access;

[0017] The storing of the valid data to be sent in the sending data storage unit comprises:

[0018] The valid data to be sent is written into the sending data storage unit based on a preset write address through the AHB bus; wherein the write address is aligned with a 32-bit boundary, that is, stored in the form of 0x0, 0x4, 0x8, 0xC addresses.

[0019] In a possible implementation manner, the internal DMA control unit is obtained by the following steps:

[0020] Acquire a target programming model, and acquire the internal DMA control unit based on the target programming model; wherein the target programming model represents a simplified programming model;

[0021] Parameter information is configured for each DMA channel of the internal DMA control unit; wherein the parameter information includes a window address, a number of bytes, a number of rows, and a row offset address.

[0022] In a possible implementation, the window address is the location of the valid data in the data storage unit, the window address is aligned according to a 32-bit boundary, and when the window address is not aligned, alignment is performed based on a preset alignment standard; the alignment standard is that the lower 2 bits are automatically filled with 0, and the address is aligned downward;

[0023] The number of bytes is the number of bytes in each row; the number of bytes is an even number; the number of bytes is configured as 2 or 4; when the number of bytes is configured as 0, the internal DMA control unit does not transfer data;

[0024] The number of rows is the number of rows in each window; when the product of the number of rows and the number of bytes is 0, data transmission is not started;

[0025] The row offset address is an offset address between the first bytes between rows in continuous rows; the row offset address is aligned with a 32-bit boundary in the memory.

[0026] In a possible implementation, the method further includes:

[0027] When the parallel communication data processing device operates in the receiving mode, the internal DMA control unit receives the valid data from the I / Q channel and writes the valid data into the receiving data storage unit;

[0028] When the parallel communication data processing device operates in the transmission mode, the internal DMA control unit reads the valid data from the address of the data storage unit and transfers the valid data to the I / Q channel of the internal DMA control unit.

[0029] In a possible implementation manner, a DMA channel of the internal DMA control unit has a transmission queue, and a descriptor exists in the transmission queue; the method further includes:

[0030] The internal DMA control unit sequentially transmits through the descriptors in the transmission queue of the DMA channel, obtains new descriptors during the transmission process, and adds the new descriptors to the transmission queue for queuing; wherein each DMA channel has at most one active transmission and one queued transmission; the active transmission is the transmission currently in progress, and the queued transmission is the transmission that has been configured but not yet started;

[0031] When the active transfer is completed, the internal DMA control unit takes the next descriptor from the transfer queue and performs a new transfer based on the descriptor.

[0032] In a possible implementation manner, obtaining I channel data and Q channel data through the I channel and the Q channel, and performing data interleaving processing on the I channel data and the Q channel data, includes:

[0033] Distributing the valid data to the I channel and the Q channel of the channel buffer FIFO unit to obtain the I channel data and the Q channel data;

[0034] The I channel data and the Q channel data are combined into one channel based on the transmission mode to perform data interleaving.

[0035] In a possible implementation manner, a queuing state machine corresponds to the transmission process of the DMA channel of the internal DMA control unit; the method further includes:

[0036] When an abnormal state occurs during the transmission process, a reset is performed based on the preset software to reset the queuing state machine to an initial state, and the descriptor is reconfigured to start the transmission again;

[0037] When the I channel and the Q channel are initialized and idle, the internal DMA control unit transmits the valid data through the DMA channel.

[0038] In a second aspect, an embodiment of the present application further provides a parallel communication data processing device, which includes a data storage unit, an internal DMA control unit, a channel buffer FIFO unit, and a transceiver control unit; the data storage unit includes a transmission data storage unit and a reception data storage unit; the transceiver control unit includes a transmission control unit and a reception control unit; the parallel communication data processing device has a data reception mode and a data transmission mode;

[0039] The parallel communication data processing device is used to execute the parallel communication data processing method provided in the embodiment of the first aspect.

[0040] In an embodiment of the present application, for a parallel communication data processing method and device, a user stores valid data to be transmitted in the transmission data storage unit. The transmission data storage unit transmits the valid data to the internal DMA control unit according to a preset user configuration. The internal DMA control unit generates a first timing for reading the transmission data storage unit, and based on the first timing, transports the valid data from the transmission data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and transports the valid data to the channel buffer FIFO unit. The channel buffer FIFO unit obtains I-channel data and Q-channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I-channel data and the Q-channel data to transmit the valid data to the transmission control unit. The transmission control unit determines a corresponding target transmission protocol mode according to the preset transmission protocol mode, and transmits the valid data to an external device based on the target transmission protocol mode. In the present application, parallel data processing is performed through four units: a data storage unit, an internal DMA control unit, a channel buffer FIFO unit, and a transceiver control unit. Through data interleaving processing of the I / O channels, data of two channels can be transmitted through one channel, and only a set of signals is mapped to the external I / O, saving I / O resources and improving the utilization rate of the transmission channel. At the same time, through the internal DMA control unit, the CPU overhead can be minimized during high-speed data transmission, thereby improving the data transmission efficiency.

[0041] To make the above objects, features, and advantages of the present application more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 is a flowchart of a parallel communication data processing method provided according to an embodiment of the present application;

[0044] Figure 2 It is a schematic diagram of the parallel communication data processing flow;

[0045] Figure 3 It is a schematic diagram of the model block diagram of the internal DMA control unit;

[0046] Figure 4 It is a schematic diagram of the front and back data interaction of the internal DMA control unit in the data transmission mode;

[0047] Figure 5 This is a schematic diagram of the address alignment of the internal DMA control unit in data transmission mode;

[0048] Figure 6 It is a schematic diagram of data interleaving between I channel and Q channel;

[0049] Figure 7 It is a schematic diagram of the DMA transfer queue state machine in data transmission mode;

[0050] Figure 8 It is a schematic diagram of the DMA transfer queue state machine in data receiving mode. DETAILED DESCRIPTION

[0051] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0052] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0053] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0054] Considering that the microcomputer system, or microcomputer system, is an important part of modern computing technology. With the production and development of microprocessors and microcomputers, microcomputer systems have gradually become an important tool in the field of information technology. From the initial 4-bit microprocessor to the current 64-bit or even higher-performance processor, the microcomputer system has experienced rapid development. In the microcomputer system, data exchange and processing are often involved.

[0055] At present, there is a universal programmable parallel I / O interface, which is widely used in almost all series of microcomputer systems. The programmable parallel I / O interface has three data ports with latches or buffers, which can exchange data with peripherals in parallel. Among them, the data bus buffer and read-write control logic realize the writing of the transmitted data and the reading of the received data.

[0056] However, the existing technology requires three 8-bit data ports for communication with peripherals, namely, the PA port, the PB port, and the PC port. The PA port, the PB port, and the PC port can only transmit their own data independently, which greatly wastes I / O resources and the utilization rate of the transmission channel is also low. Moreover, each time data is transmitted, it is necessary to continuously write and send data, which makes the CPU overhead large and leads to low data transmission efficiency.

[0057] To address this problem, the present application provides a parallel communication data processing method and device, which performs parallel data processing through four units including a data storage unit, an internal DMA control unit, a channel cache FIFO unit, and a transceiver control unit. Through data interleaving processing of the I / O channel, data from two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, thereby saving I / O resources and improving the utilization rate of the transmission channel. At the same time, through the internal DMA control unit, the CPU overhead can be minimized during high-speed data transmission, thereby improving data transmission efficiency.

[0058] Figure 1 The flowchart of the parallel communication data processing method provided according to the embodiment of the present application is applied to the parallel communication data processing device.

[0059] The parallel communication data processing device includes a data storage unit, an internal DMA (Direct Memory Access) control unit, a channel cache FIFO (First In First Out) unit and a transceiver control unit; the data storage unit includes a sending data storage unit and a receiving data storage unit; the transceiver control unit includes a sending control unit and a receiving control unit. The parallel communication data processing device has a data receiving mode and a data sending mode. The data storage unit and the channel cache FIFO unit are respectively connected to the internal DMA control unit for communication, and the channel cache FIFO unit is connected to the transceiver control unit for communication.

[0060] For example, Figure 2 As shown in the figure, TX_RAM represents the transmit data storage unit, RX_RAM represents the receive data storage unit, TX_CTRL represents the transmit control unit, RX_CTRL unit represents the receive control unit, Internal DMA represents the internal DMA control unit, and Channel FIFO represents the channel buffer FIFO unit. Figure 2 It can be seen that the transmission direction from TX_RAM to the right indicates the data sending mode, that is, the data is sent from TX_RAM, and the transmission direction from RX_RAM to the left indicates the data receiving mode, that is, the data is received from RX_CTRL.

[0061] It should be noted that, in this application, TX_RAM, RX_RAM, TX_CTRL, and RX_CTRL are used to represent the corresponding units.

[0062] like Figure 1 As shown, the parallel communication data processing method of the embodiment of the present application may specifically include:

[0063] S101. In a data transmission mode, a user stores valid data to be transmitted in a transmission data storage unit, and the transmission data storage unit transmits the valid data to an internal DMA control unit according to a preset user configuration.

[0064] S102, the internal DMA control unit generates a first timing for a read operation to send a data storage unit, and based on the first timing, transfers valid data from the send data storage unit to the internal DMA control unit through a DMA channel of the internal DMA control unit, and transfers the valid data to a channel cache FIFO unit.

[0065] S103 , the channel buffer FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit.

[0066] S104. The sending control unit determines a corresponding target sending protocol mode according to a preset sending protocol mode, and transmits valid data to an external device based on the target sending protocol mode.

[0067] In the above-mentioned parallel communication data processing method, parallel data processing is performed through four units including a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiver control unit. Through the data interleaving processing of the I / O channel, the data of two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, which saves I / O resources and improves the utilization rate of the transmission channel; at the same time, the internal DMA control unit can minimize the CPU overhead during high-speed data transmission, thereby improving the data transmission efficiency.

[0068] The above exemplary steps of the embodiment of the present application are described below with reference to specific examples:

[0069] S101, in a sending mode, a user stores valid data to be sent in a sending data storage unit, and the sending data storage unit transmits the valid data to an internal DMA control unit according to a preset user configuration.

[0070] It should be noted that before performing parallel communication data processing through the data storage unit, the internal DMA control unit, the channel buffer FIFO unit and the transceiver control unit, the four units need to be configured.

[0071] In the embodiment of the present application, valid data is data to be sent, i.e., UPP (Universal Parallel Port) data, and user configuration includes DMA configuration, i.e., configuration of the internal DMA control unit, such as the size of the data to be transmitted, bandwidth, etc.; in the transmission mode, i.e., when data is transmitted, the user stores the valid data to be transmitted in the transmission data storage unit, i.e., the TX_RAM unit, and the TX_RAM unit transmits the valid data to the internal DMA control unit according to the user configuration. For example, Figure 2 shown.

[0072] It should be noted that the internal DMA control unit is obtained through the following steps: obtaining the target programming model, obtaining the internal DMA control unit based on the target programming model; configuring parameter information for each DMA channel of the internal DMA control unit. Among them, the target programming model represents a simplified programming model, and the parameter information includes the window address (Window Address), the number of bytes (Byte Count), the number of lines (Line Count) and the line offset address (Line Offset Address). In short, the internal DMA controller is implemented using a simplified programming model, and each DMA channel can be configured with corresponding parameter information, for example, Figure 3 shown.

[0073] Among them, the window address is the position of valid data in the data storage unit (TX_RAM / RX_RAM unit), that is, the position of upp data in the TX_RAM / RX_RAM storage unit, the window address is aligned according to the 32-bit boundary, and is aligned based on the preset alignment standard when the window address is not aligned; the alignment standard is that the lower 2 bits are automatically filled with 0, and the address is aligned downward; the number of bytes is the number of bytes in each row; the number of bytes is an even number; the number of bytes is configured as 2 or 4; when the number of bytes is configured as 0, the internal DMA control unit does not move data; the number of rows is the number of rows in each window; when the product of the number of rows and the number of bytes is 0, data transmission is not started; the row offset address is the offset address between the first byte between rows in consecutive rows; the row offset address is aligned with the 32-bit boundary in the memory.

[0074] Specifically, the Window Address must be aligned to a 32-bit boundary. The non-aligned window address will be automatically adjusted to the correct aligned value, the lower 2 bits will be automatically filled with 0, and the address will be aligned downward. The address is addressed as 0x0, 0x4, 0x8, and 0xC. For Byte Count, that is, the number of bytes in each row, the number of bytes must be an even number to ensure data alignment. When Byte Count is configured to 0, DMA does not move data; since the data requires 32-bit alignment, Byte Count can be configured to 2 or 4. For Line Count, that is, the number of rows in each window, the total number of bytes transmitted is equal to B (Byte Count) x L (Line Count), where B is the number of bytes per row and L is the number of rows. When the total number of bytes is 0, data transmission is not started.

[0075] Continuing, for Line Offset Address, that is, the offset address between the first byte between rows in continuous rows, the line offset address must be aligned with the 32-bit boundary in the memory and cannot exceed 0xFFFC. Its configuration value is 0x4, 0x8, 0XC, etc. Some values ​​of the line offset address have the following special effects on the structure of the data buffer: If the line offset address = byte count, the data buffer is a continuous block in the memory, and its size is equal to (line count) x (byte count); if the line offset address = 0, the data buffer consists of a line (specifically the first line), and the total size is equal to the byte count. If the I / O channel is configured in send mode, this line (number of rows) is transmitted continuously before the DMA transfer is completed. If the I / O channel is configured in receive mode, the buffer will be repeatedly written and overwritten by the incoming data.

[0076] It should also be noted that the sending data storage unit and the receiving data storage unit are dual-port RAMs, wherein the left port supports the access protocol of the AHB bus (Advanced High-performance Bus) and supports 32-bit mode access; the right port supports the three-bus protocol for accessing the RAM interface and supports 8-bit mode access.

[0077] Optionally, when storing the valid data to be sent in the sending data storage unit, the valid data to be sent is written into the sending data storage unit based on a preset write address via the AHB bus, wherein the write address is aligned to a 32-bit boundary, that is, stored in the form of 0x0, 0x4, 0x8, 0xC addresses.

[0078] For example, the following description is made taking the sending mode as an example: Figure 4 As shown. Among them, TX_RAM is a dual-port RAM. The left port supports the standard AHB bus protocol and supports 32-bit mode access. The right side is a three-bus protocol for accessing the RAM interface, which supports 8-bit mode access. The user writes the sent data to TX_RAM through the AHB bus. The write address is aligned to the 32-bit boundary, that is, it is stored in the form of 0x0, 0x4, 0x8, and 0xC addresses, as shown below Figure 5 shown.

[0079] It should be noted that, since the internal DMA control unit of the present application supports the 8-bit access mode, the DMA will certainly encounter the situation where the window address is not 32-bit aligned when transferring data. Therefore, by aligning the window address of the internal DMA control unit, the lower 2-bit address is discarded and rounded down, that is, when the configuration window address is 0x06, the address after internal processing is 0x04, and the DMA will start to transfer data from the 0x04 position of the TX_RAM unit, thereby ensuring that the data stored in the TX_RAM unit can be completely taken away.

[0080] S102, the internal DMA control unit generates a first timing for reading the sending data storage unit, and based on the first timing, transfers valid data from the sending data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and transfers the valid data to the channel cache FIFO unit.

[0081] In the embodiment of the present application, the channel cache FIFO unit includes an I channel and a Q channel, and the first timing is the timing information for the read operation of the sending data storage unit. After receiving the valid data sent by the sending data storage unit, the internal DMA control unit generates the first timing of the read operation sending data storage unit, and based on the first timing, the valid data is transferred from the sending data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and the valid data is transferred to the channel cache FIFO unit. For example, Figure 2 shown.

[0082] S103, the channel buffer FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit.

[0083] In the embodiment of the present application, after receiving the valid data sent by the internal DMA control unit, the channel buffer FIFO unit obtains the I channel data and Q channel data corresponding to the valid data through its own I channel and Q channel, and performs data interleaving processing on the I channel data and Q channel data to interleave the valid data to the sending control unit. Figure 2 shown.

[0084] It should be noted that data interleaving is performed on the I channel data and the Q channel data according to the channel configuration information, wherein the channel configuration information is the mode of the two channels, the I channel and the Q channel, of the channel buffer FIFO unit.

[0085] Optionally, when obtaining I channel data and Q channel data through the I channel and the Q channel and performing data interleaving processing on the I channel data and the Q channel data, the valid data is distributed to the I channel and the Q channel of the channel buffer FIFO unit to obtain the I channel data and the Q channel data; and the I channel data and the Q channel data are merged into one channel based on the transmission mode to perform data interleaving. For example, Figure 6 As shown, Demux represents the data interleaving processing of the present application, and Non-Demux represents non-interleaving. This figure is only to reflect the difference between interleaving and non-interleaving, and does not mean that the two can be performed at the same time.

[0086] Continue as Figure 6As shown, according to the configuration information, a single channel I or two channels I and Q can be selected to be used, and the transmission data is stored in channel I (I_D7, I_D6, I_D5, I_D4, I_D3, I_D2, I_D1, I_D0) and channel Q (Q_D7, Q_D6, Q_D5, Q_D4, Q_D3, Q_D2, Q_D1, Q_D0), respectively. Through interleaving processing, multiple data streams are merged into one physical channel for interleaved transmission, and the output data is (I_D7, Q_D7, I_D6, Q_D6, ..., I_D0, Q_D0), which improves the utilization rate of channel resources.

[0087] Thus, data is interleaved (multiplexed) through channel I and channel Q, and multiple data streams are merged into one physical channel for transmission, allowing other data streams to be transmitted when the channel is idle, rather than just waiting for one data stream to complete transmission, thereby improving the utilization rate of channel resources and transmission efficiency. This interleaving process belongs to block interleaving technology, which has a simple structure, is easy to implement, and is suitable for situations with a large amount of storage space.

[0088] S104, the sending control unit determines a corresponding target sending protocol mode according to the preset sending protocol mode, and transmits valid data to an external device based on the target sending protocol mode.

[0089] In the embodiment of the present application, the transmission protocol mode includes a single edge mode and a dual edge mode. After receiving the valid data represented by the I channel data and the Q channel data sent by the channel buffer FIFO unit, the transmission control unit determines the corresponding target transmission protocol mode according to the transmission protocol mode, and transmits the valid data to the external device based on the target transmission protocol mode, that is, after the transmission protocol mode is selected, the valid data is transmitted to the external device through the transmission protocol mode. For example, Figure 2 As shown. Therefore, the design of the internal DMA control unit improves the data transmission efficiency and transmission stability. The internal DMA control unit can minimize the CPU overhead during high-speed data transmission and improve the data transmission efficiency. The interleaving (multiplexing) processing technology of the channel cache FIFO unit realizes the interleaving processing of data, thereby improving the utilization rate of the transmission channel.

[0090] In the parallel communication data processing method provided by the embodiment of the present application, the user stores the valid data to be sent in the sending data storage unit, the sending data storage unit transmits the valid data to the internal DMA control unit according to the preset user configuration, the internal DMA control unit generates a first timing of the reading operation of the sending data storage unit, and based on the first timing, the valid data is moved from the sending data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and the valid data is moved to the channel cache FIFO unit, the channel cache FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit, the sending control unit determines the corresponding target sending protocol mode according to the preset sending protocol mode, and transmits the valid data to the external device based on the target sending protocol mode. The parallel communication data processing method of the present application performs parallel data processing through four units: a data storage unit, an internal DMA control unit, a channel cache FIFO unit, and a transceiver control unit. Through data interleaving processing of the I / O channel, the data of two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, which saves I / O resources and improves the utilization rate of the transmission channel. At the same time, the internal DMA control unit can minimize the CPU overhead during high-speed data transmission, thereby improving data transmission efficiency.

[0091] Furthermore, in the data receiving mode, the receiving control unit determines the corresponding target sending protocol mode according to the sending protocol mode, and transfers the received valid data to the channel cache FIFO unit based on the target sending protocol mode; the channel cache FIFO unit deinterleaves the valid data, transfers the processed valid data to the corresponding I channel and Q channel respectively, and transfers the valid data to the internal DMA control unit through the I / Q channel; the internal DMA control unit receives the data of the I channel and the Q channel, and generates a second timing required for the write operation of the receiving data storage unit, and moves the data of the I channel and the Q channel to the receiving data storage unit based on the second timing; the receiving data storage unit receives the data of the I channel and the Q channel of the internal DMA control unit, and stores it in the corresponding address space.

[0092] For example, Figure 2As shown, RX_CTRL can select single-edge mode and dual-edge mode reception according to the configuration information, and transmit the received valid data to the channel cache FIFO unit. The channel cache FIFO unit deinterleaves the valid data, and then transmits the valid data to the corresponding I channel and Q channel respectively, and transmits the data to the internal DMA control unit through the I / Q channel. The internal DMA control unit receives the data of the I channel and Q channel, and generates the second timing information required for the write operation of the RX_RAM unit according to the user configuration, and moves the I / Q channel data to the RX_RAM unit according to the configuration requirements. The RX_RAM unit receives the data of the internal DMA control unit and stores it in the corresponding address space, and the user can also read the data at any time.

[0093] It should be noted that the process in the data receiving mode is similar to the process in the above-mentioned data sending mode, and will not be described in detail here. For details, please refer to the description of the above-mentioned data sending mode.

[0094] Furthermore, when the parallel communication data processing device operates in a receiving mode, the internal DMA control unit receives valid data from the I / Q channel and writes the valid data to the receiving data storage unit; when the parallel communication data processing device operates in a sending mode, the internal DMA control unit reads valid data from the address of the data storage unit and passes the valid data to the I / Q channel of the internal DMA control unit.

[0095] Specifically, when the UPP data operates in receive mode, the DMA receives incoming data from the I / O channel and writes the data to the RX_RAM unit address. When the UPP data operates in transmit mode, the DMA reads data from the TX_RAM unit address and passes the data to the I / O channel.

[0096] Furthermore, the DMA channel of the internal DMA control unit has a transmission queue, and the transmission queue has descriptors; the internal DMA control unit transmits sequentially through the descriptors in the transmission queue of the DMA channel, obtains new descriptors during the transmission process, and adds the new descriptors to the transmission queue for queuing; when the active transmission is completed, the internal DMA control unit takes the next descriptor from the transmission queue and performs a new transmission based on the descriptor. Among them, each DMA channel has at most one active transmission (active DMA transmission) and queued transmission (queued DMA transmission); the active transmission is the transmission currently in progress, and the queued transmission is the transmission that has been configured but not yet started.

[0097] It should be noted that DMA allows new descriptors to be queued during the transfer process. Each DMA channel can have at most one active transfer and one queued transfer. After the active transfer is completed, DMA will automatically take the next descriptor from the queued transfer and start a new transfer. DMA will transfer in the order of the descriptors in the queue. During the active transfer, new descriptors can be added to the queue and wait for the active transfer to complete before execution.

[0098] Therefore, the DMA queuing operation improves the data transmission efficiency.

[0099] Furthermore, a corresponding queue state machine is used during the transmission process of the DMA channel of the internal DMA control unit; when an abnormal state occurs during the transmission process, a reset is performed based on the preset software to reset the queue state machine to the initial state, and reconfigure the descriptor to start the transmission again; when the I channel and the Q channel are initialized and idle (that is, the I / O channel is initialized and idle), the internal DMA control unit transmits valid data through the DMA channel. Optionally, the software can be a reset software controlled by the CPU, and a reset button can be defined on the software.

[0100] Specifically, during the DMA transfer process, if an abnormal state (such as a transmission error, overflow error, etc.) occurs, a software reset is performed to reset the DMA queue state machine to the initial state, and then the descriptor is reconfigured to restart the DMA transfer. In addition, the internal DMA controller always transfers data in a byte-addressed manner. If the relevant I / O channel is initialized and idle, the DMA transfer starts immediately. If no abnormal conditions occur during the transfer, the transfer will continue until the configured number of bytes is transferred.

[0101] Therefore, the stability of upp transmission is increased through the soft reset processing of the internal DMA control unit.

[0102] It is understood by those skilled in the art that the descriptor is used to describe data block transmission information, including key parameters such as source address, destination address, transmission length, control information, etc., and when the descriptor is reconfigured, these parameters are reset.

[0103] The following is a detailed description of the queue state machine in the DMA transmission of the present application.

[0104] In data sending mode, the DMA transmission queue state machine is as follows Figure 7As shown: TCH_IDLE indicates that the DMA is in a non-transmission state. When the DMA transmission valid signal r_dmatx_valid (used to indicate the validity of the DMA transmission or the validity of the data) is detected, the dmatxburst_sts state machine jumps to TCH_TRANS; otherwise, it remains in the TCH_IDLE state. TCH_TRANS means that if a new descriptor enable signal i_chi_en is detected during the period when r_dmatx_valid is valid, the dmatxburst_sts state machine jumps to TCH_WAIT (queueing of descriptors). If r_dmatx_valid is detected to be invalid (indicating shutdown, such as reset), the dmatxburst_sts state machine jumps to TCH_END; otherwise, it remains in the TCH_TRANS state.

[0105] Continuing, TCH_WAIT means that in this state, it does not respond to new descriptors until r_dmatx_valid is detected to be invalid. The dmatxburst_sts state machine jumps to TCH_JUMP, and at the same time, r_txchi_en_tmp or r_txchq_en_tmp is set (reset, shutdown, or invalid). TCH_JUMP means that the dmatxburst_sts state machine jumps to TCH_END. TCH_END means that the dmatxburst_sts state machine jumps to TCH_IDLE.

[0106] In the data reception mode, the DMA transmission queuing state machine is as follows Figure 8 As shown: The description of the state machine is similar to the above data transmission mode, and will not be elaborated here.

[0107] Thus, during the DMA transmission, new descriptors are allowed to queue. Each DMA channel has at most one active transmission and one queued transmission, and the DMA queuing operation improves the data transmission efficiency.

[0108] The embodiment of the present application further provides a parallel communication data processing device, including a data storage unit, an internal DMA control unit, a channel buffer FIFO unit, and a transceiver control unit; the data storage unit includes a transmission data storage unit and a reception data storage unit; the transceiver control unit includes a transmission control unit and a reception control unit; the parallel communication data processing device has a data reception mode and a data transmission mode. The above parallel communication data processing device is used to execute the above parallel communication data processing method.

[0109] In the parallel communication data processing device provided by the embodiment of the present application, the user stores the valid data to be sent in the sending data storage unit, the sending data storage unit transmits the valid data to the internal DMA control unit according to the preset user configuration, the internal DMA control unit generates a first timing of the reading operation of the sending data storage unit, and based on the first timing, the valid data is moved from the sending data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and the valid data is moved to the channel cache FIFO unit, the channel cache FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit, the sending control unit determines the corresponding target sending protocol mode according to the preset sending protocol mode, and transmits the valid data to the external device based on the target sending protocol mode. The parallel communication data processing device of the present application performs parallel data processing through four units: a data storage unit, an internal DMA control unit, a channel cache FIFO unit, and a transceiver control unit. Through data interleaving processing of the I / O channel, data of two channels can be transmitted through one channel, and only one group of signals is mapped to the external I / O, which saves I / O resources and improves the utilization rate of the transmission channel. At the same time, through the internal DMA control unit, the CPU overhead can be minimized during high-speed data transmission, thereby improving data transmission efficiency.

[0110] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0111] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0112] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0113] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the deployment method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard drives, ROM, RAM, magnetic disks, or optical disks.

[0114] The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A parallel communication data processing method, characterized in that: Applicable to a parallel communication data processing device, the parallel communication data processing device comprises a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiver control unit; the data storage unit comprises a transmission data storage unit and a reception data storage unit; The transceiver control unit includes a transmission control unit and a reception control unit; The parallel communication data processing device has a data receiving mode and a data sending mode; the method comprises: In the data transmission mode, the user stores the valid data to be transmitted in the transmission data storage unit, and the transmission data storage unit transmits the valid data to the internal DMA control unit according to a preset user configuration; the user configuration includes a DMA configuration; The internal DMA control unit generates a first timing for reading the transmission data storage unit, and based on the first timing, the valid data is transferred from the transmission data storage unit to the internal DMA control unit through the DMA channel of the internal DMA control unit, and the valid data is transferred to the channel buffer FIFO unit; wherein the channel buffer FIFO unit includes an I channel and a Q channel; The channel buffer FIFO unit obtains I channel data and Q channel data through the I channel and the Q channel for the valid data, and performs data interleaving processing on the I channel data and the Q channel data to transmit the valid data to the sending control unit; wherein, The sending control unit determines a corresponding target sending protocol mode according to a preset sending protocol mode, and transmits the valid data to an external device based on the target sending protocol mode; wherein the sending protocol mode includes a single edge mode and a double edge mode.

2. The parallel communication data processing method according to claim 1, characterized in that: The method further comprises: In the data receiving mode, the receiving control unit determines a corresponding target sending protocol mode according to the sending protocol mode, and transmits the received valid data to the channel buffer FIFO unit based on the target sending protocol mode; The channel buffer FIFO unit performs deinterleaving processing on the valid data, transmits the processed valid data to the corresponding I channel and Q channel respectively, and transmits the valid data to the internal DMA control unit through the I / Q channel; The internal DMA control unit receives the data of the I channel and the Q channel, generates a second timing required for the write operation of the received data storage unit, and moves the data of the I channel and the Q channel to the received data storage unit based on the second timing; The received data storage unit receives the data of the I channel and the Q channel of the internal DMA control unit and stores the data into the corresponding address space.

3. The parallel communication data processing method according to claim 2, characterized in that: The sending data storage unit and the receiving data storage unit are dual-port RAMs, wherein the left port supports the access protocol of the AHB bus and supports 32-bit mode access; the right port supports the three-bus protocol for accessing the RAM interface and supports 8-bit mode access; The storing of the valid data to be sent in the sending data storage unit comprises: The valid data to be sent is written into the sending data storage unit based on a preset write address through the AHB bus; wherein the write address is aligned with a 32-bit boundary, that is, stored in the form of 0x0, 0x4, 0x8, 0xC addresses.

4. The parallel communication data processing method according to claim 3, characterized in that: The internal DMA control unit is obtained by the following steps: Acquire a target programming model, and acquire the internal DMA control unit based on the target programming model; wherein the target programming model represents a simplified programming model; Parameter information is configured for each DMA channel of the internal DMA control unit; wherein the parameter information includes a window address, a number of bytes, a number of rows, and a row offset address.

5. The parallel communication data processing method according to claim 4, characterized in that: The window address is the location of the valid data in the data storage unit, the window address is aligned according to the 32-bit boundary, and is aligned based on a preset alignment standard when the window address is not aligned; the alignment standard is that the lower 2 bits are automatically filled with 0, and the address is aligned downward; The number of bytes is the number of bytes in each row; the number of bytes is an even number; the number of bytes is configured as 2 or 4; when the number of bytes is configured as 0, the internal DMA control unit does not transfer data; The number of rows is the number of rows in each window; when the product of the number of rows and the number of bytes is 0, data transmission is not started; The row offset address is an offset address between the first bytes between rows in continuous rows; the row offset address is aligned with a 32-bit boundary in the memory.

6. The parallel communication data processing method according to claim 5, characterized in that: The method further comprises: When the parallel communication data processing device operates in the receiving mode, the internal DMA control unit receives the valid data from the I / Q channel and writes the valid data into the receiving data storage unit; When the parallel communication data processing device operates in the transmission mode, the internal DMA control unit reads the valid data from the address of the data storage unit and transfers the valid data to the I / Q channel of the internal DMA control unit.

7. The parallel communication data processing method according to claim 6, characterized in that: The DMA channel of the internal DMA control unit has a transmission queue, and the transmission queue has a descriptor; the method further includes: The internal DMA control unit sequentially transmits through the descriptors in the transmission queue of the DMA channel, obtains new descriptors during the transmission process, and adds the new descriptors to the transmission queue for queuing; wherein each DMA channel has at most one active transmission and one queued transmission; the active transmission is the transmission currently in progress, and the queued transmission is the transmission that has been configured but not yet started; When the active transfer is completed, the internal DMA control unit takes the next descriptor from the transfer queue and performs a new transfer based on the descriptor.

8. The parallel communication data processing method according to claim 7, characterized in that: The obtaining of I channel data and Q channel data through the I channel and the Q channel, and performing data interleaving processing on the I channel data and the Q channel data, includes: Distributing the valid data to the I channel and the Q channel of the channel buffer FIFO unit to obtain the I channel data and the Q channel data; The I channel data and the Q channel data are combined into one channel based on the transmission mode to perform data interleaving.

9. The parallel communication data processing method according to claim 8, characterized in that: A corresponding queuing state machine during the transmission process of the DMA channel of the internal DMA control unit; The method further comprises: When an abnormal state occurs during the transmission process, a reset is performed based on the preset software to reset the queuing state machine to an initial state, and the descriptor is reconfigured to start the transmission again; When the I channel and the Q channel are initialized and idle, the internal DMA control unit transmits the valid data through the DMA channel.

10. A parallel communication data processing device, characterized in that: The parallel communication data processing device comprises a data storage unit, an internal DMA control unit, a channel cache FIFO unit and a transceiver control unit; the data storage unit comprises a transmit data storage unit and a receive data storage unit; the transceiver control unit comprises a transmit control unit and a receive control unit; the parallel communication data processing device has a data receiving mode and a data sending mode; The parallel communication data processing device is used to execute the parallel communication data processing method as described in any one of claims 1-9.

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