SRIO multi-channel communication method and system based on FC device

Abstract

The application provides an FC device-based SRIO multi-channel communication method and system, which utilizes the superior platform of programmable and parallel data processing provided by FPGA for protocol conversion, and provides an FC device-based SRIO multi-channel communication method and system, and the FC device-based SRIO multi-channel communication is realized by means of FPGA technology to realize efficient protocol conversion. In the FC device-based SRIO multi-channel communication method and system, the application of multi-channel sorting further optimizes the communication efficiency, provides a communication solution with higher performance and lower delay, is suitable for various high-performance communication systems, and meets the increasing data exchange and communication demand.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of FC network communication, in particular to a SRIO multi-channel communication method and system based on FC equipment. BACKGROUND

[0002] Currently, the demand for high-performance, multi-channel, and low-latency communication systems continues to grow, and Serial Rapid IO (SRIO) and Fibre Channel (FC) communication protocols play important roles in different fields.

[0003] SRIO communication protocol is a high-performance serial bus protocol designed to enable fast and reliable data communication between multiple processors, DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and other devices. SRIO protocol supports multi-channel communication, with each channel having a bandwidth of up to 10 Gbps or more, meeting the demand for high-speed data transmission, commonly used in high-performance computing and embedded systems. FC communication protocol is widely used in storage networks, data centers, and high-performance storage, with both channel and network advantages, and has high bandwidth, high reliability, high stability, and resistance to electromagnetic interference, etc. It uses optical fiber media as the main connection device to meet the needs of long-distance transmission and immunity to electromagnetic interference.

[0004] Traditional protocol conversion methods usually require dedicated hardware or multiple processing units, which increases system complexity and cost. For example, a protocol conversion system that relies on dedicated hardware is usually difficult to maintain and upgrade, and when new protocol support or performance improvement of existing protocols is needed, the entire hardware unit needs to be upgraded and replaced. At the same time, multiple processing units for protocol conversion can lead to resource waste. Different processing units may be activated at different points in time, resulting in uneven utilization of overall system resources, which in turn affects system performance and efficiency. Although hardware conversion methods (such as dedicated hardware conversion devices or conversion chips) can directly handle data format and signal conversion between FC and SRIO protocols, achieving high performance and low latency conversion, they also have the above-mentioned disadvantages of maintenance and upgrade, as well as resource utilization, and involve complex hardware design and implementation. SUMMARY

[0005] In view of the defects and deficiencies of the prior art, according to the first aspect of the purpose of the present application, a SRIO multi-channel communication system based on FC equipment is proposed, comprising:

[0006] SRIO_IP core, configured to receive SRIO frame data input and convert it into AXIS interface data output;

[0007] SRIO_CTRL control module, used for conversion control between SRIO protocol frame and AXIS interface data, including data frame framing based on different FC type data after parsing the AXIS interface data, and conversion into AXIS interface data after data splitting and packetizing based on the parsing result of the received FC data packet, and sent out to the SRIO_IP core;

[0008] Arbitration module, including sending arbitration module and receiving arbitration module, respectively used for sending direction and receiving direction request arbitration;

[0009] FLOW_CTRL sending / receiving control module, used for sending control of the framed data frame, and parsing and buffering of the received FC data packet;

[0010] The SRIO_CTRL control module includes T port as sending side module, I port as receiving side, sequencing module and framing module; the FLOW_CTRL sending / receiving control module includes a plurality of sending modules corresponding to different FC types;

[0011] In the data sending direction, the T port is used for parsing the AXIS interface data output data and extracting the frame header information of the SRIO frame data as a descriptor, the descriptor including TID, type, address and data length;

[0012] The sequencing module is used for address and channel mapping according to the descriptor, and sorting according to the TID field under different channels, and sending the parsed data into the specified RAM for buffering, and judging the FC type of the protocol frame and adding the FC type into the descriptor;

[0013] The framing module is used for framing the data according to the protocol frame format corresponding to the FC type by pre-reading the FC type in the descriptor, and the framed data is sent into the arbitration module, and sent out from the sending module corresponding to the FC type after arbitration by the sending arbitration module;

[0014] In the data receiving direction, the FLOW_CTRL sending / receiving control module receives the FC data packet from the FC switching network, and obtains data and descriptor after parsing;

[0015] The receiving arbitration module performs arbitration on the receiving module, and the framing module pre-reads the parsed descriptor, finds the address according to the relationship between the channel and the address, and splits and packetizes the data according to the length of the data, obtains a plurality of data packets corresponding to the SRIO frame header, and finally obtains the data frame conforming to the AXIS protocol through the I port conversion, and sends out to the SRIO_IP core;

[0016] The SRIO_IP core, the SRIO_CTRL control module, the arbitration module and the FLOW_CTRL sending / receiving control module are configured in the FPGA of the FC device.

[0017] As an optional implementation, the sorting module is configured to obtain the channel number based on the mapping relationship between the address and the channel number, so as to determine one channel number corresponding to each frame of data. The mapping relationship is configured by a blueprint, and the FPGA of the FC device reads the blueprint flash information for configuration after power-on.

[0018] As an optional implementation, the sorting module is configured to sort and store data in the following manner:

[0019] TID is defined to represent a description field of an unfinished transaction in each pair of source ID / destination ID in the SRIO HELLO frame, and the HELLO frame is sorted according to the field, and TID∈[0, 255];

[0020] Three pointers are set, which are p_wr, p_rd and p_rd_next, wherein p_wr is a write pointer, p_rd is a read pointer, and p_rd_next is a pre-reading pointer;

[0021] TID is taken as the address of the data RAM, and the payload of the HELLO frame is taken as the content of the data RAM, which is sequentially stored in the data RAM;

[0022] TID is taken as the address of the mark RAM, and 1 or 0 is taken as the content of the mark RAM, which is initially marked as 0, and when the HELLO frame corresponding to the TID is received, the corresponding content is marked as 1, and when the data is sent to the next level, the content corresponding to the TID is marked as 0;

[0023] When it is judged that the corresponding mark contents of the positions pointed by p_rd and p_rd_next are both 1, the data RAM content at the position of p_rd is sent to the next level, p_rd and p_rd_next are both increased by 1, and the mark contents are cleared;

[0024] When the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, the sending is stopped until the write pointer p_wr is about to catch up with p_rd, the residual data content at the position of p_rd is sent to the next level, and then the p_rd and p_rd_next pointers are both increased by 2 to jump over the pointer position where no data is received for a long time; after the jumping, the data receiving condition is judged according to the previous flow, and the cyclic sorting operation is completed.

[0025] As an optional implementation, after the sorting module sorts the data, the data is sent to the Payload fifo of the FLOW_CTRL sending / receiving control module in different channels for buffering, wherein:

[0026] The FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read the descriptor in the Payload fifo to determine whether the buffered data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both channels;

[0027] After the framing module reads the data, the FC ASM framing module and the FC 818 framing module frame according to the respective protocol frame format, and after the framing is completed, the data is sent to the sending arbitration module for arbitration, and after the data is arbitrated, the data is sent out through the corresponding sending module;

[0028] Among them, the FC ASM protocol frames under all channels are arbitrated together, and the FC 818 protocol frames under all channels are arbitrated together.

[0029] According to the second aspect of the object of the application, a SRIO multi-channel communication method based on an FC device is also provided, comprising the following steps:

[0030] In the data sending direction, after the SRIO_IP core receives the SRIO frame data input, the SRIO_IP core converts the SRIO frame data input into AXIS interface data output;

[0031] The T port parses the AXIS interface data output data and extracts the frame header information of the SRIO frame data as a descriptor, wherein the descriptor includes TID, type, address and data length;

[0032] The sorting module maps the address and the channel according to the descriptor, sorts the TID field under different channels, sends the parsed data to the specified RAM for buffering, and determines the FC type of the protocol frame and adds the FC type to the descriptor;

[0033] The FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read the descriptor to determine whether the buffered data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both channels; then the FC ASM framing module and the FC 818 framing module frame according to the respective protocol frame format, and after the framing is completed, the data is sent to the sending arbitration module for arbitration, and after the data is arbitrated, the data is sent out through the corresponding sending module; wherein, the FC ASM protocol frames under all channels are arbitrated together, and the FC 818 protocol frames under all channels are arbitrated together;

[0034] In the data receiving direction, the first sending module based on FC ASM protocol and the second sending module based on FC 818 protocol in the FLOW_CTRL sending / receiving control module receive FC data packets from the FC switching network, and obtain data and descriptors after analysis;

[0035] After arbitration of the receiving module by the receiving arbitration module, the descriptors obtained after analysis are pre-read by the framing module, the address is found according to the relationship between the channel and the address, and the data is cut and packaged according to the length of the data, a plurality of data packets corresponding to the SRIO frame header are obtained, finally the data frame conforming to the AXIS protocol is obtained through I port conversion and sent to the SRIO_IP core.

[0036] As an optional implementation, the sorting module obtains the channel number based on the mapping relationship between the address and the channel number, thereby determining one channel number corresponding to each frame data, wherein the mapping relationship is configured by a blueprint, and the FC device is powered on to read the blueprint flash information for configuration.

[0037] As an optional implementation, the sorting module is configured to sort and cache data in the following manner:

[0038] TID is defined to represent the description field of an unfinished transaction in each pair of source ID / destination ID in the SRIO HELLO frame, and the HELLO frame is sorted according to the field, TID∈[0, 255];

[0039] Three pointers are set, namely p_wr, p_rd and p_rd_next, wherein p_wr is a write pointer, p_rd is a read pointer, and p_rd_next is a pre-reading pointer;

[0040] TID is used as the data RAM address, and the HELLO frame payload is used as the content of the data RAM, which is sequentially stored in the data RAM;

[0041] TID is used as the address of the mark RAM, and 1 or 0 is used as the content of the mark RAM, which is initially marked as 0, when the corresponding HELLO frame of the TID is received, the corresponding content is marked as 1, and when the data is sent to the next level, the content corresponding to the TID is marked as 0;

[0042] When it is judged that the corresponding mark contents of the positions pointed by p_rd and p_rd_next are both 1, the data RAM content at the position of p_rd is sent to the next level, p_rd and p_rd_next are both increased by 1, and the mark contents are cleared;

[0043] When the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, the sending is stopped until the write pointer p_wr is about to catch up with p_rd, the residual data content at the position of p_rd is sent to the next level, and then the p_rd and p_rd_next pointers are simultaneously added by 2 to cross the pointer position of long time without receiving data; after crossing, the data receiving condition is continuously judged according to the previous flow, and the loop sorting operation is completed.

[0044] In combination with the SRIO multi-channel communication method and system based on the FC device in the above embodiment, the application aims to utilize the superior platform of programmable and parallel data processing provided by the FPGA for protocol conversion, and provides an SRIO multi-channel communication method and system based on the FC device, which realizes efficient protocol conversion by means of the FPGA technology based on the SRIO multi-channel communication of the FC device. In the SRIO multi-channel communication method and system based on the FC device, the application of multi-channel sorting further optimizes the communication efficiency, provides a communication solution with higher performance and lower delay, and is suitable for various high-performance communication systems and meets the growing data exchange and communication demand.

[0045] It should be understood that all combinations of the foregoing concepts and additional concepts described in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter. Additionally, all combinations of claimed subject matter are contemplated as part of the inventive subject matter.

[0046] The foregoing and other aspects, embodiments and features of the present teachings can be better understood from the following description of the present teachings with reference to the drawings. Other features of the present teachings will be apparent from the detailed description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0047] The accompanying drawings are not intended to be drawn to scale. In the drawings, each identical, or nearly identical, component that is illustrated in various figures is represented with a like numeral. For purposes of clarity, not every component is called out in every drawing. Embodiments of various aspects of the present teachings are now described in example embodiments, with reference to the drawings.

[0048] Figure 1 is a schematic diagram of an SRIO multi-channel communication system based on the FC device according to an embodiment of the present application.

[0049] Figure 2 is a schematic diagram of a sorting flow under a single channel according to an embodiment of the present application.

[0050] Figure 3is a data group framing and arbitration flow diagram under multi-channel according to an embodiment of the present application.

[0051] Figure 4 is a data processing flow diagram in sending direction according to an embodiment of the present application.

[0052] Figure 5 is a data processing flow diagram in receiving direction according to an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to understand the technical contents of the present application, specific embodiments are described below with the accompanying drawings.

[0054] Aspects of the present application are described in the disclosure by reference to the drawings, in which are shown many illustrative embodiments. The embodiments of the disclosure do not necessarily have to include all aspects of the present application. It should be understood that various inventive concepts and embodiments described above, and those described in more detail below, can be implemented in any of numerous ways, as the inventive concepts and embodiments disclosed are not limited to any one implementation. Additionally, some aspects of the present application can be utilized to alone, or in any appropriate combination with other aspects of the present application.

[0055] In combination Figure 1 The exemplary FC device based SRIO multi-channel communication system shown includes an SRIO_IP core, an SRIO_CTRL control module, an arbitration module, and a FLOW_CTRL sending / receiving control module.

[0056] As shown, the SRIO_IP core is configured to receive SRIO frame data input and convert it into AXIS interface data output. Figure 1

[0057] The SRIO_CTRL control module is configured to control conversion between SRIO protocol frames and AXIS interface data, including parsing the AXIS interface data and grouping data frames based on different FC type data, and converting the data after data splitting and packet grouping based on the parsing result of the received FC data packet into AXIS interface data and sending it out to the SRIO_IP core.

[0058] The arbitration module includes a sending arbitration module and a receiving arbitration module, which are respectively configured to perform request arbitration in sending direction and receiving direction.

[0059] The FLOW_CTRL sending / receiving control module is configured to control sending of the grouped data frames, and to parse and buffer the received FC data packet.

[0060] In combination Figure 1 ​As shown, the SRIO_CTRL control module includes a T port as the transmitting side module, an I port as the receiving side module, a sorting module, and a framing module.

[0061] The FLOW_CTRL transmit / receive control module includes multiple transmit modules corresponding to different FC types.

[0062] In the data transmission direction, the T port is used to parse the AXIS interface data output data and extract the frame header information of the SRIO frame data as a descriptor, which includes TID, type, address and data length.

[0063] The sorting module is used to map addresses to channels based on descriptors, sort according to the TID field under different channels, send the parsed data into the specified RAM for buffering, and determine the FC type of the protocol frame and add the FC type to the descriptor.

[0064] The framing module is used to frame data according to the protocol frame format corresponding to the FC type by pre-reading the FC type in the descriptor. The framed data is sent to the arbitration module, where it is arbitrated by the sending arbitration module and then sent out from the sending module corresponding to the FC type.

[0065] In the data receiving direction, the FLOW_CTRL transmit / receive control module receives FC data packets from the FC switching network, parses them to obtain data and descriptors.

[0066] After the receiving arbitration module arbitrates the receiving module, the framing module pre-reads the parsed descriptor, finds the address based on the relationship between the channel and the address, and segments and assembles the data according to the data length to obtain multiple data packets with corresponding SRIO frame headers. Finally, it converts the data through the I port to obtain a data frame conforming to the AXIS protocol and sends it to the SRIO_IP core.

[0067] like Figure 1 In the example shown, the SRIO_IP core, SRIO_CTRL control module, arbitration module, and FLOW_CTRL transmit / receive control module are all configured inside the FPGA of the FC device.

[0068] In a preferred embodiment, the sorting module is configured to obtain the channel number based on the mapping relationship between address and channel number, thereby determining a channel number corresponding to each frame of data. The mapping relationship is configured via a blueprint, and the FC device's FPGA reads the blueprint flash information for configuration after power-on.

[0069] As an optional implementation, the framing module includes an FC ASM framing module and an FC 818 framing module;

[0070] FC ASM framing module, configured to frame the incoming data into FC ASM protocol frames according to the FC ASM protocol;

[0071] FC 818 framing module, configured to frame the incoming data into FC 818 protocol frames according to the FC 818 protocol.

[0072] As shown in Figure 1 , Figure 3 As shown in FIG. 8, the sending module of different FC types includes a first sending module based on the FC ASM protocol and a second sending module based on the FC 818 protocol, taking the FC 818 ip and the FC ASM ip as examples.

[0073] As shown in Figure 2 ,

[0074] TID represents a description field of an unfinished transaction in each pair of source ID / destination ID in the SRIO HELLO frame, and the HELLO frame is sorted according to the field, and TID ∈ [0, 255];

[0075] Three pointers are set, which are p_wr, p_rd and p_rd_next, wherein p_wr is a write pointer, p_rd is a read pointer, and p_rd_next is a pre-reading pointer;

[0076] TID is taken as a data RAM address, and the HELLO frame payload is taken as the content of the data RAM, and is sequentially stored in the data RAM;

[0077] TID is taken as an address of the mark RAM, and 1 or 0 is taken as the content of the mark RAM, and is initially marked as 0, when the corresponding HELLO frame of the TID is received, the corresponding content is marked as 1, and when the data is sent to the next level, the content corresponding to the TID is marked as 0;

[0078] When it is judged that the corresponding mark contents of the positions pointed by p_rd and p_rd_next are both 1, the data RAM content at the position of p_rd is sent to the next level, p_rd and p_rd_next are both increased by 1, and the mark contents are cleared;

[0079] When the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, the sending is stopped until the write pointer p_wr is about to catch up with p_rd, the residual data content at the position of p_rd is sent to the next level, and then the p_rd and p_rd_next pointers are both increased by 2 to pass the pointer position of a long time without receiving data; after passing, the data receiving condition is judged according to the previous process, and the loop sorting operation is completed.

[0080] In combination Figure 1 , 3 As shown in FIG. 1, after the sorting module sorts the data, the data is sent to the Payload fifo of the FLOW_CTRL sending / receiving control module according to different channels for buffering, wherein:

[0081] The FC ASM framing module and the FC 818 framing module in the framing module respectively pre-read the descriptor in the Payload fifo to determine whether the buffered data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both channels;

[0082] After the framing module reads the data, the FC ASM framing module and the FC 818 framing module frame according to the respective protocol frame formats, and after the framing is completed, the data is sent to the sending arbitration module for arbitration, and after the data is arbitrated, the data is sent out through the corresponding sending module;

[0083] Among them, the FC ASM protocol frames under all channels are arbitrated together, and the FC 818 protocol frames under all channels are arbitrated together.

[0084] Among them, in combination Figure 4 As shown in FIG. 1, the T module is also configured to determine whether to send a packet back to the SRIO_IP core according to the received data packet.

[0085] In combination Figure 1 , 2 , 3, 4, 5, the SRIO multi-channel communication method based on the FC device disclosed in the present application comprises the following steps:

[0086] In the data sending direction, after the SRIO_IP core receives the SRIO frame data input, the SRIO_IP core converts the SRIO frame data input into AXIS interface data output;

[0087] The T port parses the AXIS interface data output data and extracts the frame header information of the SRIO frame data as a descriptor, wherein the descriptor includes TID, type, address and data length;

[0088] The sorting module maps the address and the channel according to the descriptor, sorts the TID field under different channels, sends the parsed data to the specified RAM for buffering, and determines the FC type of the protocol frame and adds the FC type to the descriptor;

[0089] The FC ASM framing module and the FC 818 framing module respectively pre-read the descriptors, judge whether the buffered data corresponds to FC ASM protocol data, FC 818 protocol data or data sent by both, then frame according to the respective protocol frame format, send to the sending arbitration module for arbitration after framing is completed, and send out after data arbitration is completed; wherein, the FC ASM protocol frames under all channels are arbitrated together, and the FC 818 protocol frames under all channels are arbitrated together;

[0090] In the data receiving direction, the first sending module based on the FC ASM protocol and the second sending module based on the FC 818 protocol in the FLOW_CTRL sending / receiving control module receive the FC data packet from the FC switching network, and obtain data and descriptors after analysis;

[0091] After arbitration of the receiving module by the receiving arbitration module, the descriptors obtained by pre-reading and analysis are read by the framing module, the address is found according to the relationship between the channel and the address, and the data is cut and packaged according to the length of the data, a plurality of data packets corresponding to the SRIO frame header are obtained, finally the data frame conforming to the AXIS protocol is obtained through I port conversion, and is sent out to the SRIO_IP core.

[0092] As an optional implementation, the ordering module obtains the channel number based on the mapping relationship between the address and the channel number, thereby determining a channel number corresponding to each frame of data, wherein the mapping relationship is configured by a blueprint, and the FC device reads the blueprint flash information for configuration after power-on of the FPGA.

[0093] As an optional implementation, in combination with Figure 2 As shown in the figure, the ordering module is arranged to order and data buffer in the following manner:

[0094] Define TID to represent the description field of an unfinished transaction in each pair of source ID / destination ID in the SRIO HELLO frame, and sort the HELLO frame according to the field, TID∈[0, 255];

[0095] Three pointers are set, p_wr, p_rd and p_rd_next, wherein p_wr is a write pointer, p_rd is a read pointer, and p_rd_next is a pre-reading pointer;

[0096] Take TID as the data RAM address, and take the HELLO frame payload as the content of the data RAM, and store them in the data RAM in sequence;

[0097] The TID is used as the address of the mark RAM, and 1 or 0 is used as the content of the mark RAM, which is initially marked as 0, and when the HELLO frame corresponding to the TID is received, the corresponding content is marked as 1, and when the data is sent to the lower level, the content corresponding to the TID is marked as 0;

[0098] When it is judged that the corresponding mark contents of the positions pointed to by p_rd and p_rd_next are both 1, the data RAM content at the p_rd position is sent to the lower level, p_rd and p_rd_next are both incremented by 1, and the mark contents are cleared;

[0099] When the mark content corresponding to p_rd is 1 and the mark content corresponding to p_rd_next is 0, the sending is stopped until the write pointer p_wr is about to catch up with p_rd, the residual data content at the p_rd position is sent to the lower level, and then the p_rd and p_rd_next pointers are both incremented by 2, so as to pass the pointer position where no data has been received for a long time; after passing, the data receiving situation is judged according to the previous flow, and the loop sorting operation is completed.

[0100] {Example 1}

[0101] In this example, the overall logic of the SRIO multi-channel communication system based on the FC device is as shown in Figure 1 .

[0102] {Data sending}

[0103] As shown in Figure 1 , the direction from the SRIO IP to the FLOW CTRL is the data sending direction, that is, the direction from left to right in the figure is the data sending direction.

[0104] The data flows into the FPGA through the SRIO protocol frame, is converted into a data stream through the SRIO_IP core, is sent into the T port, is parsed, and the descriptor information in the frame header is extracted, wherein the address information in the frame header is used for channel number mapping (it should be understood that the mapping relationship is configured through a blueprint, and the blueprint flash information is read after the FPGA is powered on to configure), so as to obtain the channel number, and therefore each frame of data corresponds to a channel number.

[0105] The parsed data is respectively sorted according to different channel numbers in the sorting module (TID is a descriptor in the frame header, and is incremental under each channel), after sorting, enters the arbitration module to arbitrate, and one piece of data is distributed to two paths to perform different FC protocol framing (taking the FC ASM and FC 818 protocols as examples for description, other FC protocol frames can also be used), and finally is sent to the opposite device through the sending module, to complete the data transmission in the sending direction.

[0106] {Data receiving}

[0107] In combination Figure 1 As shown from FLOW CTRL to SRIO_IP core, that is, from right to left in the drawing, the data receiving direction.

[0108] After the data from the FC switching network is received by the receiving module, the protocol frame is parsed, after the parsing is completed, the arbitration module arbitrates the two-way data, after the arbitration is completed, the data is sent to the framing module, and the data packet is divided and packaged according to different FC types, the data length is divided into a payload conforming to the SRIO data length, wherein each payload corresponds to a frame header, the data is converted into a data frame conforming to the AXIS protocol through the I port and sent to the SRIO_IP core, and finally the SRIO_IP core is sent out, and the data transmission in the receiving direction is completed.

[0109] {sorting}

[0110] In combination Figure 1 , 2 In the embodiment of the application, the TID is a description field of an unfinished transaction in each pair of source ID / destination ID in the SRIO HELLO frame, and the HELLO frame is sorted according to the field.

[0111] Three pointers, p_wr, p_rd and p_rd_next, are set, wherein the p_wr is a write pointer, the p_rd is a read pointer, and the p_rd_next is a pre-reading pointer.

[0112] In Figure 2 In the example shown, TID∈[0, 255] is described, TID is used as the data RAM address, and the HELLO frame payload is used as the content of the data RAM and is sequentially stored in the data RAM.

[0113] Similarly, TID is used as the address of the mark RAM, and 1 or 0 is used as the content of the mark RAM, which is initially marked as 0, when the corresponding HELLO frame of the TID is received, the corresponding content is marked as 1, and when the data is sent to the next level, the content corresponding to the TID is marked as 0.

[0114] When it is judged that the corresponding mark contents of the positions pointed by p_rd and p_rd_next are both 1, the data RAM content at the position of p_rd is sent to the next level, p_rd and p_rd_next are both increased by 1, and the mark contents are cleared; when the corresponding mark content of p_rd is 1 and the corresponding mark content of p_rd_next is 0, the sending is stopped until the write pointer p_wr is about to catch up with p_rd (representing that the timeout / fifo is almost full, and the difference can be set), the residual data content at the position of p_rd is sent to the next level, and then the p_rd and p_rd_next pointers are both increased by 2 to pass the pointer position at which no data is received for a long time.

[0115] After passing, the data receiving situation is continuously judged according to the previous flow, and the cycle is completed.

[0116] In combination with the embodiments of the application, the advantage of using the sorting mode is that due to the design defects of hardware, the TID under a single channel may not be continuous all the time, and jumps may occur, such as shown by c in Figure 2 When the TID is 254 and no data is received (wherein the blue mark represents that the TID is received, and the white mark represents that the TID is not received), if the reference clock used is changed, the time deviation of the counting timeout will be relatively large, and the mode of using the difference between the write pointer and the read pointer can avoid the large time deviation, and at the same time, a buffer margin is left to wait for receiving the missing TID.

[0117] {Data grouping and arbitration}

[0118] The data grouping and arbitration flow under multiple channels is shown in Figure 3 After the data is sorted, it is sent into the Payload fifo according to different channels for buffering.

[0119] The FC ASM grouping module and the FC 818 grouping module will pre-read the descriptor in the Payload fifo to judge whether the data is FC ASM data, FC 818 data or data sent by both channels (the data sent by both channels needs to be copied twice, and sent to the asm and 818 respectively).

[0120] After the data is read by the grouping module, the data is grouped according to the respective protocol frame format, and after the grouping is completed, the completion signal is sent into the arbitration module, the asm protocol frames under all channels are arbitrated together, the 818 protocol frames under all channels are arbitrated together, and after the data is arbitrated, the data frame is sent out through the asm ip and the 818 ip.

[0121] In the example of the present application, arbitration can be implemented using existing algorithms. For example, using a balancing algorithm, the weight in the algorithm can be configured (the higher the weight, the more times it is read) or using an adaptive method of port flow (according to the flow size in time T, the weight size in the next time T is determined, and when the weights of the channels are the same, a polling method is used to read).

[0122] {Data transmission}

[0123] The data processing flow in the transmission direction is shown in Figure 4

[0124] In the transmission direction, a frame of 256B SRIO frame data flows in, and then is converted into AXIS interface data output after entering the SRIO_IP core. The data enters the T module, which converts the AXIS interface data into a normal data stream, and extracts the information in the SRIO frame header as a subsequent descriptor for use, including TID, type, address, and data length information.

[0125] The data and the descriptor are respectively placed in the cache. At the same time, the T module also determines whether it needs to send a packet back to the SRIO_IP core according to the type.

[0126] The lower-level sorting module pre-reads the descriptor, maps the address and channel of the descriptor, and sends the 256B data to the specified RAM for caching according to the TID field under different channels.

[0127] When the sorting is completed, the 256B data and the new descriptor are respectively stored in the cache, and the FC type is added to the descriptor according to the data content.

[0128] The flow ctrl pre-reads the descriptor, writes the data into different framing modules according to the type of FC, and when the framing module reads n 256, it completes a data packet of FC frame length, and writes the framed data frame into the cache after framing is completed, and waits for arbitration.

[0129] When the arbitration hits, the corresponding data frame is read out and sent out through the FC ASM ip and FC818 ip.

[0130] Special cases: in the sorting module, two pointers are used to determine whether to send out data, and the last frame of data is sent out according to the eop field in the data descriptor. Since the SRIO protocol frame does not contain sop and eop, the start and end of the frame are added in the data, where 4B is used to represent sop and 4B to represent eop. In addition, the format, type, length, number of rows, and other information of the FC 818 image are defined in the data. ​

[0131] {data receiving}

[0132] The data receiving direction processing flow is as shown in the figure. Figure 5

[0133] In the receiving direction, there is a frame payload length of 2096B FC ASM data packet, after FC ASM ip parsing, the SID, DID, MSG ID, frame length and other information are obtained through the frame header, the MSG ID here is the channel number, the descriptor and data are stored in different buffers respectively.

[0134] After arbitration by the arbitration module, the descriptor is pre-read by the framing module, according to the relationship between the channel number and the SRIO address, the address is found, according to the length of the data payload, the data is divided into 8 256B and 1 48B data packets conforming to the SRIO protocol. It should be understood that the 9 data packets correspond to 9 SRIO frame headers respectively, the TID field is managed according to the channel number, and finally the I port reads and converts into a data frame conforming to the AXIS protocol and sends it to the SRIO_IP core, and finally the SRIO_IP core sends it out, completing the data transmission in the receiving direction.

[0135] Although the present application has been disclosed with the preferred embodiments as above, it is not intended to limit the present application. Those skilled in the art can make various modifications and improvements without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the definition of the claims.​

Claims

1. A multi-channel SRIO communication system based on FC devices, characterized in that, include: The SRIO_IP core is used to receive SRIO frame data input and convert it into AXIS interface data output. The SRIO_CTRL control module is used for the conversion control between SRIO protocol frames and AXIS interface data. This includes parsing AXIS interface data and framing data frames based on different FC types, as well as splitting and assembling data based on the parsing results of received FC data packets, and then converting it into AXIS interface data to be sent to the SRIO_IP core. The arbitration module includes a sending arbitration module and a receiving arbitration module, which are used for requesting arbitration in the sending direction and the receiving direction, respectively; The FLOW_CTRL send / receive control module is used for controlling the transmission of data frames after framing, as well as parsing and buffering received FC data packets; The SRIO_CTRL control module includes a T port as a transmitting module, an I port as a receiving module, a sorting module, and a framing module; the FLOW_CTRL transmit / receive control module includes multiple transmitting modules corresponding to different FC types. In the data transmission direction, the T port is used to parse the AXIS interface data output data and extract the frame header information of the SRIO frame data as a descriptor. The descriptor includes TID, type, address and data length. The sorting module is used to map addresses to channels according to descriptors, sort according to the TID field under different channels, send the parsed data into the specified RAM for buffering, and determine the FC type of the protocol frame and add the FC type to the descriptor. The framing module is used to frame data according to the protocol frame format corresponding to the FC type by pre-reading the FC type in the descriptor. The framed data is sent to the arbitration module, and after arbitration by the sending arbitration module, it is sent out from the sending module corresponding to the FC type. In the data receiving direction, the FLOW_CTRL send / receive control module receives FC data packets from the FC switching network, parses them to obtain data and descriptors; After the receiving arbitration module arbitrates the receiving module, the framing module pre-reads the parsed descriptor, finds the address based on the relationship between the channel and the address, and segments and assembles the data according to the data length to obtain multiple data packets with corresponding SRIO frame headers. Finally, it converts the data frame through the I port to obtain a data frame conforming to the AXIS protocol and sends it to the SRIO_IP core. The SRIO_IP core, SRIO_CTRL control module, arbitration module, and FLOW_CTRL transmit / receive control module are all configured inside the FPGA of the FC device.

2. The SRIO multi-channel communication system based on FC devices according to claim 1, characterized in that, The sorting module is configured to obtain the channel number based on the mapping relationship between the address and the channel number, thereby determining a channel number corresponding to each frame of data.

3. The SRIO multi-channel communication system based on FC devices according to claim 2, characterized in that, The mapping relationship is configured via blueprints. After the FPGA of the FC device is powered on, it reads the blueprint flash information for configuration.

4. The SRIO multi-channel communication system based on FC devices according to claim 1, characterized in that, The framing module includes an FC ASM framing module and an FC 818 framing module; The FC ASM framing module is used to frame the incoming data according to the FC ASM protocol. The FC 818 framing module is used to frame the incoming data according to the FC 818 protocol.

5. The SRIO multi-channel communication system based on FC devices according to claim 1, characterized in that, The different FC type transmission modules include a first transmission module based on the FC ASM protocol and a second transmission module based on the FC 818 protocol.

6. The SRIO multi-channel communication system based on FC devices according to claim 1, characterized in that, The sorting module is configured to perform sorting and data caching in the following manner: Define TID as the description field of the incomplete transactions in each source ID / target ID pair in the SRIO HELLO frame. The HELLO frames are sorted according to this field, and TID∈[0,255]. Set up three pointers: p_wr, p_rd, and p_rd_next. p_wr is the write pointer, p_rd is the read pointer, and p_rd_next is the read-ahead pointer. The TID is used as the data RAM address, and the HELLO frame payload is used as the data RAM content, and they are stored in the data RAM sequentially. TID is used as the address of the tag RAM, and 1 or 0 is used as the content of the tag RAM. Initially, the tag is 0. When a HELLO frame corresponding to TID is received, the corresponding content is tagged as 1. When the data is sent to the next level, the tag of the content corresponding to TID is cleared to zero. Specifically, when it is determined that the corresponding flag content at the position pointed to by p_rd and p_rd_next is 1, the data RAM content at the p_rd position is sent to the next level, p_rd and p_rd_next are both incremented by 1, and the flag content is cleared at the same time; When the flag corresponding to p_rd is 1 and the flag corresponding to p_rd_next is 0, transmission stops until the write pointer p_wr is about to catch up with p_rd. The remaining data at the p_rd position is then sent to the next level. Then, the p_rd and p_rd_next pointers are incremented by 2, and the pointer position that has not received data for a long time is passed. After passing the pointer position, the data reception status is checked according to the previous process, and the cyclic sorting operation is completed.

7. The SRIO multi-channel communication system based on FC devices according to claim 1, characterized in that, After the sorting module completes the sorting of the data, it is sent to the payload fifo of the FLOW_CTRL send / receive control module for buffering according to different channels, wherein: The FC ASM framing module and FC 818 framing module in the framing module pre-read the descriptors in the Payload fifo to determine whether the cached data corresponds to FC ASM protocol data, FC 818 protocol data, or data sent from both channels. After the framing module reads the data, the FC ASM framing module and the FC 818 framing module frame the data according to their respective protocol frame formats. After framing, the data is sent to the transmission arbitration module for arbitration. After the data arbitration is completed, it is sent out through the corresponding transmission modules. Specifically, FC ASM protocol frames from all channels are arbitrated together, and FC 818 protocol frames from all channels are arbitrated together.

8. A method for SRIO multi-channel communication based on an FC device in a FC device-based SRIO multi-channel communication system according to any one of claims 1-7, characterized in that, Includes the following steps: In the data transmission direction, after receiving SRIO frame data input, the SRIO_IP core converts it into AXIS interface data output; The T port parses the AXIS interface data and outputs the data, extracting the frame header information of the SRIO frame data as a descriptor. The descriptor includes TID, type, address, and data length. The sorting module maps addresses to channels based on descriptors, sorts them according to the TID field under different channels, sends the parsed data into the specified RAM for buffering, and determines the FC type of the protocol frame and adds the FC type to the descriptor. The FC ASM framing module and the FC 818 framing module in the framing module pre-read the descriptor to determine whether the buffered data corresponds to FC ASM protocol data, FC 818 protocol data, or data transmitted from both channels. Then, the FC ASM framing module and the FC 818 framing module frame the data according to their respective protocol frame formats. After framing, the data is sent to the transmission arbitration module for arbitration. After the data arbitration is completed, it is sent out through the corresponding transmission module. Among them, FC ASM protocol frames from all channels are arbitrated together, and FC 818 protocol frames from all channels are arbitrated together. In the data receiving direction, the first transmitting module based on the FC ASM protocol and the second transmitting module based on the FC 818 protocol in the FLOW_CTRL transmit / receive control module receive FC data packets from the FC switching network, and obtain the data and descriptors after parsing; After the arbitration module arbitrates the receiving module, the framing module pre-reads the parsed descriptor, finds the address based on the relationship between the channel and the address, and segments and assembles the data according to the data length to obtain multiple data packets with corresponding SRIO frame headers. Finally, it converts the data frame through the I port to obtain a data frame conforming to the AXIS protocol and sends it to the SRIO_IP core.

9. The SRIO multi-channel communication method based on FC devices according to claim 8, characterized in that, The sorting module obtains the channel number based on the mapping relationship between the address and the channel number, thereby determining a channel number corresponding to each frame of data. The mapping relationship is configured through a blueprint. After the FPGA of the FC device is powered on, it reads the blueprint flash information for configuration.

10. The SRIO multi-channel communication method based on an FC device according to claim 8 or 9, characterized in that, The sorting module is configured to perform sorting and data caching in the following manner: Define TID as the description field of the incomplete transactions in each source ID / target ID pair in the SRIO HELLO frame. The HELLO frames are sorted according to this field, and TID∈[0,255]. Set up three pointers: p_wr, p_rd, and p_rd_next. p_wr is the write pointer, p_rd is the read pointer, and p_rd_next is the read-ahead pointer. The TID is used as the data RAM address, and the HELLO frame payload is used as the data RAM content, and they are stored in the data RAM sequentially. TID is used as the address of the tag RAM, and 1 or 0 is used as the content of the tag RAM. Initially, the tag is 0. When a HELLO frame corresponding to TID is received, the corresponding content is tagged as 1. When the data is sent to the next level, the tag of the content corresponding to TID is cleared to zero. Specifically, when it is determined that the corresponding flag content at the position pointed to by p_rd and p_rd_next is 1, the data RAM content at the p_rd position is sent to the next level, p_rd and p_rd_next are both incremented by 1, and the flag content is cleared at the same time; When the flag corresponding to p_rd is 1 and the flag corresponding to p_rd_next is 0, transmission stops until the write pointer p_wr is about to catch up with p_rd. The remaining data at the p_rd position is then sent to the next level. Then, the p_rd and p_rd_next pointers are incremented by 2, and the pointer position that has not received data for a long time is passed. After passing the pointer position, the data reception status is checked according to the previous process, and the cyclic sorting operation is completed.

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