Double-channel RS485-to-PCIE interface module based on HDLC protocol

Abstract

The invention discloses a dual-channel RS485-to-PCIE interface module based on an HDLC protocol. Communication reliability is guaranteed through a dual-redundancy RS485 circuit design, a traditional HDLC protocol scheme needs to be externally connected with an HDLC physical layer chip, a physical layer chip does not need to be externally connected in the dual-channel RS485-to-PCIE interface module, a PL end IP core in a PSOC achieves a link layer function, and a PS end achieves HDLC data flow control, data processing and communication. According to the full programmable PSOC, the programmable logic of the CPU and the programmable logic of the FPGA are integrated on one chip, the system performance can be greatly improved, the IO bandwidth is greatly improved, the area of the whole chip is smaller, and the power consumption is lower. And in cooperation with corresponding development software, an integrated software and hardware platform is realized, user development is facilitated, the development period is shortened, and the production cost is saved.

Description

Technical Field

[0001] The invention belongs to the field of bus communication, and in particular relates to a communication interface conversion module based on the HDLC protocol. Background Art

[0002] The HDLC (High Level Data Link Control) protocol is one of the most widely used protocols in the communications field. It is a bit-oriented high-level data link control procedure with powerful error detection, high efficiency and synchronous transmission.

[0003] HDLC supports synchronous and asynchronous physical transmission lines, and supports code-independent (i.e. data stream-oriented) transparent transmission (code-transparent data transmission).

[0004] As an efficient, reliable and flexible data link layer protocol, HDLC protocol has been widely used in network communications.

[0005] The present invention is a dual-channel RS485 to PCIE interface module based on the HDLC protocol specially developed for embedded system products in the field of avionics. However, the existing HDLC module cannot directly implement data interaction with airborne equipment or systems. Summary of the invention

[0006] In order to solve the existing problems, the present invention provides a dual-channel RS485 to PCIE interface module based on the HDLC protocol, implements a control method of the HDLC protocol based on the FPGA+SOC architecture, ensures the reliability of communication through a dual redundant RS485 circuit design, and performs data interaction with a host through a PCIE high-speed interface.

[0007] The interface module comprises a main control chip, a DDR3 storage circuit, a FLASH storage circuit, a debugging serial port circuit, a clock circuit, an HDLC protocol controller, an RS485 interface circuit, a PCIE high-speed interface and a power supply circuit.

[0008] A further solution is that the SOC integrated in the main control chip prioritizes the data receiving function, the data received by the RS485 bus interface is first received by the HDLC protocol controller, the received data is stored in the DDR3 cache through the AXI bus, and then the data is transmitted to the PCIE interface.

[0009] A further solution is that the SOC integrated in the main control chip is responsible for reading data from the PCIE host interface, caching the data into DDR3 as required, and then sending the data from DDR3 to the HDLC protocol controller to complete the data transmission through the RS485 interface.

[0010] A further solution is that the DDR3 storage circuit is used as data cache and management, and two 16-bit DDR3 chips are cascaded to form a 32-bit, 1GB storage space with a data rate of 800MT / S and a clock of 400MHz.

[0011] A further solution is that the debugging serial port circuit is connected to the UART0 controller on the PS side, and a UART to RS232 level interface is realized through a standard RS232 serial port driver chip, which is used as an interface module function debugging, meets the EIA / TIA-232-F standard, and has an operating voltage of 3.0V to 5.5V.

[0012] The clock circuit provides clocks to both the PS and PL ends of the main control chip. The interface module uses a GTX high-speed interface for external communication. The clock signal of this part is provided by an external device and is directly input to the GTX clock pin through the AC coupling circuit of the interface module.

[0013] A further solution is that the main control chip PL side realizes the HDLC protocol transceiver function, which is divided into an HDLC protocol receiving unit and an HDLC protocol sending unit.

[0014] The RS485 interface circuit is a 2-way dual-redundancy design, divided into two channels A and B, and consists of a receiving module and a sending module. The HDLC protocol controller is directly connected to the RS485 transceiver for receiving and sending data from the external bus.

[0015] The main control chip PS end has two QSPI controllers integrated inside, which can be used to connect to QSPI FLASH as the system boot program storage space. The FLASH memory is mounted on the QSPI0 interface. The FLASH memory is used for system image and boot program storage, with a storage capacity of 256Mbit and a maximum clock frequency of 100MHz.

[0016] The external power supply is stepped down for a second time by the power supply circuit to supply power to each functional unit of the module.

[0017] This application has the following beneficial effects: The dual-channel RS485 to PCIE interface module based on the HDLC protocol provided by the present invention realizes HDLC communication data conversion in the field of avionics. The module receives data from an external airborne device through an RS485 bus, parses the data according to the HDLC protocol, and sends the data to a host end through a PCIE interface for processing. At the same time, the information on the host end is processed through the HDLC protocol and then sent to the airborne device end through the RS485 bus.

[0018] The dual-channel RS485 to PCIE interface module based on the HDLC protocol provided by the present invention supports dual redundant communication interfaces, and two RS485 interfaces are designed to back up each other, thereby ensuring that data is accurate and reliable during transmission, thereby increasing data reliability.

[0019] Compared with the traditional two-chip solution of SOC and FPGA, the fully programmable PSOC integrates SOC and FPGA programmable logic on one chip, which can greatly improve system performance, greatly increase IO bandwidth, and have a smaller overall chip area and lower power consumption. With the corresponding development software, an integrated hardware and software platform is realized, which is convenient for user development, shortens the development cycle, and saves production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The present invention provides a principle block diagram of a dual-channel RS485 to PCIE interface module based on the HDLC protocol. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0022] like Figure 1 As shown, an embodiment of the present invention discloses a dual-channel RS485 to PCIE interface module based on the HDLC protocol, and the interface module performs data exchange with a host through a PCIE interface.

[0023] The interface module exchanges data with the airborne equipment via a dual redundant RS485 interface.

[0024] The interface module comprises a main control chip, a DDR3 storage circuit, a FLASH storage circuit, a debugging serial port circuit, a clock circuit, an HDLC protocol controller, an RS485 interface circuit, a PCIE high-speed interface and a power supply circuit.

[0025] The main control chip PL end integrates an HDLC protocol controller, which can be divided into a data receiving module and a data sending module.

[0026] The memory unit DDR provides a large-capacity, high-speed data cache area, and provides data cache and management for the PS end to run the data processing program.

[0027] The serial port unit can complete communication data monitoring.

[0028] The clock circuit unit provides a working clock to the PS end and the PL end of the RS485 to PCIE interface module at the same time, and provides a high-speed clock to the PCIE high-speed interface unit at the same time.

[0029] The RS485 interface circuit unit completes the bus connection between the RS485 to PCIE interface module and the airborne device end, and realizes the interaction of data with the device end.

[0030] The PCIE high-speed interface unit enables the RS485 to PCIE interface module to connect to the host for data exchange.

[0031] The power supply circuit supplies power to various circuits of the RS485 to PCIE interface module.

[0032] In a dual-channel RS485 to PCIE interface module based on the HDLC protocol provided by an example of the present invention, when used specifically, airborne device bus data is received into the module through the RS485 bus interface, and the HDLC protocol controller completes the analysis of the HDLC data, and completes the caching and transmission of the data inside the module; the main chip integrates the CPU and FPGA programmable logic on a chip, the PL-side IP core realizes the link layer function, the PS-side realizes the HDLC data flow control, and the module integrates a 1GB data cache area for high-speed data transmission; FLASH serves as the system firmware memory, which is connected to the QSPI controller integrated inside the PS-side to store the system startup program and boot files.

[0033] The reset circuit is used to prevent abnormalities from occurring. When the power supply is abnormal, the power monitoring chip can output a reset signal and send it to the PL terminal of the main chip to control the processor to reset and prevent the program from running away.

[0034] The PCIE interface is connected to the GTXs high-speed data interface inside the main chip, and data interaction between the module and the host is realized through the PCIE interface.

[0035] The RS232 serial port is used as a debugging interface to output test data.

[0036] In this example, the interface module integrates two DDR3 memories, which are cascaded into a 32-bit / 1BG capacity storage space to provide a high-speed data cache area.

[0037] In this example, the external FLASH memory on the PS side is used for system image and boot program storage, with a storage capacity of 256Mbit and a maximum clock frequency of 100MHz.

[0038] In this example, the clock circuit unit provides clocks to both the PS and PL terminals at the same time. The clock frequency of the PS terminal is 33.3333 MHz, and the clock frequency of the PL terminal is 25 MHz.

[0039] In this example, the main control chip PL side implements the HDLC protocol controller function and the high-speed PCIEx1 function.

[0040] In this example, the interface module uses a dual-redundant 2-way full-duplex RS485 interface. The RS485 interface is designed using a standard transceiver chip external bus transformer circuit to communicate with external devices.

[0041] In this example, the GTX controller built into the main control chip is used for PCIE interface expansion, with a maximum line rate of up to 6.25 Gbps. The 1.0V, 1.2V, and 1.8V operating voltages required for the normal operation of the GTX high-speed transceiver are all provided by the power supply circuit, and the high-speed synchronous clock is provided by an external LVDS or LVPECL reference clock.

[0042] The dual-channel RS485 to PCIE interface module based on the HDLC protocol provided by the example of the present invention directly connects the data of the terminal device to the host through the interface module in the aviation airborne system to realize data reception. The data of the host can also be converted through the interface module and sent to each device terminal through the RS485 bus to complete the real-time data interaction between the airborne device and the host.

[0043] The interface module provided by the example of the present invention is based on the data transmission technology of the HDLC protocol, full-duplex communication, and can send data continuously without waiting for confirmation, with high data link transmission efficiency; all frames use CRC check, and the information frames are numbered sequentially to prevent leakage or duplication, with high transmission reliability; the transmission control function is separated from the processing function, with greater flexibility and more complete control functions. It is a high-reliability interface conversion module specially developed for airborne equipment.

[0044] The above only describes in detail the specific embodiments of the present invention, but is not limited to the specific embodiments described above. It should be pointed out that the equivalent modifications and substitutions made by technicians in this field to the invention without departing from the framework of the present application are also within the protection scope of the present invention. Therefore, the protection scope of the patent application of the present invention shall be based on the claims.

Claims

1. A dual-channel RS485 to PCIE interface module based on HDLC protocol, characterized in that: The dual-channel RS485 to PCIE interface module exchanges data with the host via the PCIE interface; The dual-channel RS485 to PCIE interface module includes a main control chip, a memory unit, a serial port unit, a clock circuit, an RS485 interface circuit, a PCIE high-speed interface and a power supply circuit; The main control chip integrates CPU and FPGA programmable logic on one chip, and completes data interaction with airborne equipment through RS485 interface circuit; The memory unit DDR provides a large-capacity high-speed data cache area, providing data caching and management for the PS end running data processing programs; The serial port unit can complete communication data monitoring; The clock circuit provides a synchronous clock to the interface module and provides a high-speed clock to the PCIE high-speed interface unit; The RS485 interface circuit completes the bus connection between the interface module and the airborne device end, and realizes the interaction of data with the device end; The PCIE high-speed interface unit enables the interface module to connect with the host for data exchange.

2. A dual-channel RS485 to PCIE interface module based on HDLC protocol according to claim 1, characterized in that: The main control chip integrates a processing system (PS) based on a feature-rich quad-core processor and programmable logic (PL) in a single chip. By using multiple interfaces and numerous other connected signals, the SOC and FPGA can be tightly or loosely coupled together; it contains on-chip memory, external memory interfaces and a rich set of I / O peripherals.

3. A dual-channel RS485 to PCIE interface module based on HDLC protocol according to claim 1, characterized in that: The main control chip includes a PS end and a PL end. The PS end is a quad-core Cortex-A7 with a main frequency of up to 667MHz. The PS end uses a DDR controller and a debug serial port for data processing and communication. The PL side implements the HDLC protocol controller, PCIEx1 function and completes data transmission and reception through the RS485 interface circuit.

4. A dual-channel RS485 to PCIE interface module based on HDLC protocol according to claim 1, characterized in that: The interface module bus interface rate reaches 100Mbps, supports redundancy management, and can realize automatic switching of the main and standby channels.

5. A dual-channel RS485 to PCIE interface module based on HDLC protocol according to claim 1, characterized in that: The RS485 interface circuit is transformer coupled and impedance matched with the data bus transmission line. The bus is a shielded twisted pair, adopts differential drive, and supports full-duplex communication mode.

6. A dual-channel RS485 to PCIE interface module based on HDLC protocol according to claim 1, characterized in that: The memory unit uses two memories connected in parallel to form a memory space with a width of 32 bits and a total capacity of 1GB. The memory rate is 800MT / s and the clock is 400MHz.

7. A dual-channel RS485 to PCIE interface module based on HDLC protocol according to claim 1, characterized in that: The PL end of the interface module realizes the HDLC protocol controller function and is divided into two redundant channels, A and B, both of which are composed of a receiving unit and a sending unit. The two channels can work in parallel and can complete full-duplex communication of high-speed data.

8. The dual-channel RS485 to PCIE interface module based on HDLC protocol according to claim 1, characterized in that: The power supply circuit supplies power to each functional unit on the module. The power supply is input from the outside through the PCIE interface and is secondary stepped down by the power supply circuit on the module to meet the voltage and current requirements of each unit.

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