PCIe retimer path switching method and system

Abstract

The invention relates to the field of integrated circuit design, and provides a PCIe (Peripheral Component Interconnect Express) retimer access switching method and system, a retimer comprises a general access and a low-delay access, and is arranged between a root complex and an endpoint of a PCIe system, and the method comprises the following steps: caching a state locking code stream transmitted between the root complex and the endpoint in advance, the state locking code stream is used for keeping the current states of a root complex and an end point; detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; in the data stream firstly received by the retimer, starting from an electrical idle exit ordered set code stream position, replacing a subsequent ordered set code stream with a state locking code stream; and completing path switching before the corresponding electrical idle exit ordered set code stream position is replaced by the code stream. According to the method and the device, when the PCIe retimer is switched from a general path to a low-delay path, the PCIe system does not enter a link recovery state again due to path switching.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to a PCIe (Peripheral Component Interconnect express, a high-speed serial computer expansion bus standard) retimer path switching method and system. Background Art

[0002] In a system where PCIe RC (Root Complex) and PCIe EP (Endpoint) are interconnected, when the PCIe rate is greater than a certain rate, the signal is severely attenuated through the PCB routing. It is necessary to add a PCIe retimer between the RC and EP chips to solve the signal attenuation problem.

[0003] Although adding a PCIe retimer to the PCIe system solves the signal attenuation problem, the addition of the PCIe retimer will increase the system delay. Therefore, it is necessary to build a low-latency path in the PCIe retimer. There are two paths in the PCIe retimer: general and low-latency. See the schematic diagram. Figure 1 Among them, the general channel will perform encoding and decoding, scrambling and descrambling, SKP ordered set addition and subtraction, etc., and the delay is relatively large; the low-latency channel does not need to perform encoding and decoding, scrambling and descrambling, SKP ordered set addition and subtraction, etc. The data of this channel is passed directly, and the delay is close to 0.

[0004] When the PCIe retimer switches from the general channel to the low-latency channel, since the low-latency channel is not scrambled, when the RC and EP descramble the received code stream, there will be a period of descrambling errors and the code stream cannot be received correctly. Then, after receiving the EIEOS (Electricalldle Exit Ordered Set) code stream, the descrambling is restored. Since the time when the RC and EP devices receive EIEOS is uncertain, the recovery time of the RC and EP devices is uncertain. The one that recovers first will receive the code stream correctly first. After receiving the correct code stream, the PCIe state machine may jump to the next state and send a new type of code stream in the new state. When the latter recovers and receives the code stream, it is no longer possible to receive the code stream of the previous state of the other party, resulting in the PCIe state machine being unable to jump correctly and a state machine timeout. As a result, the PCIe state machine of the RC and EP devices returns to the link recovery state (recovery) and cannot jump to the next state as normal.

[0005] Switch from the general channel to the low-latency channel, and assume that RC receives the EIEOS code stream first. The PCIe protocol stipulates that an EIEOS code stream needs to be sent every 32 code streams to reset the descrambler of the other chip. Under the general channel, RC and EP are both in the first state A, and send the first state ordered set code stream OSA to each other, as shown in Figure 2 (a). After RC and EP receive OSA, they jump to the second state B normally, as shown in Figure 2 (b). When the system turns on the low-latency function, the PCIe retimer will switch from the general channel to the low-latency channel when RC and EP are in the first state A, and send the code stream OSA to each other through the low-latency channel, as shown in Figure 3 (a). Under normal circumstances, the state jump should be as shown in Figure 3 (b). Since the low-latency channel does not have the descrambling function, RC and EP will have descrambling errors for a period of time after the channel is switched, and cannot receive the code stream correctly. After receiving the EIEOS code stream, the descrambler is reset, and then the code stream is received normally. It is assumed that RC receives the EIEOS code stream first. Figure 4 As shown, assuming that RC receives the EIEOS code stream first, RC resets the descrambler first, RC first receives the first state ordered set code stream OSA normally, and then RC jumps to the second state B. In the second state B, RC sends the second state ordered set code stream OSB. Since EP is still in the first state A, it has been waiting to receive the first state ordered set code stream OSA, but RC has started to send the second state ordered set code stream OSB, so EP has not been able to receive OSA, resulting in EP timing out in the second state B, and the state jumps to the link recovery state (recovery), and cannot jump normally to the second state B. Summary of the invention

[0006] In view of the problems existing in the prior art, a PCIe retimer path switching method and system are provided, which can effectively solve the problem that switching to a low-latency path causes the system to enter a link recovery state (recovery).

[0007] A first aspect of the present invention provides a PCIe retimer path switching method, wherein the retimer includes a general path and a low-latency path, and is arranged between a root complex (RC) and an endpoint (EP) of a PCIe system. The path switching method includes: Pre-caching a state lock code stream transmitted between the root complex and the endpoint, wherein the state lock code stream is used to maintain the current state of the root complex and the endpoint; Detecting gaps in the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; In the data stream first received by the retimer, starting from the position of the electrical idle exit ordered set code stream, the subsequent ordered set code stream is replaced with the state lock code stream, wherein the ordered set code stream is used for the state jump of the root complex and the endpoint; wherein the length of the replaced code stream is the interval length of the detected electrical idle exit ordered set code stream; The path switching is completed before the electrical idle exit ordered set code stream position corresponding to the code stream replacement occurs.

[0008] In one embodiment of the present invention, the step of detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint comprises: Detecting the time when the retimer receives the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; Determine the shortest interval of the electrical idle exit ordered set code streams sent by both ends according to the receiving time.

[0009] In one embodiment of the present invention, the pre-caching of the state-locked code stream transmitted between the root complex and the endpoint includes: Starting from the electrical idle exit ordered set code stream position, the subsequent 16 consecutive state lock code streams are cached.

[0010] In one embodiment of the present invention, when caching state-locked code streams, if 16 consecutive state-locked code streams include a skip ordered set code stream, the cache is reset and subsequent state-locked code streams are cached starting from the next electrical idle exit ordered set code stream.

[0011] In one embodiment of the present invention, completing the path switching before the electrical idle exit ordered set code stream position corresponding to the code stream replacement occurs specifically includes: The switching from the general path to the low-latency path is completed at the previous code stream of the electrical idle exit ordered set code stream corresponding to the code stream replacement.

[0012] In one embodiment of the present invention, the method further includes detecting the synchronization header position of each code stream in the data stream, and completing the replacement of the corresponding code stream according to the synchronization header position.

[0013] A second aspect of the present invention provides a PCIe retimer path switching system, wherein the retimer is arranged between a PCIe root complex and an endpoint, the retimer includes a general path and a low-latency path, the path switching system includes a low-latency switching control module and a switching switch, and the low-latency switching control module: A ranging unit for detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; A code stream caching unit, used for caching a state-locked code stream transmitted between the root complex and the endpoint, wherein the state-locked code stream is used for maintaining the current state of the root complex and the endpoint; A synchronization head position detection unit, used for detecting the synchronization head position of each code stream in the data stream; A code stream replacement unit is used to replace the subsequent ordered set code streams with the state lock code streams starting from the electrical idle exit ordered set code stream in the data stream first received by the retimer according to the synchronization header position, wherein the ordered set code stream is used for the state jump of the root complex and the endpoint; wherein the length of the replaced code stream is the interval length of the detected electrical idle exit ordered set code stream; A switching switch is used to control the path switching according to the electrical idle exit ordered set code stream position where code stream replacement occurs.

[0014] In one embodiment of the present invention, in the code stream cache unit, starting from the electrical idle exit ordered set code stream position, the subsequent 16 consecutive state locked code streams are cached. If the consecutive 16 state locked code streams include a skipped ordered set code stream, the cache is reset and the subsequent state locked code streams are cached starting from the next electrical idle exit ordered set code stream.

[0015] In one embodiment of the present invention, a path switching state machine unit is further included, which is used to control the units to work in sequence and finally control the switch to complete the switching from the general path to the low-latency path.

[0016] In one embodiment of the present invention, the switching switch is controlled by a path switching state machine unit to complete the switching from the general path to the low-latency path at the previous code stream of the electrical idle exit ordered set code stream corresponding to the code stream replacement.

[0017] Compared with the prior art, the beneficial effect of adopting the above technical solution is that the present invention can ensure that when the PCIe retimer switches from a general path to a low-latency path, the PCIe system will not re-enter the recovery state due to the path switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the normal path and low latency path of the PCIe retimer.

[0019] FIG2( a ) is a schematic diagram of code stream reception and transmission when RC and EP are in a first state A under a general path, and FIG2( b ) is a schematic diagram of code stream reception and transmission when RC and EP are in a second state B under a general path.

[0020] FIG3 (a) is a schematic diagram of code stream reception and transmission when RC and EP are in the first state A under a low-latency path, and FIG3 (b) is a schematic diagram of code stream reception and transmission when RC and EP normally jump to the second state B under a low-latency path.

[0021] Figure 4 The figure is a schematic diagram of the code stream reception and transmission in an abnormal state under a low-latency channel.

[0022] Figure 5 Schematic diagram of traditional PCIe retimer channel switching.

[0023] Figure 6 This is a flow chart of the PCIe retimer path switching method proposed in an embodiment of the present application.

[0024] Figure 7 The figure is a schematic diagram of the synchronization header position of the code stream received by the RC side and the EP side.

[0025] Figure 8 This is a schematic diagram of code stream replacement.

[0026] Fig. 9 Schematic diagram of the PCIe retimer path switching system proposed in an embodiment of the present application. DETAILED DESCRIPTION

[0027] To make the purpose, technical scheme and advantages of the present invention clearer, the technical scheme in the embodiment of the present application will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application. In the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other arbitrarily. In addition, although the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in an order different from that here.

[0028] The terms "first" and "second" in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the term "comprising" and any variation thereof are intended to cover non-exclusive protection. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0029] Figure 5The figure is a schematic diagram of the traditional PCIe retimer path switching. In this scheme, the switching control circuit switches the data stream from the general path to the low-latency path when the link negotiation reaches a certain stage, and does not perform bit stream control based on the bit stream state, resulting in descrambling errors in the RC (Root Complex) and EP (Endpoint). Due to the uncertainty of the descrambling recovery time, the state jump timeout occurs in the post-recovery state, causing the system to re-enter the link recovery state (recovery). Based on this, in order to address the problem of system recovery caused by the current PCIe retimer switching to a low-latency path, an embodiment of the present invention proposes a PCIe retimer path switching method. The retimer includes a general path and a low-latency path, which are arranged between the PCIe root complex and the endpoint, and are used to control the path switching to ensure that the PCIe root complex and the endpoint can still perform correct state transitions after switching to the low-latency path. The specific scheme is as follows: S100: pre-cache the state-locked code stream transmitted between the root complex and the endpoint.

[0030] In this embodiment, the following description will be made by taking the example that both RC and EP can successfully jump from the first state A to the second state B. Specifically, whether RC or EP is working normally in the descrambler, when receiving the ordered set code stream (Ordered Sets, hereinafter referred to as OS) OSA sent by the other end in the first state A, it will jump to the second state B, and then send the ordered set OSB at a subsequent time. Before RC or EP enters the first state A, RC and EP both send a state-locked code stream. After receiving the state-locked code stream under a certain length, RC and EP will jump to the first state A. Because RC and EP in the first state A will send OSA, in some scenarios, it is necessary to let RC and EP hover in the first state A. The retimer between RC and EP can replace the OSA sent by both parties with the state-locked code stream. Therefore, RC and EP still receive the state-locked code stream and will remain in the first state A. This operation usually occurs in a general channel. The specific replacement and control are not the focus of this application and will not be described in detail.

[0031] It should be noted that, in this embodiment, only the first state is maintained as an example for explanation, and in fact, other states may be maintained, which essentially means maintaining the states of RC and EP before the jump. In this embodiment, the state lock code stream transmitted between the root complex and the endpoint may be pre-cached, and the state lock code stream may be used to maintain the current state of the root complex and the endpoint so that the state jump does not occur.

[0032] In the subsequent process, this application mainly uses the interval of the Electrical Idle Exit Ordered Set (hereinafter referred to as EIEOS) in the data stream sent by EP and RC to replace the OS stream to be sent with the state lock stream to delay the state jump time of one end. According to PCIe rules, the EIEOS stream in the code stream appears once every 32 code streams, and the EIEOS interval received by RC and EP should be between 0 and 16. Therefore, when caching the state lock code stream, it is sufficient to cache the subsequent 16 consecutive state lock code streams starting from the EIEOS code stream position. It should be noted that if the 16 consecutive state lock code streams contain a skip ordered set (SKP) code stream, the cache needs to be reset and the subsequent state lock code streams need to be cached again from the next EIEOS code stream.

[0033] S200: Detect the interval of the EIEOS code stream in the data stream sent by the root complex and the endpoint.

[0034] The EIEOS code stream is used to restore the PCIe root complex and endpoint descrambling functions. Because the two ends receive the EIEOS code stream at different times, the two ends will restore the descrambling function at different times, which will cause the later restored descrambling section to fail to complete the normal state jump. In order to achieve the correct state jump of the two ends, it is necessary to first determine the interval between the two ends restoring the descrambling function, and then use the obtained interval to adjust the code stream. In this embodiment, the time when the retimer receives the EISOS code stream in the data stream sent by the root complex and the endpoint is first detected, and the shortest interval for receiving the EIEOS code stream sent by the two ends is determined according to the receiving time. This interval determines the length of the code stream to be replaced later.

[0035] S300 , in the data stream first received by the retimer, starting from the EIEOS code stream position, the subsequent OS code stream is replaced with the state lock code stream.

[0036] After the channel switching, once one end receives the EIEOS code stream, the normal descrambling function will be restored. At this time, the end that has restored normal descrambling will jump to the state after receiving the OS code stream, and send the code stream after the state jump (for example, the end in the first state A will jump to the second state B after receiving the OSA code stream, and start sending the OSB code stream). The end that receives the EIEOS code stream cannot jump normally because it has not received the OSA code stream in the first state. Therefore, in order to ensure that both ends can perform normal state jumps, the embodiment of the present application delays the state jump of the end that first receives the EIEOS code stream by replacing the code stream, so that both ends complete the state jump together. Specifically, the number of code streams to be replaced is determined according to the EIEOS code stream interval determined by S200, that is, if the EIEOS code stream interval is n, the retimer replaces the last n OS code streams with the first n state-locked code streams cached in S100 starting from the EIEOS code stream position in the first received data stream. Through code stream replacement, after the end that first receives the EIEOS code stream restores the descrambling function, it will continue to receive n state-locked code streams, and the state will not jump at this time. The n+1th code stream is a normal OS code stream, and a normal state jump occurs when it is received. Correspondingly, when the end receives the n+1 code stream, the other end receives the EIEOS code stream and restores the descrambling function at the same time, and the state jumps together. That is, by delaying the state jump time of the end that first receives the EIEOS code stream, both ends can jump to the state at the same time.

[0037] When switching channels, Figure 7 As shown in the figure, since the position of the synchronization header in the code stream received by the RC side and the EP side is uncertain, before replacing the code stream, it is necessary to first detect the synchronization header position of each code stream in the data stream according to the PCIe synchronization header rule, and complete the replacement of the corresponding code stream according to the synchronization header position. Figure 8 As shown, during replacement, only the code stream is replaced, and the synchronization header is not replaced.

[0038] S400, completing the channel switching before the EIEOS code stream position corresponding to the code stream replacement occurs.

[0039] Further, in the embodiment of the present application, the timing of the channel switching is related to the position of the code stream replacement, that is, it is necessary to ensure that after the channel switching, the OS code stream after the first received EIEOS code stream is replaced, so that the end that receives the EIEOS code stream first will not jump to the state in advance. Specifically, in this embodiment, it is necessary to complete the switching from the general channel to the low-latency channel at the previous code stream of the electrical idle exit ordered set code stream corresponding to the code stream replacement. For example, the data stream is: 2bit synchronization header + EIEOS1 +... + 2bit synchronization header + 128bit code stream 1 + 2bit synchronization header + 128bit code stream 2 + 2bit synchronization header + EIEOS2 + synchronization header + 128bit code stream 3 +..., whether it is SKP code stream, EIEOS code stream, or OSA code stream, it is 128bit in length. The 128bit code stream is directly used in the aforementioned data stream instead. Assuming that the code stream replacement occurs after EIEOS2, the channel switching needs to be performed at 128bit code stream 2. This can effectively ensure that after a path switch occurs, both ends can quickly restore the descrambling function and perform the correct state jump.

[0040] It should be noted that RC to EP and EP to RC are two-way data stream transmission. In actual applications, the data stream on the side that receives the EIEOS code stream first only needs to be replaced, and the other side does not need to be replaced. Furthermore, at the time of path switching, the data stream that receives the EIEOS code stream first performs path switching, and the other data stream can be switched at the same time, or after the shortest interval time of the EIEOS code stream in the data stream sent by the root complex and the endpoint.

[0041] For the RC and EP in the first state A, through the path switching method of the present application, one end (assuming it is the EP end) receives the EIEOS code stream first. After the EP end restores the descrambling function, it will continue to receive the state-locked code stream and remain in the first state A. After an interval n, it continues to receive OSA for normal state jump. At this time, the RC end also receives the EIEOS code stream and completes the state jump according to the subsequent OSA, thereby realizing simultaneous state jump of the RC and EP ends.

[0042] In the path switching method proposed by the present invention, the state lock code stream sent by both ends is pre-cached to perform code stream replacement, rather than using the code stream generating unit to generate the code stream, which can effectively avoid the compatibility problem of the code stream generated by the code stream and the code stream sent by the RC and EP being inconsistent. By replacing the code stream, the time for both ends to receive the OS code stream is shortened, ensuring that the RC and EP can jump to the next state at the same time.

[0043] Please refer to Fig. 9The embodiment of the present invention also proposes a PCIe retimer path switching system, wherein the retimer is arranged between the PCIe root complex and the endpoint, the retimer includes a general path and a low-latency path, and the path switching system includes a low-latency switching control module and a switching switch. The low-latency switching control module mainly includes a ranging unit, a bit stream buffer unit, a synchronization head position detection unit, and a bit stream replacement unit.

[0044] Specifically, the ranging unit is mainly used to detect the interval of the EIEOS code stream in the data stream sent by the root complex and the endpoint. The EIEOS code stream in the data stream appears once every 32 code streams. The interval of the EIEOS code stream received by RC and EP is between 0-16, and this interval is used for the subsequent code stream replacement number.

[0045] The code stream cache unit is used to cache the state-locked code stream transmitted between the root complex and the endpoint, and the state-locked code stream is used to maintain the current state of the root complex and the endpoint. Since the maximum interval between the EIEOS code streams at both ends is 16 code streams, the embodiment of the present application caches 16 consecutive state-locked code streams after the EIEOS code stream through the code stream cache unit to ensure that the EIEOS interval can be fully covered. It should be noted that if there is an SKP code stream in the cached state-locked code stream, the cache is reset and the state-locked code stream after the next EIEOS code stream is cached.

[0046] The synchronization header position detection unit is mainly used to detect the synchronization header position of each code stream in the data stream according to the PCIe synchronization header rule. The synchronization header position can be used to determine the position of code stream replacement.

[0047] The code stream replacement unit is mainly used to replace the subsequent ordered set code streams with the state lock code streams starting from the electrical idle exit ordered set code stream in the data stream first received by the retimer according to the synchronization header position. The ordered set code stream is used for the state jump of the root complex and the endpoint; wherein the length of the replaced code stream is the interval length of the detected electrical idle exit ordered set code stream.

[0048] The switching switch is mainly used to control the path switching according to the EIEOS code stream position where the code stream replacement occurs.

[0049] In one embodiment, the PCIe retimer path switching system further includes a path switching state machine unit, which is used to control each unit to work in sequence, and finally control the switch to complete the switch from the general path to the low-latency path. Accordingly, the switch is controlled by the path switching state machine unit to complete the switch from the general path to the low-latency path at the previous bitstream of the electrical idle exit ordered set bitstream corresponding to the bitstream replacement.

[0050] Below Figure 8As an example, the working process of the channel switching system of this embodiment is further explained. RC sends data to EP, and EP also sends data to RC. Assuming that the retimer first receives the EIEOS in the data stream sent by RC to EP, if the channel is switched directly, it means that the EP end will restore the descrambling function first, and then jump first. At this time, in order to avoid the EP end jumping first, it is necessary to replace the code stream through the retimer, that is, replace the n OS code streams after the EIEOS code stream in the data stream with the state lock code stream, and n is the EIEOS code stream interval detected at both ends. The data stream on the other side is not replaced.

[0051] As for the switching timing of the switch for the two data streams, due to the code stream replacement performed by the data stream sent by the RC to the EP, it is necessary to switch at the code stream before the replaced EIEOS code stream.

[0052] As for the switch from EP to RC, in order to avoid compatibility issues caused by receiving the OS code stream first, it is necessary to delay the switch control on this side, and the delay time is the shortest interval time of the EIEOS code stream in the data stream sent by the root complex and the endpoint. That is, after completing the switch from RC to EP, wait for the shortest interval time before completing the switch from EP to RC. In this way, RC can directly restore the descrambling function after the channel switching, which is more suitable for actual application scenarios.

[0053] The PCIe retimer path switching system proposed in the present invention can ensure that when the PCIe retimer switches from a general path to a low-latency path, the PCIe system will not re-enter the recovery state due to the path switching.

[0054] For those skilled in the art, the specific meanings of the above terms in the present invention can be understood in specific situations; the drawings in the embodiments are used to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0055] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A PCIe retimer path switching method, characterized in that: The retimer includes a general path and a low-latency path, which are arranged between the root complex and the endpoint of the PCIe system. The path switching method includes: Pre-caching a state lock code stream transmitted between the root complex and the endpoint, wherein the state lock code stream is used to maintain the current state of the root complex and the endpoint; Detecting gaps in the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; In the data stream first received by the retimer, starting from the position of the electrical idle exit ordered set code stream, the subsequent ordered set code stream is replaced with the state lock code stream, wherein the ordered set code stream is used for the state jump of the root complex and the endpoint; wherein the length of the replaced code stream is the interval length of the detected electrical idle exit ordered set code stream; The path switching is completed before the electrical idle exit ordered set code stream position corresponding to the code stream replacement occurs.

2. The PCIe retimer path switching method according to claim 1, characterized in that: The detecting of the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint comprises: Detecting the time when the retimer receives the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; Determine the shortest interval of the electrical idle exit ordered set code streams sent by both ends according to the receiving time.

3. The PCIe retimer path switching method according to claim 1 or 2, characterized in that: The state locking code stream transmitted between the pre-cached root complex and the endpoint includes: Starting from the electrical idle exit ordered set code stream position, the subsequent 16 consecutive state lock code streams are cached.

4. The PCIe retimer path switching method according to claim 3, characterized in that: When caching the state-locked code stream, if the 16 consecutive state-locked code streams include a skipped ordered set code stream, the cache is reset, and subsequent state-locked code streams are cached starting from the next electrical idle exit ordered set code stream.

5. The PCIe retimer path switching method according to claim 1, characterized in that: The process of completing the path switching before the electrical idle exit ordered set code stream position corresponding to the code stream replacement occurs specifically includes: The switching from the general path to the low-latency path is completed at the previous code stream of the electrical idle exit ordered set code stream corresponding to the code stream replacement.

6. The PCIe retimer path switching method according to claim 1, characterized in that: The method also includes detecting the synchronization header position of each code stream in the data stream and completing the replacement of the corresponding code stream according to the synchronization header position.

7. A PCIe retimer path switching system, characterized in that: The retimer is arranged between the PCIe root complex and the endpoint, the retimer includes a general path and a low-latency path, the path switching system includes a low-latency switching control module and a switching switch, and the low-latency switching control module includes: A ranging unit for detecting the interval of the electrical idle exit ordered set code stream in the data stream sent by the root complex and the endpoint; A code stream caching unit, used for caching a state-locked code stream transmitted between the root complex and the endpoint, wherein the state-locked code stream is used for maintaining the current state of the root complex and the endpoint; A synchronization head position detection unit, used for detecting the synchronization head position of each code stream in the data stream; A code stream replacement unit is used to replace the subsequent ordered set code streams with the state lock code streams starting from the electrical idle exit ordered set code stream in the data stream first received by the retimer according to the synchronization header position, wherein the ordered set code stream is used for the state jump of the root complex and the endpoint; wherein the length of the replaced code stream is the interval length of the detected electrical idle exit ordered set code stream; A switching switch is used to control the path switching according to the electrical idle exit ordered set code stream position where code stream replacement occurs.

8. The PCIe retimer path switching system according to claim 7, wherein: In the code stream cache unit, starting from the electrical idle exit ordered set code stream position, the subsequent 16 continuous state locked code streams are cached. If the 16 continuous state locked code streams include a skipped ordered set code stream, the cache is reset, and the subsequent state locked code streams are cached starting from the next electrical idle exit ordered set code stream.

9. The PCIe retimer path switching system according to claim 7, wherein: It also includes a path switching state machine unit, which is used to control the units to work in sequence and finally control the switching switch to complete the switching from the general path to the low-latency path.

10. The PCIe retimer path switching system according to claim 7, wherein: The switch is controlled by the path switching state machine unit to complete the switching from the general path to the low-latency path at the previous code stream of the electrical idle exit ordered set code stream corresponding to the code stream replacement.

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