A multi-core system chip inter-core communication method and system

Abstract

The present invention relates to a method and system for inter-core communication in a multi-core system chip. The method comprises: first dividing an inter-core communication module into two modules, A and B, each with a bus interface; instantiating the inter-core communication module into two sub-modules, A and B; using a group control register to group and manage hardware channels within the inter-core communication module; and using group logic to set the hardware channels and access objects within each group. The present invention can significantly reduce the number of inter-core communication modules and reduce the complexity of system integration.

Description

Technical Field

[0001] The present invention belongs to the technical field of intelligent chips, and in particular relates to a method and system for inter-core communication of a multi-core system chip. Background Art

[0002] As integrated circuit technology advances to the deep submicron stage, processor architecture research is moving toward multi-core and many-core architectures. Whether for improving processor performance or considering energy consumption per unit of computing performance, multi-core and many-core architectures are currently hot research topics. On-chip communication design has also seen a wide variety of organizational hierarchies. For example, in multi-core systems based on shared caches, some use a crossbar bus to connect the local caches of each processing core with the shared cache, while others use an on-chip network. Furthermore, in multi-core systems based on a shared bus, bus architectures can be categorized as simple single buses, multi-layer buses, ring buses, crossbar buses, and on-chip networks. While these architectures broaden on-chip communication design options, they also increase the freedom and complexity of on-chip communication design. One inter-core communication approach involves an inter-core communication module between two cores, with two bus interfaces connected to the same or different buses. The inter-core communication module consists of two multiplexers (MUXs) and multiple hardware channels. The hardware channels receive write data from other cores, and the MUXs select which hardware channel to access. A single core can only access one hardware channel at a time. This approach enables communication between two cores, but as the number of communicating cores increases, the number of inter-core communication modules must be increased accordingly. For example, if there is another core 2 on the system bus, communication between core 0 and core 1 is handled by inter-core communication module 0, communication between core 2 and core 1 is handled by inter-core communication module 1, and communication between core 0 and core 2 is handled by inter-core communication module 2. If a multi-core system has N cores, a total of N*(N-1) / 2 inter-core communication modules are required, which is too complex for system integration.

[0003] Furthermore, with the decline in integrated circuit prices, integrated circuit design has begun to shift to the application layer. Currently, applications such as communications, machine vision, assisted driving, medical / bioimaging, avionics, big data analytics, and the Internet of Things all require high-performance digital signal processing, intensive data computing capabilities, and powerful graphics and image processing and display capabilities. Furthermore, these applications require flexible and adaptable systems and algorithms. After product manufacturing, the chips within the system must be able to modify, optimize, and reconfigure to meet both hardware overhead and application scenario requirements. Furthermore, the diversity of application scenarios also presents security concerns. Malicious attackers could potentially inject unauthorized software and code into bus devices through the debug port of the application CPU core, compromising bus device security.

[0004] As the number of cores continues to increase, the communication architectures between cores vary widely, and application scenarios become increasingly complex, the challenge of meeting inter-core communication needs without increasing hardware overhead or minimizing it remains a technical challenge. In reality, inter-core communication requirements are largely dependent on the system and application scenarios. Fixed communication mechanisms are unlikely to meet the inter-core communication requirements of multi-core systems, nor can they optimize communication issues.

[0005] Based on the above problems, the present invention starts from the system scenarios and application scenarios, allocates and manages inter-core communication control resources according to the different needs of the system scenarios and application scenarios, discovers the scenario changes and characteristics under different scenarios to perform specific communication resource configuration; combines the underlying hardware resource configuration and scenarios to reduce the number of inter-core communication modules, reduce the complexity of system integration, and thus reduce chip power consumption and area. Summary of the Invention

[0006] In order to solve the above problems in the prior art, the present invention proposes a multi-core system chip inter-core communication method and system, the system comprising:

[0007] A system bus, two or more cores, and an inter-core communication module; the inter-core communication module is used to control communication between the two or more cores; the inter-core communication module is divided into two modules, A and B, each of which accesses the bus through a set of bus interfaces, each set of bus interfaces is used to connect to one or more cores; each set of bus interfaces belongs to the same or different buses; the one or more cores communicate data on the chip through the bus interfaces; wherein: when the two sets of bus interfaces belong to different buses, cross-bus communication is performed between the cores accessing different sets of bus interfaces; when the two sets of bus interfaces belong to the same bus, cross-core communication based on the same bus can be performed between the cores;

[0008] Each of the A and B modules includes a set of receiving and transmitting terminals, as well as a multiplexer (MUX). The MUX is connected to the bus interface to communicate with the bus. The receiving terminal in module A includes one or more channels, which are shared with the transmitting terminal corresponding to module B. The receiving terminal in module A is connected to the MUX of module A to send data to the bus, and the transmitting terminal corresponding to module B is connected to the MUX of module B to receive data from the bus. The configuration of the other set of receiving and transmitting terminals is similar.

[0009] The group control module is used to divide the channels in the AB module into one or more groups based on the communication relationship between the receiving core and the sending core, and perform group configuration, channel enable configuration and intra-group channel configuration to identify the correspondence between the groups and the cores based on the communication relationship, so that the sending core writes the sending data into the channel corresponding to the group after the channel is enabled, and generates a core interrupt for the receiving core with which the communication relationship occurs, so that the receiving core reads the data through the corresponding channel after the interrupt occurs.

[0010] Furthermore, when the corresponding relationship between the sending core and the receiving core does not conform to the configuration information in the packet control module, an error is returned to the sending core to avoid possible communication anomalies.

[0011] Furthermore, the MUX is implemented using configurable logic.

[0012] Furthermore, the multi-core system chip is provided with two or more cores.

[0013] Furthermore, the system also includes a scenario configuration module, which is used to determine group configuration information, channel enable configuration information and intra-group channel configuration information based on the application scenario and / or system scenario, and send the configuration information to the group control module; the group control module performs configuration or reconfiguration when the configuration conditions are met.

[0014] Furthermore, the group control module includes a configuration module and a configuration lock module; the configuration module is used to perform group configuration, channel enable configuration, and intra-group channel configuration based on configuration information; the group configuration is used to group cores and indicate the cores included in each group; the channel enable configuration is used to indicate the channels included in each group; the intra-group channel configuration is used to indicate the correspondence between the channels in the group and the accessible cores; the configuration module uses the configuration register to store the above configuration information and perform configuration;

[0015] The group control module performs core interruption based on the communication request and channel identification; specifically: when module A performs a write operation, it writes to the corresponding channel in response to the write operation; the group control module and module B generate an interrupt for the receiving core for the corresponding group containing the channel, and send the interrupt to the receiving core through MUX; after the receiving core responds to the interrupt, it reads data from the group and its channel corresponding to module B and the receiving core; similarly, when the core to which module B belongs wants to write data, it writes the data to the channel corresponding to the group in response to the write operation request of the core to which module B belongs, and the group control module and module A generate an interrupt for the receiving core for the corresponding group in the channel, and send the interrupt to the receiving core through MUX; after the receiving core responds to the interrupt, it obtains data from the channel of module A.

[0016] Furthermore, the configuration condition is when the chip is initialized, the application scenario and / or the system scenario is initialized or changes.

[0017] A multi-core system chip inter-core communication control digital logic, wherein the multi-core system chip inter-core communication control digital logic is used to implement the multi-core system chip inter-core communication system.

[0018] A multi-core system chip inter-core communication control chip is used to implement the multi-core system chip inter-core communication system.

[0019] A multi-core system chip inter-core communication control circuit is characterized in that the multi-core system chip inter-core communication control circuit is used to implement the above-mentioned multi-core system chip inter-core communication system.

[0020] The beneficial effects of the present invention include:

[0021] (1) Starting from the system scenario and application scenario, the inter-core communication control resources are allocated and managed according to the different requirements of the system scenario and application scenario, and the specific communication resource configuration is carried out by discovering the scenario changes and the characteristics of different scenarios; it can be compatible with system scenario adaptation and application scenario adaptation, and can combine the underlying hardware resource configuration and scenario to reduce the number of inter-core communication modules, reduce the complexity of system integration, and thus reduce chip power consumption and area.

[0022] (2) It can simultaneously serve cross-bus communication and cross-core communication based on the same bus. For both communication modes, it can significantly reduce the number of inter-core communication modules, thereby reducing the complexity of system integration. By managing the read and write access of the inter-core communication modules through group control, the inter-core communication modules can be prevented from being misoperated at the read and write operation level, thereby improving the security of inter-core communication in multi-core system chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application, but do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 This is a schematic diagram of the cross-bus communication control system of the multi-core system chip provided by the present invention.

[0025] Figure 2 This is a schematic diagram of a cross-core communication control system based on the same bus of a multi-core system chip provided by the present invention.

[0026] Figure 3 This is a control flow logic diagram of the multi-core system chip inter-core communication method provided by the present invention. DETAILED DESCRIPTION

[0027] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The exemplary embodiments and descriptions are only used to explain the present invention but are not intended to limit the present invention.

[0028] The present invention proposes a multi-core system chip inter-core communication system, as shown in the attached Figure 1 As shown, the system includes: a system bus, two or more cores and an inter-core communication module; the inter-core communication module is used to control communication between the two or more cores; the inter-core communication module is divided into two modules AB, and the two modules AB respectively access the bus through a set of bus interfaces, and each set of bus interfaces is used to connect one or more cores; each set of bus interfaces belongs to the same or different buses; the one or more cores communicate data on the chip through the bus interface; wherein: when the two sets of bus interfaces belong to different buses, cross-bus communication is performed between the cores accessing different sets of bus interfaces, and when the two sets of bus interfaces belong to the same bus, cross-core communication based on the same bus can be performed between the cores;

[0029] The AB modules each include a set of receiving ends and transmitting ends, and a MUX; the MUX is connected to the bus interface to communicate with the bus; the receiving end in module A includes one or more channels, which are shared by the transmitting end corresponding to module B, the receiving end in module A is connected to the A module MUX to send data to the bus, and the transmitting end corresponding to module B is connected to the B module MUX to receive data from the bus; the settings of the other set of receiving ends and transmitting ends are similar, the receiving end in module B includes one or more channels, which are shared by the transmitting end corresponding to module A, the receiving end in module B is connected to the B module MUX to send data to the bus, and the transmitting end corresponding to module A is connected to the A module MUX to receive data from the bus; that is, the channel allocated to the group is shared by the transmitting end and the receiving end group, and the channel allocated to the core is shared by the sending core and the receiving core based on the communication relationship;

[0030] The group control module is configured to divide the channels in the AB module into one or more groups based on the communication relationship between the receiving core and the sending core, and perform group configuration, channel enable configuration, and intra-group channel configuration to identify the correspondence between the groups and the cores based on the communication relationship, so that the sending core writes the transmission data into the channel corresponding to the group after the channel is enabled, and generates a core interrupt for the receiving core in the communication relationship, so that the receiving core reads the data through the corresponding channel after the interrupt occurs; when the corresponding relationship between the sending core and the receiving core does not match the configuration information in the group control module, an error is returned to the sending core to avoid possible communication anomalies;

[0031] The group control module includes a configuration module and a configuration lock module; the configuration module is used to perform group configuration, channel enable configuration and intra-group channel configuration based on configuration information; the group configuration is used to group the cores and indicate the cores included in each group; the channel enable configuration is used to indicate the channels included in each group; the intra-group channel configuration is used to indicate the correspondence between the channels in the group and the accessible cores; the configuration module uses the configuration register to store the above configuration information and perform configuration;

[0032] Further: during configuration, the configuration module configures the MUX of module A and the MUX of module B based on the intra-group channel configuration information to establish communication links between the channels and cores in module A and module B, respectively;

[0033] Preferably, the MUX is implemented using configurable logic, such as FPGA;

[0034] The configuration lock module is used to lock the configuration information stored in the configuration register after the configuration is completed to prevent subsequent accidental modification;

[0035] As attached Figure 1 As shown, there are four cores on the chip, cores 0 to 3; cores 0 to 2 are set in module A, and core 3 is set in module B. The three cores on module A need to communicate with the one core on module B through the inter-core communication module. There are six pairs of channels on the inter-core communication module. Among them, the channels of module A are divided into three groups based on the intra-group channel configuration information. Each group is allocated two channels and is accessed by a designated core. The channels of module B can be ungrouped or divided into one group and accessed by core 3. Figure 1 In the example, the A module channels are divided into three groups. Specifically, channels 0-1 in modules A and B establish data communication between cores 0 and 3; channels 2-3 in modules A and B establish data communication between cores 1 and 3; channels 4-5 in modules A and B establish data communication between cores 2 and 3. When cores 0, 1, and 2 want to communicate with core 3, for core 0, the group configuration information indicates that it belongs to group 0, and the channel enable configuration information further indicates that channels 0 and 1 are included in group 0. Therefore, the data communication between core 0 and core 3 will be carried out through channels 0 and 1. Core 0 can only access B when it needs to send data. Module channel 0 / 1, that is, module A's transmitter channel 0 / 1 is mapped to module B's receiver channel 0 / 1, and the two are associated. Similarly, core 1 can only access channels 2 / 3 when sending data, and core 2 can only access channels 4 / 5 when sending data. The interrupt control of the core to which module A belongs is performed based on the grouping information, and the write operation data is written to the corresponding channel. When the receiving core reads data, the group control module generates three group interrupts, which are sent to cores 0, 1, and 2 respectively. The interrupt of module B is given to core 3. It can be understood that the receiving end of module A and the sending end of module B appear in pairs and share channels.

[0036] The group control module performs core interruption based on the communication request and channel identification; specifically: when module A performs a write operation, it writes into the corresponding channel in response to the write operation; the group control module and module B generate an interrupt for the corresponding group containing the channel for the receiving core, and send the interrupt to the receiving core through MUX; after the receiving core responds to the interrupt, it reads data from the group and its channel corresponding to module B and the receiving core; similarly, when the core to which module B belongs wants to write data, it writes the data into the channel corresponding to the group in response to the write operation request of the core to which module B belongs, and the group control module and module A generate an interrupt for the corresponding group in the channel for the receiving core, and send the interrupt to the receiving core through MUX; after the receiving core responds to the interrupt, it takes data from the channel of module A; then for the attached Figure 1 For example, when core 3 wants to communicate with cores 0, 1, and 2, it can freely access all channels of module B, because all channels are divided into group 1; when module B writes data, a receive interrupt will be generated in module A. After core 0 responds to the interrupt, it will get data from channels 0 and 1 of module A. After core 1 responds to the interrupt, it will get data from channels 2 and 3 of module A. After core 2 responds to the interrupt, it will get data from channels 4 and 5 of module A.

[0037] Preferably: when performing bus-based cross-core communication, a group control module is deployed for module A and module B respectively;

[0038] Preferably: when performing bus-based cross-core communication, the same group control module is deployed for module A and module B, and they are controlled by different parts of the group control module;

[0039] Preferably, the system further comprises a scenario configuration module, the scenario configuration module being configured to determine group configuration information, channel enable configuration information, and intra-group channel configuration information according to the application scenario and / or system scenario, and to send the configuration information to the group control module; the group control module performs configuration or reconfiguration when the configuration conditions are met; further, the scenario configuration module first determines AB module channel configuration information, which is used to indicate the number of channels belonging to the AB module; accordingly, the configuration module first divides the channels into A module or B module based on the AB module channel configuration information;

[0040] The scenario configuration module first determines the AB module channel configuration information; specifically:

[0041] Step SA1: Determine the number of cores and their bus access status based on system scenario information; Specifically: When performing cross-bus communication, determine based on system scenario information Each core is connected to bus 0. Each core accesses the first bus; the A and B modules of the inter-core communication module serve the 0th bus and the 1st bus respectively; when performing cross-core communication based on the same bus, the system scenario information is used to determine The cores access the 0th bus, where: CA cores use the 0th interface to access the bus, and Each core uses the first interface to access the bus; the A and B modules of the inter-core communication module serve the same bus through the 0th interface and the 1st interface respectively;

[0042] Step SA2: Analyze the communication data between cores in the application scenario based on the application scenario data to obtain communication relationship data and , Used to indicate the core to which module A belongs Send data to the core to which module B belongs The amount of data (or data frequency, number of visits, etc.); Used to indicate the core to which module B belongs Send data to the core of module A The amount of data (or data frequency, number of visits, etc.);

[0043] Preferably: the application scenario data is obtained based on historical monitoring data or real-time monitoring data;

[0044] Preferably: a monitoring module is set in the operating system to obtain the historical monitoring data or the real-time monitoring data;

[0045] Obviously: when communicating across the bus, the core and nuclear are different; when performing cross-core communication based on the same bus, the core and nuclear are the same or different; they need to be divided into module A or module B in advance; for any core ,like and = 0, then only the core Divided into the cores to which module A belongs; for any core ,like and = 0, then only the kernel The cores are divided into the cores belonging to module B; the remaining cores are set as the cores belonging to module A and module B; where: is the set of all kernels; The communication relationship data threshold; for example, set it to 0 or a smaller value;

[0046] Step SA3: Normalize the communication relationship data and set the communication relationship data ; ;

[0047] Step SA4: Divide the channels of modules A and B. Set the number of channels of module A to , let the number of channels of module B be N-NA; where: N is the total number of channels in the inter-core communication module; based on the number of channels in module A and the number of channels in module B, the channels belonging to module AB are divided, and the division information is used as the determined channel configuration information of module AB;

[0048] Preferably: divide the channel into module A or module B based on the channel identification;

[0049] The scenario configuration module is used to determine group configuration information, channel enable configuration information, and intra-group channel configuration information according to the application scenario and system scenario, and specifically includes the following steps:

[0050] Step SB1: Determine the communication relationship data based on the application scenario, and assign the A module to the Channels and B modules belong to The channels are allocated to different cores of module A and module B; specifically, the number of channels of core a in module A is calculated using the following formulas (1) and (2): ; Calculate the number of channels of core b in module B based on the following formulas (3) and (4): ; Allocation is based on the number of channels and channel identifiers; where: and are the core sets of module A and module B respectively;

[0051] (1);

[0052] (2);

[0053] (3);

[0054] (4);

[0055] Step SB2: Determine the group configuration information, channel enable configuration information and intra-group channel configuration information; specifically: for each receiving core in module A Assign a group and set the group ID ; and the communication relationship data between module B and the receiving core is greater than 0 ( )'s sending core is also assigned to this group , the above group allocation information is used as group configuration information; for each receiving core in module A For example, each group Contains the core of module A All the channels that belong to it;

[0056] Preferably: when the sending core in module B whose communication relationship data with the receiving core is greater than 0 is allocated multiple groups When multiple groups are connected, they are merged or retained; this is related to the management method of configuration information and does not affect the interrupt mode;

[0057] For the sending core in module B whose communication relationship data with the receiving core is greater than 0 Further determine the channel enable configuration information; based on The channel allocated to the receiving core a in module A is reassigned to the sending core in module B whose communication relationship data with the receiving core a is greater than 0 in proportion to the size of the value. , and use the channel reallocation information as the channel enable configuration information so that the sending core Toward the nucleus When writing data, you can group At the same time, the channel assigned to the core is enabled; The identifier is associated and saved as the channel configuration information within the group. The configuration information includes group configuration information, channel enable configuration information, and channel configuration information within the group, which is expressed as (core identifier of module A, group identifier, channel identifier) (core identifier of module B, group identifier, channel identifier). For example, if the configuration information is (0,0,0 / 1 / 2 / 3) (1,0,0 / 1), it means that core 0 of module A is assigned to group 0 as the receiving end and has channels 0 / 1 / 2 / 3. At this time, core 1 of module B is the sending end, and its group identifier is 0. When it initiates a write, it can enable channels 0 / 1. However, when core 2 of module B wants to write data to channel 0 / 1, an error message will be returned to core 2 of module B. When core 1 of module B wants to write data to channel 0 / 1, it will not. At this point, the construction of the sending end and the receiving end of sending data from module A to module B is completed. All groups of module A constitute the sending end of module A, and all groups of module B constitute the receiving end of module B.

[0058] The determination of the grouping configuration information, channel enable configuration information, and intra-group channel configuration information of the cores in module B, as well as the determination of the relevant configuration information for the cross-core communication mode based on the same bus, is similar and will not be repeated here. Through the grouping setting, when performing data communication, the use of channels and communication timing control of the sending core and the receiving core based on the group number can be controlled, and core interrupt control can be performed.

[0059] Preferably, when there is a core whose number of channels is 0 or less than the channel number threshold, group merging is performed, and the core and the core with the second smallest number of channels are grouped into the same group, so that the two merged cores can share channels. In this case, it is necessary to add identification logic to the group control module to identify the sending core or the receiving core, or to set reception identification logic in the communication module of the sending core or the receiving core to identify whether the communication data is received correctly.

[0060] Preferably, the configuration condition is when the chip is initialized, the application scenario and / or the system scenario is initialized or changed; for example, when the number of cores connected to the system bus changes, the system scenario will change accordingly, and the grouping of module A or module B needs to be reconfigured based on the bus to which it is connected; for example, if the number of cores connected to the bus to which module B belongs increases, the number of module B groups needs to be increased, and channels 0, 2, and 4 can be divided into group 0 for access by core 3, and channels 1, 3, and 5 can be divided into group 1 for access by core 4; when the application scenario changes, the grouping can be re-divided according to the read and write characteristics in the application scenario, so that the correspondence between groups and cores changes;

[0061] Preferably: in the inter-core communication module, the grouping strategies of module A and module B are the same or different;

[0062] The working logic of cross-bus communication and cross-core communication based on the same bus is similar. The difference is that when cross-bus communication is performed, the cores of the two modules AB are connected to different buses and use different sets of bus interfaces to communicate respectively; when cross-core communication is performed based on the same bus, the cores of the two modules AB are connected to the same bus and use different sets of bus interfaces to communicate respectively; in addition, the logic of the scenario configuration module will be more complicated. The scenario configuration module needs to additionally group the cores according to the application scenario, so that the cores belong to module A or module B respectively, and determine the configuration information based on the correspondence between module A and module B and the core; as shown in the attached figure. Figure 2 As shown in the figure, there are 3 cores on the chip, cores 0 to 2; cores 0 to 1 are set in module A, and cores 1 and 2 are set in module B. The two cores on module A need to communicate with the two cores on module B through the inter-core communication module; there are 6 pairs of channels on the inter-core communication module; among them: the channels of module A are divided into 2 groups through group configuration information, group 0 is allocated 4 channels to be accessed by core 0, and group 1 is allocated 2 channels to be accessed by core 1; the channels of module B are divided into 2 groups, group 0 is allocated 2 channels to be accessed by core 1, and group 1 is allocated 4 channels to be accessed by core 2; Appendix Figure 2In the example, the B module channels are divided into two groups. Specifically, channels 0-3 in modules A and B establish data communication between core 0 and cores 1-2 respectively; channels 4-5 in modules A and B establish data communication between core 1 and core 2. The group control module generates two group interrupts for module A, which are sent to cores 0 and 1 respectively. The group control module generates two group interrupts for module B, which are sent to cores 1 and 2 respectively.

[0063] Preferably: in cross-core communication based on the same bus, the same core can belong to module A or module B;

[0064] The present invention provides a multi-core system chip inter-core communication method and system, wherein the control flow logic of the method includes the following steps:

[0065] Step S0: The scenario configuration module is used to determine configuration information including group configuration information, channel enable configuration information and intra-group channel configuration information according to the application scenario and system scenario;

[0066] Preferably: the scene configuration module writes the configuration information into a memory of the configuration module, and the memory is used to store the configuration information;

[0067] Step S1: The configuration module in the grouping control module divides all available channels based on the above configuration information;

[0068] Step S2: Determine whether communication has started; specifically: determine whether a sending core has initiated a communication request; if so, determine that communication has started;

[0069] Preferably: the communication request is sent to the inter-core communication module, and the grouping control module of the inter-core communication module performs a core interrupt based on the grouping; further: the interrupt is an interrupt to the sending core and / or the receiving core;

[0070] Step S3: If communication begins, the sending core queries the channel status and writes data to the sending end when the corresponding channel is idle. Specifically, the sending core queries the channel status through the packet control logic. Here, the packet control logic queries the channel status of the channel that is accessible to the sending core. When the corresponding channel is idle, writing data to the sending end actually writes the data to the channel corresponding to the receiving core in the corresponding receiving end.

[0071] Step S4: Determine whether the packets match; if not, report an error and return to step S2; if they match, proceed to the next step; during the writing process, determine whether the packet written by the sending core is correct, that is, whether the written channel is correct. If correct, the writing is allowed, otherwise an error is reported;

[0072] Step S5: The data is written to the receiving end corresponding to the inter-core communication module, the channel status becomes non-idle, the receiving end flag is set, and a receive interrupt is generated to the receiving core; writing to the corresponding receiving end here indicates that the writing is completed and the channel status is changed. The channel status can be managed by the channel itself, or a separate channel management module can be set up by the inter-core communication module to manage it;

[0073] Preferably: a receiving flag is set to indicate that the receiving core can receive data;

[0074] Step S6: Determine whether the interrupt is responded to. If so, proceed to the next step; initiate an interrupt to notify the receiving core to enter the interrupt state to read the data in the channel. The receiving core responds to the packet control if it can be received.

[0075] Step S7: reading data from the corresponding hardware channel;

[0076] Preferably: clear the corresponding reception flag after reading is completed;

[0077] Step S8: Communication ends;

[0078] Preferably: the AB modules can use different grouping strategies;

[0079] The present invention proposes a multi-core system chip inter-core communication method and system, as shown in the attached Figure 3 As shown, the method includes the following steps:

[0080] Step S1: First, the inter-core communication module is divided into two modules, AB. Each module has a set of bus interfaces. The inter-core communication module is instantiated into two sub-modules A and B. Sub-modules A and B are combined to form a complete inter-core communication module.

[0081] Step S2: Use the group control register to manage the hardware channels within the inter-core communication module in groups, and use the group logic to set the hardware channels and access objects contained in each group.

[0082] A computer program (also referred to as a program, software, software application, script, or code) can be written in any form of programming language, including assembly or interpreted languages, declarative or procedural languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may, but need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple collaborative files (e.g., files storing one or more modules, subroutines, or code portions). A computer program can be deployed to execute on one computer or on multiple computers located at one site or distributed across multiple sites and interconnected by a communication network.

[0083] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0084] The present invention is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0085] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0086] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0087] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, ordinary technicians in the field should understand that the specific implementation methods of the present invention can still be modified or replaced by equivalents. Any modification or equivalent replacement that does not depart from the spirit and scope of the present invention should be covered by the scope of protection of the claims of the present invention.

Claims

1. A multi-core system chip inter-core communication system, characterized in that: The system includes: a system bus, two or more cores and an inter-core communication module; the inter-core communication module is used to control communication between the two or more cores; the inter-core communication module is divided into two modules A and B, and the two modules A and B respectively access the bus through a set of bus interfaces, each set of bus interfaces is used to connect to one or more cores; each set of bus interfaces belongs to the same or different buses; the one or more cores communicate data on the chip through the bus interface; wherein: when the two sets of bus interfaces belong to different buses, the cores connected to the different sets of bus interfaces communicate across the bus, and when the two sets of bus interfaces belong to the same bus, the cores can communicate across the cores based on the same bus; Modules A and B each include a set of receiving and transmitting terminals, as well as a multiplexer (MUX). The MUX connects to the bus interface and communicates with the bus. The receiving terminal in module A includes one or more channels, which are shared with the transmitting terminal corresponding to module B. The receiving terminal in module A connects to the MUX of module A to send data to the bus, and the transmitting terminal corresponding to module B connects to the MUX of module B to receive data from the bus. The other set of receiving and transmitting terminals is configured in the same way. The group control module is used to divide the channels in the AB module into one or more groups based on the communication relationship between the receiving core and the sending core, and perform group configuration, channel enable configuration and intra-group channel configuration to identify the correspondence between the groups and the cores based on the communication relationship, so that the sending core writes the sending data into the channel corresponding to the group after the channel is enabled, and generates a core interrupt for the receiving core with which the communication relationship occurs, so that the receiving core reads the data through the corresponding channel after the interrupt occurs.

2. The multi-core system chip inter-core communication system according to claim 1, characterized in that: When the corresponding relationship between the sending core and the receiving core does not match the configuration information in the packet control module, an error is returned to the sending core to avoid possible communication anomalies.

3. The multi-core system chip inter-core communication system according to claim 2, characterized in that: The MUX is implemented using configurable logic.

4. The multi-core system chip inter-core communication system according to claim 3, characterized in that: The multi-core system chip is provided with two or more cores.

5. The multi-core system chip inter-core communication system according to claim 4, characterized in that: The system also includes a scenario configuration module, which is used to determine group configuration information, channel enable configuration information and intra-group channel configuration information based on application scenarios and / or system scenarios, and send the configuration information to the group control module; the group control module performs configuration or reconfiguration when the configuration conditions are met.

6. The multi-core system chip inter-core communication system according to claim 5, characterized in that: The group control module includes a configuration module and a configuration lock module; the configuration module is used to perform group configuration, channel enable configuration and intra-group channel configuration based on configuration information; the group configuration is used to group the cores and indicate the cores included in each group; the channel enable configuration is used to indicate the channels included in each group; the intra-group channel configuration is used to indicate the correspondence between the channels in the group and the accessible cores; the configuration module uses the configuration register to store the above configuration information and perform configuration; The group control module performs core interruption based on the communication request and channel identification; specifically: when module A performs a write operation, it writes to the corresponding channel in response to the write operation; the group control module and module B generate an interrupt for the receiving core for the corresponding group containing the channel, and send the interrupt to the receiving core through MUX; after the receiving core responds to the interrupt, it reads data from the group and its channel corresponding to module B and the receiving core; similarly, when the core to which module B belongs wants to write data, it writes the data to the channel corresponding to the group in response to the write operation request of the core to which module B belongs, and the group control module and module A generate an interrupt for the receiving core for the corresponding group in the channel, and send the interrupt to the receiving core through MUX; after the receiving core responds to the interrupt, it obtains data from the channel of module A.

7. The multi-core system chip inter-core communication system according to claim 6, characterized in that: The configuration conditions are when the chip is initialized, the application scenario and / or the system scenario is initialized or changes occur.

8. A multi-core system chip inter-core communication method, characterized in that: The multi-core system chip inter-core communication method is used to implement the multi-core system chip inter-core communication system described in any one of claims 1 to 7.

9. A multi-core system chip inter-core communication control chip, characterized in that: The multi-core system chip inter-core communication control chip is used to implement the multi-core system chip inter-core communication system described in any one of claims 1 to 7.

10. A multi-core system chip inter-core communication control circuit, characterized in that: The multi-core system chip inter-core communication module is used to implement the multi-core system chip inter-core communication system described in any one of claims 1-7.

Images