Wiring optimization method and system considering FPGA (Field Programmable Gate Array) chip

Abstract

The invention discloses a wiring optimization method and system considering an FPGA chip. The method comprises the following steps that S1, sorting processing is carried out according to the specification of a wire net; s2, selecting a receiving point, which needs to be moved and adjusted, of each line net based on the sorted line nets as a first moving point; s3, selecting a search space needing to be adjusted based on the center point of the line network where the plurality of first moving points are located; s4, updating the position of the first moving point by using a position evaluation function in the search space; and S5, setting an updating multiple, re-executing the steps S1 to S4, and obtaining a final updating result as the final output of FPGA chip wiring based on the relation between the finally obtained updating times and the updating multiple. The method comprises the following steps: searching a target network associated network center point area, selecting a position with a high evaluation score for movement or exchange, and performing network rearrangement after updating a certain number of networks to ensure rapid convergence of a result.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic integrated circuits, and in particular to a method and system for optimizing FPGA chip wiring. Background Art

[0002] FPGA (Field Programmable Gate Array), namely field programmable gate array, is a programmable logic device widely used in digital circuit design, such as Figure 1 As shown in the figure, it is mainly composed of programmable logic blocks (PLBs), block RAMs, DSPs, and IOs in regular arrays. At present, the layout and routing of FPGAs are mainly divided into five stages: initial layout, detailed layout, routing resource allocation, routing optimization, and timing verification. The detailed layout is mainly based on the initial layout, and the position of the logic unit is further fine-tuned. Therefore, more detailed factors will be considered, such as the distribution of routing resources inside the FPGA chip and the physical characteristics of the logic unit, to ensure that the layout scheme is not only short in length, but also can better adapt to the actual physical structure of the chip, meet the timing requirements of the key network, and minimize the congestion of the interconnection. The wiring problem is the most time-consuming part of the overall FPGA EDA process. According to empirical statistics, in complex design cases, the running time of wiring can account for 50% to 70%. It can be seen that optimizing the running time of wiring is a crucial part for improving the efficiency of the EDA convergence process. In-depth analysis of the proportion of wiring time shows that the global interconnection line conflict caused by the algorithm when dealing with the complex driving relationship of the netlist across PLBs (programmable logic blocks) is the main time-consuming part. Therefore, it is necessary to fully consider future wiring requirements during the detailed layout stage.

[0003] As the scale of FPGA continues to increase, the number of logic units can reach millions or even more, and the search space for layout is growing exponentially. There are complex connection relationships and timing requirements between different logic units. How to find the optimal layout solution in the huge search space is a huge challenge and an NP-hard problem. In the detailed layout stage, it is often necessary to optimize multiple performance indicators at the same time, such as delay, power consumption, area, etc. These indicators often restrict each other. For example, in order to reduce delay, it may be necessary to increase wiring resources, resulting in increased area and power consumption. How to balance these goals to achieve overall optimization is one of the difficulties. Finally, in terms of manufacturing process, the wiring resources of FPGA are limited and complexly distributed, and the number and type of wiring resources in different areas are different. When laying out, it is necessary to consider the impact of the distribution of logic units on wiring, avoid wiring congestion, and ensure that signals can be smoothly wired and connected, which further increases the complexity and difficulty of layout.

[0004] In the face of the current large-scale integrated circuit layout and routing problems, traditional layout generally uses heuristic algorithms such as simulated annealing algorithms or genetic algorithms to perform detailed layout adjustments. This algorithm has a slow convergence speed and high complexity when facing large-scale FPGA layout, and the running results are unstable. It is difficult to effectively handle complex constraints in FPGAs. Summary of the invention

[0005] In view of the above-mentioned defects, the purpose of the present invention is to propose a method and system for optimizing FPGA chip wiring, so as to solve the problems of slow convergence speed and unstable optimization operation results of existing optimization methods.

[0006] To achieve this purpose, the present invention adopts the following technical solution: a method for optimizing FPGA chip wiring, including the following method:

[0007] Step S1: sorting according to the specifications of the wire network;

[0008] Step S2: Based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted is selected as the first moving point;

[0009] Step S3: Based on the center point of the line network where the plurality of first moving points are located, selecting the search space to be adjusted;

[0010] Step S4: in the search space, using a position evaluation function to update the position of the first moving point;

[0011] Step S5: Set the update multiple, re-execute steps S1 to S4, and based on the relationship between the last obtained update times and the update multiple, obtain the final update result as the final output of the FPGA chip wiring.

[0012] Preferably, the step S1 is specifically as follows:

[0013] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0014] The nets are sorted from smallest to largest based on the average drive length.

[0015] Preferably, the step S2 is specifically as follows:

[0016] For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement;

[0017] For a line network whose driving point is less than the first threshold and greater than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point;

[0018] For the line network with the driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

[0019] Preferably, the step S3 is specifically as follows:

[0020] Construct a set N of line networks where the first moving point is located;

[0021] Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates;

[0022] In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point;

[0023] The search space is constructed based on the first coordinate point and the second coordinate point.

[0024] Preferably, the step S4 is specifically as follows:

[0025] Step S41: Count the PLBs in the search space and calculate the density of all PLBs;

[0026] The density is obtained as follows:

[0027] Step S42: sort the densities of the PLBs from large to small, and select the first N densities as the adjustment threshold R, where the value of N is 5-10%;

[0028] Step S43: searching for a movable position in the search space, moving the first movable point to the movable position, and calculating the density r after the move, and judging whether the density r after the move is greater than the adjustment threshold R, if it is greater, the first movable point does not move, if it is less than, obtaining the score after the move based on the position evaluation function, and judging whether the score is greater than 0, if it is greater, moving the first movable point to the movable position, and if it is not greater than, the first movable point does not move;

[0029] Step S44: Replace the next first moving point and re-execute step S43 until all the first moving points are calculated.

[0030] A system considering FPGA chip wiring optimization, using the method considering FPGA chip wiring optimization, including a sorting module, a point selection module, an area selection module, an adjustment module and an update module;

[0031] The sorting module is used to perform sorting processing according to the specifications of the wire network;

[0032] The point selection module is used to select, based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted as a first moving point;

[0033] The area selection module is used to select the search space that needs to be adjusted based on the center point of the line network where the multiple first moving points are located;

[0034] The adjustment module is used to update the position of the first moving point in the search space using a position evaluation function;

[0035] The update module is used to set the update multiple, re-call the sorting module, point selection module, area selection module and adjustment module, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained update number and the update multiple.

[0036] Preferably, the sorting module performs the following operations:

[0037] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0038] The nets are sorted from smallest to largest based on the average drive length.

[0039] Preferably, the point selection module performs the following operations:

[0040] For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement;

[0041] For a line network whose driving point is less than the first threshold and greater than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point;

[0042] For the line network with the driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

[0043] Preferably, the region selection module performs the following operations:

[0044] Construct a set N of line networks where the first moving point is located;

[0045] Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates;

[0046] In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point;

[0047] The search space is constructed based on the first coordinate point and the second coordinate point.

[0048] Preferably, the updating module includes a statistical submodule, a threshold acquisition submodule, a position determination submodule and a circulation submodule;

[0049] The statistical submodule is used to count the PLBs in the search space and calculate the density of all PLBs;

[0050] The threshold acquisition submodule is used to sort the density of PLB from large to small, and select the first N density as the adjustment threshold R, where the value of N is 5-10%;

[0051] The position judgment submodule is used to search for a movable position in the search space, move the first movable point to the movable position, and calculate the density r after the movement, and judge whether the density r after the movement is greater than the adjustment threshold R. If it is greater, the first movable point will not be moved. If it is less than, the score after the movement is obtained based on the position evaluation function, and it is judged whether the score is greater than 0. If it is greater, the first movable point is moved to the movable position. If it is not greater, the first movable point will not be moved;

[0052] The loop submodule is used to replace the next first moving point and re-call the position determination submodule until all the first moving points are calculated.

[0053] One of the above technical solutions has the following advantages or beneficial effects: by sorting the line network optimization potential, the results of the line network with large optimization potential and small scale are quickly converged, thereby ensuring the success rate of the optimized layout; searching the line network center point area associated with the target line network, selecting the positions with high evaluation scores to move or exchange, and rearranging the line network after updating a certain number of line networks to ensure that the results converge quickly. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 This is the basic architecture diagram of FPGA.

[0055] Figure 2 It is a position relationship diagram between the wire networks.

[0056] Figure 3 It is a flow chart of an embodiment of the method of the present invention.

[0057] Figure 4 It is a schematic diagram of the structure of an embodiment of the system of the present invention. DETAILED DESCRIPTION

[0058] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals represent the same or similar elements or elements having the same or similar functions from beginning to end. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0059] In the description of the embodiments of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0060] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, the meaning of "plurality" is two or more. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0061] like Figures 1 to 4 As shown, a method for optimizing FPGA chip wiring includes the following methods:

[0062] Step S1: sorting according to the specifications of the wire network;

[0063] In FPGA, the number of node units is generally around 10k-100k, which are combined into wire nets of different sizes according to the connection relationship. A wire net consists of a driver and several sinks. Depending on the number of sinks, the size of the wire net varies from dozens to hundreds. For example, the size of a large fan-out wire net such as a reset signal may exceed 800. The optimization cost of such a large fan-out wire net is too high, and the calculation of the wire length and the position search are very time-consuming, and have a great impact on other wire nets. Therefore, it is necessary to sort the wire nets according to their specifications, give priority to processing wire nets with smaller specifications, and iterate the wire nets with high optimization efficiency, so as to achieve rapid convergence of the results and ensure the feasibility of the optimization results.

[0064] Step S2: Based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted is selected as the first moving point;

[0065] Step S3: Based on the center point of the line network where the plurality of first moving points are located, selecting the search space to be adjusted;

[0066] Step S4: in the search space, using a position evaluation function to update the position of the first moving point;

[0067] Step S5: Set the update multiple, re-execute steps S1 to S4, and based on the relationship between the last obtained update times and the update multiple, obtain the final update result as the final output of the FPGA chip wiring.

[0068] The present invention uses a strategy based on searching in the center area of ​​associated wire meshes. First, the wire meshes are screened by scale analysis. Due to too many layout constraints, it is necessary to comprehensively design a reasonable position evaluation function based on wire length, density, and timing. A unified evaluation is performed on a large number of complex constraints to ensure the feasibility of the optimization results. Subsequently, the wire meshes with large optimization potential and small scale are ranked to quickly converge the results, thereby ensuring the success rate of the optimized layout. The center point area of ​​the target wire mesh is searched, and positions with high evaluation scores are selected for moving or exchanging. After a certain number of wire meshes are updated, the wire meshes are rearranged to ensure that the results converge quickly.

[0069] Finally, regarding the stability of the results, since the optimization effect is relatively discrete and small in the later stage of optimization, the update multiple is set in the present invention. For example, if the update multiple is 100, when the closing time arrives and the number of updates is 260, the last update result will be selected by multiples of 100, of which 200 is closest to 260 and is a multiple of 100. At this time, the 200th update result will be selected as the final output of the FPGA chip wiring. If the update multiple is 30, when the closing time arrives and the number of updates is 260, the last update result will be selected by multiples of 30, of which 240 is closest to 260 and is a multiple of 30. At this time, the 240th update result will be selected as the final output of the FPGA chip wiring.

[0070] This ensures that the optimization results are stable after multiple runs, which meets the actual needs of enterprise production for layout and wiring. The experimental results of wire nets of different sizes show that this method can ensure that the density does not deteriorate under the condition of meeting the timing constraints, and can achieve large-scale wire nets to reduce the critical wire length and non-critical wire length, thereby reducing the subsequent wiring cost, shortening the wiring time and improving efficiency, which can save a lot of costs for enterprises. At the same time, the optimization results have great advantages for problems with complex wire net connection relationships and more constraints.

[0071] Preferably, the step S1 is specifically as follows:

[0072] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0073] The nets are sorted from smallest to largest based on the average drive length.

[0074] Since the scale of the wire network is generally positively correlated with the total length, it is necessary to perform unified sorting by the average wire length. Sort the initial wire network lengths according to the average driving length. Let the number of driven points of the wire network be d, the total length of the wire network be L, and the average driving length be Evaluate wire networks of different scales in a unified manner to prevent the influence of different wire network scales.

[0075] Preferably, the specific steps of step S2 are as follows:

[0076] For wire networks with the number of driving points greater than or equal to the first threshold, do not select receiving points for movement;

[0077] For wire networks with the number of driving points less than the first threshold and greater than the second threshold, select the receiving points with the top 50% Manhattan wire length based on the driving points as the first moving points;

[0078] For wire networks with the number of driving points less than the second threshold, select all receiving points as the first moving points.

[0079] For wire networks with a small number of driven points, the calculation is faster, so a higher selection ratio is adopted. For wire networks with a large and relatively dispersed scale, partial selection or even non-selection is carried out to prevent repeated calculation of the Steiner tree at large fan-out wire networks, which consumes a lot of time. After multiple tests, for large wire network scales, the value of the first threshold is 20. When d >= 20, movement is not considered. For medium wire network scales, the value of the second threshold can be 5. When 5 < d < 20, select the receiving points with the top 50% Manhattan wire length as the first moving points. For small wire network scales d <= 5, select all receiving points as the first moving points. By analyzing the driving points of wire networks of different scales, select receiving points with great optimization potential for subsequent searches, fully considering the characteristic that the calculation time of wire length is relatively long, and try to avoid repeated calculations for large wire networks.

[0080] Preferably, the specific steps of step S3 are as follows:

[0081] Construct a set N of wire networks where the first moving points are located;

[0082] Find the coordinates of all nodes of each wire network in set N, obtain the central coordinates based on the coordinates of all nodes, and construct a central coordinate set from multiple central coordinates;

[0083] In the central coordinate set, select the smallest abscissa and the smallest ordinate to construct a first coordinate point, and select the largest abscissa and the largest ordinate to construct a second coordinate point;

[0084] Construct the search space based on the first coordinate point and the second coordinate point.

[0085] The search range of the nodes to be moved obtained above is determined to search for feasible positions. Since a receiving point sink can be driven by multiple driving points, or can drive multiple receiving points sink to form a new network, when considering the movement of the first moving point, it is necessary to fully consider the optimization or even deterioration of other associated networks. For large-scale intensive integrated circuits, the feasible positions are limited in consideration of various resource restrictions and timing constraints, so a strategy for searching the position in the center area of ​​the associated network is used. Figure 2 As shown, assuming that there are currently three wire nets net1, net2 and net3, the coordinates of all nodes (nodes include driving points and receiving points) of each wire net of net1, net2 and net3 are obtained respectively, and the center coordinates are obtained based on the coordinates of all nodes. The calculation formula of the center coordinates is:

[0086] Where p is the total number of nodes in the network, Respectively represent the abscissa and ordinate of the jth node of the ith network;

[0087] Then we can get the center coordinates of net1 respectively The center coordinates of net2 and the center coordinates of net1 Depend on Figure 2 It can be seen that among all the horizontal coordinates, net2 has the smallest horizontal coordinate and net3 has the largest horizontal coordinate, while among the vertical coordinates, net2 has the smallest vertical coordinate and net1 has the largest vertical coordinate. At this time, the first coordinate point is The second coordinate point is A rectangular search space can be determined based on two coordinate points.

[0088] Preferably, the step S4 is specifically as follows:

[0089] Step S41: Count the PLBs in the search space and calculate the density of all PLBs;

[0090] The density is obtained as follows:

[0091] Among them I con , O con I represents the input pin and output pin of the connection network in PLB, respectively. to , O to Respectively represent all input pins and all output pins that the PLB can accommodate.

[0092] Step S42: sort the densities of the PLBs from large to small, and select the first N densities as the adjustment threshold R, where the value of N is 5-10%;

[0093] During the detailed layout process, it is necessary to ensure that the density does not deteriorate significantly, thereby reducing the congestion caused by the layout. Therefore, all PLBs are sorted by initial density, and the Nth density before the highest density is selected as the lower limit. For example, if N is 5%, when there are 1000 PLBs, the density of the first 50th PLB is selected as the adjustment threshold R.

[0094] Step S43: searching for a movable position in the search space, moving the first movable point to the movable position, and calculating the density r after the move, and judging whether the density r after the move is greater than the adjustment threshold R, if it is greater, the first movable point does not move, if it is less than, obtaining the score after the move based on the position evaluation function, and judging whether the score is greater than 0, if it is greater, moving the first movable point to the movable position, and if it is not greater than, the first movable point does not move;

[0095] The density r after movement is the density of the PLB affected by the first moving point after the movement.

[0096] The position evaluation function is as follows:

[0097] Where k is the optimization weight, Where L noncrit is the initial non-critical line length, L crit is the initial critical line length. The critical line length is the line length connected to the driving end of the key node in the line network. The others are non-critical line lengths. crit and Δl non-crit The key line length change value and the non-key line length change value before and after the first moving point are moved. The key line length is calculated by the Manhattan distance of the PLB to which it belongs, while the Steiner tree distance is calculated by the open source tool FLUTE for non-key line length.

[0098] Step S44: Replace the next first moving point and re-execute step S43 until all the first moving points are calculated.

[0099] A system considering FPGA chip wiring optimization, using the method considering FPGA chip wiring optimization, including a sorting module, a point selection module, an area selection module, an adjustment module and an update module;

[0100] The sorting module is used to perform sorting processing according to the specifications of the wire network;

[0101] The point selection module is used to select, based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted as a first moving point;

[0102] The area selection module is used to select the search space that needs to be adjusted based on the center point of the line network where the multiple first moving points are located;

[0103] The adjustment module is used to update the position of the first moving point in the search space using a position evaluation function;

[0104] The update module is used to set the update multiple, re-call the sorting module, point selection module, area selection module and adjustment module, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained update number and the update multiple.

[0105] Preferably, the sorting module performs the following operations:

[0106] Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained;

[0107] The nets are sorted from smallest to largest based on the average drive length.

[0108] Preferably, the point selection module performs the following operations:

[0109] For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement;

[0110] For a line network whose driving point is less than the first threshold and greater than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point;

[0111] For the line network with the driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

[0112] Preferably, the region selection module performs the following operations:

[0113] Construct a set N of line networks where the first moving point is located;

[0114] Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates;

[0115] In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point;

[0116] The search space is constructed based on the first coordinate point and the second coordinate point.

[0117] Preferably, the updating module includes a statistical submodule, a threshold acquisition submodule, a position determination submodule and a circulation submodule;

[0118] The statistical submodule is used to count the PLBs in the search space and calculate the density of all PLBs;

[0119] The threshold acquisition submodule is used to sort the density of PLB from large to small, and select the first N density as the adjustment threshold R, where the value of N is 5-10%;

[0120] The position judgment submodule is used to search for a movable position in the search space, move the first movable point to the movable position, and calculate the density r after the movement, and judge whether the density r after the movement is greater than the adjustment threshold R. If it is greater, the first movable point will not be moved. If it is less than, the score after the movement is obtained based on the position evaluation function, and it is judged whether the score is greater than 0. If it is greater, the first movable point is moved to the movable position. If it is not greater, the first movable point will not be moved;

[0121] The loop submodule is used to replace the next first moving point and re-call the position determination submodule until all the first moving points are calculated.

[0122] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0123] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A method for optimizing FPGA chip wiring, characterized in that: The following methods are included: Step S1: sorting according to the specifications of the wire network; Step S2: Based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted is selected as the first moving point; Step S3: Based on the center point of the line network where the multiple first moving points are located, select the search space that needs to be adjusted; Step S4: in the search space, using a position evaluation function to update the position of the first moving point; Step S5: Set the update multiple, re-execute steps S1 to S4, and based on the relationship between the last obtained update times and the update multiple, obtain the final update result as the final output of the FPGA chip wiring.

2. A method for optimizing FPGA chip wiring according to claim 1, characterized in that: The step S1 is specifically as follows: Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained; The nets are sorted from smallest to largest based on the average drive length.

3. The method for optimizing FPGA chip wiring according to claim 1, characterized in that: The step S2 is specifically as follows: For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement; For a line network whose driving point is less than the first threshold and greater than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point; For the line network with the driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

4. The method for optimizing FPGA chip wiring according to claim 1, characterized in that: The step S3 is specifically as follows: Construct a set N of line networks where the first moving point is located; Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates; In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point; The search space is constructed based on the first coordinate point and the second coordinate point.

5. The method for optimizing FPGA chip wiring according to claim 1, characterized in that: The step S4 is specifically as follows: Step S41: Count the PLBs in the search space and calculate the density of all PLBs; The density is obtained as follows: Step S42: sort the densities of the PLBs from large to small, and select the first N densities as the adjustment threshold R, where the value of N is 5-10%; Step S43: searching for a movable position in the search space, moving the first movable point to the movable position, and calculating the density r after the move, and judging whether the density r after the move is greater than the adjustment threshold R, if it is greater, the first movable point does not move, if it is less than, obtaining the score after the move based on the position evaluation function, and judging whether the score is greater than 0, if it is greater, moving the first movable point to the movable position, and if it is not greater than, the first movable point does not move; Step S44: Replace the next first moving point and re-execute step S43 until all the first moving points are calculated.

6. A system considering FPGA chip wiring optimization, characterized in that: A method for optimizing FPGA chip wiring according to any one of claims 1 to 5, comprising a sorting module, a point selection module, an area selection module, an adjustment module and an update module; The sorting module is used to perform sorting processing according to the specifications of the wire network; The point selection module is used to select, based on the sorted wire nets, a receiving point of each wire net that needs to be moved and adjusted as a first moving point; The area selection module is used to select the search space that needs to be adjusted based on the center point of the line network where the multiple first moving points are located; The adjustment module is used to update the position of the first moving point in the search space using a position evaluation function; The update module is used to set the update multiple, re-call the sorting module, point selection module, area selection module and adjustment module, and obtain the final update result as the final output of the FPGA chip wiring based on the relationship between the last obtained update number and the update multiple.

7. A system considering FPGA chip wiring optimization according to claim 6, characterized in that: The sorting module performs the following operations: Based on the number of driving points and the total length of the wire mesh, the average driving length of each wire mesh is obtained; The nets are sorted from smallest to largest based on the average drive length.

8. The FPGA chip routing optimization system according to claim 6, characterized in that: The point selection module performs the following operations: For a line net whose driving point is greater than or equal to the first threshold, no receiving point is selected for movement; For a line network whose driving point is less than the first threshold and greater than the second threshold, the receiving points in the first 50% of the Manhattan line length are selected as the first moving points based on the driving point; For the line network with the driving point smaller than the second threshold, all the receiving points are selected as the first moving points.

9. The FPGA chip routing optimization system according to claim 6, characterized in that: The region selection module performs the following operations: Construct a set N of line networks where the first moving point is located; Find the coordinates of all nodes of each line network in the set N, obtain the center coordinates based on the coordinates of all nodes, and construct a center coordinate set from multiple center coordinates; In the center coordinate set, the smallest horizontal coordinate and the smallest vertical coordinate are selected to construct the first coordinate point, and the largest horizontal coordinate and the largest vertical coordinate are selected to construct the second coordinate point; The search space is constructed based on the first coordinate point and the second coordinate point.

10. The FPGA chip routing optimization system according to claim 6, characterized in that: The updating module includes a statistical submodule, a threshold acquisition submodule, a position determination submodule and a circulation submodule; The statistical submodule is used to count the PLBs in the search space and calculate the density of all PLBs; The threshold acquisition submodule is used to sort the density of PLB from large to small, and select the first N density as the adjustment threshold R, where the value of N is 5-10%; The position judgment submodule is used to search for a movable position in the search space, move the first movable point to the movable position, and calculate the density r after the movement, and judge whether the density r after the movement is greater than the adjustment threshold R. If it is greater, the first movable point will not be moved. If it is less than, the score after the movement is obtained based on the position evaluation function, and it is judged whether the score is greater than 0. If it is greater, the first movable point is moved to the movable position. If it is not greater, the first movable point will not be moved; The loop submodule is used to replace the next first moving point and re-call the position determination submodule until all the first moving points are calculated.

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