Clock tree synthesis method based on synchronous concurrency and hierarchical clustering

Abstract

The application discloses a clock tree synthesis method based on synchronous concurrency and hierarchical clustering, belongs to the field of integrated circuits, and comprises the following steps: reading physical information of all registers and clock sources, obtaining a coarse clustering target grouping number and a single-group register number threshold; performing coarse clustering grouping on the read-in registers by using a KmeansPlus algorithm; extracting a grouping result, obtaining a fine clustering grouping number, and applying the synchronous concurrency KmeansPlus algorithm to all register groups for fine clustering; extracting fine clustering convergence point coordinates, combining the size of a buffer used for instantiating the convergence point, and judging whether overlap occurs with connected sub-registers; and extracting the buffer after instantiation as a first-level synthesis result, inputting the first-level synthesis result into a KmeansPlus algorithm as a second-level leaf node for second-level coarse clustering.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of integrated circuits, and particularly relates to a clock tree synthesis method based on synchronous concurrency and hierarchical clustering. BACKGROUND

[0002] Clock tree synthesis is an important step in digital integrated circuit design, and the speed and reliability of digital integrated circuit design can be improved by quickly and accurately performing clock tree synthesis and optimization. Digital integrated circuit clock tree synthesis refers to connecting the layout of registers to the clock source through clustering and balancing. Clustering is to divide the layout of registers into multiple groups to form leaf nodes, which are aggregated to corresponding buffers, and the buffers are finally aggregated to the root node (clock source). Balancing is the optimization balancing of the clock tree, which reduces the clock skew and latency to each sub-node and the number of buffers N as much as possible while ensuring that the number of loads carried by the buffer does not exceed the maximum fan-out and the load capacitance does not exceed the maximum load capacitance. In digital circuits, clock tree synthesis has a great influence on circuit performance, as it determines the stability and reliability of clock propagation in the circuit. Clock tree synthesis is one of the key steps in digital circuit design, which helps to ensure the correct function and performance of the circuit, thereby shortening the development time of the product and reducing the cost, and improving the quality of the product.

[0003] Digital EDA tools are usually used to design and verify the correctness of digital circuits, and these tools can help engineers simulate, test and optimize the performance of the circuit. However, as the size of integrated circuits in digital chips becomes larger and larger, the complexity of digital circuits increases, and the speed and stability of clock tree synthesis become a big problem. EDA tools cannot meet the requirements of large-scale integrated circuit clock tree synthesis, and the quality of the clock tree synthesis is poor, the digital chip design process is repeated, and the entire process is very time-consuming. The key point of clock tree synthesis is clustering, and the clustering algorithm is a method for optimizing the buffer. All registers are clustered into several groups, and a clock buffer is assigned to each group. The use of an efficient, stable and accurate clustering algorithm by EDA tools can greatly improve the speed and efficiency of clock tree synthesis, thereby speeding up the development of digital chips and shortening the time of the product to market.

[0004] The traditional Kmeans algorithm randomly selects K initial cluster centers, then assigns each data point to the nearest cluster center, and iteratively calculates each cluster center until the cluster center no longer changes significantly or the maximum number of iterations is reached. The selection of the initial cluster in Kmeans will affect the final clustering result, resulting in the algorithm falling into a local optimal solution. And with the increase of circuit elements in super large scale integrated circuits, the traditional Kmeans method of serial clustering will cause huge time overhead when processing a large number of registers, and a fast and accurate method is urgently needed to achieve high-quality clustering. SUMMARY

[0005] The application aims to overcome the deficiencies of the prior art, and provides a clock tree synthesis method based on synchronous concurrency and hierarchical clustering, which starts from reading a layout post-file, obtains a coarse clustering target grouping number and a single-group register number threshold according to a total register number and an available thread number, then inputs total register insts, the coarse clustering target grouping number n, a maximum iteration number T, a random seed value seed and other information to a KmeansPlus algorithm to perform coarse clustering grouping on registers, so that the number of registers in each group is lower than the single-group register number threshold. The coarse clustering number of each group is combined with a maximum fanout max_fanout of a used buffer Buffer and a scaling ratio ratio to calculate a fine clustering target grouping number divide_number, and the target grouping number divide_number, the maximum iteration number T, the random seed value seed and other information are input to a synchronous concurrency KmeansPlus algorithm to perform fine clustering. The method combines the advantages of multi-thread acceleration and KmeansPlus intelligent selection of a center point, and realizes accurate and fast clock tree synthesis starting from a register level. Compared with a traditional clock tree synthesis method, the running speed and accuracy of the clock tree synthesis are improved.

[0006] The application adopts the following technical scheme to achieve the above application purposes:

[0007] The clock tree synthesis method based on synchronous concurrency and hierarchical clustering comprises the following steps:

[0008] In step S1, whether the hierarchical clustering object is a register or a buffer is selected according to a level, physical information of all registers and clock sources in a layout file is read, a register level is taken as a first level to start clustering and construct a tree, and a target grouping number and a single-group register number threshold are obtained according to a total register number and an available thread number. For a hierarchical clustering iteration step in which a level read as a buffer is taken, a target grouping number and a single-group buffer number threshold are first obtained.

[0009] In step S2, total register insts, the target grouping number n, the maximum iteration number T and the random seed value seed are input to a KmeansPlus algorithm according to the single-group register number threshold to perform coarse clustering grouping on the read registers, whether the coarse clustering result of each group is less than the single-group number threshold is judged, if yes, the result is returned for fine clustering in the next step, and if not, coarse clustering is performed again.

[0010] Step S3, extracting the grouping result of step S2, obtaining the grouping number divide_number according to the number of registers in each group and the buffer Buffer maximum fanout and scaling ratio max_fanout and ratio to be used after fine clustering, inputting the register information of each group, the target grouping number divide_number, the maximum iteration number T, the random seed value seed and other physical information to the synchronous concurrent KmeansPlus algorithm for fine clustering;

[0011] Step S4, extracting the fine clustering convergence point in step S3, performing overlap judgment and line length judgment on the convergence point, determining that the convergence point coordinates combined with the buffer Buffer size do not overlap with other registers at the next level, and the line length of the convergence point and all leaf nodes connected thereto does not exceed the maximum line length; instantiating the convergence point using the buffer Buffer, setting the subunits of the buffer to all leaf nodes connected to the convergence point; the buffer result obtained by fine clustering of all groups at this level is used as the input of the next level of hierarchical clock tree synthesis.

[0012] Step S5, extracting the result of the first level synthesis in step S4 as the input of the coarse clustering in the second level clock tree synthesis, iteratively performing steps S1-S4 to obtain the second level synthesis result; performing hierarchical clustering from bottom to top from the register to the clock source, connecting the buffers of the leaf nodes and the convergence nodes level by level, until the last level buffer converges to the clock source.

[0013] As a further optimization scheme of the clock tree synthesis method based on synchronous concurrency and hierarchical clustering, the specific method of step S1 for obtaining the coarse clustering target grouping number and the single group register threshold according to the number of registers and the number of available threads is: according to the number of available threads and the number of groups processed by each thread, the coarse clustering target grouping number is obtained, according to the size of the registers in the layout information and the coarse clustering target grouping number, a reasonable grouping threshold is calculated, the number of iterations of coarse clustering is reduced, and the number of iterations of fine clustering on the coarse clustering result is also controlled within a reasonable range.

[0014] As a further optimization scheme of the clock tree synthesis method based on synchronous concurrency and hierarchical clustering, step S2 inputs the total number of registers insts, the target grouping number n, the maximum iteration number T, and the random seed value seed to the KmeansPlus algorithm to perform coarse clustering grouping on the input registers, only when the grouping result is less than the single group register number threshold, fine clustering can be performed, otherwise, coarse clustering needs to be performed again, by adjusting the single group register number threshold and the coarse clustering target grouping number, until the grouping threshold is met.

[0015] As a further optimization scheme of the clock tree synthesis method based on synchronous concurrency and hierarchical clustering, step S3 uses the number of registers insts_number after coarse clustering grouping, the maximum fanout max_fanout of the buffer Buffer used by the instantiated sink point after clustering, and the scaling ratio ratio to obtain the number of fine clustering groups divide_number, inputs the number of fine clustering groups divide_number, the maximum fanout max_fanout, the number of iterations T, and the random seed value seed into the synchronous concurrency KmeansPlus algorithm, fine clusters the registers after coarse clustering, and obtains the sink point of each group of clusters.

[0016] As a further optimization scheme of the clock tree synthesis method based on synchronous concurrency and hierarchical clustering, step S4 calculates whether the buffer and the connected registers overlap based on the sink point coordinates obtained by fine clustering and the size of the buffer Buffer, and calculates whether the Manhattan distance between the buffer and the connected registers exceeds the maximum net length max_net. If the overlap occurs or the maximum net length is exceeded, the sink point position needs to be fine-tuned.

[0017] As a further optimization scheme of the clock tree synthesis method based on synchronous concurrency and hierarchical clustering, step S5 extracts the result of the first-level synthesis in step S4 as the input of coarse clustering in the second-level clock tree synthesis, iteratively performs steps S1-S5 to obtain the second-level synthesis result, until the sink point is connected to the clock source, that is, the complete clock tree synthesis is realized. For the first-level clustering, the leaf node is a register, and the leaf node of the second-level and above clustering is a buffer. In steps S1-S5, the target grouping number, the single-group register threshold, and the read-in register information are replaced by the buffer.

[0018] A computer readable storage medium having a computer program stored thereon, the computer program being executable to perform the steps of the path timing prediction method.

[0019] The technical scheme has the following beneficial effects:

[0020] (1) the application proposes a clock tree synthesis method based on synchronous concurrency and hierarchical clustering, through using synchronous concurrency KmeansPlus method to complete clock tree synthesis of post-layout register, according to the method of constructing clock tree from bottom to top, using KmeansPlus method to perform coarse clustering grouping on register / buffer at each level, the coarse clustering result less than the threshold of single register number is entered into the thread pool through fine clustering task, synchronous concurrency KmeansPlus algorithm is applied to each group of register / buffer for fine clustering, the convergence point of the group is obtained, and the convergence buffer is instantiated, the leaf node of the register / buffer at this level is connected with the convergence buffer to construct a tree, and the buffer of all groups at this level is used as the input of coarse clustering of the next level, the clock tree is constructed from bottom to top until the clock source, the fast and accurate clock tree synthesis in digital circuit is realized, and the speed of digital chip design process is improved.

[0021] (2) the application realizes data protection by adding synchronous concurrency multithreading processing in the traditional KmeansPlus algorithm, and locking the fine clustering result as shared data; the KmeansPlus algorithm of multithreading synchronous concurrency realizes maximum resource utilization compared with the traditional serial clustering, realizes multi-group clustering in the same time period through parallel calculation when fine clustering is performed on large-scale register / buffer, accelerates in the hierarchical clustering clock tree from bottom to top, and compared with the traditional Kmeans method, the intelligent selection center point is added to improve the running speed of clock tree synthesis, and local optimal solution is avoided. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings constitute a part of this specification and are included to further a state of the application, and together with the embodiments of the application, are used to explain the application but do not constitute a limitation on the application;

[0023] Figure 1 is a flowchart of the clock tree synthesis method based on synchronous concurrency and hierarchical clustering of the application;

[0024] Figure 2 is a schematic diagram of the synchronous concurrency KmeansPlus algorithm of the application;

[0025] Figure 3 is a detailed schematic diagram of the application about coarse clustering and fine clustering;

[0026] Figure 4 is a schematic diagram of the thread pool scheme in the synchronous concurrency KmeansPlus algorithm of the application. DETAILED DESCRIPTION

[0027] The technical scheme of the application will be further described in detail below in combination with the drawings and embodiments.

[0028] In order to make the invention purposes, technical solutions and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below in conjunction with the drawings of the specification. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should fall within the protection scope of the present application.

[0029] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be practiced without other different ways from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0030] The present application is further described below in conjunction with the drawings. The clock tree synthesis method based on synchronous concurrency and hierarchical clustering as shown in Figure 1 S1-S5.

[0031] S1, according to the read-in layout post-file, read the position information of layout area, register and clock source and convert it into coordinates, read the physical information of unit resistance, unit capacitance, unit line length delay, read the constraint information of the maximum fanout max_fanout of buffer Buffer, path maximum delay, etc. For the first level register of clock tree synthesis hierarchical clustering, according to the number of registers, the number of available threads, the number of groups that each thread can process, the target grouping number is obtained, and then the number of registers in a single group threshold is obtained by combining the number of registers and the target grouping number, the threshold value is represented as formula (1):

[0032] insts_each = insts_number / n (1)

[0033] Where insts_each is the number of registers in a single group threshold, insts_number is the total number of registers, and n is the target grouping number of coarse clustering. For the buffer Buffer of other levels of clock tree, the same is true, and the number of buffers in a single group threshold can be calculated.

[0034] For example, for the register with the order of magnitude of 100k, the number of available threads is 8, each thread processes two groups of register / buffer clusters in fine clustering, the target grouping number is 16, and the grouping threshold is set to 20000. Through testing, the setting can pass the coarse clustering to meet the requirements, and the time cost is reduced compared with the traditional serial KmeansPlus method.

[0035] S2, input insts, target grouping number n, maximum iteration number T, seed value seed for randomly generating points of the total register / total buffer coordinates and name information of the hierarchical input into the KmeansPlus algorithm for rough clustering, to get the rough clustering of the preliminary grouped register / buffer.

[0036] S3, judge the number of rough clustered single group register / buffer, if the number of each group is lower than the threshold value of single group register / buffer number, return the result for the next step of fine clustering, otherwise re-rough clustering until the threshold value is met.

[0037] S4, according to the number of each group register / buffer insts_number in the thread pool, the maximum fanout max_fanout of the buffer Buffer used for instance clustering convergence point and the scaling ratio ratio, the grouping number divide_number is obtained, as shown in formula (2).

[0038] divide_number=insts_number / (max_fanout×ratio) (2)

[0039] By using the scaling ratio ratio and the maximum fanout max_fanout, the number of leaf nodes connected by each group convergence point in fine clustering is not more than the maximum fanout, and by adjusting the scaling ratio ratio, the number of convergence points connected is less than or equal to the maximum fanout, when the scaling ratio ratio is 1, the maximum fanout of each buffer Buffer can be fully utilized. The number of rough clustered registers / buffers insts, divide_number, maximum iteration number T, seed value seed for randomly generating points in the thread pool are input into the KmeansPlus algorithm for fine clustering, and the specific method of Kmeanplus algorithm is:

[0040] (1) randomly select a unit as the center point from the register / buffer to be clustered, calculate the Manhattan distance between the remaining devices and the center point, see formula (3):

[0041] D 1,l =|X1-X l |+|Y1-Y l | (3)

[0042] Where D 1,l is the sum of the distance difference of the center point 1 and other unselected units l along the X coordinate and Y coordinate directions.

[0043] (2) put the Manhattan distance between each register and the center point into the set Ω:

[0044] Ω={D1,2 D 1,3 ,...,D 1,n} (4)

[0045] where n represents the total number of units to be clustered, D 1,2 is the Manhattan distance between the center unit 1 and other units 2.

[0046] (3) Find the larger Manhattan distance, formula (5) uses all the calculated Manhattan distance divided by the total number of distances to get the probability distribution, the farther the distance, the easier to be selected as a new center point, from D p according to the probability to select a new center point.

[0047]

[0048] D p ={D′ 1,2 ,D′ 1,3 ,...,D′ 1,n} (6)

[0049] (4) Repeat (1)-(3) until k center points are found, k is the number of groups to be clustered.

[0050] (5) After finding k center points, traverse all the remaining units and use formula (7) to calculate the distance between two points, and the units with closer distance are summarized into the corresponding center point group:

[0051]

[0052] where m represents the unit selected as the center point, and l represents the remaining unit.

[0053] After coarse clustering, the results enter multi-threading through fine clustering tasks. For the example of 100k order of magnitude registers mentioned earlier, calculate divide_number for each coarse clustering result, and each thread in 8 threads is used to process two groups of registers / buffers using the KmeansPlus algorithm. The clustering point information and coordinates are put into the structure container, and each thread is destroyed and released after executing two groups of clustering. Repeat the process until all the grouped registers / buffers are clustered.

[0054] S5, in hierarchical clock tree synthesis, after the completion of a certain level of register / buffer fine clustering, the aggregation point needs to be instantiated, read the information and coordinates of each aggregation point in the structure container, judge whether the aggregation point instantiation will cause overlap or the line length will exceed the maximum line length, then instantiate each aggregation point as a buffer, and set the child of the buffer as the leaf node connected to the aggregation point. All buffers at this level are used as the input of the next level of coarse clustering until the number of buffers at a certain level is 1, indicating that the construction of the hierarchical clock tree synthesis has reached the clock source, and the clock source is connected to the last level of buffer, that is, the child of the clock source is set as the buffer. Finally, the DFS algorithm is used to forward propagate each leaf node from the clock source, calculate the delay Latency and global skew Skew of each path, and judge the quality of the clock tree synthesis. The delay and skew formulas are as follows:

[0055]

[0056] N is the number of registers and buffers in each path in the clock network, a path contains N-1 buffers and 1 register, buf delay is the delay value of the buffer, net_delay k,k+1 is the line length delay between unit k and unit k+1.

[0057]

[0058] Skew is the global skew, the difference between the longest path delay Latency and the shortest path delay.

[0059] The above specific embodiments and examples are specific supports for the technical idea of the present application, and cannot limit the protection scope of the present application. Any equivalent changes or equivalent modifications made according to the technical idea of the present application on the basis of the technical solutions of the present application still belong to the protection scope of the claims of the present application.

Claims

1. A clock tree synthesis method based on synchronized concurrency and hierarchical clustering, characterized in that, The method comprises the following steps: Step S1, reading all registers and physical information of clock sources according to a layout file, obtaining a target grouping number and a single-group register number threshold according to a register number and an available thread number; Step S2, performing coarse clustering grouping on the read-in registers by using a KmeansPlus algorithm according to the single-group register number threshold, judging whether the number of registers in each group is less than the single-group register number threshold, returning a result for fine clustering if the number is less than the threshold, or re-performing coarse clustering until the grouping result is less than the single-group register number threshold; Step S3, extracting the grouping result in step S2, combining the number of registers in the group and the maximum fanout max_fanout of a buffer Buffer used by an instantiated sink point to obtain a fine clustering grouping number divide_number, and applying a synchronous and concurrent KmeansPlus algorithm to perform fine clustering on all register groups; Step S4, extracting the fine clustering sink point coordinates in step S3, combining the size of the buffer used by the instantiated sink point to judge whether overlap occurs with the connected sub-registers, and calculating the line length between the sink point coordinates and the connected registers to judge whether each path exceeds the maximum line length constraint, and if the requirement is met, instantiating the buffer Buffer for each fine clustered group sink point, and taking all buffers Buffer at this level as inputs of the next level clustering; Step S5, extracting the buffer after instantiation in step S4 as a first-level synthesis result, taking all instantiated buffers at this level as leaf node inputs of a KmeansPlus algorithm for second-level coarse clustering, and iteratively performing steps S1 to S5 to perform bottom-up hierarchical clustering from registers to clock sources, and connecting leaf nodes and instantiated sink nodes at each level until the nodes at the last level are converged to the clock source.

2. The clock tree synthesis method based on synchronized concurrent and hierarchical clustering of claim 1, wherein, The specific method of step S1 for obtaining the target grouping number and the single-group register number threshold according to the register number and the available thread number is as follows: calculating the target grouping number according to the available thread number and the number of groups processed by each thread, and calculating the single-group register number threshold according to the total register number and the target grouping number.

3. The clock tree synthesis method based on synchronized concurrent and hierarchical clustering of claim 1, wherein, Step S2 inputs the registers insts, the single-group register number threshold n, the iteration number T, and the random seed value seed into the KmeansPlus method for coarse clustering.

4. The clock tree synthesis method based on synchronized concurrent and hierarchical clustering of claim 3, wherein, The KmeansPlus algorithm used in step S2 for coarse clustering is as follows: establishing a random generator gen; randomly selecting an inst as a center point from a plurality of insts; calculating the Manhattan distance of the remaining insts from the center point, finding an inst with the farthest Manhattan distance from the center point as a new center point, until n center points are found; traversing the remaining insts, and grouping them into the nearest center point as a group; and returning the constructed group.

5. The clock tree synthesis method based on synchronized concurrent and hierarchical clustering of claim 1, wherein, The step S3 utilizes the coarse clustering grouping result of step S2, determines the fine clustering group number divide_number according to the number of registers in each group, the maximum fan-out max_fanout of the used buffer Buffer and the scaling ratio ratio, inputs the single group of registers insts, the group number divide_number, the iteration number T and the random seed value seed into the synchronous concurrent KmeansPlus method for fine clustering, and registers are added to the thread pool for multi-thread processing through the fine clustering task. The clustering return value is set as shared data, and the shared data is locked to protect the data.

6. The clock tree synthesis method based on synchronized concurrent and hierarchical clustering of claim 1, wherein, The step S4 extracts the convergence point obtained by the KmeansPlus method fine clustering of each group in step S3, instantiates the convergence point as a buffer Buffer as the current level clock tree clustering result, and takes the buffers Buffer obtained by all fine clustering results in the current level as leaf nodes of the next level of the clock tree.

7. The clock tree synthesis method based on synchronized concurrent and hierarchical clustering of claim 1, wherein, The step S5 extracts the instantiated buffer of step S4 as the first level result of hierarchical clock tree synthesis, takes all instantiated buffers of this level as leaf nodes of the second level clock tree, and inputs the leaf nodes of the second level as the starting point until the previous level of the clock source. All convergence points are buffers Buffer, which indicates that the input of coarse clustering and fine clustering starts from the second level. At this time, the information of each level is replaced by buffer information.

8. The clock tree synthesis method based on synchronized concurrent and hierarchical clustering of claim 1, wherein, The step S5 performs coarse clustering and fine clustering on each leaf node through hierarchical clock tree synthesis to obtain a convergence node, until the number of convergence nodes is 1, which indicates that the buffer instantiated from the convergence node is a subunit of the clock source, and the clock tree synthesis is completed by connecting the clock source.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program runs to perform the steps of the clock tree synthesis method of any one of claims 1 to 8.

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