Circuit structure of low-order biological neural network based on memristor and application method

Abstract

The invention discloses a circuit structure of a low-order biological neural network based on a memristor and an application method. The circuit structure comprises the following steps: an encoding module carries out expansion processing on a 4-bit binary input vector into a 16-bit sample expansion vector; the sample memory module maps the sample expansion vector into a first group of memory pulse signals, inputs the first group of memory pulse signals into the first memristor array to adjust a corresponding resistance value, and stores the sample into the first memristor array; the tag memory module maps a predefined operation result between the sample expansion vector and a predefined sample tag vector into a second group of memory pulse signals, and inputs the second group of memory pulse signals to the second memristor array to adjust a corresponding resistance value; the mapping relation between the samples and the labels is stored in a second memristor array; and the prediction module reads corresponding prediction voltages from the first memristor array and the second memristor array, and processes the prediction voltages through preset algebraic operation to obtain a prediction probability.

Description

Technical Field

[0001] The present invention relates to the field of artificial neural network hardware, and particularly to a circuit structure and application method of a low-order biological neural network based on memristors. Background Art

[0002] With the rapid development of artificial intelligence technology, the computational requirements of neural networks are increasing day by day. However, in the traditional von Neumann architecture, the computing unit (processor) and the storage unit (memory) are independent of each other, and data needs to be frequently transferred between the two, resulting in problems such as the Memory Wall and Bandwidth Bottleneck. This architecture limits the computing efficiency, and at the same time brings high energy consumption and latency, becoming a bottleneck for the performance improvement of neural networks.

[0003] Memristors, with their non-volatile, analog conductance characteristics, and unique advantages of in-memory computing, provide new possibilities for the hardware implementation of neural networks. In particular, memristor crossbars can efficiently perform matrix operations and support large-scale parallel computing, thus significantly improving the computing performance. In addition, the network structure of low-order biological neural networks highly matches the in-memory computing characteristics of memristors, opening up an innovative path to break through the limitations of traditional computing architectures.

[0004] Therefore, developing an efficient computing hardware based on memristors to support the operation of low-order biological neural networks has become an important technical challenge that needs to be solved urgently. Summary of the Invention

[0005] The present invention provides a circuit structure and application method of a low-order biological neural network based on memristors to solve the above problems existing in the prior art.

[0006] To achieve the above object, the present invention provides the following technical solutions: A circuit structure of a low-order biological neural network based on memristors, comprising: An encoding module, configured to expand and process a 4-bit binary input vector into a 16-bit sample expansion vector; A sample memory module, configured to map the sample expansion vector into a first group of memory pulse signals, input the first group of memory pulse signals to a first memristor array to adjust the corresponding resistance values, and implement storing the sample into the first memristor array; A label memory module, configured to map the predefined operation result between the sample expansion vector and a predefined sample label vector into a second group of memory pulse signals, and input the second group of memory pulse signals to a second memristor array to adjust the corresponding resistance values, and implement storing the mapping relationship between the sample and the label into the second memristor array; The prediction module is used to read the corresponding predicted voltages from the first memristor array and the second memristor array, and process the predicted voltages through a preset algebraic operation to obtain a predicted probability.

[0007] Among them, the expansion processing steps in the encoding module include: Accepts a binary input vector of length 4 , where each element The value is {0,1}; The first bit of the extended vector is set to 0; Copy bits 2 to 5 directly from the elements of the input vector X, that is ; Calculate the binary XOR results of all bits from 6 to 11 ,Right now ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ; Calculate the ternary XOR results of all bits 12 to 15 ,Right now ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ; Calculate the 16th bit of the quaternary XOR result ⊕ ⊕ ⊕ ; Replace each element 0 in the resulting 16-bit vector with -1 to obtain a sample extension vector.

[0008] The first memristor array and the second memristor array are both composed of 16 1T1R structural units, wherein each 1T1R structural unit includes a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

[0009] Among them, the mapping relationship of the memory pulse signal in the sample memory module is: -1 in the sample extension vector corresponds to , 1 corresponds to ,in is a preset memory voltage value, used to adjust the resistance state of the memristor array; The mapping relationship of the memory pulse signal in the tag memory module is: -1 in the predefined operation result corresponds to , 1 corresponds to .

[0010] The resistance value of the memristor in the sample memory module and the tag memory module is updated by applying positive and negative pulses of the same amplitude to the top electrode of the memristor and applying pulses of different amplitudes to the gate of the transistor to achieve dynamic adjustment of the resistance value of the memristor; Among them, the resistance value of the memristor decreases when a positive pulse is applied, and the resistance value of the memristor increases when a negative pulse is applied.

[0011] Among them, the resistance change ΔR and the number of pulses N satisfy the linear relationship ΔR∝N.

[0012] Wherein, a parallel computing method is adopted to simultaneously update the resistance values ​​of the memristor units in the same row.

[0013] The predefined operation in the label memory module is the matrix multiplication of the sample extension vector and the sample label, where the sample label takes the value of {-1,1}.

[0014] The prediction module includes a preset memristor, a read memristor, a fixed resistor and an operational amplifier; By applying a preset current to the top electrodes of the preset memristor and the read memristor, and predicted current , generating a differential voltage signal; the differential voltage signal is processed by a differential amplifier circuit to generate an amplified predicted voltage; a preset algebraic operation is performed using the predicted voltage to generate a processed output signal; and a predicted probability is obtained through the output signal; The differential amplifier circuit is composed of four fixed resistors and an operational amplifier, and the output voltage is equivalent to the difference between the resistance of the preset memristor and the resistance of the read memristor; The predicted probability is calculated by the following formula:

[0015] Among them, the sample prediction voltage represents: in the memristor array of the sample memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module; the tag prediction voltage represents: in the memristor array of the tag memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module.

[0016] An application method of a circuit structure of a low-order biological neural network based on a memristor, comprising: S1: Expand the 4-bit binary input vector into a 16-bit sample expansion vector; S2: Mapping the sample extension vector into a first group of memory pulse signals, inputting the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance value, and realizing storing the sample into the first memristor array; S3: mapping a predefined operation result between the sample extension vector and the predefined sample label vector into a second set of memory pulse signals, and inputting the second set of memory pulse signals into the second memristor array to adjust the corresponding resistance value, so as to store the mapping relationship between the sample and the label in the second memristor array; S4: Reading corresponding predicted voltages from the first memristor array and the second memristor array, and processing the predicted voltages through a preset algebraic operation to obtain predicted probabilities.

[0017] Compared with the prior art, the present invention has the following advantages: the input vector encoding method of the present invention is unique, and the method of extending the vector is adopted, so that the encoded vectors have memory and distinguishability. By constructing an extended vector containing all possible binary and high-order XOR combinations, the similarities and differences between different input samples can be effectively expressed in the vector space, thereby enhancing the classification and recognition capabilities of the neural network, and improving the calculation accuracy and generalization capabilities. In terms of updating the resistance value of the memristor, the present invention adopts a dynamic pulse adjustment strategy, which realizes accurate weight adjustment by applying positive and negative pulses of fixed amplitude to the top electrode of the memristor and applying pulses of different amplitudes to the transistor gate at the same time. Compared with the traditional fixed pulse programming method, the dynamic pulse control strategy of the present invention can effectively improve the weight writing accuracy, reduce the drift error of the memristor, and improve the stability and trainability of the neural network.

[0018] Other features and advantages of the present invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the present invention.

[0019] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings: Figure 1 Schematic diagram of the circuit structure of a low-order biological neural network based on a memristor in an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit structure of the encoding module in an embodiment of the present invention; Figure 3A schematic diagram of the circuit structure of a sample memory module in an embodiment of the present invention; Figure 4 This is a schematic diagram of the circuit structure of a tag memory module in an embodiment of the present invention; Figure 5 This is a schematic diagram of the circuit structure of the prediction module in an embodiment of the present invention; Figure 6 1 is a resistance value variation curve diagram in an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0022] The embodiment of the present invention provides a circuit structure of a low-order biological neural network based on a memristor, comprising: The encoding module is used for expanding the 4-bit binary input vector into a 16-bit sample expansion vector; A sample memory module, used for mapping the sample extension vector into a first group of memory pulse signals, inputting the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance value, and realizing storing the sample into the first memristor array; A label memory module, used for mapping a predefined operation result between a sample extension vector and a predefined sample label vector into a second set of memory pulse signals, and inputting the second set of memory pulse signals into a second memristor array to adjust corresponding resistance values, so as to store a mapping relationship between samples and labels in the second memristor array; The prediction module is used to read the corresponding predicted voltages from the first memristor array and the second memristor array, and process the predicted voltages through a preset algebraic operation to obtain a predicted probability.

[0023] The working principle of the above technical solution is: the encoding module expands the input 4-bit binary vector (4-bit data composed of 0 and 1) into a 16-bit sample extension vector. The encoding module receives the 4-bit binary input vector and converts it into a 16-bit vector through a specific extension processing operation. This process increases the dimension of the data, making it more suitable for subsequent storage and calculation in the memristor array. The expanded 16-bit sample extension vector provides the neural network with richer information expression capabilities.

[0024] The sample memory module maps the 16-bit sample extension vector into the first set of memory pulse signals, and inputs these signals into the first memristor array to store the sample data by adjusting the resistance value. The sample memory module converts the 16-bit sample extension vector output by the encoding module into a series of pulse signals (called the first set of memory pulse signals), which are applied to the first memristor array to "record" the sample information by changing the resistance value of the memristor. The resistance state of the memristor can reflect the characteristics of the input sample, thereby completing the storage of the sample data.

[0025] The label memory module maps the operation results between the sample extension vector and the predefined sample label vector into a second set of memory pulse signals, and inputs these signals into the second memristor array, and stores the mapping relationship between the sample and the label by adjusting the resistance value. The label memory module first performs a predefined operation (such as matrix multiplication) on the sample extension vector and the sample label vector to obtain a result representing the association between the sample and the label. The result is then converted into a second set of memory pulse signals and input into the second memristor array. The resistance value of the memristor array is adjusted according to these pulse signals to store the mapping relationship between the sample and the label.

[0026] The prediction module reads the predicted voltages from the first memristor array and the second memristor array, and processes these voltages through preset algebraic operations to obtain the predicted probabilities. In the prediction stage, the prediction module reads the corresponding predicted voltages by applying current signals to the two memristor arrays. These voltage values ​​reflect the previously stored sample information and its mapping relationship with the labels. Subsequently, by performing algebraic operations (such as addition, multiplication, etc.) on these voltage values, the predicted probability of the input sample is calculated to complete the classification or prediction task.

[0027] like Figure 1 As shown in the figure, a 16-bit sample extension vector is obtained by inputting a 4-bit binary input vector to the encoding module for expansion processing. The memory voltage signal corresponding to the sample extension vector is input to the sample memory module to realize sample storage; at the same time, the memory voltage signal corresponding to the matrix multiplication result of the sample extension vector and the sample label is input to the label memory module to realize sample and label storage. Finally, the memory information stored in the sample memory module and the label memory module is read respectively through the prediction current signal to obtain the prediction voltage, and then algebraic operation is performed to obtain the prediction probability.

[0028] Explanation: The memory voltage signal and the memory pulse signal are equivalent technical features, both referring to signals used to adjust the resistance value of the memristor. The sample memory module and the label memory module are implemented by the first memristor array and the second memristor array respectively. The memory voltage signal corresponding to the sample extension vector is obtained by mapping the sample extension vector. The predefined operations include but are not limited to matrix multiplication operations.

[0029] The beneficial effects of the above technical solution are as follows: the circuit structure constructs a low-order biological neural network based on memristors through the collaborative work of the encoding module, sample memory module, label memory module and prediction module, which can efficiently store and process sample data and its mapping relationship with labels, thereby improving the classification and recognition capabilities of the neural network.

[0030] In another embodiment, the expansion processing step in the encoding module includes: Accepts a binary input vector of length 4 , where each element The value is {0,1}; The first bit of the extended vector is set to 0; Copy bits 2 to 5 directly from the elements of the input vector X, that is ; Calculate the binary XOR results of all bits from 6 to 11 ,Right now ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ; Calculate the ternary XOR results of all bits 12 to 15 ,Right now ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ; Calculate the 16th bit of the quaternary XOR result ⊕ ⊕ ⊕ ; Replace each element 0 in the resulting 16-bit vector with -1 to obtain a sample extension vector.

[0031] The working principle of the above technical solution is as follows: Figure 2 As shown, the schematic diagram of the circuit structure of the encoding module includes: converting a 4-bit binary input vector , where each element The value is , and the expansion processing operation is expanded into a 16-bit sample expansion vector. The encoding module consists of 17 binary memristors and 4 fixed resistors, where the high-resistance resistance of the memristor is , the low resistance value of the memristor is , the resistance of the fixed resistor , the high resistance state of the memristor represents a logic 0, and the low resistance state represents a logic 1. In the embodiment of the present invention, the setting voltage of the memristor is set , reset voltage , parameter voltage Need to meet ; The specific encoding steps are as follows: Step S1: Initialize 17 memristors to a high impedance state; Step S2: According to the logic Changing the memristor and The state, according to the logic Changing the memristor The state of the memristor Set to the state corresponding to logic 0; Step S3: and The two-bit XOR result is stored in the memristor ; Step S3 includes: memristor The status represents , by setting the voltage represent ,in , , ; when hour, ,like , at this time the memristor The partial pressure is , store logic 0; if , at this time the memristor The partial pressure is , storage logic 1; when hour, ,like , at this time the memristor The partial pressure is , store logic 1; if , at this time the memristor The partial pressure is , store logic 0; Step S4, according to the operation of step S3, the following XOR operation is calculated in parallel. To avoid repetition, the operation steps are described below while omitting the description of the same details: Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The state represents 0, by setting the voltage represent , calculate 0 and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Step S5, according to the operation of step S3, the following XOR operation is calculated in parallel. To avoid repetition, the operation steps are described below while omitting the description of the same details: Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The state represents 0, by setting the voltage represent , calculate 0 and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Step S6, according to the operation of step S3, the following XOR operation is calculated in parallel. To avoid repetition, the operation steps are described below while omitting the description of the same details: Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Step S7, read the memristors in sequence , , , , , , , , , , , , , , , The state gets the 16-bit sample extension vector.

[0032] The beneficial effects of the above technical solution are as follows: the encoding module expands the 4-bit binary input vector into a 16-bit sample extension vector, and by constructing an extension vector containing binary and high-order XOR combinations, it enhances the expressiveness of the input data, enables the similarities and differences between samples to be effectively distinguished, and improves the computational accuracy and generalization ability of the neural network.

[0033] In another embodiment, the first memristor array and the second memristor array are both composed of 16 1T1R structural units, wherein each 1T1R structural unit includes a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

[0034] The working principle of the above technical solution is as follows: Figure 3 As shown, a schematic diagram of the circuit structure of a sample memory module includes: a memristor array composed of 16 1T1R structural units, wherein each 1T1R structural unit includes a transistor and a memristor, the bottom electrode of the memristor is connected to the drain of the transistor, and the source of the transistor in the memristor array is grounded. The high-resistance resistance value of the selected memristor is 16kΩ, the low-resistance resistance value is 100Ω, and the 16 memristors are initialized to 7kΩ. Among them, the transistor used in this embodiment is a field effect transistor (such as MOSFET), or other devices with the same switching characteristics. In addition, in this embodiment, the source and drain of the transistor used are symmetrical in structure, so in practical applications, the two can be interchanged and there is no strict distinction.

[0035] like Figure 4 As shown, the circuit structure diagram of the tag memory module includes: storage process and Figure 3 The sample memory modules shown are the same, but the stored object is the matrix multiplication result of the sample extension vector and the sample label. Therefore, in order to avoid repetition, the description of the same details is omitted while describing the operation steps of the training method below. Specifically, the label memory module is composed of a memristor array composed of 16 1T1R structural units, each of which includes a transistor and a memristor, the bottom electrode of the memristor is connected to the drain of the transistor, and the sources of all transistors are grounded.

[0036] The beneficial effects of the above technical solution are as follows: the first memristor array and the second memristor array are composed of 16 1T1R structural units, which can efficiently store and read sample data and its label mapping relationship, thereby improving the storage density and read and write speed of the circuit.

[0037] In another embodiment, the mapping relationship of the memory pulse signal in the sample memory module is: -1 in the sample extension vector corresponds to , 1 corresponds to , where is a preset memory voltage value used to adjust the resistance state of the memristor array; The mapping relationship of the memory pulse signals in the tag memory module is: -1 in the predefined operation result corresponds to , and 1 corresponds to .

[0038] The working principle of the above technical solution is: To store the first sample, the memory pulse signals corresponding to the 16-bit sample expansion vector are input to the top electrode of the memristor to adjust the resistance value of the memristor. When the i-th bit of the sample expansion vector is -1, , the corresponding pulse signal is applied; when the i-th bit of the sample expansion vector is 1, , the corresponding pulse signal is applied, where , the corresponding rules of are as follows: When the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ; To store the second and subsequent samples, the memory pulse signals corresponding to the 16-bit sample expansion vector are input to the top electrode of the memristor to adjust the resistance value of the memristor. When the i-th bit of the sample expansion vector is -1, , the corresponding pulse signal is applied; when the i-th bit of the sample expansion vector is 1, , the corresponding pulse signal is applied, where , the corresponding rules of For the case where the value represented by the current memristor resistance is -1, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ; For the case where the value represented by the current memristor resistance is 1, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ; For the case where the value represented by the current memristor resistance is -2, when the i-th bit of the sample expansion vector is -1, ; when the i-th bit of the sample expansion vector is 1, ; For the case where the value represented by the current memristor resistance is 2, when the i-th bit of the sample expansion vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of -3, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of 3, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of -4, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of 4, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of -5, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of 5, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of -6, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of 6, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of -7, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current value represented by the memristor resistance is 7, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of -8, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of 8, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of -9, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; For the case where the current memristor resistance represents a value of 9, when the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; Storing samples in the memristor array is achieved.

[0039] The beneficial effect of the above technical solution is that the sample memory module and the label memory module accurately map the sample extension vector and the predefined operation result into a pulse signal through a reasonable memory pulse signal mapping relationship, thereby realizing precise adjustment of the resistance value of the memristor.

[0040] In another embodiment, the resistance value of the memristor in the sample memory module and the tag memory module is updated by applying positive and negative pulses of the same amplitude to the top electrode of the memristor and applying pulses of different amplitudes to the gate of the transistor to achieve dynamic adjustment of the resistance value of the memristor; Among them, the resistance value of the memristor decreases when a positive pulse is applied, and the resistance value of the memristor increases when a negative pulse is applied.

[0041] The working principle of the above technical solution is: in the sample memory module and the label memory module, the resistance value of the memristor is updated by applying positive and negative pulses of different amplitudes to the top electrode of the memristor and applying pulses of different amplitudes to the gate of the transistor to achieve dynamic adjustment of the resistance value of the memristor.

[0042] The specific operation process includes: When a positive pulse is applied: the resistance value of the memristor will decrease. This is because the positive pulse can cause the charge inside the memristor to be redistributed, thereby reducing its resistance value, which represents the update of the memristor state. When a negative pulse is applied: the resistance value of the memristor will increase. The application of a negative pulse will cause the charge inside the memristor to be rearranged, thereby increasing its resistance value, indicating a change in the memristor state. The effect of different pulse amplitudes on the transistor gate: At the same time, by applying pulses of different amplitudes to the transistor gate, the adjustment of the memristor resistance value can be further controlled. The control signal of the transistor gate works in synergy with the pulse signal of the memristor to ensure that the resistance value of the memristor is accurately adjusted under different operating conditions.

[0043] The beneficial effects of the above technical solution are as follows: the sample memory module and the label memory module adopt a dynamic pulse adjustment strategy to update the resistance value of the memristor, and by applying a combination of positive and negative pulses and pulses of different amplitudes, dynamic and precise adjustment of the resistance value is achieved, thereby improving the weight writing accuracy, reducing drift errors, and enhancing the stability and trainability of the neural network.

[0044] In another embodiment, the resistance change ΔR and the pulse number N satisfy a linear relationship ΔR∝N.

[0045] The working principle of the above technical solution is: the resistance change ΔR and the number of pulses N satisfy the linear relationship ΔR∝N, wherein the predicted voltage obtained by the differential amplifier circuit is equivalent to representing the difference in the resistance of the memristor. Since the resistance of the memristor is in a linear relationship, the predicted voltage represents the sample memory information.

[0046] The beneficial effects of the above technical solution are: the change in the resistance value of the memristor is linearly related to the number of pulses, which simplifies the resistance value adjustment process and improves the control accuracy and response speed of the circuit structure.

[0047] In another embodiment, a parallel computing method is adopted to simultaneously update the resistance values ​​of the memristor units in the same row.

[0048] The working principle of the above technical solution is: the resistance value of the same row of memristor units can be efficiently updated simultaneously by using parallel computing. This method utilizes the parallel access capability of the array structure and control circuit, combined with data parallelism and synchronization mechanism, to significantly improve the update speed and efficiency. This feature is particularly important in scenarios that require processing large amounts of data, such as neural network training and real-time computing tasks.

[0049] According to the operation of step S3, the following XOR operation is calculated in parallel. To avoid repetition, the operation steps are described below while omitting the description of the same details: Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; Memristor The status represents , by setting the voltage represent ,calculate and The two-bit XOR result is stored in the memristor ; The beneficial effect of the above technical solution is: the resistance values ​​of the same row of memristor units are updated simultaneously through parallel computing, which improves the computational efficiency of the circuit and shortens the time required for training and prediction.

[0050] In another embodiment, the predefined operation in the label memory module is a matrix multiplication of the sample extension vector and the sample label, wherein the sample label takes a value of {-1, 1}.

[0051] The working principle of the above technical solution is: matrix multiplication of sample extension vector and sample label, characterized in that the label corresponding to each sample takes the value of {-1,1}, thereby calculating the matrix multiplication result and storing the sample and label in the memristor array.

[0052] The beneficial effects of the above technical solution are as follows: the label memory module uses the matrix multiplication of the sample extension vector and the sample label as a predefined operation, which effectively expresses the mapping relationship between the sample and the label and improves the classification accuracy of the neural network.

[0053] In another embodiment, the prediction module includes a preset memristor, a read memristor, a fixed resistor, and an operational amplifier; By applying a preset current to the top electrodes of the preset memristor and the read memristor, and predicted current , generating a differential voltage signal; the differential voltage signal is processed by a differential amplifier circuit to generate an amplified predicted voltage; a preset algebraic operation is performed using the predicted voltage to generate a processed output signal; and a predicted probability is obtained through the output signal; The differential amplifier circuit is composed of four fixed resistors and an operational amplifier, and the output voltage is equivalent to the difference between the resistance of the preset memristor and the resistance of the read memristor; The predicted probability is calculated by the following formula:

[0054] Among them, the sample prediction voltage represents: in the memristor array of the sample memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module; the tag prediction voltage represents: in the memristor array of the tag memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module.

[0055] The working principle of the above technical solution is as follows: Figure 5 As shown, the schematic diagram of the circuit structure of the prediction memory module provided by the embodiment of the present invention includes: It consists of a memristor, a fixed resistor and an operational amplifier. and the memristor being read A preset current is applied to the top electrode and predicted current , the predicted voltage is obtained through the differential amplifier circuit.

[0056] Specifically, the prediction operation steps are as follows: Step S8: Preset memristor Initialized to 7kΩ, the memristor is read One of the 16 memristors in the sample memory module is read sequentially; Step S9: Settings and ; The predicted sample is input into the encoding module to obtain a 16-bit sample extension vector. When the i-th bit of the sample extension vector is -1, ; When the i-th bit of the sample extension vector is 1, ; Step S10: Input and To preset memristor and the memristor being read The top electrodes of the differential amplifier circuits are and ; The differential amplifier circuit is connected through four fixed value resistors and an operational amplifier. In the embodiment of the present invention, the relationship is: ; The operational amplifier is in a negative feedback state, so the voltages at the non-inverting input and the inverting input are equal, that is: ; and A voltage divider circuit is formed, so ; and A voltage dividing circuit is formed, so ; According to the virtual short characteristic of the operational amplifier, it can be deduced that ; According to the virtual open characteristic of the operational amplifier, it can be deduced that , that is ; Substitute After arrangement, we get ; Under the conditions of the embodiments of the present invention The predicted voltage is obtained ; The predicted voltage obtained through the differential amplifier circuit equivalently represents the difference in the resistance values of the memristors. Since the resistance values of the memristors are linearly related, the predicted voltage represents the sample memory information.

[0057] Step S11: Repeat step S8, but the memristor to be read is one of the 16 memristors in the label memory module; Step S12: Repeat step S9, but perform matrix multiplication on the sample expansion vector corresponding to the sample to be predicted and the sample label, and set according to the rules of step S2 through the result of the matrix multiplication and ; Step S13: Repeat step S10, and the predicted voltage represents the label memory information.

[0058] The predicted voltage obtains the predicted probability through algebraic operations, and the process of the predicted probability operation can be expressed by the following formula:

[0059] In the formula, the sample predicted voltage is the voltage obtained when the memristor included in the memristor array in the sample memory module is used as the memristor to be read, which represents the number of memory times of the sample to be predicted in the sample memory module; the label predicted voltage is the voltage obtained when the memristor included in the memristor array in the label memory module is used as the memristor to be read, which represents the number of memory times of the label memory module when the corresponding label of the sample to be predicted is 1.

[0060] As Figure 6 shown, the resistance value change curve graph provided by the embodiments of the present invention includes: The pulse duration applied to the transistor gate each time is 0.1 s; The resistance value of the memristor can vary between 2 kΩ and 12 kΩ, and the adjustment amplitude each time is ±0.5 kΩ. Thus, starting from the initial state of 7 kΩ, the memristor can be adjusted up and down by 10 levels; In addition, since the sample has the characteristic that the first bit of its extension vector is -1, it means that at most 10 samples can be stored.

[0061] The bit width of the input vector can be between 2 and 4 bits to accommodate different computing requirements. In different application scenarios, the accuracy requirements of the input vector may be different. For example, in some low-power or resource-constrained environments, a 2-bit input vector may be sufficient to meet computing requirements and reduce storage and computing overhead. In scenarios where higher computing accuracy is required, using 3-bit or 4-bit input vectors can provide finer-grained information expression, thereby improving the system's recognition ability and classification accuracy. By supporting 2 to 4-bit input vectors, the system can balance computing accuracy and resource utilization, and flexibly adjust the input format according to specific application requirements to optimize overall performance.

[0062] The label vector can contain multiple elements, not just a single label. In some application scenarios, a sample may belong to multiple categories or have multiple related features at the same time. Therefore, the label vector can take the form of multiple elements, not just a single label. In order to support this multi-label storage and matching mechanism, the number of rows of the memristor array in the label memory module needs to match the number of elements in a label vector. This means that when the dimension of the label vector increases, the number of rows of the memristor array also increases accordingly to ensure that each label element can be correctly stored and retrieved. This design helps to enhance the flexibility of the system, enabling it to handle more complex classification tasks and support advanced functions such as multi-label learning.

[0063] The beneficial effects of the above technical solution are as follows: the prediction module uses a preset memristor, a read memristor, a fixed resistor and an operational amplifier to form a differential amplifier circuit, accurately reads and processes the predicted voltage, and improves the reliability and accuracy of the prediction results. The prediction probability is calculated by combining the sample prediction voltage and the label prediction voltage through a reasonably designed formula, accurately reflecting the prediction results of the sample, and further improving the prediction performance of the neural network.

[0064] In another embodiment, a method for applying a circuit structure of a low-order biological neural network based on a memristor includes: S1: Expand the 4-bit binary input vector into a 16-bit sample expansion vector; S2: Mapping the sample extension vector into a first group of memory pulse signals, inputting the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance value, and realizing storing the sample into the first memristor array; S3: mapping a predefined operation result between the sample extension vector and the predefined sample label vector into a second set of memory pulse signals, and inputting the second set of memory pulse signals into the second memristor array to adjust the corresponding resistance value, so as to store the mapping relationship between the sample and the label in the second memristor array; S4: Reading corresponding predicted voltages from the first memristor array and the second memristor array, and processing the predicted voltages through a preset algebraic operation to obtain predicted probabilities.

[0065] The working principle of the above technical solution is as follows: the expansion process in step S1 includes: Accepts a binary input vector of length 4 , where each element The value is {0,1}; The first bit of the extended vector is set to 0; Copy bits 2 to 5 directly from the elements of the input vector X, that is ; Calculate the binary XOR results of all bits from 6 to 11 ,Right now ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ; Calculate the ternary XOR results of all bits 12 to 15 ,Right now ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ; Calculate the 16th bit of the quaternary XOR result ⊕ ⊕ ⊕ ; Replace each element 0 in the resulting 16-bit vector with -1 to obtain a sample extension vector.

[0066] The first memristor array and the second memristor array used in the method are both composed of 16 1T1R structural units, wherein each 1T1R structural unit includes a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

[0067] The mapping relationship of the memory pulse signal in step S2 is: -1 in the sample extension vector corresponds to , 1 corresponds to ,in is a preset memory voltage value, used to adjust the resistance state of the memristor array; The memory pulse signal mapping relationship in step S3 is: -1 in the predefined operation result corresponds to , 1 corresponds to .

[0068] The memristor resistance value is updated in step S2 and step S3 as follows: by applying positive and negative pulses of the same amplitude to the top electrode of the memristor and applying pulses of different amplitudes to the transistor gate, the memristor resistance value is dynamically adjusted; wherein, when a positive pulse is applied, the memristor resistance value decreases, and when a negative pulse is applied, the memristor resistance value increases.

[0069] The change in resistance value ΔR and the number of pulses N satisfy the linear relationship ΔR∝N.

[0070] The resistance values ​​of the memristor units in the same row are updated simultaneously by using parallel computing.

[0071] The predefined operation in step S3 is the matrix multiplication of the sample expansion vector and the sample label, where the sample label takes the value of {-1, 1}.

[0072] Step S4 includes: applying a preset current to the top electrodes of the preset memristor and the read memristor respectively. and predicted current , generating a differential voltage signal; the differential voltage signal is processed by a differential amplifier circuit to generate an amplified predicted voltage; a preset algebraic operation is performed using the predicted voltage to generate a processed output signal; and a predicted probability is obtained through the output signal; The differential amplifier circuit is composed of four fixed resistors and an operational amplifier, and the output voltage is equivalent to the difference between the resistance of the preset memristor and the resistance of the read memristor; The predicted probability is calculated using the following formula:

[0073] Among them, the sample predicted voltage represents: in the memristor array used in step S2, when the memristor selected according to the predetermined conditions is used as the memristor to be read, the voltage obtained through the prediction process; the label predicted voltage represents: in the memristor array used in step S3, when the memristor selected according to the predetermined conditions is used as the memristor to be read, the voltage obtained through the prediction process.

[0074] The beneficial effects of the above technical solution are: by expanding the input vector, the memory and discrimination between samples are enhanced, and the classification and recognition capabilities of the neural network are effectively improved. The dynamic pulse adjustment strategy realizes accurate memristor resistance update, improves weight writing accuracy, and reduces drift error. Compared with traditional methods, this solution improves the stability and trainability of the neural network.

[0075] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention belong to the scope of equivalent technologies of the present invention, the present invention is also intended to include these modifications and variations.

Claims

1. A circuit structure of a low-order biological neural network based on a memristor, characterized in that: include: The encoding module is used for expanding the 4-bit binary input vector into a 16-bit sample expansion vector; A sample memory module, used for mapping the sample extension vector into a first group of memory pulse signals, inputting the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance value, and realizing storing the sample into the first memristor array; A label memory module, used for mapping a predefined operation result between a sample extension vector and a predefined sample label vector into a second set of memory pulse signals, and inputting the second set of memory pulse signals into a second memristor array to adjust corresponding resistance values, so as to store a mapping relationship between samples and labels in the second memristor array; The prediction module is used to read the corresponding predicted voltages from the first memristor array and the second memristor array, and process the predicted voltages through a preset algebraic operation to obtain a predicted probability.

2. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The extended processing steps in the encoding module include: Accepts a binary input vector of length 4 , where each element The value is {0,1}; The first bit of the extended vector is set to 0; Copy bits 2 to 5 directly from the elements of the input vector X, that is ; Calculate the binary XOR results of all bits from 6 to 11 ,Right now ⊕ , ⊕ , ⊕ , ⊕ , ⊕ , ⊕ ; Calculate the ternary XOR results of all bits 12 to 15 ,Right now ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ , ⊕ ⊕ ; Calculate the 16th bit of the quaternary XOR result ⊕ ⊕ ⊕ ; Replace each element 0 in the resulting 16-bit vector with -1 to obtain a sample extension vector.

3. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The first memristor array and the second memristor array are both composed of 16 1T1R structural units, wherein each 1T1R structural unit includes a transistor and a memristor, and the bottom electrode of the memristor is connected to the drain of the transistor.

4. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The mapping relationship of the memory pulse signal in the sample memory module is: -1 in the sample extension vector corresponds to , 1 corresponds to ,in is a preset memory voltage value, used to adjust the resistance state of the memristor array; The mapping relationship of the memory pulse signal in the tag memory module is: -1 in the predefined operation result corresponds to , 1 corresponds to .

5. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The resistance value of the memristor in the sample memory module and the label memory module is updated in the following way: by applying positive and negative pulses of the same amplitude to the top electrode of the memristor and applying pulses of different amplitudes to the gate of the transistor, the resistance value of the memristor is dynamically adjusted; wherein, when a positive pulse is applied, the resistance value of the memristor decreases, and when a negative pulse is applied, the resistance value of the memristor increases.

6. The circuit structure of the low-order biological neural network based on memristor according to claim 5, characterized in that: The change in resistance value ΔR and the number of pulses N satisfy the linear relationship ΔR∝N.

7. The circuit structure of the low-order biological neural network based on memristor according to claim 5, characterized in that: The resistance values ​​of the memristor units in the same row are updated simultaneously by using parallel computing.

8. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The predefined operation in the label memory module is the matrix multiplication of the sample extension vector and the sample label, where the sample label takes the value of {-1,1}.

9. The circuit structure of the low-order biological neural network based on memristor according to claim 1, characterized in that: The prediction module includes a preset memristor, a read memristor, a fixed resistor and an operational amplifier; By applying a preset current to the top electrodes of the preset memristor and the read memristor, and predicted current , generating a differential voltage signal; the differential voltage signal is processed by a differential amplifier circuit to generate an amplified predicted voltage; a preset algebraic operation is performed using the predicted voltage to generate a processed output signal; and a predicted probability is obtained through the output signal; The differential amplifier circuit is composed of four fixed resistors and an operational amplifier, and the output voltage is equivalent to the difference between the resistance of the preset memristor and the resistance of the read memristor; The predicted probability is calculated using the following formula: ； Among them, the sample prediction voltage represents: in the memristor array of the sample memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module; the tag prediction voltage represents: in the memristor array of the tag memory module, when the memristor selected according to predetermined conditions is used as the memristor to be read, the voltage obtained by the prediction module.

10. An application method of a circuit structure of a low-order biological neural network based on a memristor, characterized in that: include: S1: Expand the 4-bit binary input vector into a 16-bit sample expansion vector; S2: Mapping the sample extension vector into a first group of memory pulse signals, inputting the first group of memory pulse signals into the first memristor array to adjust the corresponding resistance value, and realizing storing the sample into the first memristor array; S3: mapping a predefined operation result between the sample extension vector and the predefined sample label vector into a second set of memory pulse signals, and inputting the second set of memory pulse signals into the second memristor array to adjust the corresponding resistance value, so as to store the mapping relationship between the sample and the label in the second memristor array; S4: Reading corresponding predicted voltages from the first memristor array and the second memristor array, and processing the predicted voltages through a preset algebraic operation to obtain predicted probabilities.

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