Pixel circuit, driving method and display device

Abstract

The application provides a pixel circuit, a driving method and a display device. The pixel circuit comprises a driving circuit, a first control circuit, a first setting circuit, a first energy storage circuit, a second energy storage circuit and a data writing circuit. The first control circuit controls the communication or disconnection between a power supply voltage terminal and a second node under the control of a first reset control signal. The first setting circuit writes a reference voltage into a first node under the control of the first reset control signal. The data writing circuit writes a data voltage into the first node under the control of a scanning signal. The first end of the first energy storage circuit is electrically connected with the first node, and the second end of the first energy storage circuit is electrically connected with a fourth node. The first end of the second energy storage circuit is electrically connected with the second node, and the second end of the second energy storage circuit is electrically connected with a third node. The application can guarantee the data voltage writing time and the display effect under the premise of guaranteeing the display uniformity when high-frequency display is performed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel circuit, a driving method and a display device. BACKGROUND

[0002] With the rapid development of AMOLED (Active-matrix organic light-emitting diode), medium and large size tablet computers and notebook computers become important development directions in the future; customers have more and more strong demand for high frequency display; the existing pixel circuit simultaneously performs threshold voltage compensation and data voltage writing, and high frequency technology causes time compression of a row, which cannot well compensate the threshold voltage of a driving transistor in a driving circuit, and cannot realize high frequency driving. SUMMARY

[0003] The main purpose of the present application is to provide a pixel circuit, a driving method and a display device, which solve the problem that the existing pixel circuit cannot guarantee data voltage writing time when high frequency display is performed, and cannot guarantee display effect on the premise of guaranteeing display uniformity.

[0004] In one aspect, the embodiment of the present application provides a pixel circuit, comprising a driving circuit, a first control circuit, a first setting circuit, a first energy storage circuit, a second energy storage circuit and a data writing circuit;

[0005] The control end of the driving circuit is electrically connected with a first node, the first end of the driving circuit is electrically connected with a second node, and the second end of the driving circuit is electrically connected with a third node; the driving circuit is used for generating a driving current under the control of the electric potential of the first node;

[0006] The first control circuit is electrically connected with a first reset control end, a power voltage end and the second node respectively, and is used for controlling the power voltage end and the second node to be connected or disconnected under the control of a first reset control signal provided by the first reset control end;

[0007] The first setting circuit is electrically connected with the first reset control end, a reference voltage end and the first node respectively, and is used for writing a reference voltage provided by the reference voltage end into the first node under the control of the first reset control signal;

[0008] The data writing circuit is electrically connected with a scanning end, a data line and the first node respectively, and is used for writing a data voltage provided by the data line into the first node under the control of a scanning signal provided by the scanning end;

[0009] The first end of the first energy storage circuit is electrically connected with the first node, and the second end of the first energy storage circuit is electrically connected with the fourth node.

[0010] The first end of the second energy storage circuit is electrically connected with the second node, and the second end of the second energy storage circuit is electrically connected with the third node.

[0011] Optionally, the pixel circuit further comprises a light emitting element, a first light emitting control circuit and a second light emitting control circuit.

[0012] The first light emitting control circuit is electrically connected with a light emitting control terminal, a power voltage terminal and the second node respectively, and is configured to control the power voltage terminal to be connected or disconnected with the second node under the control of a light emitting control signal provided by the light emitting control terminal.

[0013] The second light emitting control circuit is electrically connected with the light emitting control terminal, the third node and the first electrode of the light emitting element respectively, and is configured to control the third node to be connected or disconnected with the first electrode of the light emitting element under the control of the light emitting control signal provided by the light emitting control terminal.

[0014] The second electrode of the light emitting element is electrically connected with the first voltage terminal.

[0015] Optionally, the pixel circuit further comprises a second setting circuit and a third setting circuit.

[0016] The second setting circuit is electrically connected with a first initial control terminal, a first initial voltage terminal and the third node respectively, and is configured to write a first initial voltage provided by the first initial voltage terminal into the third node under the control of a first initial control signal provided by the first initial control terminal.

[0017] The third setting circuit is electrically connected with a second initial control terminal, a second initial voltage terminal and the first electrode of the light emitting element respectively, and is configured to write a second initial voltage provided by the second initial voltage terminal into the first electrode of the light emitting element under the control of a second initial control signal provided by the second initial control terminal.

[0018] Optionally, the first initial control terminal and the second initial control terminal are the same control terminal.

[0019] Optionally, the pixel circuit further comprises a fourth setting circuit.

[0020] The fourth setting circuit is electrically connected with a second reset control terminal, a reference voltage terminal and the fourth node respectively, and is configured to write a reference voltage provided by the reference voltage terminal into the fourth node under the control of a second reset control signal provided by the second reset control terminal.

[0021] Optionally, the driving circuit comprises a driving transistor, the first control circuit comprises a first transistor, the first setting circuit comprises a second transistor, the data writing circuit comprises a third transistor, the first energy storage circuit comprises a first capacitor, and the second energy storage circuit comprises a second capacitor.

[0022] The gate of the driving transistor is electrically connected with a first node, the first pole of the driving transistor is electrically connected with a second node, and the second pole of the driving transistor is electrically connected with a third node.

[0023] The gate of the first transistor is electrically connected with a first reset control end, the first pole of the first transistor is electrically connected with a power voltage end, and the second pole of the first transistor is electrically connected with the second node.

[0024] The gate of the second transistor is electrically connected with the first reset control end, the first pole of the second transistor is electrically connected with a reference voltage end, and the second pole of the second transistor is electrically connected with the first node.

[0025] The gate of the third transistor is electrically connected with a scanning end, the first pole of the third transistor is electrically connected with a data line, and the second pole of the third transistor is electrically connected with the first node.

[0026] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with a fourth node.

[0027] The first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with the third node.

[0028] Optionally, the first light-emitting control circuit comprises a fourth transistor, and the second light-emitting control circuit comprises a fifth transistor.

[0029] The gate of the fourth transistor is electrically connected with a light-emitting control end, the first pole of the fourth transistor is electrically connected with a power voltage end, and the second pole of the fourth transistor is electrically connected with the second node.

[0030] The gate of the fifth transistor is electrically connected with the light-emitting control end, the first pole of the fifth transistor is electrically connected with the third node, and the second pole of the fifth transistor is electrically connected with the first pole of a light-emitting element.

[0031] Optionally, the second setting circuit comprises a sixth transistor, and the third setting circuit comprises a seventh transistor.

[0032] The gate of the sixth transistor is electrically connected with a first initial control end, the first pole of the sixth transistor is electrically connected with a first initial voltage end, and the second pole of the sixth transistor is electrically connected with the third node.

[0033] The gate of the seventh transistor is electrically connected with the second initial control end, the first pole of the seventh transistor is electrically connected with the second initial voltage end, and the second pole of the seventh transistor is electrically connected with the first pole of the light emitting element.

[0034] Optionally, the fourth setting circuit comprises an eighth transistor.

[0035] The gate of the eighth transistor is electrically connected with the second reset control end, the first pole of the eighth transistor is electrically connected with the reference voltage end, and the second pole of the eighth transistor is electrically connected with the fourth node.

[0036] In a second aspect, an embodiment of the present application provides a driving method applied to the pixel circuit, wherein a refresh frame comprises a compensation stage and a data writing stage arranged in sequence; and the driving method comprises the following steps:

[0037] In the compensation stage, the first control circuit controls the communication between the power voltage end and the second node under the control of the first reset control signal, and the first setting circuit writes the reference voltage provided by the reference voltage end into the first node under the control of the first reset control signal.

[0038] At the beginning of the compensation stage, the driving circuit controls the communication between the second node and the third node under the control of the potential of the first node, charges the first energy storage circuit and the second energy storage circuit, changes the potential of the third node, and controls the disconnection between the second node and the third node under the control of the potential of the first node.

[0039] In the data writing stage, the data writing circuit writes the data voltage provided by the data line into the first node under the control of the scanning signal.

[0040] Optionally, the pixel circuit further comprises a second setting circuit and a third setting circuit; the refresh frame further comprises a reset stage arranged before the compensation stage; and the driving method further comprises the following steps:

[0041] In the reset stage, the second setting circuit writes the first initial voltage into the third node under the control of the first initial control signal, and the third setting circuit writes the second initial voltage into the first pole of the light emitting element under the control of the second initial control signal.

[0042] In the compensation stage, the second setting circuit controls the disconnection between the first initial voltage end and the third node under the control of the first initial control signal.

[0043] Optionally, the pixel circuit further comprises a fourth setting circuit; and the driving method further comprises the following steps:

[0044] In the reset stage, the compensation stage and the data writing stage, the fourth setting circuit writes the reference voltage into the fourth node under the control of the second reset control signal.

[0045] Optionally, the driving method further comprises:

[0046] In the compensation stage and the data writing stage, the third setting circuit writes the second initial voltage into the first pole of the light emitting element under the control of the second initial control signal.

[0047] Optionally, the pixel circuit further comprises a third setting circuit, a light emitting element, a first light emitting control circuit and a second light emitting control circuit; the holding frame comprises a setting stage and a holding light emitting stage arranged in sequence; the driving method comprises:

[0048] In the setting stage, the third setting circuit writes the second initial voltage into the first pole of the light emitting element under the control of the second initial control signal; the first light emitting control circuit controls the power voltage end and the second node to be disconnected under the control of the light emitting control signal; the second light emitting control circuit controls the third node and the first pole of the light emitting element to be disconnected under the control of the light emitting control signal.

[0049] In the holding light emitting stage, the first light emitting control circuit controls the power voltage end and the second node to be connected under the control of the light emitting control signal; the second light emitting control circuit controls the third node and the first pole of the light emitting element to be connected under the control of the light emitting control signal; and the driving circuit drives the light emitting element to emit light.

[0050] Optionally, the pixel circuit further comprises a second setting circuit, and the driving method further comprises:

[0051] In the setting stage, the second setting circuit writes the first initial voltage into the third node under the control of the first initial control signal.

[0052] In a third aspect, an embodiment of the present application provides a display device comprising the pixel circuit.

[0053] The pixel circuit has the advantages that the data voltage writing and the threshold voltage compensation are designed separately, the required one-line scanning time is less, the data voltage writing time can be ensured in high-frequency display, the pixel circuit can be fully charged through the data voltage under the premise of ensuring display uniformity, and the display effect is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0054] Figure 1 is a structural diagram of the pixel circuit according to an embodiment of the present application;

[0055] Figure 2is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0056] Figure 3 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0057] Figure 4 is a structural diagram of the pixel circuit according to at least one embodiment of the present application;

[0058] Figure 5 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0059] Figure 6 is Figure 5 is a working timing diagram of at least one embodiment of the pixel circuit shown in

[0060] Figure 7A is Figure 5 is a first working state schematic diagram of the pixel circuit according to at least one embodiment of the present application;

[0061] Figure 7B is Figure 5 is a first working state schematic diagram of the pixel circuit according to at least one embodiment of the present application;

[0062] Figure 7C is Figure 5 is a first working state schematic diagram of the pixel circuit according to at least one embodiment of the present application;

[0063] Figure 7D is Figure 5 is a first working state schematic diagram of the pixel circuit according to at least one embodiment of the present application;

[0064] Figure 8 is Figure 5 is a working timing diagram of at least one embodiment of the pixel circuit shown in

[0065] Figure 9 is Figure 5 is a working timing diagram of at least one embodiment of the pixel circuit shown in

[0066] Figure 10 is a circuit diagram of the pixel circuit according to at least one embodiment of the present application;

[0067] Figure 11 is Figure 10 is a working timing diagram of at least one embodiment of the pixel circuit shown in DETAILED DESCRIPTION

[0068] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] In all embodiments of this invention, the transistors used can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. In these embodiments, to distinguish between the two terminals of the transistor other than the gate, one terminal is referred to as the first terminal, and the other as the second terminal.

[0070] In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode can be the drain and the second electrode can be the source; or, the first electrode can be the source and the second electrode can be the drain.

[0071] like Figure 1 As shown, the pixel circuit of at least one embodiment of the present invention includes a driving circuit 10, a first control circuit 11, a first setting circuit 12, a first energy storage circuit 13, a second energy storage circuit 14, and a data writing circuit 15.

[0072] The control terminal of the driving circuit 10 is electrically connected to the first node N1, the first terminal of the driving circuit 10 is electrically connected to the second node N2, and the second terminal of the driving circuit 10 is electrically connected to the third node N3. The driving circuit 10 is used to generate a driving current under the control of the potential of the first node N1.

[0073] The first control circuit 11 is electrically connected to the first reset control terminal GR1, the power supply voltage terminal ELVDD, and the second node N2, respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the first reset control signal provided by the first reset control terminal GR1.

[0074] The first set circuit 12 is electrically connected to the first reset control terminal GR1, the reference voltage terminal REF and the first node N1 respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the first node N1 under the control of the first reset control signal;

[0075] The data writing circuit 15 is electrically connected to the scanning terminal GW, the data line Dj and the first node N1 respectively, and is used to write the data voltage provided by the data line Dj into the first node N1 under the control of the scanning signal provided by the scanning terminal GW.

[0076] The first end of the first energy storage circuit 13 is electrically connected with the first node N1, and the second end of the first energy storage circuit 13 is electrically connected with the fourth node N4.

[0077] The first end of the second energy storage circuit 14 is electrically connected with the second node N2, and the second end of the second energy storage circuit 14 is electrically connected with the third node N3.

[0078] The pixel circuit Figure 1 At least one embodiment of the pixel circuit shown in the working process, the refresh frame can include a compensation phase and a data write phase arranged in sequence;

[0079] In the compensation phase, the first control circuit 11 controls the communication between the power supply voltage end ELVDD and the second node N2 under the control of the first reset control signal, and the first set circuit 12 writes the reference voltage Vref provided by the reference voltage end REF into the first node N1 under the control of the first reset control signal;

[0080] At the beginning of the compensation phase, the driving circuit 10 controls the communication between the second node N2 and the third node N3 under the control of the potential of the first node N1, charges the first energy storage circuit 13 and the second energy storage circuit 14, and changes the potential of the third node N3 until the driving circuit 10 controls the disconnection between the second node N2 and the third node N3 under the control of the potential of the first node N1 to perform threshold voltage compensation;

[0081] In the data write phase, the data write circuit 15 writes the data voltage provided by the data line Dj into the first node N1 under the control of the scanning signal.

[0082] The pixel circuit in at least one embodiment of the present application separates the design of data voltage writing and threshold voltage compensation in the working process, requires less scanning time of a row, so that in high-frequency display, the data voltage writing time can be ensured, the pixel circuit can be fully charged by the data voltage under the premise of ensuring the display uniformity, and the display effect is ensured.

[0083] In the pixel circuit in at least one embodiment of the present application, the first control circuit 11 and the first set circuit 12 share the first reset control end, so that the number of GOA (Gate On Array, gate driving circuit arranged on the array substrate) modules used by the display device can be reduced, and narrow frame can be realized.

[0084] As Figure 2 As Figure 1 Based on at least one embodiment of the pixel circuit shown, the pixel circuit in at least one embodiment of the present application further comprises a light emitting element E1, a first light emitting control circuit 21 and a second light emitting control circuit 22.

[0085] The first light-emitting control circuit 21 is electrically connected to the light-emitting control terminal EM, the power supply voltage terminal ELVDD and the second node N2 respectively, and is used to control the connection or disconnection between the power supply voltage terminal ELVDD and the second node N2 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0086] The second light-emitting control circuit 22 is electrically connected to the light-emitting control terminal EM, the third node N3, and the first pole of the light-emitting element E1, respectively, and is used to control the connection or disconnection between the third node N3 and the first pole of the light-emitting element E1 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0087] The second electrode of the light-emitting element E1 is electrically connected to the first voltage terminal V1.

[0088] Optionally, the first voltage terminal can be a low voltage terminal.

[0089] Optionally, the light-emitting element can be an OLED (Organic Light-Emitting Diode), the first electrode of the light-emitting element can be an anode, and the second electrode of the light-emitting element can be a cathode, but this is not a limitation. In specific implementations, the light-emitting element can be other types of light-emitting diodes.

[0090] The pixel circuit described in at least one embodiment of the present invention further includes a second setting circuit and a third setting circuit;

[0091] The second setting circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first initial control signal provided by the first initial control terminal;

[0092] The third setting circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

[0093] In a specific implementation, the pixel circuit may further include a second setting circuit and a third setting circuit (T8); the second setting circuit, under the control of the first initial control signal, writes the first initial voltage into the third node to initialize the potential of the third node; the third setting circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element to clear the residual charge on the first electrode of the light-emitting element.

[0094] like Figure 3 As shown, in Figure 2Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a second set circuit 32 and a third set circuit 33;

[0095] The second setting circuit 32 is electrically connected to the first initial control terminal GI1, the first initial voltage terminal I1 and the third node N3 respectively, and is used to write the first initial voltage Vinit1 provided by the first initial voltage terminal I1 into the third node N3 under the control of the first initial control signal provided by the first initial control terminal GI1.

[0096] The third setting circuit 33 is electrically connected to the second initial control terminal GI2, the second initial voltage terminal I2 and the first pole of the light-emitting element E1, respectively, and is used to write the second initial voltage Vinit2 provided by the second initial voltage terminal I2 into the first pole of the light-emitting element E1 under the control of the second initial control signal provided by the second initial control terminal GI2.

[0097] In at least one embodiment of the present invention, the first initial control terminal and the second initial control terminal are the same control terminal, so as to reduce the number of control terminals used, thereby reducing the number of GOA (Gate On Array) modules used in the display device, which is beneficial to achieving a narrow bezel.

[0098] The pixel circuit described in at least one embodiment of the present invention further includes a fourth setting circuit;

[0099] The fourth set circuit is electrically connected to the second reset control terminal, the reference voltage terminal, and the fourth node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the fourth node under the control of the second reset control signal provided by the second reset control terminal.

[0100] In a specific implementation, the pixel circuit may further include a fourth setting circuit, which, under the control of the second reset control signal, writes a reference voltage into the fourth node to set the potential of the fourth node.

[0101] like Figure 4 As shown, in Figure 3 Based on at least one embodiment of the pixel circuit shown, the pixel circuit of at least one embodiment of the present invention further includes a fourth setting circuit 34;

[0102] The fourth set circuit 34 is electrically connected to the second reset control terminal GR2, the reference voltage terminal REF, and the fourth node N4, respectively, and is used to write the reference voltage Vref provided by the reference voltage terminal REF into the fourth node N4 under the control of the second reset control signal provided by the second reset control terminal GR2.

[0103] The present application Figure 4 At least one embodiment of the pixel circuit shown in the working process further comprises a reset stage arranged before the compensation stage;

[0104] In the reset stage, the second setting circuit 32 writes the first initial voltage Vinit1 into the third node N3 under the control of the first initial control signal; the third setting circuit 33 writes the second initial voltage Vinit2 into the first electrode of the light emitting element E1 under the control of the second initial control signal.

[0105] In the compensation stage, the second setting circuit 32 controls the disconnection between the first initial voltage terminal I1 and the third node N3 under the control of the first initial control signal.

[0106] In the specific implementation, the transistor included in the first control circuit 11 is turned on only after the transistor included in the second setting circuit 32 is turned off, so that the setting of the third node N3 does not affect the threshold voltage compensation of the driving transistor included in the driving circuit.

[0107] The present application Figure 4 At least one embodiment of the pixel circuit shown in the working process further comprises a reset stage arranged before the compensation stage;

[0108] The present application Figure 4 At least one embodiment of the pixel circuit shown in the working process further comprises a reset stage arranged before the compensation stage;

[0109] In the reset stage, the second setting circuit 32 writes the first initial voltage Vinit1 into the third node N3 under the control of the first initial control signal; the third setting circuit 33 writes the second initial voltage Vinit2 into the first electrode of the light emitting element E1 under the control of the second initial control signal.

[0110] The present application Figure 4 At least one embodiment of the pixel circuit shown in the working process further comprises a reset stage arranged before the compensation stage;

[0111] In the setting stage, the third setting circuit 33 writes the second initial voltage Vinit2 into the first electrode of the light emitting element E1 under the control of the second initial control signal; the second setting circuit 32 writes the first initial voltage Vinit1 into the third node N3 under the control of the first initial control signal; the first light emitting control circuit 21 controls the disconnection between the power voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal; the second light emitting control circuit 22 controls the disconnection between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal.

[0112] In the holding light emitting stage, the first light emitting control circuit 21 controls the connection between the power voltage terminal ELVDD and the second node N2 under the control of the light emitting control signal; the second light emitting control circuit 22 controls the connection between the third node N3 and the first electrode of the light emitting element E1 under the control of the light emitting control signal; the driving circuit 10 drives the light emitting element E1 to emit light.

[0113] In the specific implementation, in the holding frame, the setting stage is arranged before the holding light emitting stage; in the setting stage, the light emitting element does not emit light, the third setting circuit 33 writes the second initial voltage Vinit2 into the first electrode of the light emitting element E1 under the control of the second initial control signal, so as to clear the residual charge of the first electrode of the light emitting element E1; the second setting circuit 32 writes the first initial voltage Vinit1 into the third node N3 under the control of the first initial control signal, so as to improve the hysteresis phenomenon of the driving transistor included in the driving circuit.

[0114] Optionally, the driving circuit includes a driving transistor, the first control circuit includes a first transistor, the first setting circuit includes a second transistor, the data writing circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.

[0115] The gate of the driving transistor is electrically connected with the first node, the first electrode of the driving transistor is electrically connected with the second node, and the second electrode of the driving transistor is electrically connected with the third node.

[0116] The gate of the first transistor is electrically connected with the first reset control terminal, the first electrode of the first transistor is electrically connected with the power voltage terminal, and the second electrode of the first transistor is electrically connected with the second node.

[0117] The gate of the second transistor is electrically connected with the first reset control terminal, the first electrode of the second transistor is electrically connected with the reference voltage terminal, and the second electrode of the second transistor is electrically connected with the first node.

[0118] The gate of the third transistor is electrically connected with a scan end, the first pole of the third transistor is electrically connected with a data line, and the second pole of the third transistor is electrically connected with a first node;

[0119] The first end of the first capacitor is electrically connected with the first node, and the second end of the first capacitor is electrically connected with a fourth node;

[0120] The first end of the second capacitor is electrically connected with the second node, and the second end of the second capacitor is electrically connected with a third node.

[0121] Optionally, the first light-emitting control circuit comprises a fourth transistor, and the second light-emitting control circuit comprises a fifth transistor;

[0122] The gate of the fourth transistor is electrically connected with a light-emitting control end, the first pole of the fourth transistor is electrically connected with a power voltage end, and the second pole of the fourth transistor is electrically connected with a second node;

[0123] The gate of the fifth transistor is electrically connected with the light-emitting control end, the first pole of the fifth transistor is electrically connected with the third node, and the second pole of the fifth transistor is electrically connected with the first pole of the light-emitting element.

[0124] Optionally, the second setting circuit comprises a sixth transistor, and the third setting circuit comprises a seventh transistor;

[0125] The gate of the sixth transistor is electrically connected with a first initial control end, the first pole of the sixth transistor is electrically connected with a first initial voltage end, and the second pole of the sixth transistor is electrically connected with the third node;

[0126] The gate of the seventh transistor is electrically connected with a second initial control end, the first pole of the seventh transistor is electrically connected with a second initial voltage end, and the second pole of the seventh transistor is electrically connected with the first pole of the light-emitting element.

[0127] Optionally, the fourth setting circuit comprises an eighth transistor;

[0128] The gate of the eighth transistor is electrically connected with a second reset control end, the first pole of the eighth transistor is electrically connected with a reference voltage end, and the second pole of the eighth transistor is electrically connected with the fourth node.

[0129] As Figure 5 shown, on the basis of at least one embodiment of the pixel circuit shown in Figure 4 The driving circuit comprises a driving transistor DT, the first control circuit comprises a first transistor T1, the first setting circuit comprises a second transistor T2, the data writing circuit comprises a third transistor T3, the first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2.

[0130] The first gate of the driving transistor DT is electrically connected with the first node N1, the second gate of the driving transistor DT is electrically connected with the drain of the driving transistor DT; the source of the driving transistor DT is electrically connected with the second node N2, and the drain of the driving transistor DT is electrically connected with the third node N3;

[0131] The gate of the first transistor T1 is electrically connected with the first reset control end GR1, the source of the first transistor T1 is electrically connected with the power voltage end ELVDD, and the drain of the first transistor T1 is electrically connected with the second node N2;

[0132] The gate of the second transistor T2 is electrically connected with the first reset control end GR1, the source of the second transistor T2 is electrically connected with the reference voltage end REF, and the drain of the second transistor T2 is electrically connected with the first node N1; the reference voltage end REF is used for providing a reference voltage Vref;

[0133] The gate of the third transistor T3 is electrically connected with the scanning end GW, the source of the third transistor T3 is electrically connected with the data line Dj, and the drain of the third transistor T3 is electrically connected with the first node N1;

[0134] The first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the fourth node N4;

[0135] The first end of the second capacitor C2 is electrically connected with the second node N2, and the second end of the second capacitor C2 is electrically connected with the third node N3;

[0136] The first light-emitting control circuit comprises a fourth transistor T4, the second light-emitting control circuit comprises a fifth transistor T5; and the light-emitting element is an organic light-emitting diode O1;

[0137] The gate of the fourth transistor T4 is electrically connected with the light-emitting control end EM, the source of the fourth transistor T4 is electrically connected with the power voltage end ELVDD, and the drain of the fourth transistor T4 is electrically connected with the second node N2;

[0138] The gate of the fifth transistor T5 is electrically connected with the light-emitting control end EM, the source of the fifth transistor T5 is electrically connected with the third node N3, and the drain of the fifth transistor T5 is electrically connected with the anode of the organic light-emitting diode O1; the cathode of O1 is electrically connected with the low voltage end ELVSS;

[0139] The second setting circuit comprises a sixth transistor T6, and the third setting circuit comprises a seventh transistor T7;

[0140] The gate of the sixth transistor T6 is electrically connected to the first initial control terminal GI1, the source of the sixth transistor T6 is electrically connected to the first initial voltage terminal I1, and the drain of the sixth transistor T6 is electrically connected to the third node N3; the first initial voltage terminal I1 is used to provide the first initial voltage Vinit1.

[0141] The gate of the seventh transistor T7 is electrically connected to the first initial control terminal GI1, the source of the seventh transistor T7 is electrically connected to the second initial voltage terminal I2, and the drain of the seventh transistor T7 is electrically connected to the anode of O1; the second initial voltage terminal I2 is used to provide the second initial voltage Vinit2.

[0142] The fourth set circuit includes an eighth transistor T8;

[0143] The gate of the eighth transistor T8 is electrically connected to the second reset control terminal GR2, the source of the eighth transistor T8 is electrically connected to the reference voltage terminal REF, and the drain of the eighth transistor T8 is electrically connected to the fourth node N4.

[0144] exist Figure 5 In at least one embodiment of the pixel circuit shown, the first initial control terminal and the second initial control terminal are the same control terminal, so as to reduce the number of control terminals used, reduce the number of GOA modules included in the display device, and facilitate the realization of narrow bezels.

[0145] I1 and I2 can share the same initial voltage terminal, but this is not a limitation.

[0146] exist Figure 5 In at least one embodiment of the pixel circuit shown, DT is a dual-gate transistor.

[0147] exist Figure 5 In at least one embodiment of the pixel circuit shown, T1-T8 are n-type transistors and DT is an n-type transistor, but not limited thereto.

[0148] like Figure 6 As shown, the present invention Figure 5 When at least one embodiment of the pixel circuit shown is in operation, the refresh frame FS may include a reset phase S11, a compensation phase S12, a data writing phase S13, and a refresh light emission phase S14 that are set sequentially.

[0149] During the reset phase S11, EM provides a low voltage signal, GR1 provides a low voltage signal, GR2 provides a high voltage signal, GI1 provides a high voltage signal, and GW provides a high voltage signal. Figure 7AAs shown, T8 is on, Vref is written into N4, and the potential of N4 is reset; T6 and T7 are on, Vinit1 is written into N3, and Vinit2 is written into the anode of O1; T3, T2, T4, T5 and T1 are off;

[0150] In the compensation stage S12, EM provides a low voltage signal, GR1 provides a high voltage signal, GR2 provides a high voltage signal, GI1 provides a low voltage signal, and GW provides a low voltage signal, as shown in FIG. 4. Figure 7B As shown, T8 remains on, T6 and T7 are off, T2 and T1 are on, and the initialization of the potential of N1 is completed.

[0151] At the beginning of the compensation stage S12, DT is on, and current flows through T1 and DT to charge C1 and C2, changes the potential of N3, and until DT is off, at which time the potential of N3 gradually changes from Vinit1 to Vref-Vth, Vth being the threshold voltage of DT, and the threshold voltage compensation is completed.

[0152] At the beginning of the compensation stage S12, the gate-drain voltage Vgd of DT needs to be less than Vth, that is, Vref-Vdd is less than Vth, Vdd being the voltage value of the power supply voltage provided by ELVDD;

[0153] In the data writing stage S13, EM provides a low voltage signal, GR1 provides a low voltage signal, GR2 provides a high voltage signal, GI1 provides a low voltage signal, and G2 provides a high voltage signal, as shown in FIG. 5. Figure 7C As shown, T8 remains on, T3 is on, and the data line Dj provides the data voltage Vdata to N1; T2, DT, T4, T5, T1, T7 and T6 are off; the potential of N4 is stabilized by T8, so the potential of N3 is not disturbed and is maintained at Vref-Vth.

[0154] In the refresh and light emitting stage S14, EM provides a high voltage signal, GR1 and GR2 provide low voltage signals, GI1 provides a low voltage signal, and GW provides a low voltage signal, as shown in FIG. 6. Figure 7D As shown, DT, T4 and T5 are on, current flows through T4, DT and T5 to charge the anode of O1 until O1 is stable and emits light, the anode voltage of O1 becomes the light emitting voltage Vo1 of O1, the potential of N3 can be approximately equal to the anode voltage of O1, the change amount of the potential of N1 is equal to the change amount of the potential of N3 through the coupling and bootstrap of C1 and C2, the difference between the potential of N1 and the potential of N3 is maintained as Vdata-Vref+Vth; the driving current Id generated by DT to drive O1 to emit light can be K(Vref-Vdata) 2Wherein, K is the current coefficient of the DT; Id is not affected by the threshold voltage of the DT, the brightness of the image output from the display panel can be uniformly maintained, regardless of the characteristics of the DT.

[0155] The present application Figure 5 At least one embodiment of the pixel circuit shown in the working process, after T6 is turned off, T1 is turned on, so that the setting of the potential of N3 does not affect the threshold voltage compensation of the driving transistor.

[0156] As Figure 8 And Figure 9 The present application Figure 5 At least one embodiment of the pixel circuit shown in the working process, the holding frame FB can include a setting stage S21 and a holding light-emitting stage S22 set in sequence;

[0157] In the setting stage S21, EM provides a low voltage signal, GR1 and GR2 provide a low voltage signal, GI1 provides a high voltage signal, GW provides a low voltage signal, T6 and T7 are both turned on, I1 provides a first initial voltage Vinit1 to N3, I2 provides a second initial voltage Vinit2 to the anode of O1;

[0158] In the holding light-emitting stage S22, EM provides a high voltage signal, GR1, GR2, GI1 and GW all provide a low voltage signal, T4 and T5 are turned on, and DT drives O1 to emit light.

[0159] As Figure 8 The duration of the setting stage S21 is less than Figure 9 The duration of the setting stage S21.

[0160] As Figure 9 The duration of S21 is extended to be able to fully initialize the anode of O1.

[0161] The present application Figure 10 At least one embodiment of the pixel circuit shown in the working process is different from the present application Figure 5 The difference between at least one embodiment of the pixel circuit shown in the present application and at least one embodiment of the pixel circuit shown in the present application is as follows:

[0162] The gate of T7 is electrically connected with the second initial control end GI2.

[0163] As Figure 11 The present application Figure 10 At least one embodiment of the pixel circuit shown in the working process, T6 and T7 are controlled by GI1 and GI2 respectively, in the refresh frame FS, T7 can be turned on for a longer time to fully initialize the anode of O1, and the turning-on time of T6 is shorter.

[0164] As Figure 11As shown, in the reset stage S11, the compensation stage S12 and the data writing stage S13, GI2 provides a high voltage signal, and T7 is opened to initialize the anode potential of O1.

[0165] As shown, in the reset stage S11, the compensation stage S12 and the data writing stage S13, GI2 provides a high voltage signal, and T7 is opened to initialize the anode potential of O1. Figure 11 Figure 10 As shown, in the reset stage S11, the compensation stage S12 and the data writing stage S13, GI2 provides a high voltage signal, and T7 is opened to initialize the anode potential of O1.

[0166] As shown, in the reset stage S11, the compensation stage S12 and the data writing stage S13, GI2 provides a high voltage signal, and T7 is opened to initialize the anode potential of O1.

[0167] As shown, in the reset stage S11, the compensation stage S12 and the data writing stage S13, GI2 provides a high voltage signal, and T7 is opened to initialize the anode potential of O1.

[0168] The driving method provided by the embodiment of the present application is applied to the pixel circuit, and the refresh frame comprises the compensation stage and the data writing stage arranged in sequence; the driving method comprises the following steps:

[0169] In the compensation stage, the first control circuit controls the communication between the power supply voltage terminal and the second node under the control of the first reset control signal, and the first set circuit writes the reference voltage provided by the reference voltage terminal into the first node under the control of the first reset control signal;

[0170] In the beginning of the compensation stage, the driving circuit controls the communication between the second node and the third node under the control of the potential of the first node, charges the first energy storage circuit and the second energy storage circuit, changes the potential of the third node, and controls the disconnection between the second node and the third node under the control of the potential of the first node.

[0171] In the data writing stage, the data writing circuit writes the data voltage provided by the data line into the first node under the control of the scanning signal.

[0172] In the driving method provided by the embodiment of the present application, the data voltage writing and the threshold voltage compensation are designed separately, the required scanning time of one row is less, the data voltage writing time can be ensured in high-frequency display, the pixel circuit can be fully charged by the data voltage under the premise of ensuring the display uniformity, and the display effect is ensured.

[0173] In at least one embodiment of the present application, the pixel circuit further comprises a second set circuit and a third set circuit; the refresh frame further comprises a reset stage arranged before the compensation stage; and the driving method further comprises the following steps:

[0174] ​In the reset stage, the second setting circuit writes the first initial voltage into the third node under the control of the first initial control signal to initialize the potential of the third node; and the third setting circuit writes the second initial voltage into the first electrode of the light emitting element under the control of the second initial control signal to clear the residual charge of the first electrode of the light emitting element.

[0175] In the compensation stage, the second setting circuit controls the disconnection between the first initial voltage terminal and the third node under the control of the first initial control signal.

[0176] In at least one embodiment of the present application, the pixel circuit further comprises a fourth setting circuit; and the driving method further comprises:

[0177] In the reset stage, the compensation stage and the data writing stage, the fourth setting circuit writes the reference voltage into the fourth node under the control of the second reset control signal to set the potential of the fourth node.

[0178] The driving method in at least one embodiment of the present application further comprises:

[0179] In the compensation stage and the data writing stage, the third setting circuit writes the second initial voltage into the first electrode of the light emitting element under the control of the second initial control signal to clear the residual charge of the first electrode of the light emitting element.

[0180] In at least one embodiment of the present application, the pixel circuit further comprises a third setting circuit, a light emitting element, a first light emitting control circuit and a second light emitting control circuit; the maintaining frame comprises a setting stage and a maintaining light emitting stage arranged in sequence; and the driving method comprises:

[0181] In the setting stage, the third setting circuit writes the second initial voltage into the first electrode of the light emitting element under the control of the second initial control signal to clear the residual charge of the first electrode of the light emitting element; the first light emitting control circuit controls the disconnection between the power voltage terminal and the second node under the control of the light emitting control signal; and the second light emitting control circuit controls the disconnection between the third node and the first electrode of the light emitting element under the control of the light emitting control signal.

[0182] In the maintaining light emitting stage, the first light emitting control circuit controls the communication between the power voltage terminal and the second node under the control of the light emitting control signal; the second light emitting control circuit controls the communication between the third node and the first electrode of the light emitting element under the control of the light emitting control signal; and the driving circuit drives the light emitting element to emit light.

[0183] In at least one embodiment of the present application, the pixel circuit further comprises a second setting circuit; and the driving method further comprises:

[0184] In the setting stage, the second setting circuit writes the first initial voltage into the third node under the control of the first initial control signal, so as to improve the hysteresis of the driving transistor included in the driving circuit.

[0185] The display device includes the pixel circuit.

[0186] The above is the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles of the present application, can make a number of improvements and refinements, these improvements and refinements should also be considered as the protection scope of the present application.

Claims

1. A pixel circuit, characterized in that, It includes a drive circuit, a first control circuit, a first set circuit, a first energy storage circuit, a second energy storage circuit, and a data writing circuit; The control terminal of the driving circuit is electrically connected to the first node, the first terminal of the driving circuit is electrically connected to the second node, and the second terminal of the driving circuit is electrically connected to the third node. The driving circuit is used to generate a driving current under the control of the potential of the first node. The first control circuit is electrically connected to the first reset control terminal, the power supply voltage terminal and the second node respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the first reset control signal provided by the first reset control terminal; The first set circuit is electrically connected to the first reset control terminal, the reference voltage terminal and the first node respectively, and is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the first reset control signal; The data writing circuit is electrically connected to the scanning end, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the scanning signal provided by the scanning end; The first end of the first energy storage circuit is electrically connected to the first node, and the second end of the first energy storage circuit is electrically connected to the fourth node. The first end of the second energy storage circuit is electrically connected to the fourth node, and the second end of the second energy storage circuit is electrically connected to the third node. The refresh frame includes a compensation phase and a data writing phase that are set sequentially. The first control circuit is used to control the connection between the power supply voltage terminal and the second node under the control of the first reset control signal during the compensation phase. The first set circuit is used to write the reference voltage provided by the reference voltage terminal into the first node under the control of the first reset control signal during the compensation phase. The data writing circuit is used to write the data voltage provided by the data line to the first node under the control of the scanning signal during the data writing stage. The pixel circuit also includes a first light-emitting control circuit; The first light-emitting control circuit is electrically connected to the light-emitting control terminal, the power supply voltage terminal, and the second node, respectively, and is used to control the connection or disconnection between the power supply voltage terminal and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal.

2. The pixel circuit as described in claim 1, characterized in that, It also includes a light-emitting element and a second light-emitting control circuit; The second light-emitting control circuit is electrically connected to the light-emitting control terminal, the third node, and the first electrode of the light-emitting element, respectively, and is used to control the connection or disconnection between the third node and the first electrode of the light-emitting element under the control of the light-emitting control signal provided by the light-emitting control terminal; The second electrode of the light-emitting element is electrically connected to the first voltage terminal.

3. The pixel circuit as described in claim 2, characterized in that, It also includes a second set circuit and a third set circuit; The second setting circuit is electrically connected to the first initial control terminal, the first initial voltage terminal and the third node respectively, and is used to write the first initial voltage provided by the first initial voltage terminal into the third node under the control of the first initial control signal provided by the first initial control terminal; The third setting circuit is electrically connected to the second initial control terminal, the second initial voltage terminal, and the first electrode of the light-emitting element, respectively, and is used to write the second initial voltage provided by the second initial voltage terminal into the first electrode of the light-emitting element under the control of the second initial control signal provided by the second initial control terminal.

4. The pixel circuit as described in claim 3, characterized in that, The first initial control terminal and the second initial control terminal are the same control terminal.

5. The pixel circuit according to any one of claims 1 to 4, characterized in that, It also includes a fourth set circuit; The fourth set circuit is electrically connected to the second reset control terminal, the reference voltage terminal, and the fourth node, respectively, and is used to write the reference voltage provided by the reference voltage terminal into the fourth node under the control of the second reset control signal provided by the second reset control terminal.

6. The pixel circuit as described in claim 1, characterized in that, The driving circuit includes a driving transistor, the first control circuit includes a first transistor, the first set circuit includes a second transistor, the data writing circuit includes a third transistor, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor. The gate of the driving transistor is electrically connected to the first node, the first electrode of the driving transistor is electrically connected to the second node, and the second electrode of the driving transistor is electrically connected to the third node. The gate of the first transistor is electrically connected to the first reset control terminal, the first terminal of the first transistor is electrically connected to the power supply voltage terminal, and the second terminal of the first transistor is electrically connected to the second node. The gate of the second transistor is electrically connected to the first reset control terminal, the first terminal of the second transistor is electrically connected to the reference voltage terminal, and the second terminal of the second transistor is electrically connected to the first node. The gate of the third transistor is electrically connected to the scan terminal, the first terminal of the third transistor is electrically connected to the data line, and the second terminal of the third transistor is electrically connected to the first node. The first terminal of the first capacitor is electrically connected to the first node, and the second terminal of the first capacitor is electrically connected to the fourth node. The first end of the second capacitor is electrically connected to the fourth node, and the second end of the second capacitor is electrically connected to the third node.

7. The pixel circuit as described in claim 2, characterized in that, The first light-emitting control circuit includes a fourth transistor, and the second light-emitting control circuit includes a fifth transistor; The gate of the fourth transistor is electrically connected to the light-emitting control terminal, the first terminal of the fourth transistor is electrically connected to the power supply voltage terminal, and the second terminal of the fourth transistor is electrically connected to the second node. The gate of the fifth transistor is electrically connected to the light-emitting control terminal, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the light-emitting element.

8. The pixel circuit as described in claim 3, characterized in that, The second set circuit includes a sixth transistor, and the third set circuit includes a seventh transistor; The gate of the sixth transistor is electrically connected to the first initial control terminal, the first terminal of the sixth transistor is electrically connected to the first initial voltage terminal, and the second terminal of the sixth transistor is electrically connected to the third node. The gate of the seventh transistor is electrically connected to the second initial control terminal, the first terminal of the seventh transistor is electrically connected to the second initial voltage terminal, and the second terminal of the seventh transistor is electrically connected to the first terminal of the light-emitting element.

9. The pixel circuit as described in claim 5, characterized in that, The fourth set circuit includes an eighth transistor; The gate of the eighth transistor is electrically connected to the second reset control terminal, the first terminal of the eighth transistor is electrically connected to the reference voltage terminal, and the second terminal of the eighth transistor is electrically connected to the fourth node.

10. A driving method applied to a pixel circuit as described in any one of claims 1 to 9, characterized in that, The refresh frame includes a compensation phase and a data writing phase set sequentially; the driving method includes: During the compensation phase, the first control circuit, under the control of the first reset control signal, controls the connection between the power supply voltage terminal and the second node, and the first set circuit, under the control of the first reset control signal, writes the reference voltage provided by the reference voltage terminal into the first node. At the start of the compensation phase, the drive circuit, under the control of the potential of the first node, controls the connection between the second and third nodes to charge the first and second energy storage circuits, and changes the potential of the third node until the drive circuit, under the control of the potential of the first node, controls the disconnection between the second and third nodes. During the data writing phase, the data writing circuit, under the control of the scanning signal, writes the data voltage provided by the data line into the first node.

11. The driving method as described in claim 10, characterized in that, The pixel circuit further includes a second set circuit and a third set circuit; the refresh frame further includes a reset phase set before the compensation phase; the driving method further includes: During the reset phase, the second set circuit, under the control of the first initial control signal, writes the first initial voltage into the third node; the third set circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element. During the compensation phase, the second set circuit, under the control of the first initial control signal, controls the disconnection between the first initial voltage terminal and the third node.

12. The driving method as described in claim 10, characterized in that, The pixel circuit further includes a fourth setting circuit; the driving method further includes: During the reset, compensation, and data writing phases, the fourth set circuit, under the control of the second reset control signal, writes the reference voltage to the fourth node.

13. The driving method as described in claim 11, characterized in that, Also includes: During the compensation and data writing phases, the third set circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element.

14. The driving method as described in claim 10, characterized in that, The pixel circuit further includes a third setting circuit, a light-emitting element, a first light-emitting control circuit, and a second light-emitting control circuit; the holding frame includes a setting phase and a holding light-emitting phase set sequentially; the driving method includes: During the setting phase, the third setting circuit, under the control of the second initial control signal, writes the second initial voltage into the first electrode of the light-emitting element; the first light-emitting control circuit, under the control of the light-emitting control signal, controls the power supply voltage terminal to disconnect from the second node; the second light-emitting control circuit, under the control of the light-emitting control signal, controls the third node to disconnect from the first electrode of the light-emitting element. During the light-emitting phase, the first light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the power supply voltage terminal and the second node. The second light-emitting control circuit, under the control of the light-emitting control signal, controls the connection between the third node and the first electrode of the light-emitting element. The driving circuit drives the light-emitting element to emit light.

15. The driving method as described in claim 14, characterized in that, The pixel circuit further includes a second setting circuit, and the driving method further includes: During the setting phase, the second setting circuit, under the control of the first initial control signal, writes the first initial voltage into the third node.

16. A display device, characterized in that, Includes the pixel circuit as described in any one of claims 1 to 9.

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