Preparation method of semiconductor rear-end interconnection structure
By using a stacked structure of metal nitride layer and metal layer in the semiconductor back-end interconnect structure and performing mechanical brushing, the problem of peeling between the metal hard mask layer and the low-k material layer is solved, and the stability and yield of the interconnect line are improved.
Patent Information
- Application Number
- CN202311577317.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-23
- Publication Date
- 2025-05-23
AI Technical Summary
When the Damascus process using the damascus technology in the prior art realizes the semiconductor back-end interconnect structure, peeling is prone to occur between the metal hard mask layer and the low-k material layer, resulting in poor problems such as breaking of the interconnection line.
A laminated structure consisting of a metal nitride layer and a metal layer is formed on the low k dielectric layer, and the stress direction is adjusted to match the front low k dielectric layer, and the peripheral edges are mechanically brushed after formation to remove the easily peeled metal nitride layer.
It effectively improves the adhesion strength between the metal hard mask stack structure and the low-k dielectric layer, reduces the risk of peeling, and improves the stability and yield of the interconnection line.
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Figure CN120033068A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the technical field of semiconductor integrated circuit manufacturing, and in particular relates to a method for preparing a semiconductor back-end interconnection structure. Background Art
[0002] The development of semiconductor integrated circuit technology has put forward new demands on interconnection technology. Interconnection integration technology will face a series of technical and physical limitation challenges in the near and long term development. As the size of semiconductor devices continues to shrink, the interconnection structure has become narrower and narrower, resulting in higher and higher interconnection resistance. With its excellent conductivity, copper has become one of the solutions for interconnection integration technology in the field of integrated circuit technology.
[0003] Traditionally, metal interconnects of integrated circuits are made by etching the metal layer, then filling the dielectric layer, chemically and mechanically polishing the dielectric layer, and repeating the above process to successfully stack multiple layers of metal. However, since dry etching of copper is difficult and the etching residue cannot be sucked out, the Damascus process of inlay technology is often used to complete copper interconnections.
[0004] At present, low-k material layers are often used and metal hard mask layers are used as etching mask layers for low-k material layers to achieve embedding of copper interconnect metal in low-k material layers. However, metal hard mask layers generally have strong compressive stress and are relatively brittle. When the thickness increases, it is easy to peel off from the underlying low-k material layer. The fallen particles may cover the etching pattern, causing the etching pattern to be damaged or lost (pattern broken / loss), resulting in defects such as broken interconnect lines, affecting the yield. Summary of the invention
[0005] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a method for preparing a semiconductor back-end interconnect structure, which is used to solve the problem of peeling between the metal hard mask layer and the low-k material layer, resulting in breakage of the interconnect line, etc. in the semiconductor back-end interconnect structure realized by the Damascus process using the damascene technology in the prior art.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor back-end interconnect structure, including a method for preparing a laminated structure, wherein the method for preparing the laminated structure comprises:
[0007] Providing a front-end device layer, and forming an etching stop layer and a low-k dielectric layer on the front-end device layer;
[0008] Forming a metal hard mask stack structure on the low-k dielectric layer, the metal hard mask stack structure being formed by stacking a metal nitride layer and a metal layer at least once; wherein when forming the metal nitride layer, the nitrogen content in the metal nitride layer is reduced by reducing the nitrogen content in the reactant;
[0009] Mechanically scrubbing the peripheral edge of the metal hard mask stack structure to obtain the stack structure;
[0010] After forming the stacked structure, the method further comprises:
[0011] Etching the stacked structure to form through holes and / or grooves;
[0012] removing the metal hard mask stack structure;
[0013] Fill the through holes and / or trenches with metal material to electrically connect with the front-end device layer.
[0014] Optionally, the material of the metal layer is the same as the metal material in the metal nitride layer.
[0015] Optionally, the surface of the metal hard mask stack structure is washed with water while the peripheral edge of the metal hard mask stack structure is brushed; and the surface of the metal hard mask stack structure is washed with water again after the peripheral edge of the metal hard mask stack structure is brushed.
[0016] Optionally, the metal nitride layer is one of a titanium nitride layer, a tantalum nitride layer and an aluminum nitride layer.
[0017] Furthermore, the ratio of nitrogen atoms to metal atoms in the metal nitride layer is 3:10 to 6:10, including endpoint values.
[0018] Furthermore, the metal hard mask stack structure is prepared by a PVD process.
[0019] Furthermore, when preparing the metal nitride layer in the metal hard mask stack structure, the reaction environment is changed from a nitrogen-rich mode to a metal-rich mode.
[0020] Optionally, the metal hard mask stack structure is formed by stacking a metal nitride layer and a metal layer one to three times.
[0021] Optionally, before forming the metal hard mask stack structure, the method further includes forming a barrier layer stack on the low-k dielectric layer.
[0022] Optionally, the method of forming the through hole and / or the groove includes:
[0023] forming a photoresist layer on the surface of the metal hard mask stack structure and performing patterning;
[0024] Etching the metal hard mask stack structure based on the patterned photoresist layer to obtain a patterned metal hard mask stack structure, and removing the patterned photoresist layer;
[0025] The low-k dielectric layer and the etching barrier layer are etched based on the patterned metal hard mask stack structure to form the through hole and / or trench.
[0026] As described above, the method for preparing a semiconductor back-end interconnect structure of the present invention forms a metal hard mask stack structure composed of a stacked pair of metal nitride layers / metal layers stacked in sequence on the low-k dielectric layer when etching the low-k dielectric layer. Since the metal nitride layer has compressive stress and the metal layer has tensile stress, the metal nitride layer with compressive stress and the metal layer with tensile stress cooperate with each other to effectively adjust the stress direction of the entire metal hard mask stack structure to be consistent with the stress direction of the front low-k dielectric layer, so as to alleviate the stress inconsistency between the metal hard mask stack structure and the front low-k dielectric layer. Matching, thereby improving the adhesion strength between the metal hard mask stack structure and its previous low-k dielectric layer; in addition, after the metal hard mask stack structure is formed, its circumferential edge is mechanically brushed to remove the metal nitride layer that is easy to peel off at the edge in advance, thereby further reducing the risk of peeling between the metal hard mask stack structure and the low-k dielectric layer due to collision during the transmission of the subsequent stack structure, and further reducing the content of nitrogen in the metal nitride layer to reduce the brittleness of the metal nitride layer, thereby further inhibiting the peeling of the metal nitride layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 A cross-sectional schematic diagram of an exemplary stacked film structure for preparing a semiconductor back-end interconnect structure is shown.
[0028] Figure 2 Show as pair Figure 1 Schematic diagram of the cross-sectional structure of the stacked film structure after the photoresist mask layer is patterned.
[0029] Figure 3 Show as pair Figure 1 Schematic diagram of the cross-sectional structure of the stacked film structure after etching.
[0030] Figure 4 Show as pair Figure 3 A schematic diagram of a cross-sectional structure of a metal pattern fracture after the formed holes and / or trenches are filled with metal.
[0031] Figure 5 Show as pair Figure 1Schematic diagram of the cross-sectional structure of the etching window covered by particle impurities peeled off from the metal hard mask layer after the photoresist mask layer of the stacked film structure is patterned.
[0032] Figure 6 Display as Figure 5 Schematic diagram of the cross-sectional structure in which the erroneous etching pattern generated in the process is transferred to the metal hard mask layer.
[0033] Figure 7 Displayed as Figure 6 Schematic diagram of a cross-sectional structure in which the etching pattern is lost after etching the stacked film structure on the basis of.
[0034] Figure 8 Display as Figure 1 Schematic diagram of the structure in which peeling occurs between a metal hard mask layer and a front material layer in contact with it in a stacked film structure.
[0035] Fig. 9 Displayed as Figure 1 An SEM image of an interconnect structure prepared by a stacked film structure for preparing a semiconductor back-end interconnect structure, in which the metal pattern is missing.
[0036] Fig.10 It is a schematic cross-sectional structure diagram of a laminated film structure for preparing a semiconductor back-end interconnection structure according to the present invention.
[0037] Fig.11 It is a schematic cross-sectional structure diagram showing the matching of a metal hard mask stack with its front material layer in a stacked film structure for preparing a semiconductor back-end interconnect structure according to the present invention.
[0038] Fig.12 It is a schematic structural diagram showing the mechanical cleaning of a metal hard mask stack after the metal hard mask stack is formed during the preparation process of the stacked film structure for preparing a semiconductor back-end interconnect structure according to the present invention.
[0039] Fig.13 It is a schematic cross-sectional structure diagram showing a photoresist layer formed on the surface of a laminated film structure for preparing a semiconductor back-end interconnect structure according to the present invention.
[0040] Fig.14 Display pair Fig.13 Schematic diagram of the cross-sectional structure of patterning the photoresist layer.
[0041] Fig.15 Shown is a schematic cross-sectional structure diagram for patterning a metal hard mask stack structure in a stacked film structure.
[0042] Fig.16 The schematic diagram shows a cross-sectional structure of etching a stacked film structure to form through holes and / or trenches.
[0043] Fig.17 Shown is a schematic cross-sectional structure diagram of a metal material layer filled in a through hole and / or a trench.
[0044] Component number description
[0045] 10 Front-end device layer
[0046] 11 Etch stop layer
[0047] 12 Low-k dielectric layer
[0048] 13 Metal Hard Mask Layer
[0049] 14 Metal Hard Mask Stack
[0050] 140 Metal nitride layer
[0051] 141 Metal Layer
[0052] 15 Photoresist layer
[0053] 17 Front Material Layer
[0054] 18 Brush Head
[0055] 19 Barrier layer stack
[0056] 20 Through holes and / or grooves
[0057] 21 Metal Materials DETAILED DESCRIPTION
[0058] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0059] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0060] like Figure 1As shown in FIG. 1 , a laminated film structure for preparing a semiconductor back-end interconnect structure includes a front-end device layer 10, an etching stop layer 11, a low-k dielectric layer 12, a metal hard mask layer 13, and a photoresist layer 15. The metal hard mask layer 13 generally has a strong compressive stress and is brittle, so when the thickness increases, it is easy to peel off from the underlying low-k dielectric layer 12. Figure 8 As shown, generally after forming the low-k dielectric layer 12 of the stacked film structure, the wafer will bend. At this time, the metal hard mask layer 13 has compressive stress and is brittle, so it will peel off from the previous material layer 17 (i.e., the low-k dielectric layer). Figures 2 to 3 As shown, the photoresist layer 15 is patterned and the metal hard mask layer 13, the low-k dielectric layer 12 and the etching barrier layer 11 are sequentially etched to form holes, and the holes are filled with a metal layer to form an interconnect structure. Since the metal hard mask layer 13 and the low-k dielectric layer 12 may be peeled off, during the etching process, the particles dropped from the metal hard mask layer 13 may cover the etching window, such as Figure 5 and Figure 6 This will cause the subsequent metal layer to break as shown in Figure 4 As shown in A in the figure, the metal layer is broken and cannot be connected to the front-end device layer, and even produces Figure 7 The etched pattern shown is lost and cannot be transferred to the low-k dielectric layer, causing the fill metal layer to be lost. Fig. 9 Area B in the figure is the SEM image where the interconnect metal layer is lost.
[0061] Based on this, this embodiment provides a method for preparing a semiconductor back-end interconnect structure, which includes a method for preparing a laminated structure, which can effectively inhibit the peeling between the metal hard mask layer and its front material layer, and specifically includes:
[0062] like Fig.10 As shown, a front-end device layer 10 is provided, and an etching stop layer 11 and a low-k dielectric layer 12 are formed on the front-end device layer 10;
[0063] A metal hard mask stack structure 14 is formed on the low-k dielectric layer 12, wherein the metal hard mask stack structure 14 is formed by stacking a metal nitride layer 140 and a metal layer 141 at least once; wherein when forming the metal nitride layer, the nitrogen content in the metal nitride layer is reduced by reducing the nitrogen content in the reactant;
[0064] like Fig.12 As shown, the peripheral edge of the metal hard mask stack structure 14 is mechanically brushed to obtain the stack structure.
[0065] After forming the stacked structure, the method further comprises:
[0066] like Fig.16 As shown, the stacked structure is etched to form a through hole and / or a groove 20;
[0067] like Fig.17 As shown, the metal hard mask stack structure 14 is removed;
[0068] like Fig.17 As shown, a metal material 21 is filled in the through hole and / or the groove 20 to be electrically connected to the front-end device layer 10 .
[0069] The through hole and / or the trench 20 are filled with metal material 21 to obtain a semiconductor back-end interconnection structure. The method of forming the semiconductor back-end interconnection structure is not limited here, for example, the metal interconnection can be completed by a single damascene process or a dual damascene process.
[0070] In the method for preparing the semiconductor back-end interconnect structure of the present embodiment, when etching the low-k dielectric layer, a metal hard mask stack structure consisting of a metal nitride layer / metal layer stacked in sequence is formed on the low-k dielectric layer. Since the metal nitride layer has compressive stress and the metal layer has tensile stress, the metal nitride layer with compressive stress and the metal layer with tensile stress cooperate with each other to effectively adjust the stress direction of the entire metal hard mask stack structure to be consistent with the stress direction of the front low-k dielectric layer, so as to alleviate the stress mismatch between the metal hard mask stack structure and the front low-k dielectric layer, such as Fig.11 As shown, the stress between the metal hard mask stack structure and the previous material layer (including the previous low-k dielectric layer) is completely matched, thereby improving the adhesion strength between the metal hard mask stack structure and its previous low-k dielectric layer; in addition, after the metal hard mask stack structure is formed, its circumferential edge is mechanically brushed to remove the metal nitride layer that is easy to peel off at its edge in advance, thereby further reducing the risk of peeling between the metal hard mask stack structure and the low-k dielectric layer due to collision during the transmission of the subsequent stack structure; further, the content of nitrogen in the metal nitride layer 140 is reduced to reduce the brittleness of the metal nitride layer 140, thereby further inhibiting the peeling of the metal nitride layer.
[0071] The front-end device layer generally includes a front-end device and a first interconnection layer for leading out the electrodes of the front-end device. The front-end device can be designed into various device structures according to actual needs, and the corresponding lead-out electrodes are also designed according to different front-end device structures. For example, a MOS tube structure generally includes three-terminal lead-out electrodes of source, gate and drain.
[0072] As an example, the front-end devices in the front-end device layer can be prepared based on existing suitable semiconductor materials, such as commonly used semiconductor silicon materials.
[0073] As a preferred example, the material of the metal layer 141 in the stack is the same as the metal material in the metal nitride layer 140 to facilitate process preparation.
[0074] As another preferred example, the metal nitride layer 140 is one of a titanium nitride layer, a tantalum nitride layer or an aluminum nitride layer.
[0075] As another preferred example, the brittleness of the metal nitride layer 140 can be reduced by reducing the nitrogen content in the metal nitride layer 140, thereby further inhibiting the peeling of the metal nitride layer. For example, the nitrogen content in the metal nitride layer 140 is reduced to a ratio of nitrogen atoms to metal atoms between 0.3 and 0.6, for example 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, etc. In a specific process, the metal hard mask stack structure 14 is generally prepared by a PVD process. During this process, if the nitrogen content in the metal nitride layer 140 is to be reduced, the nitrogen content can be reduced by changing the reaction environment from a nitrogen-rich mode to a metal-rich mode.
[0076] As an example, the more times the stack composed of the metal nitride layer 140 / metal layer 141 is stacked, the more accurate the adjustment of its stress direction is, but the more times the stack is stacked, the greater the process difficulty and complexity is. Therefore, it is generally better to select a stack composed of 1 to 3 metal nitride layers 140 / metal layers 141 that are cyclically deposited. That is, for a metal hard mask stack structure 14 of a preset thickness, it can be formed by a stack composed of 1 metal nitride layer 140 / metal layer 141, or by a stack composed of 2 metal nitride layers 140 / metal layers 141 that are stacked in sequence, or by a stack composed of 3 metal nitride layers 140 / metal layers 141 that are stacked in sequence. There is no limitation on the stacking method of the two layers of materials in the stack composed of the metal nitride layer 140 / metal layer 141, that is, the metal nitride layer 140 can be in the upper layer and the metal layer 141 can be in the lower layer; or the metal nitride layer 140 can be in the lower layer and the metal layer 141 can be in the upper layer. In addition, the thickness of the two layers of materials in the stack composed of the metal nitride layer 140 / metal layer 141 can be the same or different. Furthermore, when more than two stacks composed of metal nitride layers 140 / metal layers 141 are required to be stacked in sequence to form the metal hard mask stack structure 14, the thickness of different metal nitride layers 140 / metal layers 141 stacks can be the same or different.
[0077] like Fig.10As shown, the etching stop layer 11 is subsequently used as a stop layer for etching the low-k dielectric layer 12, and is generally selected to be a carbon-doped silicon nitride layer. The low-k dielectric layer 12 is a single-layer material structure, or a multi-layer stacked material structure, for example, a single-layer material structure with a dielectric constant between 2.3 and 3.8, or a stacked structure of a silicon dioxide layer and a dielectric layer with a dielectric constant between 2.3 and 3.8.
[0078] like Fig.10 As shown, a barrier layer stack 19 can also be formed between the low-k dielectric layer 12 and the metal hard mask stack structure 14. The barrier layer stack 19 generally includes an etch barrier layer and an anti-reflection layer, such as a carbon-doped silicon nitride etch barrier layer and an anti-reflection layer suitable for the metal hard mask stack structure 14.
[0079] like Fig.12 As shown, as a preferred example, the peripheral edge of the metal hard mask stack structure 14 is brushed while the surface of the metal hard mask stack structure 14 is washed with water; and after the peripheral edge of the metal hard mask stack structure 14 is brushed, the surface of the metal hard mask stack structure 14 is washed with water. That is, the surface of the metal hard mask stack structure 14 needs to be washed with water while and after the peripheral edge of the metal hard mask stack structure 14 is brushed, so as to improve the brushing effect of the metal hard mask stack structure 14 and improve the cleanliness. Fig.12 As shown, the peripheral edge of the metal hard mask stack structure 14 is generally brushed by controlling the brush head 18, preferably using deionized water for brushing.
[0080] As a specific example, the method of forming the through hole and / or the groove 20 includes:
[0081] like Fig.13 As shown, firstly, a photoresist layer 15 is formed on the surface of the metal hard mask stack structure 14. Fig.14 As shown, and patterning it to form the patterned photoresist layer 15;
[0082] like Fig.14 and Fig.15 As shown, the metal hard mask stack structure 14 is then etched based on the patterned photoresist layer 15 to obtain a patterned metal hard mask stack structure 14, and the patterned photoresist layer 15 is removed;
[0083] like Fig.16As shown, the low-k dielectric layer 12 and the etch barrier layer 11 are etched based on the patterned metal hard mask stack structure 14 to form the through hole and / or trench 20. Of course, when a barrier layer stack 19 is further included between the low-k dielectric layer 12 and the metal hard mask stack structure 14, the barrier layer stack 19 also needs to be etched in this step.
[0084] Of course, it should be noted here that before filling the metal material 21, the metal hard mask stack structure 14 and the barrier layer stack 19 need to be removed first.
[0085] In summary, the present invention provides a method for preparing a semiconductor back-end interconnect structure. In the preparation method, when etching a low-k dielectric layer, a metal hard mask stack structure composed of a metal nitride layer / metal layer is formed on the low-k dielectric layer in sequence. Since the metal nitride layer has compressive stress and the metal layer has tensile stress, the metal nitride layer with compressive stress and the metal layer with tensile stress cooperate with each other to effectively adjust the stress direction of the entire metal hard mask stack structure to make it consistent with the stress direction of the front low-k dielectric layer, so as to alleviate the stress between the metal hard mask stack structure and the front low-k dielectric layer. The stress mismatch between the metal hard mask stack structure and the low-k dielectric layer before it is improved; in addition, after the metal hard mask stack structure is formed, its peripheral edge is mechanically scrubbed to remove the metal nitride layer that is easy to peel off at the edge in advance, further reducing the risk of peeling between the metal hard mask stack structure and the low-k dielectric layer due to collision during the transmission of the subsequent stack structure, and further reducing the nitrogen content in the metal nitride layer to reduce the brittleness of the metal nitride layer, thereby further inhibiting the peeling of the metal nitride layer. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0086] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor back-end interconnect structure, comprising a method for preparing a laminated structure, It is characterized in that The method for preparing the laminated structure comprises: Providing a front-end device layer, and forming an etching stop layer and a low-k dielectric layer on the front-end device layer; Forming a metal hard mask stack structure on the low-k dielectric layer, the metal hard mask stack structure being formed by stacking a metal nitride layer and a metal layer at least once; wherein when forming the metal nitride layer, the nitrogen content in the metal nitride layer is reduced by reducing the nitrogen content in the reactant; Mechanically scrubbing the peripheral edge of the metal hard mask stack structure to obtain the stack structure; After forming the stacked structure, the method further comprises: Etching the stacked structure to form through holes and / or grooves; removing the metal hard mask stack structure; Fill the through holes and / or trenches with metal material to electrically connect with the front-end device layer.
2. The method for preparing a semiconductor back-end interconnect structure according to claim 1, Features: The material of the metal layer is the same as the metal material in the metal nitride layer.
3. The method for preparing a semiconductor back-end interconnect structure according to claim 1, Features: brushing the peripheral edge of the metal hard mask stack structure and washing the surface of the metal hard mask stack structure with water; After brushing the peripheral edge of the metal hard mask stack structure, the surface of the metal hard mask stack structure is washed with water.
4. The method for preparing a semiconductor back-end interconnect structure according to claim 1, Features: The metal nitride layer is one of a titanium nitride layer, a tantalum nitride layer and an aluminum nitride layer.
5. The method for preparing a semiconductor back-end interconnect structure according to any one of claims 1 to 4, Features: The ratio of nitrogen atoms to metal atoms in the metal nitride layer is 3:10 to 6:10, including endpoint values.
6. The method for preparing a semiconductor back-end interconnect structure according to claim 5, Features: The metal hard mask stack structure is prepared by a PVD process.
7. The method for preparing a semiconductor back-end interconnect structure according to claim 6, Features: When preparing the metal nitride layer in the metal hard mask stack structure, the reaction environment is changed from a nitrogen-rich mode to a metal-rich mode.
8. The method for preparing a semiconductor back-end interconnect structure according to claim 1, Features: The metal hard mask stack structure is formed by stacking a metal nitride layer and a metal layer one to three times.
9. The method for preparing a semiconductor back-end interconnect structure according to claim 1, Features: Before forming the metal hard mask stack structure, the method further includes forming a barrier layer stack on the low-k dielectric layer.
10. The method for preparing a semiconductor back-end interconnect structure according to claim 1, Features: The method of forming the through hole and / or the groove comprises: forming a photoresist layer on the surface of the metal hard mask stack structure and performing patterning; Etching the metal hard mask stack structure based on the patterned photoresist layer to obtain a patterned metal hard mask stack structure, and removing the patterned photoresist layer; The low-k dielectric layer and the etching barrier layer are etched based on the patterned metal hard mask stack structure to form the through hole and / or trench.