Semiconductor structure and forming method thereof
The grooves are formed through dry etching and the side walls of the active region are protected. The residuals of the isolation structure are removed in combination with wet etching, which solves the problem of side wall consumption of the active region during the back etching of the shallow trench isolation structure, and improves the reliability and performance of the semiconductor structure.
Patent Information
- Application Number
- CN202510378944.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2025-05-23
AI Technical Summary
In semiconductor devices, during the back etching of shallow trench isolation structure, the side walls of the active region are easily consumed, resulting in sharp angles, causing leakage, breakdown, electrical and reliability problems.
The shallow trench isolation structure is back-etched by dry etching, forming grooves and keeping the remaining isolation structure covering the groove side walls, thereby protecting the active area side walls. The isolation structure on the liner layer and the groove side walls are then removed by a wet etching process, exposing the active region side walls.
It effectively avoids the consumption of the side wall of the active region during the back etching process, ensures the maintenance of the characteristic size of the active region, improves the reliability and performance of the semiconductor structure, and improves the top surface flatness of the shallow trench isolation structure by removing the residual structure of the "triangle" shape.
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Figure CN120033078A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art
[0002] As the feature size of semiconductor devices continues to shrink, it is required that the density of transistors in semiconductor devices increases while semiconductor devices also need to achieve excellent performance. Embedded memory devices need to obtain large currents on active areas with smaller feature sizes to meet their performance requirements, which requires that the transistors in embedded memory must have a sufficiently long channel length. In order to increase the length of the channel in the transistor, the current main method is to etch back the shallow trench isolation structure (i.e., STI) to expose the sidewalls of the active area, which usually requires the STI to be etched back by about 20 nanometers to 30 nanometers. The existing process uses a wet process and uses BOE (buffered HF solution) with a high etching rate to etch the STI, but the sidewalls of the active area will be etched, resulting in a cut edge phenomenon and sharp corners in the active area. The appearance of sharp corners will lead to the following problems: on the one hand, it is easy to cause leakage and breakdown; on the other hand, the loss of the active area will cause a series of electrical and reliability problems. Moreover, after wet etching, a "W-shaped" profile easily appears at the bottom of the STI, and a "triangular" oxide residue appears close to the side wall of the active area, which is not conducive to controlling the thickness of the gate oxide layer, and thus is not conducive to further improving the performance of the transistor.
[0003] Therefore, how to prevent the active area from being consumed during the back etching process of the shallow trench isolation structure, thereby improving the reliability of the semiconductor structure and improving the performance of the semiconductor structure, is a technical problem that needs to be solved urgently. Summary of the invention
[0004] The present invention provides a semiconductor structure and a forming method thereof, which are used to prevent an active area from being consumed during a shallow trench isolation structure back-etching process, thereby improving the reliability of the semiconductor structure and improving the performance of the semiconductor structure.
[0005] According to some embodiments, the present invention provides a method for forming a semiconductor structure, comprising the following steps:
[0006] Forming a substrate, the substrate comprising a substrate, a liner layer covering the front surface of the substrate, and a shallow trench isolation structure penetrating the liner layer along a first direction and extending into the substrate, the substrate having a plurality of active areas arranged at intervals along a second direction, the shallow trench isolation structure being located between adjacent active areas, and the first direction intersecting the second direction perpendicularly;
[0007] Etching back part of the shallow trench isolation structure to form a groove, and the remaining shallow trench isolation structure also covers the sidewall of the groove;
[0008] The liner layer and the shallow trench isolation structure on the sidewall of the groove are removed to expose a portion of the sidewall of the active area.
[0009] In some embodiments, the specific steps of forming the substrate include:
[0010] Providing the substrate, wherein the substrate comprises a front surface and a back surface which are relatively distributed along the first direction;
[0011] forming a liner layer on the front surface of the substrate;
[0012] forming a first mask layer on the surface of the liner layer, wherein the first mask layer has a first opening penetrating through the first mask layer along the first direction and exposing the liner layer;
[0013] Etching the liner layer and the substrate downward along the first opening to form an isolation trench penetrating the liner layer along the first direction and extending into the substrate, wherein a plurality of the isolation trenches separate the substrate into a plurality of the active areas spaced apart along the second direction;
[0014] An insulating material is filled in the first opening and the isolation trench to form the shallow trench isolation structure whose top surface is flush with the top surface of the first mask layer.
[0015] In some embodiments, the material of the liner layer is the same as the material of the shallow trench isolation structure.
[0016] In some embodiments, the specific steps of etching back part of the shallow trench isolation structure to form a groove include:
[0017] A dry etching process is used to etch back part of the shallow trench isolation structure to form a groove on the top of the remaining shallow trench isolation structure, and the bottom surface of the groove is lower than the front surface of the substrate.
[0018] In some embodiments, the specific steps of etching back part of the shallow trench isolation structure using a dry etching process include:
[0019] forming a second mask layer on a top surface of the first mask layer, wherein the second mask layer has a second opening penetrating the second mask layer along the first direction and exposing the shallow trench isolation structure, and the width of the second opening is smaller than the width of the top of the shallow trench isolation structure;
[0020] The shallow trench isolation structure is partially etched along the second opening to form the groove.
[0021] In some embodiments, the thickness of the shallow trench isolation structure etched back by the dry etching process is 20 nm to 30 nm.
[0022] In some embodiments, a center of the second opening is aligned with a center of the shallow trench isolation structure along the first direction.
[0023] In some embodiments, a difference between a thickness of the shallow trench isolation structure covering a sidewall of the groove and a thickness of the liner layer is less than or equal to 1 nm.
[0024] In some embodiments, before removing the liner layer and the shallow trench isolation structure on the sidewall of the groove, the method further includes the following steps:
[0025] The second mask layer, the first mask layer and a portion of the shallow trench isolation structure on the sidewall of the groove are removed to expose the liner layer, and the top surface of the shallow trench isolation structure on the sidewall of the groove is flush with the top surface of the liner layer.
[0026] In some embodiments, the specific steps of removing the liner layer and the shallow trench isolation structure on the sidewall of the groove include:
[0027] The liner layer and the shallow trench isolation structure on the sidewall of the groove are removed simultaneously by a wet etching process.
[0028] According to some other embodiments, the present invention further provides a semiconductor structure formed by the method for forming a semiconductor structure as described above; the semiconductor structure comprises:
[0029] A substrate, comprising a front surface and a back surface that are relatively distributed along a first direction, wherein the substrate has a plurality of active regions that are spaced apart and arranged along a second direction, wherein the first direction intersects the second direction perpendicularly;
[0030] A shallow trench isolation structure is located between adjacent active regions in the substrate, and a top surface of the shallow trench isolation structure is lower than a top surface of the active region along the first direction.
[0031] The semiconductor structure and the method for forming the same provided by the present invention form a groove on the top of the remaining shallow trench isolation structure when etching back a portion of the shallow trench isolation structure, and the remaining shallow trench isolation structure also covers the sidewall of the groove, so that the sidewall of the active area can be protected by the shallow trench isolation structure remaining on the sidewall of the groove, avoiding the sidewall of the active area from being consumed during the process of etching back the shallow trench isolation structure, ensuring that the characteristic size of the active area maintains the design value, thereby improving the reliability of the semiconductor structure and improving the performance of the semiconductor structure. At the same time, the present invention removes the shallow trench isolation structure remaining on the sidewall of the groove when removing the liner layer, that is, the "triangle" shaped shallow trench isolation structure residue on the sidewall of the active area is eliminated through two consecutive removal processes, improving the flatness of the top surface of the shallow trench isolation structure, thereby further improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] Figure 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention;
[0033] Figure 2 is a schematic structural diagram of a substrate in a specific embodiment of the present invention;
[0034] Figure 3 is a schematic structural diagram of a specific embodiment of the present invention after a second mask layer is formed on a substrate;
[0035] Figure 4 It is a schematic diagram of the structure after the shallow trench isolation structure of the etched-back part is shown in a specific embodiment of the present invention;
[0036] Figure 5 is a schematic diagram of the structure after the first mask layer and the second mask layer are removed in a specific embodiment of the present invention;
[0037] Figure 6 is a schematic diagram of the structure after the liner layer is removed in a specific embodiment of the present invention;
[0038] Figure 7 It is a transmission electron microscope image of a semiconductor structure in a specific embodiment of the present invention.
[0039] Description of Reference Numerals
[0040] 20 Substrate
[0041] 21 Shallow Trench Isolation Structure
[0042] 22 cushion layer
[0043] 23 First mask layer
[0044] 24 Active area
[0045] 30 Second mask layer
[0046] 31 Second Opening
[0047] 40 grooves DETAILED DESCRIPTION
[0048] The specific implementation manner of the semiconductor structure and the method for forming the same provided by the present invention will be described in detail below with reference to the accompanying drawings.
[0049] This specific embodiment provides a method for forming a semiconductor structure. Figure 1 1 is a flow chart of a method for forming a semiconductor structure in a specific embodiment of the present invention. Figure 1 As shown, the method for forming the semiconductor structure comprises the following steps:
[0050] Step S11, forming a substrate, the substrate comprising a substrate, a liner layer covering the front surface of the substrate, and a shallow trench isolation structure penetrating the liner layer along a first direction and extending into the substrate, the substrate having a plurality of active areas arranged at intervals along a second direction, the shallow trench isolation structure being located between adjacent active areas, and the first direction intersecting the second direction perpendicularly;
[0051] Step S12, etching back part of the shallow trench isolation structure to form a groove, and the remaining shallow trench isolation structure also covers the sidewall of the groove;
[0052] Step S13, removing the liner layer and the shallow trench isolation structure on the sidewall of the groove to expose a portion of the sidewall of the active area.
[0053] Figure 2 Schematic diagram of the structure of the substrate in a specific embodiment of the present invention. In some embodiments, the specific steps of forming the substrate include:
[0054] Providing the substrate 20, wherein the substrate 20 includes a front surface and a back surface that are relatively distributed along the first direction D1;
[0055] forming a liner layer 22 on the front surface of the substrate 20;
[0056] forming a first mask layer 23 on the surface of the liner layer 22 , wherein the first mask layer 23 has a first opening penetrating the first mask layer 23 along the first direction D1 and exposing the liner layer 22 ;
[0057] Etching the liner layer 22 and the substrate 20 downward along the first opening to form an isolation trench penetrating the liner layer 22 along the first direction D1 and extending into the substrate 20, wherein the plurality of isolation trenches separate the substrate 20 into the plurality of active areas 24 spaced apart along the second direction D2;
[0058] An insulating material is filled in the first opening and the isolation trench to form the shallow trench isolation structure 21 whose top surface is flush with the top surface of the first mask layer 23 .
[0059] Specifically, the substrate 20 may be, but is not limited to, a silicon substrate. This specific embodiment is described by taking the substrate 20 as a silicon substrate as an example. In one example, a thermal oxidation process may be used to oxidize the front surface of the substrate 20 to form the liner layer 22 whose material includes silicon dioxide. Afterwards, a hard mask material such as silicon nitride is deposited on the surface of the liner layer 22 away from the substrate 20 to form the first mask layer 23. The first mask layer 23 is patterned to form a plurality of first openings in the first mask layer 23 that penetrate the first mask layer 23 along the first direction D1 and expose the liner layer 22, and the plurality of first openings are arranged at intervals along the second direction D2. At the same time, the liner layer 22 and the substrate 20 are etched downward along the plurality of first openings to form a plurality of isolation trenches that penetrate the liner layer 22 along the first direction D1 and extend into the substrate 20, and the plurality of isolation trenches separate the substrate 20 into a plurality of active areas 24 that are arranged at intervals along the second direction D2. Fill the first opening and the isolation trench with insulating materials such as silicon dioxide, and form the shallow trench isolation structure 21 whose top surface is flush with the top surface of the first mask layer 23 by a planarization process such as chemical mechanical polishing. Figure 2 The multiple mentioned in this specific implementation mode refers to more than two.
[0060] In some embodiments, the material of the liner layer 22 is the same as that of the shallow trench isolation structure 21, so that a suitable etchant can be subsequently selected to simultaneously remove the liner layer 22 and the shallow trench isolation structure, while further reducing the manufacturing cost of the semiconductor structure.
[0061] Figure 3 is a schematic structural diagram of a specific embodiment of the present invention after a second mask layer is formed on a substrate, Figure 4 1 is a schematic diagram of the structure after the shallow trench isolation structure of the etched back part is etched back in a specific embodiment of the present invention. In some embodiments, the specific steps of etching back the shallow trench isolation structure of the etched back part to form a groove include:
[0062] A dry etching process is used to etch back part of the shallow trench isolation structure 21 to form a groove 40 on the top of the remaining shallow trench isolation structure 21 , and the bottom surface of the groove 40 is lower than the front surface of the substrate 20 .
[0063] In some embodiments, the specific steps of etching back part of the shallow trench isolation structure 21 using a dry etching process include:
[0064] Forming a second mask layer 30 on the top surface of the first mask layer 23, wherein the second mask layer 30 has a second opening 31 penetrating the second mask layer 30 along the first direction D1 and exposing the shallow trench isolation structure 21, and the width of the second opening 31 is smaller than the width of the top of the shallow trench isolation structure 21;
[0065] A portion of the shallow trench isolation structure 21 is etched along the second opening 31 to form the groove 40 .
[0066] For example, the second mask layer 30 is deposited on the top surface of the first mask layer 23 (i.e., the surface of the first mask layer 23 facing away from the substrate 20), and the second mask layer 30 is patterned to form a plurality of second openings 31 in the second mask layer 30 that penetrate the second mask layer 30 along the first direction D1 and expose the shallow trench isolation structure 21, and the plurality of second openings 31 are arranged at intervals along the second direction D2, and the plurality of second openings 31 correspond one-to-one to the plurality of shallow trench isolation structures 21. By setting the width of the second opening 31 (e.g., the width of the second opening 31 along the second direction D2) to be smaller than the width of the top of the shallow trench isolation structure 21 (e.g., the width of the top of the shallow trench isolation structure 21 along the second direction D2), the patterned second mask layer 30 covers part of the top surface of the shallow trench isolation structure 21, thereby avoiding the loss of the sidewall of the active area 24 during the back etching of the shallow trench isolation structure 21 by the dry etching process, and ensuring the stability of the characteristic size of the active area 24. The use of the dry etching process to back-etch part of the shallow trench isolation structure 21 can avoid the problem of active area loss caused by the long-term contact of the active area with the wet etching solution in the wet etching process, thereby further ensuring that the characteristic size of the active area maintains the design value.
[0067] In some embodiments, the thickness of the shallow trench isolation structure 21 etched back by the dry etching process is 20 nm to 30 nm.
[0068] For example, by controlling the etching parameters in the dry etching process, such as the dosage of the dry etchant, the etching time, the etching pressure and / or the etching temperature, the thickness of the shallow trench isolation structure 21 etched by the dry etching process (for example, the thickness along the first direction D1) is 20nm to 30nm. On the one hand, it can avoid the effect of the shallow trench isolation structure 21 isolating the adjacent active area 24 due to the thickness of the shallow trench isolation structure 21 being etched back being too thick; on the other hand, it can avoid the effect of not being able to obtain a large current on the active area due to the thickness of the shallow trench isolation structure 21 being etched back being too thin.
[0069] In some embodiments, the center of the second opening 31 is aligned with the center of the shallow trench isolation structure 21 along the first direction D1, so that the remaining portion of the shallow trench isolation structure 21 is distributed around the periphery of the groove 40 to protect the side walls of the active area 24 at the periphery of the shallow trench isolation structure 21 (for example, on opposite sides of the shallow trench isolation structure 21 along the second direction D2), so as to further improve and enhance the performance of the semiconductor structure.
[0070] In some embodiments, a difference between a thickness of the shallow trench isolation structure 21 covering the sidewall of the groove 40 and a thickness of the liner layer 22 is less than or equal to 1 nm.
[0071] In one example, the thickness of the liner layer 22 (for example, the thickness of the liner layer 22 along the first direction D1) is 11 nm, and the thickness of the shallow trench isolation structure 21 covering the sidewall of the groove 40 (for example, the thickness along the second direction D2) is 10 nm to 12 nm. By making the difference between the thickness of the shallow trench isolation structure 21 covering the sidewall of the groove 40 and the thickness of the liner layer 22 less than or equal to 1 nm, the thickness of the shallow trench isolation structure 21 covering the sidewall of the groove 40 is close to the thickness of the liner layer 22, thereby ensuring that the shallow trench isolation structure 21 remaining on the sidewall of the groove 40 is fully removed when the liner layer 22 is removed, and reducing the loss of the shallow trench isolation structure 21 remaining at the bottom of the groove 40, thereby improving the flatness of the top surface of the remaining shallow trench isolation structure 21.
[0072] Figure 5 2 is a schematic diagram of a structure after removing the first mask layer and the second mask layer in a specific embodiment of the present invention. In some embodiments, before removing the liner layer 22 and the shallow trench isolation structure 21 on the sidewall of the groove 40, the following steps are also included:
[0073] The second mask layer 30 , the first mask layer 23 and a portion of the shallow trench isolation structure 21 on the sidewall of the groove 40 are removed to expose the liner layer 22 , and the top surface of the shallow trench isolation structure 21 on the sidewall of the groove 40 is flush with the top surface of the liner layer 22 .
[0074] In one example, by adjusting the material of the first mask layer 23, the material of the second mask layer 30 and / or the type of etchant, the second mask layer 30, the first mask layer 23 and a portion of the shallow trench isolation structure 21 on the side wall of the groove 40 can be simultaneously removed to expose the liner layer 22, and the top surface of the shallow trench isolation structure 21 on the side wall of the groove 40 is flush with the top surface of the liner layer 22, thereby further improving the manufacturing efficiency of the semiconductor structure.
[0075] Figure 6 is a schematic diagram of the structure after the liner layer is removed in a specific embodiment of the present invention, Figure 7 is a transmission electron microscope image of a semiconductor structure in a specific embodiment of the present invention. In some embodiments, the specific steps of removing the liner layer and the shallow trench isolation structure on the sidewall of the groove include:
[0076] The liner layer 22 and the shallow trench isolation structure 21 on the sidewall of the groove 40 are removed simultaneously by a wet etching process.
[0077] For example, the parameters of the wet etching process can be controlled, such as any one or a combination of two or more of the type of wet etchant, the dosage of the wet etchant, the etching temperature, the etching pressure and the etching time, so that the wet etching process is stopped after the liner layer 22 and the shallow trench isolation structure 21 on the side wall of the groove 40 are simultaneously removed, so that the shallow trench isolation structure 21 on part of the side wall of the active area 24 is fully removed through two successive removal processes, and the "triangle" shaped shallow trench isolation structure 21 residue on the side wall of the active area 24 is eliminated, thereby improving the flatness of the top surface of the shallow trench isolation structure 21 after the wet etching process, so that the top surface of the shallow trench isolation structure 21 remaining after the wet etching process is close to flat, such as Figure 7 As shown, the performance of the semiconductor structure is further improved.
[0078] This specific embodiment also provides a semiconductor structure, which is formed by the semiconductor structure forming method as described above. Figure 1-Figure 7 , the schematic diagram of the semiconductor structure can be seen in Figure 6 and Figure 7 .like Figure 1-Figure 7 As shown, the semiconductor structure comprises:
[0079] A substrate 20, comprising a front surface and a back surface that are relatively distributed along a first direction D1, wherein the substrate 20 has a plurality of active regions 24 that are spaced apart along a second direction D2, wherein the first direction D1 intersects the second direction D2 perpendicularly;
[0080] The shallow trench isolation structure 21 is located between adjacent active regions 24 in the substrate 20 , and a top surface of the shallow trench isolation structure 21 is lower than a top surface of the active region 24 along the first direction D1 .
[0081] The semiconductor structure and the method for forming the same provided in this specific embodiment form a groove on the top of the remaining shallow trench isolation structure when etching back part of the shallow trench isolation structure, and the remaining shallow trench isolation structure also covers the sidewall of the groove, so that the sidewall of the active area can be protected by the shallow trench isolation structure remaining on the sidewall of the groove, avoiding the sidewall of the active area from being consumed in the process of etching back the shallow trench isolation structure, ensuring that the characteristic size of the active area remains at the designed value, thereby improving the reliability of the semiconductor structure and improving the performance of the semiconductor structure. At the same time, this specific embodiment removes the shallow trench isolation structure remaining on the sidewall of the groove when removing the liner layer, that is, the "triangle" shaped shallow trench isolation structure residue on the sidewall of the active area is eliminated through two consecutive removal processes, thereby improving the flatness of the top surface of the shallow trench isolation structure, thereby further improving the performance of the semiconductor structure.
[0082] The above is only a preferred embodiment of the present invention. It should be pointed out that ordinary technicians in this technical field can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.
Claims
1. A method for forming a semiconductor structure, characterized in that: The steps include: Forming a substrate, the substrate comprising a substrate, a liner layer covering the front surface of the substrate, and a shallow trench isolation structure penetrating the liner layer along a first direction and extending into the substrate, the substrate having a plurality of active areas arranged at intervals along a second direction, the shallow trench isolation structure being located between adjacent active areas, and the first direction intersecting the second direction perpendicularly; Etching back part of the shallow trench isolation structure to form a groove, and the remaining shallow trench isolation structure also covers the sidewall of the groove; The liner layer and the shallow trench isolation structure on the sidewall of the groove are removed to expose a portion of the sidewall of the active area.
2. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of forming the substrate include: Providing the substrate, wherein the substrate comprises a front surface and a back surface which are relatively distributed along the first direction; forming a liner layer on the front surface of the substrate; forming a first mask layer on the surface of the liner layer, wherein the first mask layer has a first opening penetrating through the first mask layer along the first direction and exposing the liner layer; Etching the liner layer and the substrate downward along the first opening to form an isolation trench penetrating the liner layer along the first direction and extending into the substrate, wherein a plurality of the isolation trenches separate the substrate into a plurality of the active areas spaced apart along the second direction; An insulating material is filled in the first opening and the isolation trench to form the shallow trench isolation structure whose top surface is flush with the top surface of the first mask layer.
3. The method for forming a semiconductor structure according to claim 2, wherein: The material of the liner layer is the same as that of the shallow trench isolation structure.
4. The method for forming a semiconductor structure according to claim 2, wherein: The specific steps of etching back part of the shallow trench isolation structure to form a groove include: A dry etching process is used to etch back part of the shallow trench isolation structure to form a groove on the top of the remaining shallow trench isolation structure, and the bottom surface of the groove is lower than the front surface of the substrate.
5. The method for forming a semiconductor structure according to claim 4, characterized in that: The specific steps of etching back part of the shallow trench isolation structure using a dry etching process include: forming a second mask layer on a top surface of the first mask layer, wherein the second mask layer has a second opening penetrating the second mask layer along the first direction and exposing the shallow trench isolation structure, and the width of the second opening is smaller than the width of the top of the shallow trench isolation structure; The shallow trench isolation structure is partially etched along the second opening to form the groove.
6. The method for forming a semiconductor structure according to claim 5, characterized in that: The thickness of the shallow trench isolation structure etched back by the dry etching process is 20nm-30nm.
7. The method for forming a semiconductor structure according to claim 5, characterized in that: The center of the second opening is aligned with the center of the shallow trench isolation structure along the first direction.
8. The method for forming a semiconductor structure according to claim 1, wherein: A difference between a thickness of the shallow trench isolation structure covering the sidewall of the groove and a thickness of the liner layer is less than or equal to 1 nm.
9. The method for forming a semiconductor structure according to claim 5, wherein: Before removing the liner layer and the shallow trench isolation structure on the sidewall of the groove, the method further includes the following steps: The second mask layer, the first mask layer and a portion of the shallow trench isolation structure on the sidewall of the groove are removed to expose the liner layer, and the top surface of the shallow trench isolation structure on the sidewall of the groove is flush with the top surface of the liner layer.
10. The method for forming a semiconductor structure according to claim 1, wherein: The specific steps of removing the liner layer and the shallow trench isolation structure on the sidewall of the groove include: The liner layer and the shallow trench isolation structure on the sidewall of the groove are removed simultaneously by a wet etching process.
11. A semiconductor structure, characterized in that: The semiconductor structure is formed by the method for forming a semiconductor structure according to claim 1; the semiconductor structure comprises: A substrate, comprising a front surface and a back surface that are relatively distributed along a first direction, wherein the substrate has a plurality of active regions that are spaced apart and arranged along a second direction, wherein the first direction intersects the second direction perpendicularly; A shallow trench isolation structure is located between adjacent active regions in the substrate, and a top surface of the shallow trench isolation structure is lower than a top surface of the active region along the first direction.