Micro bump stack welding chip assembly and three-dimensional stack packaging method

Abstract

The invention relates to the field of three-dimensional stack packaging, and provides a micro bump stack welding chip assembly and a three-dimensional stack packaging method. The micro salient point stacking welding chip assembly comprises a composite chip and a carrier chip, one surface of the composite chip is a first functional surface, and the first functional surface is provided with a plurality of functional micro salient points for welding and a plurality of self-alignment solder balls arranged at intervals; one surface of the carrier chip is a second functional surface, and the second functional surface is provided with a plurality of functional pads in one-to-one correspondence with the plurality of functional micro bumps and a plurality of carrier pads in one-to-one correspondence with the plurality of self-aligned solder balls. The packaging method comprises the step of welding the composite chip and the carrier chip. In the chip welding process, self-alignment of the functional micro convex points can be achieved through surface tension traction of the self-alignment welding balls, chip offset is reduced, the packaging yield is improved, the requirement for equipment alignment precision is not too high, the chip stacking production efficiency is greatly improved, and the production cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of three-dimensional stacking packaging, and in particular to a micro-bump stacking welding chip component and a three-dimensional stacking packaging method. Background Art

[0002] The rapid development of 3D packaging technology mainly relies on the microbump bonding interconnection technology. According to the pitch of the bumps, the stacking bonding methods of copper pillar bumps are divided into two methods: reflow soldering and thermal compression bonding (TCB). Reflow soldering is mainly suitable for bumps with a pitch greater than 50 microns. As the number of chip pins increases and the pitch of pads decreases, bridges and short circuits are prone to occur between larger bumps. In order to improve the bridging and short circuit problems, microbumps with a pitch less than 50 microns can be used for stacking bonding. When the bump pitch is less than 50 microns, the limited solder volume surface tension in the microbump structure is not enough to achieve self-alignment of the copper pillar and the solder cap, resulting in offset between the bumps, which greatly affects the yield and reliability of the packaged chip. The TCB method uses a pair of ultra-high-precision cameras that image upward and downward to identify the microbumps on the chip and the substrate pads, which can achieve precise alignment of the microbumps. However, the TCB bonding method has high requirements for equipment alignment accuracy, long single-chip operation time and low operation efficiency, which increases production costs and operation cycles.

[0003] In view of this, this application is hereby filed. Summary of the invention

[0004] The purpose of the present invention includes providing a micro-bump stacking welding chip assembly and a three-dimensional stacking packaging method, aiming to improve at least one problem mentioned in the background technology.

[0005] The embodiments of the present invention can be implemented as follows: In a first aspect, the present invention provides a micro-bump stacked welding chip assembly, comprising a composite chip and a carrier chip for stacking and welding each other; One side of the composite chip is a first functional side, on which a plurality of functional micro-bumps for welding and a plurality of self-aligned solder balls arranged at intervals are arranged, and a pitch of the functional micro-bumps is less than 50 μm; One side of the carrier chip is a second functional surface, on which a plurality of functional pads corresponding to a plurality of functional micro-bumps and a plurality of carrier pads corresponding to a plurality of self-aligned solder balls are arranged.

[0006] In an optional embodiment, the composite chip includes a chip body, a first dielectric layer, a redistribution layer, a second dielectric layer, functional micro-bumps, and self-aligned solder balls; One side of the chip body has a plurality of pads, a first dielectric layer is arranged on the side of the chip body having the pads, the first dielectric layer is provided with conductive holes corresponding to the plurality of pads one by one, and each conductive hole is filled with a conductive metal; The redistribution layer is arranged on a side of the first dielectric layer away from the chip body, and the redistribution layer includes a plurality of functional redistribution parts and a plurality of non-functional redistribution parts, and each functional redistribution part is electrically connected to the conductive metal in the corresponding conductive hole; The second dielectric layer covers the redistribution layer, and the second dielectric layer is provided with a plurality of first solder holes and a plurality of second solder holes. A functional micro-bump is arranged in each first solder hole, and the functional micro-bump is electrically connected to the functional redistribution part; a self-alignment solder ball is arranged in each second solder hole, and the self-alignment solder ball is connected to a non-functional redistribution part.

[0007] In an optional embodiment, the plurality of functional micro-bumps are located in an internal effective area of ​​the composite chip, and the plurality of self-aligned solder balls are located near an edge of the composite chip or in an open area within the effective area.

[0008] In an optional embodiment, the functional micro-bump has a diameter of 5 to 50 μm and a height of 10 to 50 μm.

[0009] In an optional embodiment, the self-aligned solder ball has a diameter of 50-300 μm and a height of 50-200 μm.

[0010] In an optional embodiment, a testing and wire bonding pad is further provided in a region near the edge of the second functional surface of the carrier chip.

[0011] In an alternative embodiment, the element composition of the self-aligned solder ball includes one or more of tin, silver, copper, lead, bismuth and indium.

[0012] In an optional embodiment, the element composition of the functional micro-bump includes one or more of copper, nickel, tin, silver, lead, bismuth and indium.

[0013] In a second aspect, the present invention provides a three-dimensional stacking packaging method for welding a micro-bump stacking welding chip assembly as described in any of the above embodiments, comprising: The first functional surface of the composite chip is oriented toward the second functional surface of the carrier chip for welding. Under the pulling action of the surface tension of the self-aligned solder balls, the functional micro-bumps and the corresponding functional pads are aligned and welded.

[0014] In an optional embodiment, the soldering method is reflow soldering or TCB soldering.

[0015] The beneficial effects of the micro-bump stacking welding chip assembly and the three-dimensional stacking packaging method provided by the embodiments of the present invention include: Since one side of the composite chip with functional microbumps is provided with a plurality of self-aligning solder balls, when two chips are aligned and welded, the temperature of the self-aligning solder balls rises to a liquid or semi-solid state. Since the solder balls have a larger welding volume relative to the functional microbumps, they can achieve self-alignment with the corresponding carrier pads under the action of the surface tension of the solder balls. At the same time as the solder balls achieve self-alignment, the functional microbumps can also be aligned with the functional pads, and this alignment does not require the equipment to have too high precision.

[0016] Therefore, the microbump stacked and welded chip assembly and the three-dimensional stacked packaging method provided by the present invention can achieve self-alignment of functional microbumps during the chip welding process, which not only reduces chip offset and improves the packaging yield, but also does not require too high precision for the equipment alignment accuracy, greatly improving the chip stacking production efficiency and reducing the production cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can also be obtained based on these drawings without creative efforts.

[0018] Figure 1 It is a schematic structural diagram of a chip body; Figure 2 It is a schematic structural diagram of a first dielectric layer provided on the chip body; Figure 3 It is a schematic structural diagram after depositing conductive metal in the conductive holes on the first dielectric layer; Figure 4 It is a schematic structural diagram of a redistribution layer provided on the first dielectric layer; Figure 5 It is a schematic structural diagram of a second dielectric layer provided on the redistribution layer; Figure 6 It is a schematic structural diagram after setting functional microbumps in the first solder holes of the second dielectric layer; Figure 7 It is a schematic structural diagram after setting self-aligning solder balls in the second solder holes of the second dielectric layer; Figure 8 It is a schematic diagram when the composite chip and the carrier chip are welded.

[0019] Reference numerals: 10 - microbump stacked and welded chip assembly; 100-composite chip; 101-functional micro-bump; 102-self-aligned solder ball; 110-chip body; 111-pad; 120-first dielectric layer; 121-conductive hole; 122-conductive metal; 130-rewiring layer; 131-functional rewiring part; 132-non-functional rewiring part; 140-second dielectric layer; 141-first solder hole; 142-second solder hole; 200 - carrier chip; 201 - functional pad; 202 - carrier pad; 203 - test and wire bonding pad. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0023] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0024] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0025] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0026] like Figure 8 As shown, an embodiment of the present invention provides a micro-bump stacked welding chip assembly 10, including a composite chip 100 and a carrier chip 200.

[0027] One side of the composite chip 100 is a first functional side, and the first functional side is provided with a plurality of functional micro bumps 101 for welding and a plurality of self-aligned solder balls 102 arranged at intervals.

[0028] Alternatively, if Figures 1 to 8 As shown, the composite chip 100 includes a chip body 110, a first dielectric layer 120, a redistribution layer 130, a second dielectric layer 140, functional micro-bumps 101 and self-aligned solder balls; One side of the chip body 110 has a plurality of pads 111. The first dielectric layer 120 is disposed on the side of the chip body 110 having the pads 111. The first dielectric layer 120 is provided with conductive holes 121 corresponding to the plurality of pads 111. Each conductive hole 121 is filled with a conductive metal 122. The redistribution layer 130 is disposed on a side of the first dielectric layer 120 away from the chip body 110 . The redistribution layer 130 includes a plurality of functional redistribution portions 131 and a plurality of non-functional redistribution portions 132 . Each functional redistribution portion 131 is electrically connected to the conductive metal 122 in the corresponding conductive hole 121 . The second dielectric layer 140 covers the redistribution layer 130, and a plurality of first solder holes 141 and a plurality of second solder holes 142 are opened on the second dielectric layer 140. A functional micro-bump 101 is arranged in each first solder hole 141, and the functional micro-bump 101 is electrically connected to the functional redistribution part 131; a self-alignment solder ball 102 is arranged in each second solder hole 142, and the self-alignment solder ball 102 is connected to a non-functional redistribution part 132.

[0029] Optionally, the plurality of functional micro-bumps 101 are located in the middle of the composite chip 100 , and the plurality of self-aligned solder balls 102 are located near the edge of the composite chip 100 or in an open area within the effective area.

[0030] The middle of the composite chip 100 belongs to the effective area, the functional micro bumps 101 are located in the effective area, the area near the edge of the composite chip 100 belongs to the ineffective area, and the self-aligned solder balls are located on the ineffective area or in the empty area inside.

[0031] Furthermore, the packaging method of the composite chip 100 includes: S1, such as Figure 1 and Figure 2 As shown, a first dielectric layer 120 is disposed on the chip body 110, and a conductive hole 121 is formed by opening a window at a position corresponding to the pad 111 on the first dielectric layer 120; Optionally, the material of the first dielectric layer 120 is polyimide (PI), poly(p-phenylene benzobisoxazole) (PBO), silicon dioxide, silicon nitride or phosphosilicate glass (PSG).

[0032] S2, such as Figure 3 As shown, a conductive metal 122 is deposited in the conductive hole 121 by metal deposition or the like, so that the conductive metal 122 is electrically connected to the pad 111; Optionally, the conductive metal 122 may be titanium, tungsten, aluminum, copper, gold, or alloys thereof, and copper is generally preferred.

[0033] S3, such as Figure 4 As shown, a redistribution layer 130 is disposed on the first dielectric layer 120 by electroplating, metal deposition, etc., including a functional redistribution portion 131 and a non-functional redistribution portion 132, so that the functional redistribution portion 131 is electrically connected to the conductive metal 122 in the corresponding conductive hole 121, the functional redistribution portion 131 is used to carry the functional micro-bump 101, and the non-functional redistribution portion 132 is used to carry the self-aligned solder ball; Optionally, the redistribution layer 130 may be made of titanium, tungsten, aluminum, copper, gold or alloys of the aforementioned metals.

[0034] S4, such as Figure 5 As shown, a second dielectric layer 140 is covered on the redistribution layer 130 , and a first welding hole 141 and a second welding hole 142 are opened on the second dielectric layer 140 ; Optionally, the material of the second dielectric layer 140 is polyimide (PI), poly(p-phenylene benzobisoxazole) (PBO), silicon dioxide, silicon nitride or phospho-silicate glass (PSG).

[0035] S5, such as Figure 6 As shown, a functional micro-bump 101 is provided in the first welding hole 141 by electroplating or metal deposition; Optionally, the element composition of the functional micro-bump 101 includes one or more of copper, nickel, tin, silver, lead, bismuth and indium.

[0036] Optionally, the diameter r of the functional micro-bump 101 is 1 5~50μm (e.g. 5μm, 10μm, 15μm, 20μm, 30μm, 40μm or 50μm), height h 1 50~200μm (for example, 50μm, 80μm, 100μm, 150μm or 200μm).

[0037] Functional micro-bumps 101 of this size can ensure welding quality and avoid bridging and short circuits.

[0038] S6, such as Figure 7 As shown, a self-aligned solder ball 102 is disposed in the second solder hole 142 by electroplating or ball planting, and the self-aligned solder ball 102 is placed on the non-functional redistribution portion 132 .

[0039] Optionally, the material of the self-aligned solder ball is a conventional solder material for packaging, for example, the element composition of the self-aligned solder ball includes one or more of tin, silver, copper, lead, bismuth and indium.

[0040] Optionally, the diameter r of the self-aligning solder ball 2 50~300μm (e.g. 50μm, 80μm, 100μm, 150μm, 200μm, 250μm or 300μm), height h 2 50~200μm (for example, 50μm, 80μm, 100μm, 150μm or 200μm).

[0041] The self-aligned solder balls of this size have sufficient surface tension to ensure self-alignment during soldering.

[0042] One side of the carrier chip 200 is a second functional surface, on which a plurality of functional pads 201 corresponding one-to-one to the plurality of functional micro-bumps 101 and a plurality of carrier pads 202 corresponding one-to-one to the plurality of self-aligned solder balls 102 are arranged.

[0043] Furthermore, a testing and wire bonding pad 203 is disposed in an area near the edge of the second functional surface of the carrier chip 200 .

[0044] like Figure 8 As shown, a three-dimensional stacking packaging method provided by an embodiment of the present invention is used to weld the functional micro-bump stacking welding chip assembly 10 provided by an embodiment of the present invention, comprising: The first functional surface of the composite chip 100 is oriented toward the second functional surface of the carrier chip 200 for welding. Under the action of the self-aligned solder balls, the functional micro-bumps 101 and the corresponding functional pads 201 are aligned and welded.

[0045] Since the packaging method uses the composite chip 100 with self-aligned solder balls to weld with the carrier chip 200, the functional micro-bumps 101 and the corresponding functional pads 201 can be aligned during welding.

[0046] Optionally, the soldering method is reflow soldering or TCB soldering.

[0047] The micro-bump stacking welding chip assembly 10 and the three-dimensional stacking packaging method provided by the embodiments of the present invention have the following advantages: Since one side of the composite chip 100 having the functional micro-bumps 101 is provided with a plurality of self-alignment solder balls 102, when the two chips are aligned and welded, the temperature of the self-alignment solder balls rises and they become liquid or semi-solid. Since the self-alignment solder balls 102 have a larger volume than the functional micro-bumps 101, they can achieve self-alignment with the corresponding carrier pads 202 under the action of the surface tension of the self-alignment solder balls. While the self-alignment solder balls achieve self-alignment, they can also align the functional micro-bumps 101 with the functional pads 201. This alignment does not require the equipment to have too high precision.

[0048] Therefore, the micro-bump stacked welding chip assembly 10 and the three-dimensional stacked packaging method provided by the present invention can achieve self-alignment of the functional micro-bumps 101 during the chip welding process, which not only reduces chip offset and improves packaging yield, but also does not have too high requirements on equipment positioning accuracy, greatly improving chip stacking production efficiency and reducing production costs.

[0049] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a technician familiar with the technical field within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A micro-bump stacked welding chip assembly, characterized in that: It includes a composite chip and a carrier chip for stacking and welding with each other; One side of the composite chip is a first functional side, the first functional side is provided with a plurality of functional micro-bumps for welding and a plurality of self-aligned solder balls arranged at intervals, and the pitch of the functional micro-bumps is less than 50 μm; One side of the carrier chip is a second functional surface, on which a plurality of functional pads corresponding one-to-one to the plurality of functional micro-bumps and a plurality of carrier pads corresponding one-to-one to the plurality of self-aligned solder balls are arranged.

2. The micro-bump stacking welding chip assembly according to claim 1, characterized in that: The composite chip comprises a chip body, a first dielectric layer, a redistribution layer, a second dielectric layer, the functional micro-bumps and the self-aligned solder balls; One side of the chip body has a plurality of pads, the first dielectric layer is arranged on the side of the chip body having the pads, the first dielectric layer is provided with conductive holes corresponding to the plurality of pads one by one, and each of the conductive holes is filled with a conductive metal; The redistribution layer is arranged on a side of the first dielectric layer away from the chip body, the redistribution layer comprises a plurality of functional redistribution parts and a plurality of non-functional redistribution parts, each of the functional redistribution parts is electrically connected to the conductive metal in the corresponding conductive hole; The second dielectric layer covers the redistribution layer, and a plurality of first solder holes and a plurality of second solder holes are opened on the second dielectric layer. A functional micro-bump is arranged in each of the first solder holes, and the functional micro-bump is electrically connected to the functional redistribution part; a self-alignment solder ball is arranged in each of the second solder holes, and the self-alignment solder ball is connected to one of the non-functional redistribution parts.

3. The micro-bump stack welding chip assembly according to claim 1, characterized in that: The plurality of functional micro-bumps are located in an internal effective area of ​​the composite chip, and the plurality of self-aligned solder balls are located near an edge of the composite chip or in an open area within the effective area.

4. The micro-bump stack welding chip assembly according to claim 1, characterized in that: The functional micro-bumps have a diameter of 5-50 μm and a height of 10-50 μm.

5. The micro-bump stack welding chip assembly according to claim 1, characterized in that: The self-aligned solder ball has a diameter of 50-300 μm and a height of 50-200 μm.

6. The micro-bump stack welding chip assembly according to claim 1, characterized in that: A testing and wire bonding pad is also provided in an area close to the edge of the second functional surface of the carrier chip.

7. The micro-bump stack welding chip assembly according to claim 1, characterized in that: The element composition of the self-aligned solder ball includes one or more of tin, silver, copper, lead, bismuth and indium.

8. The micro-bump stack welding chip assembly according to claim 1, characterized in that: The element composition of the functional micro-bumps includes one or more of copper, nickel, tin, silver, lead, bismuth and indium.

9. A three-dimensional stacking packaging method, characterized in that: Used for welding the functional micro-bump stack welding chip assembly as claimed in any one of claims 1 to 8, comprising: The first functional surface of the composite chip is oriented toward the second functional surface of the carrier chip to weld the two together, and under the surface tension traction of the self-aligned solder balls, the functional micro-bumps and the corresponding functional pads are aligned and welded.

10. The three-dimensional stacking packaging method according to claim 9, characterized in that: The soldering method is reflow soldering or TCB soldering.

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