Low-coupling rewiring packaging structure and preparation method thereof

Abstract

The invention provides a low-coupling rewiring packaging structure and a preparation method thereof, and relates to the chip packaging technology, the packaging structure comprises a chip, a plastic package body, a dielectric layer, a reconfiguration circuit layer and solder balls, and the front surface of the chip is provided with a metal layer; the plastic package body wraps the periphery of the chip; the dielectric layer is arranged on the surface of the metal layer and covers the plastic package body; the reconstruction line layer is arranged in the dielectric layer and is connected with the metal layer; the solder ball is arranged on one side, far away from the chip, of the dielectric layer and is connected with the reconfiguration circuit layer; wherein the metal layer is etched to form an avoiding gap, the avoiding gap penetrates through the metal layer, and the projection of the reconstruction circuit layer on the front surface of the chip is at least partially overlapped with the avoiding gap. Compared with the prior art, by forming the avoiding gap overlapped with the reconstruction circuit layer on the metal layer, the overlapping area of the reconstruction circuit layer and the metal layer can be greatly reduced, the coupling effect with the RDL is reduced, and the return loss result of a high-frequency signal is greatly improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a low-coupling redistribution packaging structure and a preparation method thereof. Background Art

[0002] In current FO (Fan-Out) products, a certain thickness of PI dielectric is filled between the reconstruction line (RDL) and the Al metal on the chip surface. The distance between the reconstruction line and the Al layer on the chip surface is relatively close, and the reconstruction line is also made of metal. Therefore, a layer of non-conductive material is sandwiched between two layers of metal, forming a capacitor. The current RDL wiring range overlaps with the Al metal over a large area, resulting in capacitive coupling in the transmission path, causing low signal impedance and poor return loss of high-frequency signals (-4dB). Summary of the Invention

[0003] The purpose of the present invention is to provide a low-coupling rewiring packaging structure and a method for preparing a low-coupling rewiring packaging structure, which can reduce the overlapping area between the RDL wiring range and the Al metal, reduce the coupling effect with the RDL, and significantly improve the return loss of high-frequency signals (-11dB).

[0004] In a first aspect, the present invention provides a low-coupling redistribution packaging structure, comprising:

[0005] A chip, wherein a metal layer is provided on the front side of the chip;

[0006] A plastic package body, the plastic package body covering around the chip;

[0007] a dielectric layer, the dielectric layer being disposed on the surface of the metal layer and covering the plastic package;

[0008] a reconstructed circuit layer, wherein the reconstructed circuit layer is disposed in the dielectric layer and connected to the metal layer;

[0009] a solder ball, the solder ball being arranged on a side of the dielectric layer away from the chip and connected to the reconstructed circuit layer;

[0010] A relief notch is etched on the metal layer, the relief notch penetrates the metal layer, and a projection of the reconstruction circuit layer on the front surface of the chip at least partially overlaps with the relief notch.

[0011] In an optional embodiment, the avoidance gap is filled with a passivation layer.

[0012] In an optional embodiment, the thickness of the passivation layer is the same as the thickness of the metal layer, so that the passivation layer and the metal layer are flush with each other.

[0013] In an optional embodiment, the avoidance gap is rectangular, and at least one side edge of the avoidance gap overlaps with a projected edge of the reconstruction circuit layer on the front surface of the chip.

[0014] In an optional embodiment, a projection area Sa of the reconstructed circuit layer on the front surface of the chip is smaller than a projection area Sb of the solder ball on the front surface of the chip.

[0015] In an optional embodiment, a projection area Sa of the reconstructed circuit layer on the front surface of the chip is less than or equal to half of a projection area Sb of the solder ball on the front surface of the chip.

[0016] In an optional embodiment, the dielectric layer includes a first PI layer and a second PI layer, the first PI layer is arranged on the surface of the plastic package and the metal layer and covers the avoidance gap, the second PI layer covers the first PI layer, and the reconstruction circuit layer is arranged in the second PI layer.

[0017] In an optional embodiment, a first conductive layer is further provided in the first PI layer. The first conductive layer is staggered with the avoidance gap and is connected to the metal layer and the reconstruction circuit layer at the same time.

[0018] In an optional embodiment, the dielectric layer also includes a third PI layer, the third PI layer covers the second PI layer, and a second conductive layer is provided in the third PI layer, the second conductive layer is connected to the reconstruction circuit layer, and the solder ball is provided on the side of the third PI layer away from the chip and is connected to the second conductive layer.

[0019] In an optional embodiment, a third conductive layer is further provided on the third PI layer, the third conductive layer is connected to the second conductive layer, and the solder ball is provided on the third conductive layer.

[0020] In a second aspect, the present invention provides a method for preparing a low-coupling rewiring package structure, which is used to prepare the low-coupling rewiring package structure as described in the above embodiment, and the preparation method comprises:

[0021] providing a vehicle;

[0022] Mounting a chip on the carrier, wherein the front side of the chip faces upward and is provided with a metal layer;

[0023] forming a plastic package on the carrier, wherein the plastic package covers the periphery of the chip;

[0024] Etching a relief notch on the metal layer, wherein the relief notch penetrates the metal layer;

[0025] forming a dielectric layer and a reconstructed circuit layer on the surface of the plastic package, wherein the dielectric layer is disposed on the surface of the metal layer and covers the plastic package, and the reconstructed circuit layer is disposed in the dielectric layer and connected to the metal layer;

[0026] forming solder balls on a side of the dielectric layer away from the chip, wherein the solder balls are connected to the reconstructed circuit layer;

[0027] The projection of the reconstructed circuit layer on the front surface of the chip at least partially overlaps with the avoidance gap.

[0028] In an optional embodiment, after the step of etching the metal layer to form an avoidance gap, the preparation method further comprises:

[0029] A passivation layer is formed by filling the avoidance gap.

[0030] The beneficial effects of the embodiments of the present invention include:

[0031] The low-coupling rewiring packaging structure and its preparation method provided by the embodiment of the present invention are as follows: a metal layer is provided on the front side of the chip, a plastic package is wrapped around the chip, and then a dielectric layer is provided on the surface of the metal layer and covers the plastic package. A reconstruction circuit layer is provided in the dielectric layer, and the reconstruction circuit layer is electrically connected to the metal layer. At the same time, a solder ball is provided on the side of the dielectric layer away from the chip, and the solder ball is connected to the reconstruction circuit layer. A avoidance notch is etched on the metal layer, and the avoidance notch passes through the metal layer, and the projection of the reconstruction circuit layer on the front side of the chip at least partially overlaps with the avoidance notch. Compared with the prior art, the low-coupling rewiring packaging structure provided by the embodiment of the present invention can significantly reduce the overlapping area of ​​the reconstruction circuit layer and the metal layer by forming a avoidance notch on the metal layer that overlaps with the reconstruction circuit layer, reducing the coupling effect with the RDL, and significantly improving the return loss of high-frequency signals (-11dB). BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0033] Figure 1 A schematic cross-sectional view of a low-coupling rewiring package structure provided by an embodiment of the present invention;

[0034] Figure 2 for Figure 1 A partial enlarged schematic diagram of point II in the middle;

[0035] Figure 3 is a partial cross-sectional schematic diagram of a low-coupling redistribution packaging structure in another preferred embodiment of the present invention;

[0036] Figure 4 A top view of a low-coupling redistribution packaging structure provided by an embodiment of the present invention;

[0037] Figure 5 is a cross-sectional schematic diagram of a low-coupling redistribution packaging structure in another preferred embodiment of the present invention;

[0038] Figures 6 to 10 A process flow chart of a method for preparing a low-coupling rewiring packaging structure provided by an embodiment of the present invention.

[0039] Icons: 100-low-coupling rewiring packaging structure; 110-chip; 111-metal layer; 113-avoidance gap; 115-passivation layer; 130-plastic package; 150-dielectric layer; 151-first PI layer; 152-second PI layer; 153-third PI layer; 154-first conductive layer; 155-second conductive layer; 156-third conductive layer; 170-reconstructed circuit layer; 190-solder ball; 200-carrier. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0041] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0042] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0043] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0044] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0045] As disclosed in the background technology, the Fan-Out packaging product has a 7um PI dielectric filling between the redistribution layer (RDL) and the chip surface metal layer (Top Al Metal), and the spacing is relatively close (two layers of metal sandwich a layer of non-conductive material to form a capacitor). Using conventional process methods, there is a large area of ​​overlap between the chip end Top Metal and the RDL layer metal, causing a sudden change in the impedance of the signal transmission path, thereby reducing the signal transmission quality. The inventors found that this is mainly due to the close spacing between the reconstruction circuit and the Al metal on the surface of the chip, and the overlapping part of the reconstruction circuit and the Al metal constitutes a plate-type capacitor structure. According to the capacitance formula C=εS / d, where ε represents the dielectric constant, S represents the facing area of ​​the plate (i.e., the overlapping area), and d represents the spacing between the plates. Therefore, it is not difficult to see that when the RDL wiring range overlaps with the Al metal on a large area, the capacitance effect will be more obvious, resulting in capacitive coupling in the transmission path, causing the signal impedance to be low, and the return loss result of the high-frequency signal is poor (-4dB).

[0046] In order to solve the above problems, an embodiment of the present invention provides a low-coupling rewiring packaging structure and a method for preparing a low-coupling rewiring packaging structure. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0047] See also Figure 1 and Figure 2 The embodiment of the present invention provides a low-coupling redistribution packaging structure 100, which can significantly reduce the overlapping area between the reconstruction circuit layer 170 and the metal layer 111, reduce the coupling effect with the RDL, and significantly improve the return loss of high-frequency signals (-11dB). While ensuring signal quality, it also protects the surface metal layer 111.

[0048] The low-coupling rewiring packaging structure 100 provided in an embodiment of the present invention includes a chip 110, a plastic encapsulation body 130, a dielectric layer 150, a reconstruction circuit layer 170 and a solder ball 190. A metal layer 111 is provided on the front of the chip 110; the plastic encapsulation body 130 is wrapped around the chip 110; the dielectric layer 150 is provided on the surface of the metal layer 111 and covers the plastic encapsulation body 130; the reconstruction circuit layer 170 is provided in the dielectric layer 150 and connected to the metal layer 111; the solder ball 190 is provided on the side of the dielectric layer 150 away from the chip 110 and connected to the reconstruction circuit layer 170; wherein, an avoidance gap 113 is etched on the metal layer 111, the avoidance gap 113 penetrates the metal layer 111, and the projection of the reconstruction circuit layer 170 on the front of the chip 110 at least partially overlaps with the avoidance gap 113.

[0049] In some embodiments, the metal layer 111 on the surface of the chip 110 may be an Al metal layer 111, which serves as an external electrical connection for the chip 110. The specific structure and manufacturing principles can refer to the chip 110 structure in the prior art. After the chip 110 (die) is received, it can be encapsulated with a molding compound to expose the metal layer 111. The metal layer 111 is then etched to form an escape notch 113. A rewiring process is then performed to form the dielectric layer 150 and the reconstructed circuit layer 170. Finally, solder balls 190 are implanted, and the packaging process is completed after dicing.

[0050] It should be noted that by forming an avoidance gap 113 on the metal layer 111 that overlaps with the reconstruction circuit layer 170, the overlapping area between the reconstruction circuit layer 170 and the metal layer 111 can be greatly reduced, reducing the coupling effect with the RDL, and significantly improving the return loss of high-frequency signals (-11dB).

[0051] In some embodiments, the avoidance gap 113 is filled with a passivation layer 115. Specifically, the passivation layer 115 can be made of SiN material, which can isolate the reconstruction circuit layer 170 from the chip 110, preventing leakage current from affecting the performance of the chip 110. Furthermore, the passivation layer 115 can provide structural support, preventing the dielectric layer 150 and the reconstruction circuit layer 170 from collapsing.

[0052] Furthermore, the thickness of the passivation layer 115 is the same as that of the metal layer 111, so that the passivation layer 115 is flush with the metal layer 111. Specifically, the passivation layer 115 is flush with the metal layer 111, so that the passivation layer 115 can completely fill the avoidance gap 113, making the surface of the metal layer 111 flat, which is more conducive to the preparation of the dielectric layer 150 and the reconstruction circuit layer 170.

[0053] See also Figure 3In other preferred embodiments of the present invention, the thickness of the passivation layer 115 may also be greater than the thickness of the metal layer 111, so that the passivation layer 115 can be relatively protruded from the metal layer 111, and the protrusion height is between 3-5 nm. This structural form increases the contact area between the dielectric layer 150 and the passivation layer 115 after the dielectric layer 150 is prepared, thereby improving the bonding force between the dielectric layer 150 and the passivation layer 115 and avoiding delamination.

[0054] In other preferred embodiments of the present invention, the avoidance gap 113 may not be filled with the passivation layer 115, but the dielectric layer 150 may be filled into the avoidance gap 113. On the one hand, the preparation process steps of the passivation layer 115 can be reduced and the process can be simplified. On the other hand, the bonding strength between the dielectric layer 150 and the metal layer 111 can also be enhanced to avoid stratification.

[0055] See Figure 4 In some embodiments, the clearance gap 113 is rectangular, and at least one side edge of the clearance gap 113 overlaps with the projected edge of the reconstruction circuit layer 170 on the front surface of the chip 110. Specifically, two adjacent edges of the clearance gap 113 overlap with the edges of the reconstruction circuit layer 170. This design allows the clearance gap 113 to correspond as closely as possible with the reconstruction circuit layer 170, thereby minimizing the overlap area between the reconstruction circuit layer 170 and the metal layer 111 and further alleviating the capacitance effect. Preferably, the area of ​​the clearance gap 113 can be at least half the area of ​​the reconstruction circuit layer 170, effectively reducing the overlap area.

[0056] In other preferred embodiments of the present invention, the avoidance gap 113 may also be circular, polygonal, or irregular in shape, and may be specifically set according to the shape of the reconstruction circuit layer 170 , which is not specifically limited here.

[0057] See also Figure 5 In some preferred embodiments of the present invention, the projected area Sa of the reconstructed wiring layer 170 on the front surface of the chip 110 is smaller than the projected area Sb of the solder balls 190 on the front surface of the chip 110. Specifically, the structural design of the reconstructed wiring layer 170 can be optimized to reduce the area of ​​reconstructed wiring between the metal layer 111 and the solder balls. Furthermore, the projected area of ​​the reconstructed wiring layer 170 is smaller than the projected area of ​​the solder balls 190. This also reduces the overlap area with the metal layer 111, thereby alleviating the phenomenon of decreased transmission path impedance and signal reflection caused by the capacitive coupling effect.

[0058] Furthermore, the projected area Sa of the reconstructed circuit layer 170 on the front surface of the chip 110 is less than or equal to half the projected area Sb of the solder balls 190 on the front surface of the chip 110. Preferably, through structural optimization design, the projected area of ​​the reconstructed circuit layer 170 is half the projected area of ​​the solder balls 190, thereby significantly reducing the projected areas of the reconstructed circuit layer 170 and the metal layer 111 and mitigating the capacitive coupling effect.

[0059] Please continue to see Figure 2 In some embodiments, the dielectric layer 150 includes a first PI layer 151 and a second PI layer 152. The first PI layer 151 is disposed on the surface of the plastic package 130 and the metal layer 111 and covers the avoidance gap 113. The second PI layer 152 covers the first PI layer 151, and the reconstruction circuit layer 170 is disposed in the second PI layer 152. The first PI layer 151 and the second PI layer 152 can be prepared by a coating process, and the first PI layer 151 can cover the surface of the passivation layer 115.

[0060] Furthermore, a first conductive layer 154 is provided in the first PI layer 151. The first conductive layer 154 is offset from the avoidance notch 113 and is connected to both the metal layer 111 and the reconstructed circuit layer 170. Specifically, the first conductive layer 154 is spaced from the avoidance notch 113, enabling electrical connection between the metal layer 111 and the reconstructed circuit layer 170. In actual fabrication, a layer of dielectric material can be first applied to form the first PI layer 151. Then, an exposure and development process is performed to create an opening in the first PI layer 151, and metal electroplating is performed to form the first conductive layer 154. Then, a dielectric material is coated on the first PI layer 151 to form a second PI layer 152. The second PI layer 152 completely covers the first PI layer 151. Then, patterning is performed through an exposure and development process to form a patterned opening on the second PI layer 152. The patterned opening can expose the first conductive layer 154. After metal electroplating, a reconstructed circuit layer 170 is formed. The reconstructed circuit layer 170 is electrically connected to the metal layer 111 through the first conductive layer 154.

[0061] In some embodiments, the dielectric layer 150 further includes a third PI layer 153, which covers the second PI layer 152. A second conductive layer 155 is disposed in the third PI layer 153, and the second conductive layer 155 is connected to the reconstruction circuit layer 170. The solder balls 190 are disposed on a side of the third PI layer 153 away from the chip 110 and connected to the second conductive layer 155. Specifically, after the reconstruction circuit layer 170 is completed, a dielectric material can be coated again on the second PI layer 152 to form the third PI layer 153. Then, an exposure and development process is performed to open the third PI layer 153, and metal is electroplated to form the second conductive layer 155. The second conductive layer 155 is connected to the reconstruction circuit layer 170 to lead out the signals of the reconstruction circuit layer 170.

[0062] Furthermore, a third conductive layer 156 is disposed on the third PI layer 153. The third conductive layer 156 is connected to the second conductive layer 155. A solder ball 190 is disposed on the third conductive layer 156. Specifically, the third conductive layer 156 is a UBM metal layer 111, which is formed on the third PI layer 153 through an electroplating process and covers the second conductive layer 155. The solder ball 190 is disposed on the third conductive layer 156, thereby achieving electrical connection between the solder ball 190 and the reconstruction circuit layer 170.

[0063] An embodiment of the present invention further provides a method for preparing a low-coupling rewiring package structure 100, which is used to prepare the aforementioned low-coupling rewiring package structure 100. The method comprises the following steps:

[0064] S1: Provide a carrier 200.

[0065] Specifically, a carrier 200 can be provided first. The carrier 200 can be a substrate or base plate structure, for example, it can be made of materials such as silicon dioxide, silicon, sapphire, metal, etc., and then a layer of adhesive layer is coated on the carrier 200. The adhesive layer can be UV glue to facilitate subsequent peeling.

[0066] S2 : Mounting the chip 110 on the carrier 200 , wherein the front side of the chip 110 faces upward and is provided with a metal layer 111 .

[0067] See also Figure 6 Specifically, multiple chips 110 are mounted upright on carrier 200, with the backside of each chip 110 attached to the adhesive layer and the front side of each chip 110 facing upward. A metal layer 111, preferably an Al layer, is formed on the front side of each chip 110. Furthermore, multiple chips 110 are spaced apart in an array to facilitate subsequent formation of a reconstructed wafer.

[0068] S3 : forming a plastic package 130 on the carrier 200 , and the plastic package 130 covers the periphery of the chip 110 .

[0069] See also Figure 7 Specifically, a plastic encapsulation process can be used to form a plastic encapsulation body 130 on the carrier 200 . The plastic encapsulation body 130 covers the periphery of the chip 110 , and the front surface of the chip 110 can be exposed to the plastic encapsulation body 130 .

[0070] S3 : etching the metal layer 111 to form an escape notch 113 , wherein the escape notch 113 penetrates the metal layer 111 .

[0071] See also Figure 8 Specifically, through an exposure and development process, the metal layer 111 of the chip 110 is etched with an etching solution to form a clearance gap 113. The clearance gap 113 penetrates the metal layer 111. After the clearance gap 113 is formed by etching, a passivation layer 115 is filled in the clearance gap 113. The passivation layer 115 can be flush with the metal layer 111.

[0072] S4: forming a dielectric layer 150 and a reconstructed circuit layer 170 on the surface of the plastic package body 130 .

[0073] See also Figure 9 , wherein the dielectric layer 150 is disposed on the surface of the metal layer 111 and covers the plastic package 130, and the reconstructed circuit layer 170 is disposed within the dielectric layer 150 and connected to the metal layer 111. Specifically, a layer of dielectric material can be first coated on the surfaces of the metal layer 111 and the plastic package 130 to form a first PI layer 151. Then, an exposure and development process is performed to form an opening in the first PI layer 151, and then metal is electroplated to form a first conductive layer 154. Then, a dielectric material is coated on the first PI layer 151 to form a second PI layer 152. The second PI layer 152 completely covers the first PI layer 151. Then, an exposure and development process is performed to pattern the second PI layer 152 to form a patterned opening that exposes the first conductive layer 154. Then, metal is electroplated to form the reconstructed circuit layer 170. The reconstructed circuit layer 170 is electrically connected to the metal layer 111 through the first conductive layer 154. The projection of the reconstructed circuit layer 170 on the front surface of the chip 110 at least partially overlaps with the avoidance notch 113.

[0074] After completing the reconstruction of the circuit layer 170, the dielectric material can be coated again on the second PI layer 152 to form a third PI layer 153. Then, through an exposure and development process, an opening is opened on the third PI layer 153, and then metal is electroplated to form a second conductive layer 155. The second conductive layer 155 is connected to the reconstruction circuit layer 170 to lead out the signal of the reconstruction circuit layer 170.

[0075] S5 : forming a solder ball 190 on a side of the dielectric layer 150 away from the chip 110 , wherein the solder ball 190 is connected to the reconstructed circuit layer 170 .

[0076] See also Figure 10 Specifically, after the third PI layer 153 and the second conductive layer 155 are completed, a third conductive layer 156 can be formed by electroplating on the surface of the third PI layer 153. Then, solder balls 190 are formed on the third conductive layer 156 to achieve electrical connection between the solder balls 190 and the reconstructed circuit layer 170. Finally, the carrier 200 is peeled off and cut along the dicing streets to form individual products.

[0077] In summary, the low-coupling rewiring packaging structure 100 and the preparation method thereof provided by the embodiment of the present invention are as follows: a metal layer 111 is provided on the front side of the chip 110, a plastic package body 130 is wrapped around the chip 110, and then a dielectric layer 150 is provided on the surface of the metal layer 111 and covers the plastic package body 130; a reconstruction circuit layer 170 is provided in the dielectric layer 150, and the reconstruction circuit layer 170 is connected to the metal layer 111 to achieve electrical connection; at the same time, a solder ball 190 is provided on the side of the dielectric layer 150 away from the chip 110, and the solder ball 190 is connected to the reconstruction circuit layer 170, wherein an avoidance gap 113 is etched on the metal layer 111, and the avoidance gap 113 passes through the metal layer 111, and the projection of the reconstruction circuit layer 170 on the front side of the chip 110 at least partially overlaps with the avoidance gap 113. Compared with the prior art, the low-coupling redistribution packaging structure 100 provided in an embodiment of the present invention can significantly reduce the overlapping area between the reconstruction circuit layer 170 and the metal layer 111 by forming an avoidance gap 113 on the metal layer 111 that overlaps with the reconstruction circuit layer 170, thereby reducing the coupling effect with the RDL, and significantly improving the return loss of high-frequency signals (-11dB).

[0078] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A low-coupling rewiring packaging structure, characterized in that: include: A chip, wherein a metal layer is provided on the front side of the chip; A plastic package body, the plastic package body covering the periphery of the chip; a dielectric layer, the dielectric layer being disposed on the surface of the metal layer and covering the plastic package; a reconstructed circuit layer, wherein the reconstructed circuit layer is disposed in the dielectric layer and connected to the metal layer; a solder ball, the solder ball being arranged on a side of the dielectric layer away from the chip and connected to the reconstructed circuit layer; A relief notch is etched on the metal layer, the relief notch penetrates the metal layer, and a projection of the reconstruction circuit layer on the front surface of the chip at least partially overlaps with the relief notch.

2. The low-coupling rewiring packaging structure according to claim 1, characterized in that: The avoidance gap is filled with a passivation layer.

3. The low-coupling rewiring packaging structure according to claim 2, characterized in that: The thickness of the passivation layer is the same as that of the metal layer, so that the passivation layer and the metal layer are flush with each other.

4. The low-coupling rewiring packaging structure according to claim 1, characterized in that: The avoidance gap is rectangular, and at least one side edge of the avoidance gap overlaps with a projection edge of the reconstruction circuit layer on the front surface of the chip.

5. The low-coupling rewiring packaging structure according to claim 1, characterized in that: The projection area Sa of the reconstructed circuit layer on the front surface of the chip is smaller than the projection area Sb of the solder ball on the front surface of the chip.

6. The low-coupling rewiring packaging structure according to claim 5, characterized in that: The projection area Sa of the reconstructed circuit layer on the front surface of the chip is less than or equal to half of the projection area Sb of the solder ball on the front surface of the chip.

7. The low-coupling rewiring packaging structure according to any one of claims 1 to 6, characterized in that: The dielectric layer includes a first PI layer and a second PI layer. The first PI layer is arranged on the surface of the plastic package and the metal layer and covers the avoidance gap. The second PI layer covers the first PI layer. The reconstruction circuit layer is arranged in the second PI layer.

8. The low-coupling rewiring packaging structure according to claim 7, characterized in that: A first conductive layer is further provided in the first PI layer. The first conductive layer is staggered with the avoidance gap and is connected to the metal layer and the reconstruction circuit layer at the same time.

9. The low-coupling rewiring packaging structure according to claim 7, wherein: The dielectric layer also includes a third PI layer, which covers the second PI layer, and a second conductive layer is provided in the third PI layer, and the second conductive layer is connected to the reconstruction circuit layer. The solder ball is provided on a side of the third PI layer away from the chip and is connected to the second conductive layer.

10. The low-coupling rewiring packaging structure according to claim 9, characterized in that: A third conductive layer is further provided on the third PI layer, the third conductive layer is connected to the second conductive layer, and the solder balls are provided on the third conductive layer.

11. A method for preparing a low-coupling rewiring package structure, for preparing the low-coupling rewiring package structure according to claim 1, characterized in that: The preparation method comprises: providing a vehicle; Mounting a chip on the carrier, wherein the front side of the chip faces upward and is provided with a metal layer; forming a plastic package on the carrier, wherein the plastic package covers the periphery of the chip; Etching a relief notch on the metal layer, wherein the relief notch penetrates the metal layer; forming a dielectric layer and a reconstructed circuit layer on the surface of the plastic package, wherein the dielectric layer is disposed on the surface of the metal layer and covers the plastic package, and the reconstructed circuit layer is disposed in the dielectric layer and connected to the metal layer; forming solder balls on a side of the dielectric layer away from the chip, wherein the solder balls are connected to the reconstructed circuit layer; The projection of the reconstructed circuit layer on the front surface of the chip at least partially overlaps with the avoidance gap.

12. The method for preparing a low-coupling rewiring package structure according to claim 11, characterized in that: After the step of etching the metal layer to form an avoidance gap, the preparation method further comprises: A passivation layer is formed by filling the avoidance gap.

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