Current sharing circuit and method for a multiphase buck unit

Abstract

The present invention discloses a current sharing circuit and method for a multi-phase buck unit, belonging to the technical field of power conversion. The circuit includes an N-phase current sharing unit. The first ends of each phase current sharing unit are short-circuited. Each phase current sharing unit correspondingly collects the inductor current signal of one phase of the buck unit, and the second end of each phase current sharing unit correspondingly outputs the control signal of the switch in one phase of the buck unit. The current sharing circuit and method for a multi-phase buck unit provided by the present invention can achieve current sharing among the phases of the multi-phase buck unit.

Description

Technical Field

[0001] The present invention relates to the technical field of power conversion, and particularly to a current sharing circuit and method for a multi-phase buck unit. Background Art

[0002] In a buck-type power management system, the buck converter (BUCK) is the core power conversion module, and its load-carrying capacity directly affects the output performance of the system. A single-phase buck converter is limited by factors such as the current-carrying capacity of power devices, heat dissipation conditions, and parasitic parameters. Generally, the maximum load current is about 25A. To meet higher power requirements, the industrial community generally adopts a parallel architecture of multi-phase buck units to increase the total load-carrying capacity of the system by superimposing multi-phase currents. Ideally, the currents of each phase should be evenly distributed to achieve optimal thermal distribution and efficiency. However, in practical applications, due to factors such as process deviations of each phase buck chip, control signal delay differences, and mismatches of parasitic parameters in the power loop, the current distribution of each phase will be uneven, which will lead to problems such as the risk of local overheating, efficiency reduction, and reliability hidden dangers.

[0003] Therefore, there is an urgent need for an efficient and reliable current sharing circuit and method for multi-phase buck units, which can achieve fast dynamic current sharing under complex working conditions, while taking into account system cost and integration, to meet the stringent requirements of high-power density power systems. Summary of the Invention

[0004] The present invention aims to provide a current sharing circuit and method for a multi-phase buck unit.

[0005] To achieve the above object, the technical solution of the present invention is:

[0006] A current sharing circuit for a multi-phase buck unit includes N-phase current sharing units. The first ends of each phase current sharing unit are short-circuited. Each phase current sharing unit correspondingly collects the inductor current signal of one phase buck unit, and the second end of each phase current sharing unit correspondingly outputs the control signal of the switch in one phase buck unit.

[0007] The current sharing unit includes a voltage dividing module, an error amplifying module, a PWM generating module, a conduction time generating module, an RS triggering module, and a logic control module. The first end of the voltage dividing module is connected to the output voltage of the buck unit, the second end of the voltage dividing module is connected to the negative input terminal of the error amplifying module, the positive input terminal of the error amplifying module is connected to the chip reference voltage, the output terminal of the error amplifying module outputs a first voltage and is connected to the first end of the PWM generating module, the second end of the PWM generating module is connected to the first input terminal of the RS triggering module, the second input terminal of the RS triggering module is connected to the conduction time generating module, the first output terminal of the RS triggering module is connected to the first end of the logic control module, and the second and third ends of the logic control module output the control signal of the switch in the buck unit.

[0008] In a specific embodiment, the PWM generation module includes a plurality of transistors, a plurality of amplifiers and a first current source. The first ends of a second transistor, a third transistor and a fourth transistor are connected to a second voltage. The second end of the second transistor is connected to the first current source. The second end of the third transistor is connected to the first end of a first trimming resistor, and the second end of the first trimming resistor is connected to a first ground. The third end of the second transistor is connected to the third end of the third transistor, the second end of the second transistor, and the third end of the fourth transistor. The second end of the fourth transistor is connected to the negative input terminal of a second amplifier and the first end of a fourth resistor, and the second end of the fourth resistor is connected to a second ground. The positive input terminal of the second amplifier is connected to a first voltage, and the output terminal of the second amplifier is connected to the third end of an eighth transistor. The first end of the eighth transistor is connected to the first end of the fourth resistor. The second end of the eighth transistor is connected to the second end, the third end of a ninth transistor, and the third end of a tenth transistor. The first ends of the ninth transistor and the tenth transistor are connected to the second voltage. The second end of the tenth transistor is connected to the first end of a second trimming resistor, and the second end of the second trimming resistor is connected to a third voltage. The first end of a first proportional trimmer is connected to the second voltage, the second end of the first proportional trimmer is connected to the second end of the tenth transistor, and the third end of the first proportional trimmer is connected to the third end of the ninth transistor. The second end of the tenth transistor is connected to the positive input terminal of a third amplifier. The negative input terminal of the third amplifier is connected to a fourth voltage, and the output terminal of the third amplifier outputs a PWM signal.

[0009] In a specific embodiment, the PWM generation module includes a plurality of transistors, a plurality of amplifiers, and a plurality of resistors. The positive input terminal of the fourth amplifier is connected to the chip reference voltage. The negative input terminal of the fourth amplifier is connected to the first terminal of the eighteenth transistor. The output terminal of the fourth amplifier is connected to the third terminal of the eighteenth transistor. The first terminal of the eighteenth transistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to the first terminal of the first resistor trimmer. The second terminal of the first resistor trimmer is connected to the second ground. The second voltage is connected to the first terminals of the nineteenth transistor and the twenty-second transistor. The second terminal of the nineteenth transistor is connected to the third terminal of the nineteenth transistor, the second terminal of the eighteenth transistor, the third terminal of the twenty-second transistor, and the third terminal of the thirty-first transistor. The second terminal of the twenty-second transistor is connected to the first terminal of the third trimmer resistor. The second terminal of the third trimmer resistor is connected to the first ground. The first terminal of the second ratio trimmer is connected to the second voltage. The third terminal of the second ratio trimmer is connected to the third terminal of the nineteenth transistor. The second terminal of the second ratio trimmer is connected to the second terminal of the twenty-second transistor. The second terminal of the thirty-first transistor is connected to the negative input terminal of the fifth amplifier and the first terminal of the ninth resistor. The first positive input terminal of the fifth amplifier is connected to the first voltage. The second positive input terminal of the fifth amplifier is connected to the fifth voltage. The output terminal of the fifth amplifier is connected to the third terminal of the thirty-second transistor. The first terminal of the thirty-second transistor is connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the first terminal of the second resistor trimmer. The second terminal of the second resistor trimmer is connected to the second ground. The second voltage is connected to the first terminals of the thirty-third transistor and the thirty-fourth transistor. The second terminal of the thirty-third transistor is connected to the third terminal of the thirty-fourth transistor, the third terminal of the thirty-third transistor, and the second terminal of the thirty-second transistor. The second terminal of the thirty-fourth transistor is connected to the first terminal of the fourth trimmer resistor. The second terminal of the fourth trimmer resistor is connected to the third voltage. The second terminal of the thirty-fourth transistor is connected to the positive input terminal of the sixth amplifier. The negative input terminal of the sixth amplifier is connected to the fourth voltage. The output terminal of the sixth amplifier outputs a PWM signal.

[0010] In a specific embodiment, the first ratio trimmer includes a plurality of transistors, and every two transistors are connected in series between the second voltage and the second terminal of the tenth transistor.

[0011] The second ratio trimmer includes a plurality of transistors, and every two transistors are connected in series between the second voltage and the second terminal of the twenty-second transistor.

[0012] In a specific embodiment, the first trimmer resistor, the second trimmer resistor, the third trimmer resistor, and the fourth trimmer resistor each include an equivalent resistance formed by a plurality of transistors connected in series.

[0013] In a specific embodiment, the first resistor trimming device includes a plurality of resistors and a plurality of transistors. The plurality of resistors are connected in series between the fifth resistor and the second ground, and a transistor is connected in parallel across each resistor.

[0014] The second resistor trimming device includes a plurality of resistors and a plurality of transistors. The plurality of resistors are connected in series between the ninth resistor and the second ground, and a transistor is connected in parallel across each resistor.

[0015] In a specific embodiment, the driving circuit of the transistor includes a second current source, a first fuse, a first Schmitt trigger, and a first inverter. The second current source is connected to the first end of the first fuse, the second end of the first fuse is connected to the second ground, and the first end of the first fuse, the first Schmitt trigger, and the first inverter are connected in sequence.

[0016] In a specific embodiment, the driving circuit of the transistor further includes a second inverter, and the first end of the first fuse, the first Schmitt trigger, the first inverter, and the second inverter are connected in sequence.

[0017] In a specific embodiment, the current sharing circuit of the multi-phase buck unit further includes a clamping module. The output end of the error amplification module is connected to the first end of the clamping module, and the second end of the clamping module is connected to the first end of the PWM generation module.

[0018] A current sharing method for a multi-phase buck unit, which is applied to the current sharing circuit of the above multi-phase buck unit, includes:

[0019] Connecting the first voltages of each phase current sharing unit together;

[0020] Adjusting the current sampling resistor and the output voltage of the error amplification module at zero inductor current through a proportionality coefficient.

[0021] The above current sharing method for a multi-phase buck unit further includes adjusting the target current limit.

[0022] Beneficial effects: The current sharing circuit and method for a multi-phase buck unit of the present invention can achieve current sharing among the phases of the multi-phase buck unit; the voltage V C0 and the current sampling resistor R I are adjusted through a proportionality coefficient, so as to ensure that when the voltage V C of each phase current sharing unit is short-circuited, the inductor currents I L are equal, realizing current sharing among the phases; in addition, the current sampling resistor R I and the output voltage V C0 of the error amplification module at zero inductor current can be adjusted separately, and there is no need to additionally adjust the target current limit I MAXAdjusted separately again, saving the adjustment steps and testing time.

[0023] To make the above features and advantages of the invention more obvious and understandable, specific embodiments are given below and described in detail in conjunction with the accompanying drawings as follows. Brief Description of the Drawings

[0024] Figure 1 It is a schematic structural diagram of a current sharing circuit of a multi-phase buck unit of the present invention.

[0025] Figure 2 For Figure 1 It is a schematic circuit diagram of the current sharing unit in

[0026] Figure 3 For Figure 2 It is a schematic circuit diagram of the first specific embodiment of the PWM generation module in

[0027] Figure 4 For Figure 2 It is a schematic circuit diagram of the second specific embodiment of the PWM generation module in

[0028] Figure 5 It is a schematic circuit diagram of the first specific embodiment of the transistor drive circuit.

[0029] Figure 6 It is a schematic circuit diagram of the second specific embodiment of the transistor drive circuit.

[0030] Figure 7 For Figure 4 It is a schematic circuit diagram of the amplifier A5 in Detailed Description of the Embodiments

[0031] To make the objectives and technical solutions of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. Based on the described embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0032] Figure 1 It is a schematic structural diagram of a current sharing circuit of a multi-phase buck unit of the present invention. As Figure 1As shown in the figure, a current sharing circuit 1 of a multi-phase buck unit of the present invention is connected to a multi-phase buck circuit 2. Among them, the multi-phase buck circuit 2 includes N-phase buck units, specifically the first-phase buck unit 21, the second-phase buck unit 22, up to the Nth-phase buck unit 2N. The input ends of the N-phase buck units are connected in parallel, and the output ends of the N-phase buck units are connected in parallel. The current sharing circuit 1 of the multi-phase buck unit includes N-phase current sharing units, specifically the first-phase current sharing unit 11, the second-phase current sharing unit 12, up to the Nth-phase current sharing unit 1N. The first ends of each phase current sharing unit are short-circuited. Each phase current sharing unit correspondingly collects the inductor current signal of one phase buck unit, and the second end of each phase current sharing unit correspondingly outputs the control signal of the switch in one phase buck unit.

[0033] Please refer to Figure 2 , taking the first-phase buck unit 21 and the first-phase current sharing unit 11 as examples, the specific topology of the current sharing circuit of a multi-phase buck unit of the present invention is introduced below. More specifically, the first-phase buck unit 21 includes a switch S1, a switch S2, an inductor L1, and a capacitor C1. The positive pole of the input voltage V in is connected to the first end of the switch S1. The second end of the switch S1 is connected to the first end of the switch S2. The second end of the switch S2 is connected to the negative pole of the input voltage V in . The first end of the switch S2 is connected to the first end of the inductor L1. The second end of the inductor L1 is connected to the first end of the capacitor C1. The second end of the capacitor C1 is connected to the second end of the switch S2. The two ends of the capacitor C1 are the output voltage V o . Among them, the node voltage of the switch S1 and the switch S2 is the voltage V SW . The switch S1 is the upper transistor of the buck unit, and the switch S2 is the lower transistor of the buck unit.

[0034] More specifically, the first current sharing unit 11 includes a voltage dividing module 111, an error amplifying module 112, a clamping module 113, a PWM generating module 114, a conduction time generating module 115, an RS trigger module 116, and a logic control module 117. The first end of the voltage dividing module 111 is connected to the output voltage V o . The second end of the voltage dividing module 111 is connected to the negative input end of the error amplifying module 112. The positive input end of the error amplifying module 112 is connected to the chip reference voltage V ref . The output end of the error amplifying module 112 outputs the voltage V C and is connected to the first end of the clamping module 113. The second end of the clamping module 113 is connected to the first end of the PWM generating module 114. The second end of the PWM generating module 114 is connected to the S input end of the RS trigger module 116. The R input end of the RS trigger module 116 is connected to the conduction time generating module 115. The Q output end of the RS trigger module 116 is connected to the first end of the logic control module 117. The second end and the third end of the logic control module 117 output the control signal G S1The control signal G for switch S2 S2 .

[0035] More specifically, the voltage dividing unit 111 includes a resistor R1 and a resistor R2. The first end of the resistor R1 is connected to the output voltage V o , the second end of the resistor R1 is connected to the first end of the resistor R2, the second end of the resistor R2 is connected to the first ground PGND, and the first end of the resistor R2 outputs the voltage V FB to the negative input terminal of the error amplification module 112.

[0036] More specifically, the error amplification module 112 includes an amplifier. The second end of the voltage dividing module 111 is connected to the negative input terminal of the amplifier, and the positive input terminal of the amplifier is connected to the chip reference voltage V ref , and the output terminal of the amplifier outputs the voltage V C and is connected to the first end of the clamping module 113.

[0037] More specifically, the clamping module 113 includes an amplifier A1 and a transistor Q1. The first end of the transistor Q1 is connected to the output terminal of the error amplification module 112, the second end of the transistor Q1 is grounded, the third end of the transistor Q1 is connected to the output terminal of the amplifier A1, the negative input terminal of the amplifier A1 is connected to the output terminal of the error amplification module 112 and the first end of the PWM generation module 114, and the positive input terminal of the amplifier A1 is connected to the voltage V CMAX . Wherein, when the voltage V C at the negative input terminal of the amplifier A1 is greater than the voltage V CMAX , the output terminal of the amplifier A1 outputs a low level, turning on the transistor Q1 and pulling down the voltage V C so that it is less than the voltage V CMAX again. The output terminal of the amplifier A1 outputs a high level, turning off the transistor Q1, thereby realizing the clamping of the voltage V C . Clamping the maximum value of the voltage V C to the voltage V CMAX , that is, the maximum inductor current of the buck unit can be limited, that is, the "current limit" function can be conveniently realized by using the current loop. Wherein, the voltage V CMAX is the upper limit of the voltage V C of the buck chip.

[0038] Furthermore, the first current sharing unit 11 may further include a filtering module 118. The output terminal of the error amplification module 112 is grounded through the filtering module 118, which is used to filter the voltage V C output by the error amplification module 112.

[0039] More specifically, the filtering module 118 includes a resistor R3 and a capacitor C2. The first end of the resistor R3 is connected to the output end of the error amplification module 112. The second end of the resistor R3 is connected to the first end of the capacitor C2. The second end of the capacitor C2 is grounded to SGND.

[0040] More specifically, the conduction time generation module 115 outputs a level signal related to the conduction time T of the switch S1 on of the switch S1.

[0041] Furthermore, the first current sharing unit 11 may further include a first driving module 119 and a second driving module 1110. The second end of the logic control module 117 outputs the control signal G of the switch S1 through the first driving module 119 S1 , and the third end of the logic control module 117 outputs the control signal G of the switch S2 through the second driving module 1110 S2 .

[0042] More specifically, the voltage dividing module 111 samples the output voltage V of the first-phase buck unit 21 o , generates the voltage V FB to the error amplification module 112. The error amplification module 112 amplifies the error between the chip reference voltage V ref and the voltage V FB to obtain the voltage V C . Then, it generates a PWM signal through the PWM generation module 114 to the S input end of the RS trigger module 116. The conduction time generation module 115 outputs a level signal related to the conduction time T on of the switch S1 to the Q input end of the RS trigger module 116. The RS trigger module 116 outputs a level signal to the logic control module 117, and the logic control module 117 outputs the control signal G S1 of the switch S1 and the control signal G S2 of the switch S2.

[0043] Among them, the voltage V C has a fixed proportional relationship with the inductor current. In the valley current mode, the voltage V C has a fixed proportional relationship with the valley value of the inductor current; in the peak current mode, the voltage V C has a fixed proportional relationship with the peak value of the inductor current. When the load becomes heavier, the voltage V C increases and the inductor current increases; conversely, when the load becomes lighter, the voltage V C decreases and the inductor current decreases. Therefore, in a multi-phase buck circuit, by short-circuiting the output ends of the error amplification modules of each phase current sharing unit, that is, short-circuiting the voltages V C of each phase current sharing unit together and ensuring that this proportional relationship is the same, the current sharing of each phase can be achieved. Among them, this proportional relationship is realized by the PWM generation modules of each phase.

[0044] Further, the topologies and functions of the remaining phase buck units and the remaining phase current sharing units are the same as those in Figure 2 and will not be elaborated herein.

[0045] Further, please refer to Figure 3 , Figure 3 which is a schematic diagram of the first specific embodiment of the PWM generation module. In this specific embodiment, the PWM generation module includes a plurality of transistors, a plurality of amplifiers and a current source I b , the first ends of transistor Q2, transistor Q3 and transistor Q4 are connected to voltage Vcc, and the second end of transistor Q2 is connected to current source I b , the second end of transistor Q3 is connected to the first end of resistor R DS1 , and the second end of resistor R DS1 is connected to the first ground PGND. The third end of transistor Q2 is connected to the third end of transistor Q3, the second end of transistor Q2, and the third end of transistor Q4. The second end of transistor Q4 is connected to the negative input terminal of amplifier A2 and the first end of resistor R4. The second end of resistor R4 is connected to the second ground SGND. The positive input terminal of amplifier A2 is connected to voltage V C , the output terminal of amplifier A2 is connected to the third end of transistor Q8. The first end of transistor Q8 is connected to the first end of resistor R4. The second end of transistor Q8 is connected to the second end of transistor Q9, the third end of transistor Q9, and the third end of transistor Q10. The first ends of transistor Q9 and transistor Q10 are connected to voltage Vcc. The second end of transistor Q10 is connected to the first end of resistor R DS2 , and the second end of resistor R DS2 is connected to voltage V SW ; the first end of the first proportional trimming regulator 1141 is connected to voltage Vcc, the second end of the first proportional trimming regulator 1141 is connected to the second end of transistor Q10, and the third end of the first proportional trimming regulator 1141 is connected to the third end of transistor Q9; the second end of transistor Q10 is connected to the positive input terminal of amplifier A3, the negative input terminal of amplifier A3 is connected to voltage V R , and the output terminal of amplifier A3 outputs a PWM signal. Among them, voltage V R is the voltage across resistor R DS1 , and voltage V X is the voltage at the first end of resistor R DS2 .

[0046] Further, the first proportional trimming regulator 1141 includes a plurality of transistors, and every two transistors are connected in series between voltage Vcc and the second end of transistor Q10. In Figure 3In the embodiment, the first proportional tuner 1141 includes four transistors. The first ends of transistors Q14 and Q15 are connected to voltage Vcc. The second end of transistor Q14 is connected to the first end of transistor Q16. The second end of transistor Q16 is connected to the second end of transistor Q10. The second end of transistor Q15 is connected to the first end of transistor Q17. The second end of transistor Q17 is connected to the second end of transistor Q10. The third end of transistor Q16 is connected to control signal TR1. The third end of transistor Q17 is connected to control signal TR2. Among them, transistors Q9 and Q10 form a current mirror. By controlling the switches of transistors Q16 and Q17, the number of transistors connected to the current mirror can be controlled, thereby adjusting the proportionality coefficient k.

[0047] Further, resistor R DS1 includes the equivalent resistance after multiple transistors are connected in series. In Figure 3 the specific embodiment, resistor R DS1 includes the equivalent resistance after transistors Q5, Q6, and Q7 are connected in series. Transistors Q5, Q6, and Q7 operate in the linear region. The third ends of transistors Q5, Q6, and Q7 are connected to voltage Vcc.

[0048] Further, resistor R DS2 includes the equivalent resistance after multiple transistors are connected in series. In Figure 3 the specific embodiment, resistor R DS2 includes the equivalent resistance after transistors Q11, Q12, and Q13 are connected in series. Transistors Q11, Q12, and Q13 operate in the linear region. The third ends of transistors Q11, Q12, and Q13 are connected to voltage Vcc.

[0049] More specifically, current source I b passes through the current mirror composed of transistors Q2, Q3, and Q4, and generates voltage V DS1 on resistor R R which is I b *R DS1 . Comparator A2 and transistor Q8 form a voltage holding circuit, which holds the voltage at the negative input terminal of comparator A2 as the voltage V C at the positive input terminal, and generates current I VC flowing through resistor R4. Among them, I VC =V C / R4, and transfers the current through the second end of transistor Q8 to the current mirror composed of transistors Q9, Q10, Q14, and Q15. This current flows through resistor R DS2 to generate voltage, and the voltage is superimposed on voltage V SW to obtain voltage V X。

[0050] At voltage V X and voltage V R being equal, the following equation can be obtained:

[0051] , (1)

[0052] where k is the proportionality coefficient.

[0053] For the valley current mode, the relationship between voltage V SW and inductor current I L is V SW = -I L ×R on , where R on is the on-resistance of switch S2. Substituting it into Equation (1) gives:

[0054] . (2)

[0055] Taking the derivative of Equation (2) gives:

[0056] (3)

[0057] where R I is the current sampling resistor, which is one of the key parameters in the multiphase buck design; R I is the ratio of the change in voltage V C to the change in inductor current I , that is, how much voltage V L changes, inductor current I changes accordingly by the same amount. C L C0 L

[0058] Let the inductor current be equal to 0, Equation (2) becomes:

[0059] (4)

[0060] where voltage V C0 is the output voltage of the error amplification module at zero inductor current, that is, the output voltage of error amplification module 112 when inductor current I L is equal to 0.

[0061] where the relationship between voltage V C and inductor current I L can usually be simplified to the expression:

[0062] (5)

[0063] It can be seen that in the case of multi-phase buck application (i.e., the voltages VC of each phase are shorted together and equal), even if the current sampling resistors RI are exactly the same, there are significant differences in the output voltage VC0 of the error amplification module at zero inductor current, which will still lead to significant differences in the inductor current IL, that is, the current sharing effect is not good. Therefore, the output voltage VC0 of the error amplification module at zero inductor current is also one of the key parameters in multi-phase buck application.

[0064] In the actual operation of multi-phase buck, due to the differences between chips, the voltage V C0 and the current sampling resistor R I will also have differences, thus resulting in different inductor currents I L , that is, the result of poor current sharing effect. Therefore, referring to Equation (3) and Equation (4), Figure 3 the circuit in C0 adjusts the voltage V I and the current sampling resistor R C by the proportionality coefficient k, that is, changes the ratio of the current generated by the voltage V DS2 to the current flowing through the resistor R C in the current mirror, so as to ensure that the inductor currents I L are equal when the voltages V

[0065] of each phase current sharing unit are shorted, and achieve current sharing between each phase. I In addition, after adjusting the current sampling resistor R C0 or the output voltage V MAX of the error amplification module at zero inductor current, the target current limit I C needs to be adjusted again. Among them, current limiting is usually achieved by clamping the voltage V C . Since the voltage V CMAX is clamped at the highest level of V MAX , the target current limit I

[0066] is as shown in Equation (6):

[0067] Therefore, after improving the current sharing performance by adjusting the current sampling resistor R I or the output voltage V C0 of the error amplification module at zero inductor current, the target current limit I MAX must be continuously adjusted, otherwise the differences in current limits between multi-phase buck chips will become relatively significant again.

[0068] Optionally, the current sampling resistor R I usually adopts a temperature coefficient resistor, and the resistor R DS1 and the resistor R DS2Take a power transistor resistor of the same type as the lower transistor, so that better temperature characteristics can be obtained, and these two parameters can also change less when the process changes.

[0069] When switch S1 is turned off and switch S2 is turned on, voltage V SW is the inductor current I L multiplied by the on-resistance R of switch S2 on , which is a negative voltage with respect to ground. As the inductor current I L decreases during this period, voltage V SW gradually increases, and voltage V X also gradually increases; when voltage V X is greater than voltage V R , the PWM signal output by comparator A3 is at a high level, the off-time T off ends, switch S1 turns on, switch S2 turns off. At this time, the level signal output by the on-time generation module 115 is at a low level, and the duration is the on-time T of switch S1 on . When the level signal output by the on-time generation module 115 is at a high level, the on-time T on ends, and the next cycle begins. During this stage, the inductor current I L rises, voltage V SW gradually decreases, and voltage V X also gradually decreases. Among them, the on-time T on can be fixed after the input voltage V in and the output voltage V o are determined, and is controlled by the on-time generation module 115; the off-time T off is determined by the PWM generation module 114.

[0070] Furthermore, please refer to Figure 4 , Figure 4 which is a schematic diagram of the second specific embodiment of the PWM generation module. In this specific embodiment, the PWM generation module includes multiple transistors, multiple amplifiers, and multiple resistors. The positive input terminal of amplifier A4 is connected to the chip reference voltage V ref , the negative input terminal of amplifier A4 is connected to the first terminal of transistor Q18, the output terminal of amplifier A4 is connected to the third terminal of transistor Q18, the first terminal of transistor Q18 is connected to the first terminal of resistor R5, the second terminal of resistor R5 is connected to the first terminal of the first resistor trimmer 1143, the second terminal of the first resistor trimmer 1143 is grounded to SGND, voltage Vcc is connected to the first terminals of transistor Q19 and transistor Q22, the second terminal of transistor Q19 is connected to the third terminal of transistor Q19, the second terminal of transistor Q18, the third terminal of transistor Q22, and the third terminal of transistor Q31. The second terminal of transistor Q22 is connected to the first terminal of resistor R DS3 ...DS3 The second end of is connected to the first ground PGND. The first end of the second ratio trimmer 1142 is connected to the voltage Vcc. The third end of the second ratio trimmer 1142 is connected to the third end of the transistor Q19. The second end of the second ratio trimmer 1142 is connected to the second end of the transistor Q22. The second end of the transistor Q31 is connected to the negative input terminal of the amplifier A5 and the first end of the resistor R9. The first positive input terminal of the amplifier A5 is connected to the voltage V C and the second positive input terminal of the amplifier A5 is connected to the voltage V CMAX . The output terminal of the amplifier A5 is connected to the third end of the transistor Q32. The first end of the transistor Q32 is connected to the first end of the resistor R9. The second end of the resistor R9 is connected to the first end of the second resistor trimmer 1144. The second end of the second resistor trimmer 1144 is connected to the second ground SGND. The voltage Vcc is connected to the first ends of the transistors Q33 and Q34. The second end of the transistor Q33 is connected to the third end of the transistor Q34, the third end of the transistor Q33, and the second end of the transistor Q32. The second end of the transistor Q34 is connected to the first end of the resistor R DS4 . The second end of the resistor R DS4 is connected to the voltage V SW . The second end of the transistor Q34 is connected to the positive input terminal of the amplifier A6. The negative input terminal of the amplifier A6 is connected to the voltage V R . The output terminal of the amplifier A6 outputs a PWM signal. Wherein, the voltage V R is the voltage across the resistor R DS3 , and the voltage V X is the voltage at the first end of the resistor R DS4 . Wherein, the resistance values of the resistor R5 and the resistor R9 are equal.

[0071] Furthermore, the first resistor trimmer 1143 includes a plurality of resistors and a plurality of transistors. The plurality of resistors are connected in series between the resistor R5 and the second ground SGND, and a transistor is connected in parallel across each resistor. In Figure 4 the embodiment, the first resistor trimmer 1143 includes three resistors. The resistors R6, R7, and R8 are connected in series between the resistor R5 and the second ground SGND. The two ends of the resistor R6 are connected in parallel to the first and second ends of the transistor Q25. The two ends of the transistor R7 are connected in parallel to the first and second ends of the transistor Q26. The two ends of the transistor R8 are connected in parallel to the first and second ends of the transistor Q27. The third end of the transistor Q25 is connected to the control signal TRN1. The third end of the transistor Q26 is connected to the control signal TRN2. The third end of the transistor Q27 is connected to the control signal TRN3.

[0072] Optionally, the resistance values of resistor R6, resistor R7, and resistor R8 are equal to the resistance value of resistor R5. By controlling the on / off states of transistor Q25, transistor Q26, and transistor Q27, the resistance value after resistor R5 is connected in series with the first resistor trimmer 1143 is k1*R5.

[0073] Further, the second ratio trimmer 1142 includes multiple transistors. After every two transistors are connected in series, they are connected between voltage Vcc and the second terminal of transistor Q22. In Figure 4 the embodiment, the second ratio trimmer 1142 includes four transistors. The first terminal of transistor Q20 is connected to voltage Vcc, the second terminal of transistor Q20 is connected to the first terminal of transistor Q23, the second terminal of transistor Q23 is connected to the second terminal of transistor Q22, the second terminal of transistor Q21 is connected to the first terminal of transistor Q24, the second terminal of transistor Q24 is connected to the second terminal of transistor Q22, the third terminal of transistor Q23 is connected to control signal TR3, and the third terminal of transistor Q24 is connected to control signal TR4. Among them, transistor Q19 and transistor Q22 form a current mirror. By controlling the switches of transistor Q23 and transistor Q24, the number of transistors connected to the current mirror can be controlled, thereby adjusting the ratio coefficient k2. In addition, transistor Q19 and transistor Q31 form a current mirror.

[0074] Further, resistor R DS3 includes the equivalent resistance after multiple transistors are connected in series. In Figure 4 the specific embodiment, resistor R DS3 includes the equivalent resistance after transistor Q28, transistor Q29, and transistor Q30 are connected in series. Transistor Q28, transistor Q29, and transistor Q30 operate in the linear region, and the third terminals of transistor Q28, transistor Q29, and transistor Q30 are connected to voltage Vcc.

[0075] Further, resistor R DS4 includes the equivalent resistance after multiple transistors are connected in series. In Figure 4 the specific embodiment, resistor R DS4 includes the equivalent resistance after transistor Q38, transistor Q39, and transistor Q40 are connected in series. Transistor Q38, transistor Q39, and transistor Q40 operate in the linear region, and the third terminals of transistor Q38, transistor Q39, and transistor Q40 are connected to voltage Vcc.

[0076] Further, the second resistor trimmer 1144 includes multiple resistors and multiple transistors. After the multiple resistors are connected in series, they are connected between resistor R9 and the second ground SGND, and a transistor is connected in parallel across each resistor. In Figure 4In the embodiment, the second resistor trimmer 1144 includes three resistors. Resistor R9, resistor R10, and resistor R11 are connected in series between resistor R9 and the second ground SGND. The two ends of resistor R9 are connected in parallel with the first end and the second end of transistor Q35. The two ends of transistor R10 are connected in parallel with the first end and the second end of transistor Q36. The two ends of transistor R11 are connected in parallel with the first end and the second end of transistor Q37. The third end of transistor Q35 is connected to the control signal TRN4. The third end of transistor Q26 is connected to the control signal TRN5. The third end of transistor Q27 is connected to the control signal TRN6.

[0077] Optionally, the resistance values of resistor R9, resistor R10, and resistor R11 are equal to the resistance value of resistor R9. The resistance value of resistor R5 is equal to the resistance value of resistor R9. By controlling the on / off states of transistor Q35, transistor Q36, and transistor Q37, the resistance value after resistor R9 is connected in series with the second resistor trimmer 1144 is k1*R5.

[0078] In Figure 4 In a specific embodiment, comparator A4 and transistor Q18 form a voltage holding circuit to hold the voltage at the negative input terminal of comparator A4 to the voltage V at the positive input terminal ref , then the current I R5 flowing through resistor R5 is V ref / (k1*R5). The current I R5 flowing through resistor R5 is transmitted to resistor R DS3 through a current mirror, then the voltage V R is V ref / (k1*R5) * k2*R DS3 . The current I R5 flowing through resistor R5 is transmitted to the second end of transistor Q31 through a current mirror. In addition, comparator A5 and transistor Q32 form a voltage holding circuit to hold the voltage at the negative input terminal of comparator A5 to the voltage V at the first positive input terminal C , then the current I Q33 flowing through transistor Q33 is V C / (k1*R5) - V ref / (k1*R5). Transistor Q33 and transistor Q34 also form a current mirror, then the voltage V X is (V C / (k1*R5) - V ref / (k1*R5)) * R DS4 + V SW .

[0079] Thus, the following equation can be obtained:

[0080] (7)

[0081] (8)

[0082] 。 (9)

[0083] In addition, Figure 4 the amplifier A5 in the specific embodiment includes two positive input terminals, and its function is that when the voltage V C is greater than the voltage V CMAX , the amplifier A5 uses the voltage V CMAX for voltage holding, so as to achieve the purpose of clamping the voltage V C and limiting the current of the chip. When the amplifier A5 is used in Figure 4 , the clamping module 113 in Figure 2 can be omitted.

[0084] As shown in equations (8) and (9), compared with the specific embodiment in Figure 3 , it can be seen that in the specific embodiment of Figure 4 , the current sampling resistor R I and the output voltage V C0 of the error amplification module at zero inductance current can be trimmed separately. More specifically, the proportional coefficient k2 can be trimmed first to adjust the output voltage V C0 of the error amplification module at zero inductance current, and then the proportional coefficient k1 can be trimmed to trim the current sampling resistor R I . Thus, under the condition that the phase voltages V C are short-circuited, it is ensured that the current sampling resistor R I and the output voltage V C0 of the error amplification module at zero inductance current are equal, so as to ensure that the inductance currents I L of each phase are equal.

[0085] In addition, Figure 4 the specific embodiment of C0 has another advantage: as shown in equation (6), after trimming the output voltage V MAX of the error amplification module at zero inductance current, the target current limit I I can be directly adjusted by adjusting the proportional coefficient k1, that is, only one-step trimming is required to complete the adjustment of the two parameters of the current sampling resistor R MAX and the target valley current limit I C of the buck chip, the upper limit V CMAX of the voltage V C0 usually comes from the reference module and must be trimmed first before the chip leaves the factory, so the consistency between chips is high. It can be seen from equation (6) that after trimming the output voltage V C0 of the error amplification module at zero inductance current, the target current limit I of each chip is made by adjusting the proportional coefficient k1MAX When they are equal, the current sampling resistor R I is naturally equal. That is, in this way, there is no need to separately trim the target current limit I MAX again, saving the trimming steps and testing time.

[0086] It should be noted that the transistors in this application include but are not limited to devices such as MOSFETs and IGBTs. Among them, the MOSFET can be a P-type MOSFET or an N-type MOSFET.

[0087] For example, for Figure 3 the transistors Q16 and Q17 in Figure 4 and the P-type MOSFETs such as the transistors Q23 and Q24 in Figure 5 as shown, the transistor drive circuit can be adopted, specifically including a current source I1, a fuse F1, a Schmitt trigger Trigger 1, and an inverter Inv 1. The current source I1 is connected to the first end of the fuse F1, the second end of the fuse F1 is connected to the second ground SGND, the first end of the fuse F1, the Schmitt trigger Trigger 1, and the inverter Inv 1 are connected in sequence, and the inverter Inv 1 outputs the control signal TRx of the transistor, where x = 1, 2, 3, 4.

[0088] More specifically, the resistance of the fuse is very small (such as 50 ohms), and the current flowing through it is about 10 uA; when the fuse F1 is not blown, the voltage across the fuse F1 is only 0.5 mV, and the output of the inverter Inv 1 is at a low level; when the fuse F1 is blown, the resistance of the fuse will increase greatly, reaching the level of several hundred K ohms (such as 300 K ohms). At this time, the voltage across the fuse F1 will be 3V, and the output of the inverter Inv 1 is at a high level. Thus, the relevant proportional coefficient can be adjusted by controlling the on / off of the fuse. Among them, the function of the Schmitt trigger Trigger 1 is anti-interference.

[0089] Optionally, Figure 5 the Schmitt trigger Trigger 1 in

[0090] For example, for Figure 4 the N-type MOSFETs such as the transistors Q25, Q26, Q27, Q35, Q36, and Q37 in Figure 6The transistor driving circuit shown specifically includes a current source I2, a fuse F2, a Schmitt trigger Trigger 2, an inverter Inv2, and an inverter Inv3. The current source I2 is connected to the first end of the fuse F2. The second end of the fuse F2 is connected to the second ground SGND. The first end of the fuse F2, the Schmitt trigger Trigger 2, the inverter Inv2, and the inverter Inv3 are connected in sequence. The inverter Inv3 outputs a control signal TRy for the transistor, where y = 1, 2, 3, 4, 5, 6.

[0091] More specifically, the resistance of the fuse is very small (such as 50 ohms), and the current flowing through it is about 10 uA. When the fuse F2 is not blown, the voltage across the fuse F2 is only 0.5 mV, and the output of the inverter Inv3 is high level. When the fuse F2 is blown, the resistance of the fuse will increase greatly, reaching the level of several hundred K ohms (such as 300 K ohms). At this time, the voltage across the fuse F2 will be 3 V, and the output of the inverter Inv3 is low level. Thus, by controlling the on / off of the fuse, the relevant proportional coefficient can be adjusted. Among them, the function of the Schmitt trigger Trigger 2 is anti-interference.

[0092] Optionally, Figure 6 the Schmitt trigger Trigger 2 in

[0093] In Figure 5 and Figure 6 specific embodiments, the default state of the control signal TRx and the control signal Try is to drive the transistor to turn on. After the corresponding fuse is blown, the driving transistor turns off. According to the actual application situation, an additional inverter can also be added in the specific embodiments of Figure 5 and Figure 6 so that the default state of the control signal TRx and the control signal Try is that the transistor is off. After the corresponding fuse is blown, the driving transistor turns on. The present invention is not limited thereto.

[0094] Figure 7 For Figure 4Schematic diagram of a circuit of a specific embodiment of amplifier A5. Amplifier A5 includes multiple transistors. Voltage Vcc is connected to the first ends of transistors Q41, Q42, Q44, and Q47. The second end of transistor Q41 is connected to the third end of transistor Q41 and current source I3. The third end of transistor Q42 is connected to the third end of transistor Q41. The second end of transistor Q42 is connected to the second and third ends of transistor Q43. The first end of transistor Q43 is connected to second ground SGND. The third end of transistor Q44 is connected to the third end of transistor Q41. The second end of transistor Q44 is connected to the second and third ends of transistor Q45. The first end of transistor Q45 is connected to second ground SGND; the second end of transistor Q46 is connected to the second end of transistor Q48. The third end of transistor Q48 is connected to the third end of transistor Q43. The first end of transistor Q48 is connected to second ground SGND; the third end of transistor Q47 is connected to the third end of transistor Q41. The second end of transistor Q47 is connected to the first ends of transistors Q49, Q50, and Q51. The third end of transistor Q49 is connected to second input terminal IN2. The second end of transistor Q49 is connected to the second end of transistor Q50. The third end of transistor Q50 is connected to first input terminal IN1. The second end of transistor Q50 is connected to the second end of transistor Q58. The third end of transistor Q51 is connected to third input terminal IN3. The second end of transistor Q51 is connected to the second end of transistor Q59; voltage Vcc is connected to the first ends of transistors Q52 and Q53. The second end of transistor Q52 is connected to the first end of transistor Q54. The third end of transistor Q52 is connected to the second end of transistor Q54 and the third end of transistor Q53. The second end of transistor Q54 is connected to the second end of transistor Q56. The first end of transistor Q56 is connected to the second end of transistor Q58. The third end of transistor Q56 is connected to the third end of transistor Q43. The third end of transistor Q58 is connected to the third end of transistor Q43. The first input end of transistor Q58 is connected to second ground SGND. The second end of transistor Q53 is connected to the first end of transistor Q55. The third end of transistor Q55 is connected to the third end of transistor Q46. The second end of transistor Q55 is connected to the second end of transistor Q57. The third end of transistor Q57 is connected to the third end of transistor Q45. The first end of transistor Q57 is connected to the second end of transistor Q59. The third end of transistor Q59 is connected to the third end of transistor Q43. The first end of transistor Q59 is connected to second ground SGND. The second end of transistor Q57 is the output terminal OUT. When the voltage of the first input terminal IN1 is higher than the voltage of the second input terminal IN2, it will be limited by the voltage of the second output terminal IN2 to achieve the purpose of C clamping the voltage V and limiting the current of the chip.

[0095] Among them, the first input terminal IN1 corresponds to the first positive input terminal of amplifier A5 and is connected to voltage VC ; The second input terminal IN2 corresponds to the second positive input terminal of the amplifier A5 and is connected to the voltage V CMAX ; The third input terminal IN3 corresponds to the negative input terminal of the amplifier A5; the output terminal OUT is connected to the output terminal of the amplifier A5.

[0096] The present invention also provides a current sharing method for a multi-phase buck unit, including,

[0097] Step S1, connect the voltages V of each phase current sharing unit together; C Connect them together;

[0098] Step S2, adjust the current sampling resistor R and the output voltage V of the error amplification module at zero inductor current through the proportional coefficient. I The output voltage V of the error amplification module when the inductor current is zero C0 For adjustment.

[0099] More specifically, for the specific embodiment in, Figure 3 Adjust the current sampling resistor R and the output voltage V of the error amplification module at zero inductor current according to Equations (3) and (4). I The output voltage V of the error amplification module when the inductor current is zero C0 For adjustment.

[0100] More specifically, for the specific embodiment in, Figure 4 Adjust the current sampling resistor R and the output voltage V of the error amplification module at zero inductor current according to Equations (8) and (9). I The output voltage V of the error amplification module when the inductor current is zero C0 For adjustment.

[0101] Furthermore, the current sharing method for a multi-phase buck unit of the present invention further includes,

[0102] Step S3, adjust the target current limit I. MAX For adjustment.

[0103] More specifically, adjust the target current limit I according to Equation (6). MAX For adjustment.

[0104] Although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field to which the present invention pertains may make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application.

Claims

1. A current sharing circuit for a multi-phase buck unit, characterized in that, It includes an N-phase current sharing unit. The first ends of the current sharing units of each phase are short-circuited. The current sharing unit of each phase correspondingly collects the inductor current signal of a buck unit of one phase, and the second end of the current sharing unit of each phase correspondingly outputs the control signal of the switch in a buck unit of one phase. The current sharing unit includes a voltage dividing module, an error amplifying module, a PWM generating module, a conduction time generating module, an RS trigger module, and a logic control module. The first end of the voltage dividing module is connected to the output voltage of the buck unit. The second end of the voltage dividing module is connected to the negative input terminal of the error amplifying module. The positive input terminal of the error amplifying module is connected to the chip reference voltage. The output terminal of the error amplifying module outputs a first voltage and is connected to the first end of the PWM generating module. The second end of the PWM generating module is connected to the first input terminal of the RS trigger module. The second input terminal of the RS trigger module is connected to the conduction time generating module. The first output terminal of the RS trigger module is connected to the first end of the logic control module. The second end and the third end of the logic control module output the control signal of the switch in the buck unit. The PWM generating module includes a plurality of transistors, a plurality of amplifiers, and a first current source. The first ends of the second transistor, the third transistor, and the fourth transistor are connected to a second voltage. The second end of the second transistor is connected to the first current source. The second end of the third transistor is connected to the first end of a first trimming resistor. The second end of the first trimming resistor is connected to a first ground. The third end of the second transistor is connected to the third end of the third transistor, the second end of the second transistor, and the third end of the fourth transistor. The second end of the fourth transistor is connected to the negative input terminal of a second amplifier and the first end of a fourth resistor. The second end of the fourth resistor is connected to a second ground. The positive input terminal of the second amplifier is connected to the first voltage. The output terminal of the second amplifier is connected to the third end of an eighth transistor. The first end of the eighth transistor is connected to the first end of the fourth resistor. The second end of the eighth transistor is connected to the second end, the third end of a ninth transistor, and the third end of a tenth transistor. The first ends of the ninth transistor and the tenth transistor are connected to the second voltage. The second end of the tenth transistor is connected to the first end of a second trimming resistor. The second end of the second trimming resistor is connected to a third voltage. The first end of a first proportional trimming regulator is connected to the second voltage. The second end of the first proportional trimming regulator is connected to the second end of the tenth transistor. The third end of the first proportional trimming regulator is connected to the third end of the ninth transistor. The second end of the tenth transistor is connected to the positive input terminal of a third amplifier. The negative input terminal of the third amplifier is connected to a fourth voltage. The output terminal of the third amplifier outputs a PWM signal.

2. The current sharing circuit of a multi-phase buck unit according to claim 1, characterized in that, The first proportional trimming regulator includes a plurality of transistors. After every two transistors are connected in series, they are connected between the second voltage and the second end of the tenth transistor.

3. The current sharing circuit of a multi-phase buck unit according to claim 1, characterized in that, The first trimming resistor and the second trimming resistor each include the equivalent resistance after a plurality of transistors are connected in series.

4. The current sharing circuit of a multiphase buck unit as claimed in claim 1, wherein The driving circuit of the transistor includes a second current source, a first fuse, a first Schmitt trigger, and a first inverter. The second current source is connected to the first end of the first fuse. The second end of the first fuse is connected to a second ground. The first end of the first fuse, the first Schmitt trigger, and the first inverter are connected in sequence.

5. The current sharing circuit of a multi-phase buck unit according to claim 4, characterized in that, The driving circuit of the transistor further includes a second inverter. The first end of the first fuse, the first Schmitt trigger, the first inverter, and the second inverter are connected in sequence.

6. The current sharing circuit of a multi-phase buck unit as described in claim 1, characterized in that, It further includes a clamping module. The output end of the error amplification module is connected to the first end of the clamping module. The second end of the clamping module is connected to the first end of the PWM generation module.

7. A current sharing circuit for a multi-phase buck unit, characterized in that, It includes an N-phase current sharing unit. The first ends of each phase current sharing unit are short-circuited. Each phase current sharing unit correspondingly collects the inductor current signal of a phase-down unit. The second end of each phase current sharing unit correspondingly outputs the control signal of the switch in a phase-down unit. The current sharing unit includes a voltage division module, an error amplification module, a PWM generation module, a conduction time generation module, an RS trigger module, and a logic control module. The first end of the voltage division module is connected to the output voltage of the step-down unit. The second end of the voltage division module is connected to the negative input end of the error amplification module. The positive input end of the error amplification module is connected to the chip reference voltage. The output end of the error amplification module outputs a first voltage and is connected to the first end of the PWM generation module. The second end of the PWM generation module is connected to the first input end of the RS trigger module. The second input end of the RS trigger module is connected to the conduction time generation module. The first output end of the RS trigger module is connected to the first end of the logic control module. The second end and the third end of the logic control module output the control signal of the switch in the step-down unit. The PWM generation module includes multiple transistors, multiple amplifiers, and multiple resistors. The positive input terminal of the fourth amplifier is connected to the chip reference voltage. The negative input terminal of the fourth amplifier is connected to the first terminal of the eighteenth transistor. The output terminal of the fourth amplifier is connected to the third terminal of the eighteenth transistor. The first terminal of the eighteenth transistor is connected to the first terminal of the fifth resistor. The second terminal of the fifth resistor is connected to the first terminal of the first resistor trimmer. The second terminal of the first resistor trimmer is connected to the second ground. The second voltage is connected to the first terminals of the nineteenth transistor and the twenty-second transistor. The second terminal of the nineteenth transistor is connected to the third terminal of the nineteenth transistor, the second terminal of the eighteenth transistor, the third terminal of the twenty-second transistor, and the third terminal of the thirty-first transistor. The second terminal of the twenty-second transistor is connected to the first terminal of the third trim resistor. The second terminal of the third trim resistor is connected to the first ground. The first terminal of the second ratio trimmer is connected to the second voltage. The third terminal of the second ratio trimmer is connected to the third terminal of the nineteenth transistor. The second terminal of the second ratio trimmer is connected to the second terminal of the twenty-second transistor. The second terminal of the thirty-first transistor is connected to the negative input terminal of the fifth amplifier and the first terminal of the ninth resistor. The first positive input terminal of the fifth amplifier is connected to the first voltage. The second positive input terminal of the fifth amplifier is connected to the fifth voltage. The output terminal of the fifth amplifier is connected to the third terminal of the thirty-second transistor. The first terminal of the thirty-second transistor is connected to the first terminal of the ninth resistor. The second terminal of the ninth resistor is connected to the first terminal of the second resistor trimmer. The second terminal of the second resistor trimmer is connected to the second ground. The second voltage is connected to the first terminals of the thirty-third transistor and the thirty-fourth transistor. The second terminal of the thirty-third transistor is connected to the third terminal of the thirty-fourth transistor, the third terminal of the thirty-third transistor, and the second terminal of the thirty-second transistor. The second terminal of the thirty-fourth transistor is connected to the first terminal of the fourth trim resistor. The second terminal of the fourth trim resistor is connected to the third voltage. The second terminal of the thirty-fourth transistor is connected to the positive input terminal of the sixth amplifier. The negative input terminal of the sixth amplifier is connected to the fourth voltage. The output terminal of the sixth amplifier outputs a PWM signal.

8. The current sharing circuit of a multi-phase buck unit as described in claim 7, characterized in that, The second ratio trimmer includes multiple transistors, and every two transistors are connected in series between the second voltage and the second terminal of the twenty-second transistor.

9. The current sharing circuit of a multi-phase buck unit according to claim 7, characterized in that, The third trim resistor and the fourth trim resistor each include an equivalent resistor formed by multiple transistors connected in series.

10. The current sharing circuit of a multi-phase buck unit according to claim 7, characterized in that, The first resistor trimmer includes multiple resistors and multiple transistors. The multiple resistors are connected in series between the fifth resistor and the second ground, and a transistor is connected in parallel across each resistor. The second resistor trimmer includes multiple resistors and multiple transistors. The multiple resistors are connected in series between the ninth resistor and the second ground, and a transistor is connected in parallel across each resistor.

11. The current sharing circuit of a multi-phase buck unit according to claim 7, characterized in that, The driving circuit of the transistor includes a second current source, a first fuse, a first Schmitt trigger, and a first inverter. The second current source is connected to the first end of the first fuse. The second end of the first fuse is connected to a second ground. The first end of the first fuse, the first Schmitt trigger, and the first inverter are connected in sequence.

12. The current sharing circuit of a multi-phase buck unit as claimed in claim 11, wherein, The driving circuit of the transistor further includes a second inverter. The first end of the first fuse, the first Schmitt trigger, the first inverter, and the second inverter are connected in sequence.

13. The current sharing circuit of a multiphase buck unit according to claim 7, characterized in that, It further includes a clamping module. The output end of the error amplification module is connected to the first end of the clamping module. The second end of the clamping module is connected to the first end of the PWM generation module.

14. A current sharing method for a multi-phase buck unit, characterized in that, Applied to the current sharing circuit of a multi-phase buck unit as described in any one of claims 1-13, it includes Connecting the first voltages of each phase current sharing unit together; Adjusting the current sampling resistor and the output voltage of the error amplification module at zero inductor current through a proportionality coefficient.

15. The current sharing method of a multi-phase buck unit according to claim 14, characterized in that, It further includes adjusting the target current limit.

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