Low-delay ringing removing structure of CAN receiving circuit

Abstract

The invention discloses a low-delay ringing removal structure of a CAN receiving circuit. The low-delay ringing removal structure comprises a time detection circuit, a comparator circuit, an edge detection extraction circuit, a subtractor circuit, a delay sampling circuit, a logic gate and a D trigger, the time detection circuit is used for detecting the duration of dominant and implicit states of an input signal; the comparator circuit is used for amplifying and shaping an output signal of the time detection circuit; the edge detection extraction circuit is used for extracting a rising edge and a falling edge of an output signal of the comparator circuit; the subtracter circuit and the delay sampling circuit are used for delay compensation and compensating the phase difference between the extracted edge signal and the actual signal; the logic gate and the D trigger are used for signal output of the whole circuit structure. According to the invention, accurate processing and stable transmission of input receiving signals are realized, and communication errors caused by ringing signals are reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of CAN network communication, and in particular relates to a ringing removal structure of a low-delay CAN receiving circuit. Background Art

[0002] With the widespread application of Controller Area Network (CAN) in modern automotive electronic systems, industrial automation and other distributed embedded systems, CAN networks have achieved high reliability and real-time data transmission through differential signal transmission between multiple nodes. However, with the increase in the number of nodes in the CAN network and the increase in data transmission rate, signal integrity issues have become increasingly prominent, especially the signal ringing problem. The ringing signal is mainly caused by parasitic inductance and capacitance in the circuit. When high-speed signal switching occurs, the characteristic impedance mismatch of the transmission line will cause reflection, which will superimpose oscillation on the signal to form ringing. The ringing signal will appear on the rising and falling edges of the signal, causing the signal level to jump repeatedly in a short time, interfering with normal bit detection. These ringing signals may cause the receiver to mistakenly detect high or low levels, thereby increasing the bit error rate (BER). Especially at high data rate transmission (such as 1M bps and above), the impact of the ringing signal on signal integrity is particularly significant, which may cause unstable communication links or even data loss.

[0003] In the existing CAN structure, in order to suppress the ringing signal that occurs during signal transmission, the traditional method often uses a common mode choke. The common mode choke is designed to reduce the impact of high-frequency ringing signals and common mode noise on signal transmission by connecting an inductor consisting of two windings wound in opposite directions on the same magnetic core in series on the signal line of the CAN bus. This method uses the common mode choke's high impedance characteristic to common mode noise, hoping to effectively suppress high-frequency interference signals without significantly affecting normal differential mode signal transmission.

[0004] Although common mode chokes are excellent at suppressing high-frequency ringing and common-mode noise, this method also has some inherent disadvantages and limitations. The first is frequency dependence. The effective suppression frequency range of common mode chokes is limited. It has a good suppression effect on noise and ringing signals of certain specific frequencies, but its suppression ability will drop significantly at higher frequencies or wider bandwidths. This frequency characteristic means that ringing signals outside the frequency range may not be effectively filtered out, resulting in some high-frequency noise still existing in the signal.

[0005] Secondly, there is the disadvantage of signal attenuation. Although the common mode choke provides high impedance to common mode noise, it may also cause certain losses to the useful differential mode signal, especially at high frequencies. This signal attenuation may affect the amplitude and integrity of the signal, resulting in a decrease in signal quality at the receiving end.

[0006] In addition, efficient common-mode chokes usually require a large size and complex manufacturing process, which increases the space requirements and manufacturing costs of circuit design. In miniaturized and low-cost electronic devices, the use of common-mode chokes may not be economical and practical.

[0007] In addition, there is the issue of design complexity. The design of common-mode chokes requires precise selection of core materials, winding turns, and structures to achieve the desired frequency response and impedance characteristics. The design and debugging process is complex and may require multiple iterations to achieve the desired suppression effect. Summary of the invention

[0008] In order to overcome the shortcomings of the above-mentioned prior art, the purpose of the present invention is to provide a low-delay CAN receiving circuit ringing removal structure, which performs explicit and implicit level sampling on the input receiving signal through a sampling and holding circuit, removes high-frequency noise through a filtering circuit, and ensures that only effective signal changes can cause the state change of the receiver by a comparator and a trigger, so as to achieve accurate processing and stable transmission of the input receiving signal, and reduce communication errors caused by ringing signals. In addition, the present invention also solves the large delay problem in the edge extraction process through a delay compensation structure, further improving the efficiency and reliability of signal processing.

[0009] In order to achieve the above object, the technical solution adopted by the present invention is:

[0010] A low-delay ringing removal structure for a CAN receiving circuit includes a time detection circuit, a comparator circuit, an edge detection extraction circuit, a subtractor circuit, a delay sampling circuit, a logic gate and a D flip-flop;

[0011] The time detection circuit is used to detect the duration of dominant and recessive states of the input signal, and then the output after detection is DC and RC respectively;

[0012] The comparator circuit is used to amplify and shape the output signal of the time detection circuit;

[0013] The edge detection extraction circuit is used to extract the rising edge and falling edge of the output signal of the comparator circuit;

[0014] The subtractor circuit and the delayed sampling circuit are used for delay compensation to compensate for the phase difference between the extracted edge signal and the actual signal;

[0015] Logic gates and D flip-flops are used for signal output of the entire circuit structure. The edge triggering of the D flip-flop is used to convert the extracted edge signal into a persistent logic level signal.

[0016] The time detection circuit includes an explicit time detection circuit and a recessive time detection circuit;

[0017] The recessive detection circuit includes a resistor R1, a capacitor C1, a transistor Q1 and a current source, and inputs a NEWRXD signal shaped by an inverter to control the conduction of Q1. When it is turned on, the current source charges C1 to detect the recessive duration of the bus; when Q1 is turned off, the recessive detection circuit does not work; ensure that the recessive duration complies with the bus protocol, the protocol stipulates a working rate of 5Mbps, and the explicit and implicit time bit width is 200ns;

[0018] The dominant detection circuit includes a resistor R2, a capacitor C2, a transistor Q2 and a current source. A NEWRXD signal is input to control the conduction of Q2. When it is turned on, the current source charges C2 to detect the dominant duration of the bus. When Q2 is turned off, the dominant detection circuit does not work and is used to detect the duration to ensure that the dominant duration complies with the bus protocol.

[0019] When the charging time of capacitors C1 and C2 is much less than 200ns, the output RC or DC signal cannot reach the reference voltage value of the comparator circuit; when the charging time is much greater than 200ns, the output RC or DC signal can reach the comparator circuit part and compare with the reference voltage to obtain OUT1 and OUT2 signals.

[0020] The output signal of the recessive detection circuit is compared with the reference voltage VREF and shaped by the comparator to generate an OUT1 signal; when RC is less than VREF, the output OUT1 is a high level; when RC is greater than VREF, the output OUT1 is a low level;

[0021] The output signal of the dominant detection circuit is compared with the reference voltage VREF and shaped by the comparator to generate the OUT2 signal; when DC is less than VREF, the output OUT2 is a high level; when DC is greater than VREF, the output OUT2 is a low level.

[0022] The edge detection and extraction circuit is divided into two with the same structure. One is used to receive the OUT1 signal and extract the correct falling edge signal with a time bit width of 200ns that meets the protocol requirements; the other is used to receive the OUT2 signal and extract the correct rising edge signal with a time bit width of 200ns that meets the protocol requirements, ensuring that the time difference from the rising edge to the next falling edge is 200ns, which meets the protocol requirements.

[0023] OUTRC is the falling edge signal extracted from the recessive state, and OUTDC is the rising edge signal extracted from the dominant state. The sum of the two is the rising edge and the falling edge, that is, all the extracted edges are used as the CLK signal DFF_CLK of the D flip-flop. The input of the flip-flop is the falling edge in OLDRXD. The output result of the flip-flop is ANDed with OLDRXD to ensure that the dominant state of the bus remains unchanged, while removing the ringing signal of the recessive state.

[0024] The OLDRXD indicates an initial bus receive signal state with ringing.

[0025] The edge detection and extraction circuit is a NOT gate and an AND gate, and the original signal is ANDed with the delayed reverse signal.

[0026] The delay compensation circuit includes a subtractor and a delay sampling circuit, which performs a difference between the signals O and OLDRXD after preliminary ringing removal, and obtains a signal that is a delayed phase difference. The edge trigger of the D flip-flop is used to process OUTRC to obtain a persistent logic level signal Q1, and Q1 is ANDed with OLDRXD to eliminate the ringing, and obtain a signal O that is preliminary ringing removed. The phase difference part is sampled to obtain a compensation signal, and then a logical operation is performed on the compensation signal with the O signal to obtain the final NEWRXD signal after delay compensation, thereby ensuring the edge consistency between the extracted edge signal and the actual signal.

[0027] A method for operating a ringing removal structure of a low-latency CAN receiving circuit comprises the following steps:

[0028] Step 1: The input signal NEWRXD enters the dominant and recessive time detection circuit through a set of resistors and capacitors;

[0029] The recessive detection circuit is used to detect the duration and ensure that the recessive duration complies with the bus protocol;

[0030] The dominant detection circuit is used to detect the dominant duration of the bus, and is used to detect the duration to ensure that the dominant duration complies with the bus protocol;

[0031] The output signal of the recessive detection circuit is amplified and shaped by the comparator to generate the OUTRC signal;

[0032] The output signal of the dominant detection circuit is amplified and shaped by the comparator to generate the OUTDC signal;

[0033] Step 2: The OUTRC and OUTDC signals pass through the edge detection and extraction circuit, and only the correct rising and falling edge signals that meet the protocol time width requirements are extracted, ensuring that only the change of the valid non-ringing signal that jumps at the correct edge will cause the state change of the receiver;

[0034] The delay compensation circuit makes a difference between the signals O and OLDRXD after preliminary ringing removal, and the obtained signal is the delayed phase difference part. The phase difference part is sampled to obtain the compensation signal, and then the compensation signal is logically operated with the O signal to obtain the final NEWRXD signal after delay compensation, ensuring the edge consistency between the extracted edge signal and the actual signal;

[0035] Step 3: The signal after edge detection and delay compensation is further processed through logic gates and D flip-flops;

[0036] Step 4: The combinational logic circuit and the output driver generate a NEWRXD signal after processing, indicating a new bus receive signal state, and OLDRXD indicates a previous bus receive signal state.

[0037] In step 3, the specific processing method steps of the logic gate and the D flip-flop are as follows:

[0038] OUTRC and OUTDC are the edge extraction results after the recessive state and dominant state detection results respectively. The two are added to obtain DFF_CLK, which is the result of the effective edge extraction of OLDRXD. At the same time, it serves as the clock signal of the trigger. The input of the trigger is the falling edge in OLDRXD, that is, a normal signal without ringing. The output result of the trigger is ANDed with OLDRXD. The purpose is to ensure that the dominant state of the bus remains unchanged and remove the ringing signal of the recessive state.

[0039] The D flip-flop latches the current signal state according to the change of the input signal.

[0040] Beneficial effects of the present invention:

[0041] Compared with the common mode choke, the present invention has obvious advantages in removing signal ringing. First, it can efficiently perform edge detection, and detect the rising edge and falling edge of the input signal respectively through the explicit and implicit detection circuit to ensure the accuracy and reliability of signal processing. Secondly, the circuit amplifies and shapes the input signal through the comparator, effectively filters out the ringing noise in the input signal, and ensures the purity and stability of the output signal. Although the common mode choke can suppress common mode noise, its effect is limited when processing high-speed digital signals, especially in removing high-frequency ringing signals.

[0042] Furthermore, the present invention employs logic processing and latching functions to stably maintain and transfer signal states and prevent false triggering and signal loss, whereas common mode chokes lack similar fine control in this regard.

[0043] The present invention can flexibly adapt to input signals of different frequencies and characteristics by adjusting the parameters of RC and DC circuits, while the common mode choke coil needs to accurately match the characteristic impedance of the transmission line in design, and has poor flexibility.

[0044] In summary, the present invention not only improves the accuracy and reliability of signal processing, but also has significant advantages in anti-interference ability and adaptability, and provides a more effective signal protection and processing method. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the ringing removal structure of the CAN transceiver receiving circuit of the present invention.

[0046] Figure 2 It is a timing diagram of ringing removal of the receiving circuit of the present invention.

[0047] Figure 3 It is a timing diagram of delay compensation of the receiving circuit of the present invention.

[0048] Figure 4 It is a schematic diagram of large delay simulation of the receiving circuit of the present invention.

[0049] Figure 5 It is a schematic diagram of the overall circuit simulation of the present invention. DETAILED DESCRIPTION

[0050] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0051] An embodiment of the present invention provides a ringing removal structure for a CAN transceiver receiving circuit, which is connected after a normal receiving structure.

[0052] like Figure 1 As shown, the structure includes a time detection circuit, a comparator circuit, an edge detection extraction circuit, a subtractor circuit, a delay sampling circuit, and a logic gate and a D flip-flop;

[0053] The time detection circuit is used to detect the duration of dominant and recessive states of the input signal, and then the output after detection is DC and RC respectively;

[0054] The comparator circuit is used to amplify and shape the output signal of the time detection circuit;

[0055] The edge detection extraction circuit is used to extract the rising edge and falling edge of the output signal of the comparator circuit;

[0056] The subtractor circuit and the delayed sampling circuit are used for delay compensation to compensate for the phase difference between the extracted edge signal and the actual signal;

[0057] Logic gates and D flip-flops are used for signal output of the entire circuit structure. The edge triggering of the D flip-flop is used to convert the extracted edge signal into a persistent logic level signal.

[0058] The time detection circuit is divided into an explicit time detection circuit and a recessive time detection circuit;

[0059] First, the input signal NEWRXD enters the dominant and recessive time detection circuit through a pair of protection resistors R5 and R6;

[0060] The recessive detection circuit includes a resistor R1, a capacitor C1, a transistor Q1 and a current source, which are used to detect the recessive duration of the bus; the purpose of detecting the duration is to ensure that the recessive duration complies with the bus protocol (the protocol stipulates a working rate of 5Mbps and a recessive time bit width of 200ns).

[0061] The dominant detection circuit includes a resistor R2, a capacitor C2, a transistor Q2 and a current source, and is used to detect the dominant duration of the bus. The purpose of detecting the duration is to ensure that the dominant duration complies with the bus protocol.

[0062] The output signal of the recessive detection circuit is compared with VREF by comparator 1, amplified and shaped to generate OUT1 signal;

[0063] The output signal of the dominant detection circuit is compared with VREF by comparator 2, amplified and shaped to generate OUT2 signal.

[0064] Next, OUT1 passes through edge extraction circuit 1, and OUT2 passes through edge extraction circuit 2, which only extracts the correct rising and falling edge signals that meet the protocol time width requirements, ensuring that only changes in valid non-ringing signals that jump at the correct edge will cause the receiver's state to change. The extracted edge signals are OUTRC and OUTDC.

[0065] The structure of the edge detection extraction circuit is a NOT gate and an AND gate, and the original signal is ANDed with the delayed reverse signal.

[0066] The extracted edge signals OUTRC and OUTDC are added through OR gate 1 to obtain all edge signals, which are used as the CLK signal of the D flip-flop after passing through the filter circuit composed of R3 and C3.

[0067] In order to solve the delay problem that may be introduced in the edge extraction process, the present invention introduces a delay compensation circuit, which is composed of a subtractor and a delayed sampling circuit. The resistance values ​​of R7 to R10 are equal, and they form a subtractor circuit with OP1. The difference between the signals O and OLDRXD after preliminary ringing removal is made, and the obtained signal is the delayed phase difference part, wherein the edge trigger of the D flip-flop is used to process OUTRC to obtain a persistent logic level signal Q1, and Q1 and OLDRXD are ANDed to eliminate the ringing, and the signal O after preliminary ringing removal is obtained; OP2 and C4 form a delayed sampling circuit, sample this part, obtain a compensation signal, and then use the signal after inverter cascade shaping to perform an OR logic operation with the O signal to obtain the final NEWRXD signal after delay compensation. Ensure the edge consistency of the extracted edge signal and the actual signal, and improve the accuracy and stability of signal processing.

[0068] Finally, the signal after edge detection and delay compensation is further processed through logic gates (AND gate 2 and OR gate 2) and D flip-flops.

[0069] Specific processing steps for logic gates and D flip-flops:

[0070] OUTRC and OUTDC are the edge extraction results after the recessive state and dominant state detection results respectively. The two are added to obtain DFF_CLK, which is the result of the effective edge extraction of OLDRXD. At the same time, it serves as the clock signal of the trigger. The input of the trigger is the falling edge in OLDRXD, that is, a normal signal without ringing. The output result of the trigger is ANDed with OLDRXD. The purpose is to ensure that the dominant state of the bus remains unchanged and remove the ringing signal of the recessive state.

[0071] The D flip-flop latches (as described above) the current signal state according to changes in the input signal.

[0072] Finally, the combinational logic circuit and the output driver generate a NEWRXD signal after processing, indicating the new bus receiving signal state, and OLDRXD indicates the previous bus receiving signal state.

[0073] The duration of the dominant and recessive levels needs to meet the CAN bus protocol standard. In the detection circuit, the duration of the high and low levels of the input receiving signal is obtained through sampling and calculation, where the high level represents the recessive state of the bus and the low level represents the dominant state of the bus. The detection time is determined by adjusting the capacitance of the circuit. The detection time is related to the charging time of the capacitance. The capacitance is charged by the detected signal. The larger the capacitance, the longer the detection time. This is C1 and C2 in the figure.

[0074] After the detection is completed, the detected signal RC representing the duration of the recessive state is compared with the reference voltage VREF. This step is to ensure that the recessive state lasts for a time that meets the protocol standard. In the open-loop comparator composed of this op amp, when the RC signal is higher than VREF, the output result of the op amp will be flipped;

[0075] The detection of the dominant state is similar. The detected signal DC representing the duration of the dominant state is compared with the reference voltage VREF. This step is to ensure that the dominant state lasts for a time that meets the protocol standard. When the DC signal is higher than VREF, the output result will be flipped.

[0076] After the recessive state detection circuit outputs the result, it and the result after passing through the inverter are connected to the AND gate for edge extraction;

[0077] The same is true for the dominant part, and the corresponding edge signals OUTRC and OUTDC are obtained. The two are added together to obtain the edge part of the bus input signal. In this step, it should be noted that due to the existence of the comparison part, the extracted edges are all valid signals rather than the edges of the ringing signal, because the comparison part requires that both the dominant and recessive states last for a period of time to be used as valid signals.

[0078] The extracted edge signal is used as the clock signal of the trigger triggered by the rising edge, and finally a received signal without a ringing signal is output. However, since there is a large delay in the edge extraction process of the edge extraction circuit, it is necessary to subtract the output signal from OLDRXD. The obtained signal is the part of the delay difference. This part is sampled to obtain the compensation signal, and then it is logically operated with the O signal. The compensation signal is added to the signal O with delay but after the ringing is removed to compensate for the phase caused by the delay between the two, and the final low-delay NEWRXD signal with delay compensation is obtained.

[0079] Figure 2 The timing diagram of the structure to remove ringing is shown. OLD_RXD is the initial input signal, RC and DC are the output signals of the time detection circuit, OUTRC and OUTDC are the output signals after amplification and shaping by the comparator, DFF_CLK is the result of the AND operation of the rising and falling edge signals of the edge extraction circuit, and NEW_RXD is the final output signal of the circuit.

[0080] The recessive state in the second half cycle is accompanied by a ringing signal.

[0081] First, the dominant and recessive states of OLD_RXD are sampled and tested, and the results are shown in RC and DC. In it, the ringing signal only shows a small fluctuation, which cannot flip the comparison output result in the process of comparing with the reference voltage, achieving the purpose of filtering out the ringing signal, and OUTRC and OUTDC are the edge extraction results after the recessive state and dominant state detection results respectively. The two are added to obtain DFF_CLK, which is the result of the effective edge extraction of OLD_RXD. At the same time, as the clock signal of the trigger, the input end of the trigger is the falling edge in OLD_RXD, that is, a normal signal without ringing. The output result of the trigger is ANDed with OLD_RXD, the purpose is to ensure that the dominant state of the bus remains unchanged and remove the ringing signal of the recessive state.

[0082] Figure 3 The timing diagram of the delay compensation part of the circuit is shown. OLD_RXD is the initial input signal, O is the signal with delay after removing the ringing, and Delay compensate is the pulse wave generated by delay compensation. After compensation, NEWRXD with low delay is formed.

[0083] Among them, ΔT is the receiving output delay caused by the delay of the edge detection part, the O signal is the output signal with delay, and Delay compensate is the pulse wave generated by delay compensation. After compensation, a low-delay NEWRXD is formed.

[0084] Figure 4 This is the circuit simulation result without adding a delay compensation structure. It can be seen from the attached figure that although there is a certain delay in the circuit due to edge extraction, it does not affect the overall ringing removal effect. However, a large delay will affect the bus stability.

[0085] Figure 5 The circuit simulation result of the overall structure is shown in Figure 1. Under the premise of removing the error signal caused by ringing, the delay is reduced. In the figure, OLDRXD is the received signal with the error recognition result, DC is the sampling result of the bus dominant state, RC is the sampling result of the bus recessive state, OUTRC and OUTDC are the edge extraction parts. It can be seen that a large delay is generated in the extraction process. CP is the pulse signal generated by the delay compensation, and NEWRXD is the final output signal. From the simulation results, the delay is only 19ns.

Claims

1. A low-latency ringing removal structure for a CAN receiving circuit, characterized in that: It includes a time detection circuit, a comparator circuit, an edge detection extraction circuit, a subtractor circuit, a delay sampling circuit, and a logic gate and a D flip-flop; The time detection circuit is used to detect the duration of dominant and recessive states of the input signal, and then the output after detection is DC and RC respectively; The comparator circuit is used to amplify and shape the output signal of the time detection circuit; The edge detection extraction circuit is used to extract the rising edge and falling edge of the output signal of the comparator circuit; The subtractor circuit and the delayed sampling circuit are used for delay compensation to compensate for the phase difference between the extracted edge signal and the actual signal; Logic gates and D flip-flops are used for signal output of the entire circuit structure. The edge triggering of the D flip-flop is used to convert the extracted edge signal into a persistent logic level signal.

2. The ringing removal structure of a low-latency CAN receiving circuit according to claim 1, characterized in that: The time detection circuit includes an explicit time detection circuit and a recessive time detection circuit; The recessive detection circuit includes a resistor R1, a capacitor C1, a transistor Q1 and a current source, and inputs a NEWRXD signal shaped by an inverter to control the conduction of Q1. When it is turned on, the current source charges C1 to detect the recessive duration of the bus; when Q1 is turned off, the recessive detection circuit does not work; ensure that the recessive duration complies with the bus protocol, the protocol stipulates a working rate of 5Mbps, and the explicit and implicit time bit width is 200ns; The dominant detection circuit includes a resistor R2, a capacitor C2, a transistor Q2 and a current source. A NEWRXD signal is input to control the conduction of Q2. When it is turned on, the current source charges C2 to detect the dominant duration of the bus. When Q2 is turned off, the dominant detection circuit does not work to ensure that the dominant duration complies with the bus protocol.

3. The ringing removal structure of a low-latency CAN receiving circuit according to claim 2, characterized in that: When the charging time of capacitors C1 and C2 is much less than 200ns, the output RC or DC signal cannot reach the reference voltage value of the comparator circuit; when the charging time is much greater than 200ns, the output RC or DC signal can reach the comparator circuit part and compare with the reference voltage to obtain OUT1 and OUT2 signals.

4. The ringing removal structure of a low-latency CAN receiving circuit according to claim 2, characterized in that: The output signal of the recessive detection circuit is compared with the reference voltage VREF and shaped by the comparator to generate an OUT1 signal; when RC is less than VREF, the output OUT1 is a high level; when RC is greater than VREF, the output OUT1 is a low level; The output signal of the dominant detection circuit is compared with the reference voltage VREF and shaped by the comparator to generate the OUT2 signal; when DC is less than VREF, the output OUT2 is a high level; when DC is greater than VREF, the output OUT2 is a low level.

5. The ringing removal structure of a low-latency CAN receiving circuit according to claim 4, characterized in that: The edge detection and extraction circuit is divided into two with the same structure. One is used to receive the OUT1 signal and extract the correct falling edge signal with a time bit width of 200ns that meets the protocol requirements; the other is used to receive the OUT2 signal and extract the correct rising edge signal with a time bit width of 200ns that meets the protocol requirements, ensuring that the time difference from the rising edge to the next falling edge is 200ns, which meets the protocol requirements.

6. The ringing removal structure of a low-latency CAN receiving circuit according to claim 5, characterized in that: OUTRC is the falling edge signal extracted from the recessive state, and OUTDC is the rising edge signal extracted from the dominant state. The sum of the two is the rising edge and the falling edge, that is, all the extracted edges are used as the CLK signal DFF_CLK of the D flip-flop. The input of the flip-flop is the falling edge in OLDRXD. The output result of the flip-flop is ANDed with OLDRXD to ensure that the dominant state of the bus remains unchanged, while removing the ringing signal of the recessive state. The OLDRXD indicates an initial bus receive signal state with ringing.

7. The ringing removal structure of a low-latency CAN receiving circuit according to claim 6, characterized in that: The edge detection and extraction circuit is a NOT gate and an AND gate, and the original signal is ANDed with the delayed reverse signal; The delay compensation circuit includes a subtractor and a delay sampling circuit, which performs a difference between the signals O and OLDRXD after preliminary ringing removal, and obtains a signal that is a delayed phase difference. The edge trigger of the D flip-flop is used to process OUTRC to obtain a persistent logic level signal Q1, and Q1 is ANDed with OLDRXD to eliminate the ringing, and obtain a signal O that is preliminary ringing removed. The phase difference part is sampled to obtain a compensation signal, and then a logical operation is performed on the compensation signal with the O signal to obtain the final NEWRXD signal after delay compensation, thereby ensuring the edge consistency between the extracted edge signal and the actual signal.

8. The method for operating the ringing removal structure of a low-latency CAN receiving circuit according to any one of claims 1 to 7, characterized in that: The steps include: Step 1: The input signal NEWRXD enters the dominant time detection circuit and the recessive time detection circuit through a group of resistors and capacitors; The recessive detection circuit is used to detect the duration and ensure that the recessive duration complies with the bus protocol; The dominant detection circuit is used to detect the dominant duration of the bus, and is used to detect the duration to ensure that the dominant duration complies with the bus protocol; The output signal of the recessive detection circuit is amplified and shaped by the comparator to generate the OUTRC signal; The output signal of the dominant detection circuit is amplified and shaped by the comparator to generate the OUTDC signal; Step 2: The OUTRC and OUTDC signals pass through the edge detection and extraction circuit, and only the correct rising and falling edge signals that meet the protocol time width requirements are extracted, ensuring that only the change of the valid non-ringing signal that jumps at the correct edge will cause the state change of the receiver; The delay compensation circuit makes a difference between the signals O and OLDRXD after preliminary ringing removal, and the obtained signal is the delayed phase difference part. The phase difference part is sampled to obtain the compensation signal, and then the compensation signal is logically operated with the O signal to obtain the final NEWRXD signal after delay compensation, ensuring the edge consistency between the extracted edge signal and the actual signal; Step 3: The signal after edge detection and delay compensation is further processed through logic gates and D flip-flops; Step 4: The combinational logic circuit and the output driver generate a NEWRXD signal after processing, indicating a new bus receive signal state, and OLDRXD indicates a previous bus receive signal state.

9. The method for operating a ringing removal structure of a low-latency CAN receiving circuit according to claim 8, characterized in that: In step 3, the specific processing method steps of the logic gate and the D flip-flop are as follows: OUTRC and OUTDC are the edge extraction results after the recessive state and dominant state detection results respectively. The two are added to obtain DFF_CLK, which is the result of the effective edge extraction of OLDRXD. At the same time, it serves as the clock signal of the trigger. The input of the trigger is the falling edge in OLDRXD, that is, a normal signal without ringing. The output result of the trigger is ANDed with OLDRXD to ensure that the dominant state of the bus remains unchanged and the ringing signal of the recessive state is removed.

10. The method for operating the ringing removal structure of a low-latency CAN receiving circuit according to claim 9, characterized in that: The D flip-flop latches the current signal state according to the change of the input signal.

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