Analog-to-digital conversion circuit, analog-to-digital conversion method, chip and electronic equipment

Abstract

The invention discloses an analog-to-digital conversion circuit, an analog-to-digital conversion method, a chip and electronic equipment, and the analog-to-digital conversion circuit is used as a cyclic approximation type analog-to-digital converter and comprises a capacitance degradation amplifier, a digital-to-analog converter, a comparator, a first switched capacitor circuit and a second switched capacitor circuit. The digital-to-analog converter is connected with the comparator, the first switched capacitor circuit and the second switched capacitor circuit. And the comparator is respectively connected with the first and second switched capacitor circuits. And the capacitance degeneration amplifier is respectively connected with the first and second switched capacitor circuits. The cyclic approximation type analog-to-digital converter is realized based on an open-loop capacitance degradation amplifier, and the power consumption of the cyclic approximation type analog-to-digital converter is greatly reduced on the premise of ensuring high linearity by applying charge sharing and other low-power-consumption technologies.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an analog-to-digital conversion circuit, an analog-to-digital conversion method, a chip, and an electronic device. Background Art

[0002] The cyclic approximation analog-to-digital converter (Cyclic ADC) is a type of analog-to-digital converter with a faster processing speed. It is suitable for fast measurement applications. It can also be combined with a Sigma delta ADC to form a hybrid structure to reduce the number of conversion cycles for high-precision measurements. The cyclic approximation analog-to-digital converter has the characteristics of high circuit reusability and low hardware requirements. It is widely used in image sensors, biomedical sensors and other fields. Based on considerations such as heat and power consumption, when designing on-chip circuits, it is necessary to minimize the power consumption of the designed circuits, and then optimize the cyclic approximation analog-to-digital converters contained in the on-chip circuits. Summary of the invention

[0003] The main technical problem solved by the present application is how to reduce power consumption while maintaining high linearity of a cyclic approximation analog-to-digital converter.

[0004] According to the first aspect, in one embodiment of the present application, an analog-to-digital conversion circuit is provided, which is used as a cyclic approximation analog-to-digital converter, including a capacitive degeneration amplifier, a digital-to-analog converter, a comparator, a first switched capacitor circuit and a second switched capacitor circuit; The digital-to-analog converter comprises a first conversion connection terminal, a second conversion connection terminal, a first comparison connection terminal, a first switch control connection terminal and a second switch control connection terminal; the first conversion connection terminal and the second conversion connection terminal of the digital-to-analog converter are used as input and output connection terminals of the analog-to-digital conversion circuit, respectively for a preset first reference voltage V refp and the second reference voltage V refn The first comparison connection terminal of the digital-to-analog converter is connected to the comparator; the first switch control connection terminal and the second switch control connection terminal of the digital-to-analog converter are respectively connected to the first switch capacitor circuit and the second switch capacitor circuit; The comparator comprises a first connection terminal, a second connection terminal and a third connection terminal; the first connection terminal and the second connection terminal of the comparator are respectively connected to the first switch capacitor circuit and the second switch capacitor circuit; the third connection terminal of the comparator is connected to the first comparison connection terminal of the digital-to-analog converter; The capacitance degeneration amplifier comprises a positive input connection terminal, a negative input connection terminal, a positive output connection terminal and a negative output connection terminal; the positive input connection terminal and the negative output connection terminal of the capacitance degeneration amplifier are connected to the first switching capacitor circuit, and the negative input connection terminal and the positive output connection terminal of the capacitance degeneration amplifier are connected to the second switching capacitor circuit.

[0005] In one embodiment, the capacitive degeneration amplifier includes a first switch Φ CS11 , the second switch Φ CS21 、The third switch Φ A11 、The fourth switch Φ A21 、The fifth switch Φ A12 、The sixth switch Φ A21 、Seventh switch Φ CS12 、The eighth switch Φ CS22 , the first capacitor C DEG1 , the second capacitor C DEG2 , the first transistor M A11 , the second transistor M A21 , the third transistor M A12 , the fourth transistor M A22 , the first node V SP11 , the second node V SP21 、The third node V SP12 , the fourth node V SP22 and degraded switch S R ; The first transistor M A11 and the third transistor M A12 The control electrode of is used as the positive input connection terminal of the capacitance degradation amplifier; the second transistor M A21 and the fourth transistor M A22 The control electrode of is used as the negative input connection terminal of the capacitance degeneration amplifier, and the degeneration switch S R The two ends of are respectively used as the positive output connection terminal and the negative output connection terminal of the capacitive degeneration amplifier; The first transistor M A11 The second electrode of the third transistor M A12 The second electrode of the second transistor M is connected A21 The second electrode of the fourth transistor M A22 The second pole connection; The first switch Φ CS11 One end is used for working power supply V DD The other end is connected to the first node V SP11 Connection; the second switch Φ CS21 One end is used for the working voltage V DD The other end is connected to the second node V SP21The third switch Φ A11 One end and the first node V SP11 The other end is connected to the first transistor M A11 The first pole of the fourth switch Φ A21 One end and the second node V SP21 The other end is connected to the second transistor M A21 The first pole connection; The fifth switch Φ A12 One end of the third transistor M A12 The first electrode is connected to the third node V SP12 The sixth switch Φ A21 One end of the fourth transistor M A22 The first electrode is connected to the fourth node V SP22 The seventh switch Φ CS12 One end and the third node V SP12 The other end is connected to the ground; the eighth switch Φ CS22 One end of the fourth node V SP22 Connect, and ground the other end; The first capacitor C DEG1 One end and the second node V SP21 Connect the other end to the third node V SP12 Connection: The second capacitor C DEG2 One end and the first node V SP11 The other end is connected to the fourth node V SP22 connect; The degradation switch S R One end of the first transistor M A11 The second electrode is connected to the second transistor M A21 The second pole connection.

[0006] In one embodiment, the first switched capacitor circuit and the second switched capacitor circuit respectively include an analog input first connection terminal, a converter connection terminal, a comparator connection terminal, an amplification first connection terminal, an amplification second connection terminal, a third capacitor C ref , the fourth capacitor C s , the fifth capacitor C L , the first capacitor switch Φ A0 , the second capacitor switch Φ re 、The third capacitor switch Φ S_BAR , the fourth capacitor switch Φ CS1 、The fifth capacitor switch Φ COM 、The sixth capacitor switch Φ A1 、The seventh capacitor switch Φ CS2 、The eighth capacitor switch ΦA2 、Ninth capacitor switch Φ CS3 、The tenth capacitor switch Φ CS4 、11th capacitor switch Φ A3 、12th capacitor switch Φ CS5 , the first capacitor node V CK0 , the second capacitor node V CK1 , the third capacitor node V CK2 , the fourth capacitor node V CK3 , the fifth capacitor node V CK4 , the sixth capacitor node V CK5 and voltage conversion node V CM ; The voltage conversion node V CM A connection node for a reference common-mode voltage signal; The analog input first connection terminal is used as an analog signal V BN / P Input; The converter connection end is connected to the digital-to-analog converter; The comparator connection terminal is connected to the comparator; The first amplifying connection terminal and the second amplifying connection terminal are respectively connected to the positive input connection terminal and the negative output connection terminal of the capacitance degeneration amplifier, or to the negative input connection terminal and the positive output connection terminal of the capacitance degeneration amplifier; The first capacitive switch Φ A0 One end is connected to the amplified second connection end, and the other end is connected to the fifth capacitor node V CK4 Connection; the second capacitor switch Φ re One end of the fifth capacitor node V CK4 connected, and the other end connected to the voltage conversion node V CM The third capacitor switch Φ S_BAR One end of the fifth capacitor node V CK4 The fourth capacitor switch Φ CS1 One end is connected to the comparator connection end, and the other end is connected to the fourth capacitor node V CK3 The fifth capacitor switch Φ COM One end of the fourth capacitor node V CK3 The other end is connected to the third capacitor node V CK2 The sixth capacitor switch Φ A1 One end of the fourth capacitor node V CK3 The seventh capacitor switch Φ CS2 One end of the third capacitor node V CK2 connected, and the other end connected to the voltage conversion node VCM The eighth capacitor switch Φ A2 One end of the third capacitor node V CK2 Connect the other end to the second capacitor node V CK1 The ninth capacitor switch Φ CS3 One end is connected to the converter connection end, and the other end is connected to the second capacitor node V CK1 The tenth capacitor switch Φ CS4 One end of the voltage conversion node V CM Connect the other end to the first capacitor node V CK0 The eleventh capacitor switch Φ A3 One end of the first capacitor node V CK0 The twelfth capacitor switch Φ CS5 One end of the analog input first connection end is connected to the analog input first connection end, and the other end of the analog input first connection end is connected to the amplification first connection end; The third capacitor C ref One end of the first capacitor node V CK0 Connect the other end to the second capacitor node V CK1 Connect; the fourth capacitor C s One end of the third capacitor node V CK2 The other end is connected to the fourth capacitor node V CK3 Connect; the fifth capacitor C L One end of the voltage conversion node V CM The other end is connected to the fifth capacitor node V CK4 connect.

[0007] In one embodiment, the first switched capacitor circuit and the second switched capacitor circuit further include an analog input second connection terminal, a sixth capacitor C S_pre 、Thirteenth capacitor switch Φ S 、14th capacitor switch Φ S_pre 、15th capacitor switch Φ S_pre_BAR and the sixth capacitor node V CK5 ; The analog input second connection terminal is used as a first analog input signal V inp Or simulate the second input signal V inn Input; The sixth capacitor C S_pre One end of the voltage conversion node V CM The other end is connected to the sixth capacitor node V CK5 connect; The thirteenth capacitor switch Φ SOne end is connected to the comparator connection end, and the other end is connected to the sixth capacitor node V CK5 connect; The fourteenth capacitance switch Φ S_pre One end of the sixth capacitor node V CK5 connected, and the other end is connected to the analog input second connection end; The fifteenth capacitor switch Φ S_pre_BAR One end of the sixth capacitor node V CK5 connected, and the other end connected to the voltage conversion node V CM connect.

[0008] In one embodiment, the first capacitor C DEG1 The second capacitor C DEG2 , the third capacitor C ref , the fourth capacitor C s , the fifth capacitor C L and the sixth capacitor C S_pre The proportional relationship of the capacitance values ​​is a preset fixed value.

[0009] In one embodiment, the digital-to-analog converter further comprises a second comparison connection terminal, and the second comparison connection terminal of the digital-to-analog converter is connected to the comparator; The comparator further comprises a fourth connection terminal, and the fourth connection terminal of the comparator is connected to the second comparison connection terminal of the digital-to-analog converter; The digital-to-analog converter is used to convert the 1.5-bit digital signal output by the comparator into an analog signal.

[0010] In one embodiment, the comparator includes a first comparison circuit and a second comparison circuit; The first comparison circuit and the second comparison circuit respectively include a first input connection terminal, a second input connection terminal and a comparison output terminal; A first input connection terminal and a second input connection terminal of the first comparison circuit are connected to the first switched capacitor circuit and the second switched capacitor circuit respectively, and a comparison output terminal of the first comparison circuit is connected to a first comparison connection terminal of the digital-to-analog converter; The first input connection terminal and the second input connection terminal of the second comparison circuit are connected to the first switched capacitor circuit and the second switched capacitor circuit respectively, and the comparison output terminal of the second comparison circuit is connected to the second comparison connection terminal of the digital-to-analog converter.

[0011] According to a second aspect, an analog-to-digital conversion method is provided in an embodiment of the present application, which is applied to the analog-to-digital conversion circuit as described in the first aspect, and the analog-to-digital conversion method includes: When the capacitor degeneration amplifier works in the amplification stage, the degeneration switch SR When the capacitor degradation amplifier is operating in the off phase, the degradation switch S R Closed conduction.

[0012] According to the third aspect, in one embodiment of the present application, a chip is provided, comprising the analog-to-digital conversion circuit as described in the first aspect.

[0013] According to a fourth aspect, an electronic device is provided in an embodiment of the present application, comprising the chip as described in the third aspect.

[0014] According to the analog-to-digital conversion circuit in the above embodiment, a cyclic approximation analog-to-digital converter is implemented based on an open-loop capacitive degeneration amplifier, and low-power technologies such as charge sharing are applied to greatly reduce the power consumption of the cyclic approximation analog-to-digital converter while ensuring high linearity. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A schematic diagram of the structural connection of an analog-to-digital conversion circuit in an embodiment; Figure 2 A circuit connection diagram of a capacitance degeneration amplifier in one embodiment; Figure 3 A schematic diagram of circuit connection between a first switched capacitor circuit and a second switched capacitor circuit in an embodiment; Figure 4 is a circuit diagram of a capacitor degeneration amplifier; Figure 5 is a curve diagram of the linear amplification characteristics of the capacitor degeneration amplifier; Figure 6 Schematic diagram of the effect of the drain parasitic capacitance of a capacitance-degraded amplifier on the output signal; Figure 7 This is a schematic diagram of the input voltage compression circuit implementation; Figure 8 It is a schematic diagram of input voltage value compression; Fig. 9 FIG. 4 is a timing diagram of a circular approximation analog-to-digital converter in one embodiment. DETAILED DESCRIPTION

[0016] The present invention is further described in detail below by specific embodiments in conjunction with the accompanying drawings. Wherein similar elements in different embodiments adopt associated similar element numbers. In the following embodiments, many detailed descriptions are for making the present application better understood. However, those skilled in the art can easily recognize that some features can be omitted in different situations, or can be replaced by other elements, materials, methods. In some cases, some operations related to the present application are not shown or described in the specification, this is to avoid the core part of the present application being overwhelmed by too much description, and for those skilled in the art, it is not necessary to describe these related operations in detail, and they can fully understand the related operations according to the description in the specification and the general technical knowledge in the art.

[0017] In addition, the features, operations or characteristics described in the specification can be combined in any appropriate manner to form various implementations. At the same time, the steps or actions in the method description can also be interchanged or adjusted in a manner that is obvious to those skilled in the art. Therefore, the various sequences in the specification and the drawings are only for the purpose of clearly describing a certain embodiment and are not meant to be a required sequence, unless otherwise specified that a certain sequence must be followed.

[0018] The serial numbers for the components herein, such as "first", "second", etc., are only used to distinguish the objects described and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). The terms "include", "comprise" or any other variants thereof herein are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the statement "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0019] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, explanations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner. "Multiple" in the embodiments of the present application refers to two or more. In view of this, "multiple" can also be understood as "at least two" in the embodiments of the present application. "At least one" can be understood as one or more, for example, as one, two or more. For example, including at least one means including one, two or more, and it is not limited which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A and B and C can be included.

[0020] It should be emphasized that in the embodiments of the present application, "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent three situations: A exists alone, A and B exist at the same time, and B exists alone. There is also the character " / ", which, unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship. The "connection" in the embodiments of the present application can be understood as an electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0021] The first pole / first end of each transistor used in the embodiments of the present application is one of the source and the drain, and the second pole / second end of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first pole / first end and the second pole / second end of the transistor in the embodiments of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first pole / first end of the transistor is the source, and the second pole / second end is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first pole / first end of the transistor is the drain, and the second pole / second end is the source.

[0022] A general cyclic approximation analog-to-digital converter includes a sample-and-hold circuit, an operational amplifier, a comparator, and a digital-to-analog converter. Among them, the operational amplifier is the key module for realizing the cyclic operation logic and occupies a large part of the power consumption. Therefore, optimizing the cyclic approximation analog-to-digital converter requires optimizing the amplifier circuit first. The open-loop amplifier has obvious advantages over the traditional operational amplifier in terms of low power consumption, but its linearity is greatly limited due to the change of transconductance. The amplification factor of the capacitor degeneration amplifier does not depend on the transconductance stability of the transistor and has a very high linearity.

[0023] In the embodiment of the present application, a multi-bit Cyclic ADC is implemented based on an open-loop capacitive degeneration amplifier, and low-power technologies such as charge sharing are used in the cycle, which greatly reduces the power consumption of the Cyclic ADC while ensuring high linearity.

[0024] Embodiment 1: Please refer to Figure 1 , is a schematic diagram of the structure connection of an analog-to-digital conversion circuit in an embodiment, the analog-to-digital conversion circuit is used as a cyclic approximation type analog-to-digital converter, including a capacitive degeneration amplifier 10, a digital-to-analog converter 30, a comparator 20, a first switch capacitor circuit 40 and a second switch capacitor circuit 50. The digital-to-analog converter 30 includes a first conversion connection terminal, a second conversion connection terminal, a first comparison connection terminal, a first switch control connection terminal and a second switch control connection terminal. The first conversion connection terminal and the second conversion connection terminal of the digital-to-analog converter 30 are used as input and output connection terminals of the analog-to-digital conversion circuit, respectively for a preset first reference voltage V refp and the second reference voltage V refn The first comparison connection terminal of the digital-to-analog converter 30 is connected to the comparator 20, and the first switch control connection terminal and the second switch control connection terminal of the digital-to-analog converter 30 are respectively connected to the first switch capacitor circuit 40 and the second switch capacitor circuit 50. The digital-to-analog converter 30 is used to convert the digital signal output by the comparator 20 into an analog signal, and output the converted analog signal to the first switch capacitor circuit 40 and the second switch capacitor circuit 50. The comparator 20 includes a first connection terminal, a second connection terminal and a third connection terminal. The first connection terminal and the second connection terminal of the comparator 20 are respectively connected to the first switch capacitor circuit 40 and the second switch capacitor circuit 50, and the third connection terminal of the comparator 20 is connected to the first comparison connection terminal of the digital-to-analog converter 30. The capacitance degradation amplifier 10 includes a positive input connection terminal, a negative input connection terminal, a positive output connection terminal and a negative output connection terminal. The positive input connection terminal and the negative output connection terminal of the capacitance degradation amplifier 10 are connected to the first switch capacitor circuit 40, and the negative input connection terminal and the positive output connection terminal of the capacitance degradation amplifier 10 are connected to the second switch capacitor circuit 50.

[0025] Please refer to Figure 2, is a circuit connection diagram of a capacitance degradation amplifier in an embodiment, the capacitance degradation amplifier includes a first switch Φ CS11 , the second switch Φ CS21 、The third switch Φ A11 、The fourth switch Φ A21 、The fifth switch Φ A12 、The sixth switch Φ A21 、Seventh switch Φ CS12 、The eighth switch Φ CS22 , the first capacitor C DEG1 , the second capacitor C DEG2 , the first transistor M A11 , the second transistor M A21 , the third transistor M A12 , the fourth transistor M A22 , the first node V SP11 , the second node V SP21 、The third node V SP12 , the fourth node V SP22 and degraded switch S R .

[0026] The first transistor M A11 and the third transistor M A12 The control electrode of the capacitor degeneration amplifier 10 is used as the positive input connection terminal, and the second transistor M A21 and the fourth transistor M A22 The control electrode of is used as the negative input connection terminal of the capacitor degeneration amplifier 10, and the degeneration switch S R The two ends of are respectively used as the positive output connection terminal and the negative output connection terminal of the capacitance degeneration amplifier 10.

[0027] The first transistor M A11 The second electrode and the third transistor M A12 The second electrode of the second transistor M A21 The second electrode of the fourth transistor M A22 The second pole of the first switch Φ CS11 One end is used for working power supply V DD The other end is connected to the first node V SP11 Connect. Second switch Φ CS21 One end is used for the working voltage V DD The other end is connected to the second node V SP21 Connection. The third switch Φ A11 One end and the first node V SP11 The other end is connected to the first transistor M A11 The fourth switch Φ A21 One end and the second node V SP21 The other end is connected to the second transistor M A21The first pole of the fifth switch Φ A12 One end of the third transistor M A12 The first electrode is connected to the other end of the third node V SP12 Connection. The sixth switch Φ A21 One end of the fourth transistor M A22 The first electrode is connected to the fourth node V SP22 Connection. Seventh switch Φ CS12 One end and the third node V SP12 The other end is connected to the ground. CS22 One end of the fourth node V SP22 The other end is connected to the ground. DEG1 One end and the second node V SP21 Connect the other end to the third node V SP12 Connect the second capacitor C DEG2 One end and the first node V SP11 Connect the other end to the fourth node V SP22 Connection. Degeneration switch S R One end of the first transistor M A11 The second electrode is connected to the second transistor M A21 When the capacitor degeneration amplifier 10 operates in the amplification stage, the degeneration switch S R When the capacitor degeneration amplifier 10 is in the off stage, the degeneration switch S R Closed conduction.

[0028] Please refer to Figure 3 , is a circuit connection diagram of a first switch capacitor circuit and a second switch capacitor circuit in an embodiment. In an embodiment, the first switch capacitor circuit 40 and the second switch capacitor circuit 50 respectively include an analog input first connection terminal, a converter connection terminal, a comparator connection terminal, an amplification first connection terminal, an amplification second connection terminal, and a third capacitor C ref , the fourth capacitor C s , the fifth capacitor C L , the first capacitor switch Φ A0 , the second capacitor switch Φ re 、The third capacitor switch Φ S_BAR , the fourth capacitor switch Φ CS1 、The fifth capacitor switch Φ COM 、The sixth capacitor switch Φ A1 、The seventh capacitor switch Φ CS2 、The eighth capacitor switch Φ A2 、Ninth capacitor switch Φ CS3 、The tenth capacitor switch Φ CS4 、11th capacitor switch Φ A3 、12th capacitor switch Φ CS5, the first capacitor node V CK0 , the second capacitor node V CK1 , the third capacitor node V CK2 , the fourth capacitor node V CK3 , the fifth capacitor node V CK4 , the sixth capacitor node V CK5 and voltage conversion node V CM . The voltage conversion node V CM Used as a connection node for the reference common mode voltage signal. The first analog input connection terminal is used as the analog signal V BN / P The converter connection end is connected to the digital-to-analog converter 30, the comparator connection end is connected to the comparator 20, the amplification first connection end and the amplification second connection end are respectively connected to the positive input connection end and the negative output connection end of the capacitance degradation amplifier 10, or to the negative input connection end and the positive output connection end of the capacitance degradation amplifier 10. The first capacitance switch Φ A0 One end is connected to the second connection end of the amplifier, and the other end is connected to the fifth capacitor node V CK4 Connection. Second capacitor switch Φ re One end of the fifth capacitor node V CK4 The other end is connected to the voltage conversion node V CM Connection. The third capacitor switch Φ S_BAR One end of the fifth capacitor node V CK4 The fourth capacitor switch Φ CS1 One end is connected to the comparator connection end, and the other end is connected to the fourth capacitor node V CK3 Connection. The fifth capacitor switch Φ COM One end of the fourth capacitor node V CK3 The other end is connected to the third capacitor node V CK2 The sixth capacitor switch Φ A1 One end of the fourth capacitor node V CK3 The seventh capacitor switch Φ CS2 One end of the third capacitor node V CK2 The other end is connected to the voltage conversion node V CM The eighth capacitor switch Φ A2 One end of the third capacitor node V CK2 Connect the other end to the second capacitor node V CK1 Connection. Ninth capacitor switch Φ CS3 One end is connected to the converter connection end, and the other end is connected to the second capacitor node V CK1 Connection. Tenth capacitor switch Φ CS4 One end is connected to the voltage conversion node V CM The other end is connected to the first capacitor node V CK0Connection. Eleventh capacitor switch Φ A3 One end of the first capacitor node V CK0 The other end is connected to the analog input first connection end. CS5 One end of the third capacitor C is connected to the analog input first connection terminal, and the other end is connected to the amplification first connection terminal. ref One end of the first capacitor node V CK0 Connect the other end to the second capacitor node V CK1 Connect the fourth capacitor C s One end of the third capacitor node V CK2 The other end is connected to the fourth capacitor node V CK3 Connect the fifth capacitor C L One end of the voltage conversion node V CM Connect the other end to the fifth capacitor node V CK4 In one embodiment, the first switch capacitor circuit 40 and the second switch capacitor circuit 50 further include an analog input second connection terminal, a sixth capacitor C S_pre 、Thirteenth capacitor switch Φ S 、14th capacitor switch Φ S_pre 、15th capacitor switch Φ S_pre_BAR and the sixth capacitor node V CK5 The second analog input connection terminal is used as the analog first input signal V inp (like Figure 3 As shown, the analog input signal of the first switched capacitor circuit 40) or the analog second input signal V inn Input (such as Figure 3 As shown, the analog input signal of the second switched capacitor circuit 50). The sixth capacitor C S_pre One end of the voltage conversion node V CM The other end is connected to the sixth capacitor node V CK5 Connection. Thirteenth capacitor switch Φ S One end is connected to the comparator connection end, and the other end is connected to the sixth capacitor node V CK5 Connection. Fourteenth capacitor switch Φ S_pre One end of the sixth capacitor node V CK5 The other end is connected to the analog input second connection end. S_pre_BAR One end of the sixth capacitor node V CK5 The other end is connected to the voltage conversion node V CM connect.

[0029] In one embodiment, the first capacitor C DEG1 , the second capacitor C DEG2 , the third capacitor C ref , the fourth capacitor C s, the fifth capacitor C L and the sixth capacitor C S_pre The proportional relationship of the capacitance values ​​is a preset fixed value.

[0030] In one embodiment, if Figure 1 As shown, the digital-to-analog converter 30 also includes a second comparison connection terminal, and the second comparison connection terminal of the digital-to-analog converter 30 is connected to the comparator 20. The comparator 20 also includes a fourth connection terminal, and the fourth connection terminal of the comparator 20 is connected to the second comparison connection terminal of the digital-to-analog converter 30. The digital-to-analog converter 30 is used to convert the digital signal output by the comparator 20 into an analog signal, and the comparator 20 is used to convert the continuous analog signal into a 1.5-bit digital signal in each cycle. In one embodiment, the comparator 20 includes a first comparison circuit and a second comparison circuit. The first comparison circuit and the second comparison circuit respectively include a first input connection terminal, a second input connection terminal and a comparison output terminal. The first input connection terminal and the second input connection terminal of the first comparison circuit are respectively connected to the first switch capacitor circuit 40 and the second switch capacitor circuit 50, and the comparison output terminal of the first comparison circuit is connected to the first comparison connection terminal of the digital-to-analog converter 30. The first input connection terminal and the second input connection terminal of the second comparison circuit are respectively connected to the first switch capacitor circuit 40 and the second switch capacitor circuit 50, and the comparison output terminal of the second comparison circuit is connected to the second comparison connection terminal of the digital-to-analog converter 30.

[0031] In order to facilitate understanding of the embodiments of the present application, the capacitive degeneration amplifier is applied to the Cyclic ADC to replace the traditional closed-loop operational amplifier to realize the cyclic operation function, and the capacitive degeneration amplifier is improved to improve the performance of the ADC. The following describes in detail the implementation of the capacitive degeneration amplifier and the Cyclic ADC, including: Please refer to Figure 4 , is a circuit diagram of a capacitor degeneration amplifier, and Figure 2 Compared with the capacitor degeneration amplifier circuit in the figure, the degeneration switch S is not included. R , but is also connected to an external circuit (a first switched capacitor circuit 40 and a second switched capacitor circuit 50), wherein the capacitor C L1 , Capacitor switch Φ RE1 and voltage conversion node V cm13 is the fifth capacitor C of the first switched capacitor circuit 40 L , the second capacitor switch Φ re and voltage conversion node V CM , capacitor C L2 , Capacitor switch Φ RE2 and voltage conversion node V cm23 is the fifth capacitor C of the second switched capacitor circuit 50 L , the second capacitor switch Φ reand voltage conversion node V CM .

[0032] Please refer to Figure 5 , is a curve diagram of the linear amplification characteristics of the capacitor degeneration amplifier, where A opt is the linear magnification, t opt is the first capacitor switch Φ A0 The duration of linear amplification during conduction is based on the MOS tube subthreshold current formula and charge conservation, t opt The formula for obtaining is: ; For input signals of different sizes, there will be a linear amplification factor A opt =2C DEG / nC L ; Among them, the capacitor C DEG The first capacitor C DEG1 Or the second capacitor C DEG2 Capacitance value, C L The fifth capacitor C L The value of .

[0033] like Figure 5 The linear amplification characteristics shown can meet the multiplication requirements in Cyclic ADC. In the simulation of the ADC working cycle, it is observed that the output curve of the capacitor degeneration amplifier has a short and fast charging process in the initial stage.

[0034] Please refer to Figure 6 , is a schematic diagram of the effect of the drain parasitic capacitance of the capacitor-degenerate amplifier on the output signal, where the capacitance C D1 This phenomenon is caused by the parasitic capacitance C of the MOS tube drain. D1 The charge stored on the capacitor causes the first capacitor switch Φ to A0 At the end of conduction, the switch between the transistor, power supply and load is disconnected, and the drain voltage remains at the value at the end of the previous amplification cycle. When the switch is closed in the next cycle, the parasitic capacitance C D1 The charge stored on the capacitor is first released to the fifth capacitor C as the load capacitor. L This destroys the charge conservation in the amplification stage.

[0035] Please refer to Figure 7 and Figure 8 , which is a schematic diagram of input voltage compression circuit implementation and input voltage value compression. Figure 3The analog-to-digital conversion circuit shown performs comparison, multiplication by 2, and addition or subtraction of a reference voltage on the signal to determine one bit of output in each cycle. The proposed ADC uses two comparators and implements a 1.5-bit per cycle algorithm, which significantly reduces the requirements for comparator accuracy. The differential push-pull capacitor degeneration amplifier has a total of four input terminals, and for simplicity, only one representative input terminal on each differential side is shown. The capacitor degeneration amplifier is connected to the fifth capacitor C before the output signal is fully settled. L disconnected, thereby obtaining a linearly amplified output signal which is stored in the fifth capacitor C L The charge on the capacitor is represented by the charge on the capacitor, which is not driven by a stable voltage. Therefore, in order to perform subsequent signal processing and feed the signal back to the input end of the next cycle, charge transfer and sharing between different capacitors is required. In one embodiment, the amplifier first amplifies the signal by 4 times, and then switches the fifth capacitor C L With the same size of the fourth capacitor C s They are connected in parallel to realize charge sharing, and finally generate a signal twice the size of the original signal as the input of the next cycle. Figure 2 As shown, the positive input connection terminal, the negative input connection terminal, the positive output connection terminal and the negative output connection terminal of the capacitance degeneration amplifier 10 are respectively input with V BP +V in_duff / 2 、V BN +V in_duff / 2 、V BP +V in_duff / 2 and V BN +V in_duff / 2 , plus or minus V ref The traditional adder relies on a stable voltage drive, which is not suitable for charge mode signals. Considering the additional number of switches and timing complexity caused by adding charge sharing, the present invention adopts a series capacitor structure to achieve the addition of voltage signals. In the comparison stage, the addition and subtraction of V ref The charge is stored in the capacitor C ref On, and through the capacitor C ref and capacitor C s The series connection realizes voltage addition.

[0036] The input range of the capacitor-degraded amplifier is limited by the subthreshold working condition, so the input voltage needs to be scaled to match the input range of the amplifier. In one embodiment of the present application, charge sharing technology is used to achieve this. Figure 7 As shown, in the pre-sampling stage, the input voltage is first sampled to the capacitor C S_pre Then through the parallel capacitor C s Charge sharing is performed to reduce the input voltage to one fifth of the original value, thus achieving an input voltage range of ±3V. In one ADC cycle, in addition to the first capacitor CDEG1 Or the second capacitor C DEG2 Except for the charging stage, all circuit operations are completed through charge transfer and sharing, thus achieving zero static power consumption.

[0037] Please refer to Fig. 9 , is a timing diagram of a cyclic approximation analog-to-digital converter in an embodiment, in which the capacitor switch Φ S_pre (Pre-sampling) stage, the input signal is sampled and stored in the pre-sampling capacitor C S_pre Capacitor switch Φ S is the sampling phase. During this phase, the capacitor C S_pre Through the switch and capacitor C S The capacitor switch Φ A stage (including capacitor switch Φ A0 , Capacitor switch Φ A1 , Capacitor switch Φ A2 and capacitor switch Φ A3 ) is the amplification stage, capacitor C ref and capacitor C s The series connection, capacitor C ref The lower plate of the capacitor is connected to the bias voltage, which transfers the input signal to the bias voltage baseline. The internal transistor of the capacitor degeneration amplifier is turned on, and the circuit works in the amplification state. com In the compare stage, the output of the amplifier is fed into the comparator to generate a 1.5-bit result. At the same time, this stage also clears the capacitor C s The charge on the capacitor switch Φ CS (Including capacitor switch Φ CS1 , Capacitor switch Φ CS2 , Capacitor switch Φ CS3 , Capacitor switch Φ CS4 and capacitor switch Φ CS5 ) During the charge sharing phase, the capacitor C L The charge on the capacitor is transferred to the capacitor C through switch sharing. S , and the capacitor C ref Connect to the output of the DAC to store ±V ref Or 0V voltage signal. Capacitor switch Φ re is what happens when the capacitor switches Φ CS and capacitor switch Φ A The reset phase between the capacitor switches Φ re phase, stored in the floating capacitor C LThe charge on the ADC is cleared to prepare for the next amplification cycle. In the embodiment of the present application, the timing stage ensures that the Cyclic ADC can accurately convert the analog signal into a digital signal, and uses the charge sharing mechanism and accurate timing control to maintain low power consumption and high linearity.

[0038] In one embodiment of the present application, an analog-to-digital conversion method is also disclosed, which is applied to the analog-to-digital conversion circuit as described above. The analog-to-digital conversion method includes: when the capacitor degeneration amplifier works in the amplification stage, the degeneration switch S R When the capacitor degradation amplifier is operating in the off phase, the degradation switch S R Closed conduction.

[0039] In one embodiment of the present application, a chip is also disclosed, including the analog-to-digital conversion circuit as described above.

[0040] An electronic device is also disclosed in an embodiment of the present application, including the chip as described above.

[0041] The analog-to-digital conversion circuit disclosed in the embodiment of the present application is used as a cyclic approximation analog-to-digital converter, including a capacitor degeneration amplifier, a digital-to-analog converter, a comparator, a first switch capacitor circuit and a second switch capacitor circuit. The digital-to-analog converter is connected to the comparator, the first switch capacitor circuit and the second switch capacitor circuit respectively. The comparator is connected to the first and second switch capacitor circuits respectively. The capacitor degeneration amplifier is connected to the first and second switch capacitor circuits respectively. The cyclic approximation analog-to-digital converter is realized based on the open-loop capacitor degeneration amplifier, and low-power technologies such as charge sharing are applied to greatly reduce the power consumption of the cyclic approximation analog-to-digital converter under the premise of ensuring high linearity.

[0042] The above specific examples are used to illustrate the present invention, which is only used to help understand the present invention and is not intended to limit the present invention. For those skilled in the art, according to the concept of the present invention, some simple deductions, modifications or substitutions can be made.

Claims

1. An analog-to-digital conversion circuit, characterized in that: Used as a cyclic approximation analog-to-digital converter, comprising a capacitive degeneration amplifier, a digital-to-analog converter, a comparator, a first switched capacitor circuit and a second switched capacitor circuit; The digital-to-analog converter comprises a first conversion connection terminal, a second conversion connection terminal, a first comparison connection terminal, a first switch control connection terminal and a second switch control connection terminal; the first conversion connection terminal and the second conversion connection terminal of the digital-to-analog converter are used as input and output connection terminals of the analog-to-digital conversion circuit, respectively for a preset first reference voltage V refp and the second reference voltage V refn The first comparison connection terminal of the digital-to-analog converter is connected to the comparator; the first switch control connection terminal and the second switch control connection terminal of the digital-to-analog converter are respectively connected to the first switch capacitor circuit and the second switch capacitor circuit; The comparator comprises a first connection terminal, a second connection terminal and a third connection terminal; the first connection terminal and the second connection terminal of the comparator are respectively connected to the first switch capacitor circuit and the second switch capacitor circuit; the third connection terminal of the comparator is connected to the first comparison connection terminal of the digital-to-analog converter; The capacitance degeneration amplifier comprises a positive input connection terminal, a negative input connection terminal, a positive output connection terminal and a negative output connection terminal; the positive input connection terminal and the negative output connection terminal of the capacitance degeneration amplifier are connected to the first switching capacitor circuit, and the negative input connection terminal and the positive output connection terminal of the capacitance degeneration amplifier are connected to the second switching capacitor circuit.

2. The analog-to-digital conversion circuit according to claim 1, characterized in that: The capacitive degeneration amplifier comprises a first switch Φ CS11 , the second switch Φ CS21 、The third switch Φ A11 、The fourth switch Φ A21 、The fifth switch Φ A12 、The sixth switch Φ A21 、Seventh switch Φ CS12 、The eighth switch Φ CS22 , the first capacitor C DEG1 , the second capacitor C DEG2 , the first transistor M A11 , the second transistor M A21 , the third transistor M A12 , the fourth transistor M A22 , the first node V SP11 , the second node V SP21 、The third node V SP12 , the fourth node V SP22 and degraded switch S R ; The first transistor M A11 and the third transistor M A12 The control electrode of is used as the positive input connection terminal of the capacitance degradation amplifier; the second transistor M A21 and the fourth transistor M A22 The control electrode of is used as the negative input connection terminal of the capacitance degeneration amplifier, and the degeneration switch S R The two ends of are respectively used as the positive output connection terminal and the negative output connection terminal of the capacitive degeneration amplifier; The first transistor M A11 The second electrode of the third transistor M A12 The second electrode of the second transistor M is connected A21 The second electrode of the fourth transistor M A22 The second pole connection; The first switch Φ CS11 One end is used for working power supply V DD The other end is connected to the first node V SP11 Connection; the second switch Φ CS21 One end is used for the working voltage V DD The other end is connected to the second node V SP21 The third switch Φ A11 One end and the first node V SP11 The other end is connected to the first transistor M A11 The first pole of the fourth switch Φ A21 One end and the second node V SP21 The other end is connected to the second transistor M A21 The first pole connection; The fifth switch Φ A12 One end of the third transistor M A12 The first electrode is connected to the third node V SP12 The sixth switch Φ A21 One end of the fourth transistor M A22 The first electrode is connected to the fourth node V SP22 The seventh switch Φ CS12 One end and the third node V SP12 The other end is connected to the ground; the eighth switch Φ CS22 One end of the fourth node V SP22 Connect, and ground the other end; The first capacitor C DEG1 One end and the second node V SP21 Connect the other end to the third node V SP12 Connection: The second capacitor C DEG2 One end and the first node V SP11 The other end is connected to the fourth node V SP22 connect; The degradation switch S R One end of the first transistor M A11 The second electrode is connected to the second transistor M A21 The second pole connection.

3. The analog-to-digital conversion circuit according to claim 2, characterized in that: The first switch capacitor circuit and the second switch capacitor circuit respectively include an analog input first connection terminal, a converter connection terminal, a comparator connection terminal, an amplification first connection terminal, an amplification second connection terminal, a third capacitor C ref , the fourth capacitor C s , the fifth capacitor C L , the first capacitor switch Φ A0 , the second capacitor switch Φ re 、The third capacitor switch Φ S_BAR , the fourth capacitor switch Φ CS1 、The fifth capacitor switch Φ COM 、The sixth capacitor switch Φ A1 、The seventh capacitor switch Φ CS2 、The eighth capacitor switch Φ A2 、Ninth capacitor switch Φ CS3 、The tenth capacitor switch Φ CS4 、11th capacitor switch Φ A3 、12th capacitor switch Φ CS5 , the first capacitor node V CK0 , the second capacitor node V CK1 , the third capacitor node V CK2 , the fourth capacitor node V CK3 , the fifth capacitor node V CK4 , the sixth capacitor node V CK5 and voltage conversion node V CM ; The voltage conversion node V CM A connection node for a reference common-mode voltage signal; The analog input first connection terminal is used as an analog signal V BN / P Input; The converter connection end is connected to the digital-to-analog converter; The comparator connection terminal is connected to the comparator; The first amplifying connection terminal and the second amplifying connection terminal are respectively connected to the positive input connection terminal and the negative output connection terminal of the capacitance degeneration amplifier, or to the negative input connection terminal and the positive output connection terminal of the capacitance degeneration amplifier; The first capacitive switch Φ A0 One end is connected to the amplified second connection end, and the other end is connected to the fifth capacitor node V CK4 Connection; the second capacitor switch Φ re One end of the fifth capacitor node V CK4 connected, and the other end connected to the voltage conversion node V CM The third capacitor switch Φ S_BAR One end of the fifth capacitor node V CK4 The fourth capacitor switch Φ CS1 One end is connected to the comparator connection end, and the other end is connected to the fourth capacitor node V CK3 The fifth capacitor switch Φ COM One end of the fourth capacitor node V CK3 The other end is connected to the third capacitor node V CK2 The sixth capacitor switch Φ A1 One end of the fourth capacitor node V CK3 The seventh capacitor switch Φ CS2 One end of the third capacitor node V CK2 connected, and the other end connected to the voltage conversion node V CM The eighth capacitor switch Φ A2 One end of the third capacitor node V CK2 Connect the other end to the second capacitor node V CK1 The ninth capacitor switch Φ CS3 One end is connected to the converter connection end, and the other end is connected to the second capacitor node V CK1 The tenth capacitor switch Φ CS4 One end of the voltage conversion node V CM connect the other end to the first capacitor node V CK0 The eleventh capacitor switch Φ A3 One end of the first capacitor node V CK0 The twelfth capacitor switch Φ CS5 One end of the analog input first connection end is connected to the analog input first connection end, and the other end of the analog input first connection end is connected to the amplification first connection end; The third capacitor C ref One end of the first capacitor node V CK0 Connect the other end to the second capacitor node V CK1 Connect; the fourth capacitor C s One end of the third capacitor node V CK2 The other end is connected to the fourth capacitor node V CK3 Connect; the fifth capacitor C L One end of the voltage conversion node V CM The other end is connected to the fifth capacitor node V CK4 connect.

4. The analog-to-digital conversion circuit according to claim 3, characterized in that: The first switched capacitor circuit and the second switched capacitor circuit respectively further include an analog input second connection terminal, a sixth capacitor C S_pre 、Thirteenth capacitor switch Φ S 、14th capacitor switch Φ S_pre 、15th capacitor switch Φ S_pre_BAR and the sixth capacitor node V CK5 ; The analog input second connection terminal is used as a first analog input signal V inp Or simulate the second input signal V inn Input; The sixth capacitor C S_pre One end of the voltage conversion node V CM The other end is connected to the sixth capacitor node V CK5 connect; The thirteenth capacitor switch Φ S One end is connected to the comparator connection end, and the other end is connected to the sixth capacitor node V CK5 connect; The fourteenth capacitance switch Φ S_pre One end of the sixth capacitor node V CK5 connected, and the other end is connected to the analog input second connection end; The fifteenth capacitor switch Φ S_pre_BAR One end of the sixth capacitor node V CK5 connected, and the other end connected to the voltage conversion node V CM connect.

5. The analog-to-digital conversion circuit according to claim 4, characterized in that: The first capacitor C DEG1 The second capacitor C DEG2 , the third capacitor C ref , the fourth capacitor C s , the fifth capacitor C L and the sixth capacitor C S_pre The proportional relationship of the capacitance values ​​is a preset fixed value.

6. The analog-to-digital conversion circuit according to claim 1, characterized in that: The digital-to-analog converter further comprises a second comparison connection terminal, and the second comparison connection terminal of the digital-to-analog converter is connected to the comparator; The comparator further comprises a fourth connection terminal, and the fourth connection terminal of the comparator is connected to the second comparison connection terminal of the digital-to-analog converter.

7. The analog-to-digital conversion circuit according to claim 6, characterized in that: The comparator comprises a first comparison circuit and a second comparison circuit; The first comparison circuit and the second comparison circuit respectively include a first input connection terminal, a second input connection terminal and a comparison output terminal; A first input connection terminal and a second input connection terminal of the first comparison circuit are connected to the first switched capacitor circuit and the second switched capacitor circuit respectively, and a comparison output terminal of the first comparison circuit is connected to a first comparison connection terminal of the digital-to-analog converter; The first input connection terminal and the second input connection terminal of the second comparison circuit are connected to the first switched capacitor circuit and the second switched capacitor circuit respectively, and the comparison output terminal of the second comparison circuit is connected to the second comparison connection terminal of the digital-to-analog converter.

8. An analog-to-digital conversion method, characterized in that: Applied to the analog-to-digital conversion circuit according to any one of claims 2 to 7, the method comprises: When the capacitor degeneration amplifier works in the amplification stage, the degeneration switch S R When the capacitor degradation amplifier is operating in the off phase, the degradation switch S R Closed conduction.

9. A chip, characterized in that: The method comprises the analog-to-digital conversion circuit as claimed in any one of claims 1 to 7.

10. An electronic device, characterized in that: Comprising the chip as claimed in claim 9.

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