ADC signal processing method and device, electronic equipment and medium

Abstract

The invention provides an ADC signal processing method and device, electronic equipment and a medium, and effectively solves the problem that an existing ADC acquisition platform cannot meet the requirements of industrial production and scientific research due to the fact that the existing ADC acquisition platform does not have a digital signal processing algorithm. The method comprises the following steps: acquiring corresponding ADC signals based on a plurality of acquisition modes set by the ADC platform, and screening out a target ADC signal from the ADC signals; judging a target processing type of the target ADC signal, and calling a target processing mode corresponding to the target processing type; processing the target ADC signal through the target processing mode to search a target data point; and converting the ADC signal based on the target data point to obtain ADC data, and uploading the ADC data to an application layer module in the ADC platform to complete processing of the ADC signal.

Description

Technical Field

[0001] The present application relates to the field of signal processing technology, and in particular to an ADC signal processing method, device, electronic device and medium. Background Art

[0002] With the rapid development of the electronic information field, digital signal processing is becoming increasingly important in the field of modern electronic design and signal processing. Analog-to-digital converters (ADCs) are key components for digital signal processing, and their demand has increased significantly in the fields of communications, medical treatment, visual processing, military industry, and electrical automation, and the scale of growth is expanding. FPGA has obvious advantages in the field of data parallel processing, and it also has the characteristics of flexibility and high-speed processing, so it has become an important choice for high-speed AD acquisition and digital signal processing platforms.

[0003] The basic ADC acquisition platform requires functions such as system clock management, chip configuration, interface driver, and data flow control management. Nowadays, the high-speed ADC acquisition process faces the risk of noise and interference introduced by the circuit; at the same time, it also faces the risk of signal distortion caused by data loss during high-speed transmission due to excessive data rate; and in industrial applications, it also faces the risk of increasingly stringent synchronization trigger conditions. The ADC acquisition platform simply plays the role of drive control, which is obviously not enough to meet the needs of industrial production and scientific research. In order to cope with the above risks and maximize the high concurrency characteristics of FPGA, it is particularly important to add digital signal processing algorithms to the ADC acquisition platform to form a fully functional integrated signal acquisition and processing platform in the current signal acquisition field. Summary of the invention

[0004] In view of this, the purpose of the present application is to provide an ADC signal processing method, device, electronic device and medium, which effectively solves the problem that the existing ADC acquisition platform does not have a digital signal processing algorithm, resulting in the ADC acquisition platform being unable to meet the needs of industrial production and scientific research.

[0005] In a first aspect, an embodiment of the present application provides an ADC signal processing method, which is applied to an ADC platform. The method includes: The corresponding ADC signals are collected based on the multiple collection modes set by the ADC platform, and the target ADC signals are screened out from the ADC signals; the ADC signals are signals collected by the ADC chip; the ADC platform is built based on FPGA technology; Matching the target ADC signal with the processing module type of the ADC platform to determine the target processing type of the target ADC signal, and calling the target processing method corresponding to the target processing type; different processing types correspond to different processing methods; Processing the target ADC signal by the target processing method to search for a target data point based on the phase of the processed target ADC signal; The ADC signal is converted based on the target data point to obtain ADC data, and the ADC data is uploaded to the application layer module in the ADC platform to complete the processing of the ADC signal.

[0006] In combination with the first aspect, an embodiment of the present application provides a first possible implementation manner of the first aspect, wherein determining the target processing type of the target ADC signal includes: Determine whether the target ADC signal meets the processing conditions preset by the ADC platform based on multiple dimensions, and generate a corresponding determination result; The judgment results of multiple dimensions are integrated to select a target processing type of the target ADC signal from a plurality of processing types preset by the ADC platform. In combination with the first aspect, the embodiment of the present application provides a second possible implementation of the first aspect, wherein the fusion of the judgment results of multiple dimensions to select the target processing type of the target ADC signal from the multiple processing types preset by the ADC platform includes: Determine the processing module type of the ADC platform corresponding to the target ADC signal based on the fusion result generated by the judgment results of the multiple dimensions; According to the mapping relationship between the processing module type of the ADC platform and the processing type of the target ADC signal, the processing type corresponding to the target ADC signal is screened out.

[0007] In combination with the first aspect, an embodiment of the present application provides a third possible implementation of the first aspect, wherein converting the ADC signal based on the target data point to obtain ADC data includes: reordering the target ADC signal based on the target data point, and shifting the bit width of the reordered target ADC signal to the target bit width; A data frame header is added to the reordered target ADC signal at the target bit width to obtain ADC data corresponding to the target ADC signal.

[0008] In combination with the first aspect, the embodiment of the present application provides a fourth possible implementation manner of the first aspect, wherein the reordering of the target ADC signal based on the target data point includes: Determine the position of the target data point according to a preset mapping relationship between the target data point and the target ADC signal; Based on the location of the target data point, the ordering manner of the data stream in the target ADC signal is adjusted.

[0009] In combination with the first aspect, the embodiment of the present application provides a fifth possible implementation of the first aspect, wherein uploading the ADC data to the application layer module in the ADC platform includes: Determining a target interface type based on the ADC data and an interface type of the ADC platform; An uploading method for uploading the ADC data is determined based on the target interface type, and the uploading method is called to upload the ADC data to the application layer module.

[0010] In combination with the first aspect, the embodiment of the present application provides a sixth possible implementation of the first aspect, wherein the dimension at least includes a filtering dimension; The filtering out the processing type corresponding to the target ADC signal includes: Based on the target ADC signal, the target ADC signal is matched with a plurality of filtering modes to obtain a matching result; A target filtering mode for the target ADC signal is determined according to the matching result, and the target filtering mode is called.

[0011] In a second aspect, an embodiment of the present application provides an ADC signal processing device, which is applied to an ADC platform, and the device includes: An acquisition module, used for acquiring corresponding ADC signals based on multiple acquisition modes set by the ADC platform, and filtering out target ADC signals from the ADC signals; the ADC signals are signals acquired by the ADC chip; the ADC platform is built based on FPGA technology; A matching module, used for matching the target ADC signal with the processing module type of the ADC platform to determine the target processing type of the target ADC signal and call the target processing method corresponding to the target processing type; different processing types correspond to different processing methods; A processing module, configured to process the target ADC signal by the target processing method, so as to search for a target data point based on a phase of the processed target ADC signal; An uploading module is used to convert the ADC signal based on the target data point to obtain ADC data, and upload the ADC data to the application layer module in the ADC platform to complete the processing of the ADC signal.

[0012] In a third aspect, an embodiment of the present application provides an electronic device, comprising: a processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor communicates with the memory through the bus, and when the machine-readable instructions are executed by the processor, the steps of any one of the ADC signal processing methods are performed.

[0013] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the ADC signal processing methods are executed.

[0014] An ADC signal processing method provided in an embodiment of the present application is applied to an ADC platform. The method first collects corresponding ADC signals based on multiple acquisition modes set by the ADC platform, and filters out a target ADC signal from the ADC signal; the ADC signal is a signal collected by an ADC chip; the ADC platform is built based on FPGA technology; secondly, the target ADC signal is matched with the processing module type of the ADC platform to determine the target processing type of the target ADC signal, and call the target processing method corresponding to the target processing type; different processing types correspond to different processing methods; then the target ADC signal is processed by the target processing method to search for a target data point based on the phase of the processed target ADC signal; finally, the target ADC signal is processed based on the target The ADC signal is converted into ADC data by the marked data points, and the ADC data is uploaded to the application layer module in the ADC platform to complete the processing of the ADC signal. That is, the present application realizes the effect of processing the ADC signal based on the ADC platform, improves the richness of the functions of the ADC acquisition platform, realizes the processing of the ADC signal by calling the corresponding processing method, and also realizes the compensation of the ADC signal. It also ensures the effect of accurate triggering of the synchronous trigger condition based on the trigger signal, and maximizes the high concurrency characteristics of FPGA, and integrates driving, signal processing, data transmission and bus management, thereby forming a fully functional signal acquisition and processing integrated platform with strong compatibility, very good reusability and portability, and meets the needs of industrial production and scientific research. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0016] Figure 1 A schematic flow chart of a first ADC signal processing method provided in an embodiment of the present application is shown; Figure 2 A schematic diagram of the structure of the ADC platform constructed in the embodiment of the present application is shown; Figure 3 A schematic diagram of a process for obtaining an ADC signal provided in an embodiment of the present application is shown; Figure 4 A structural block diagram of a first ADC signal processing device provided in an embodiment of the present application is shown; Figure 5 A structural block diagram of a first electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0017] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of explanation and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn in real proportion. The flowchart used in this application shows the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowchart can be implemented out of sequence, and the steps without logical context can be reversed in order or implemented simultaneously. In addition, those skilled in the art can add one or more other operations to the flowchart under the guidance of the content of the present application, or remove one or more operations from the flowchart.

[0018] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0019] It should be noted that the term "comprising" will be used in the embodiments of the present application to indicate the existence of the features declared thereafter, but does not exclude the addition of other features.

[0020] The current ADC acquisition platform faces the risk of noise and interference introduced by the circuit during high-speed ADC acquisition. At the same time, it also faces the risk of signal distortion caused by data loss during high-speed transmission due to excessive data rate. In industrial applications, it also faces the risk of increasingly stringent synchronization trigger conditions. The ADC acquisition platform simply plays the role of drive control, which is obviously not enough to meet the needs of industrial production and scientific research.

[0021] Based on this, the embodiments of the present application provide an ADC signal processing method, device, electronic device and medium, which are described below through embodiments.

[0022] Example 1 To facilitate understanding of this embodiment, firstly, an ADC signal processing method disclosed in the embodiment of this application is described in detail. Figure 1 The flowchart of an ADC signal processing method shown in the figure, an ADC signal processing method provided by the present application is applied to an ADC platform, and the method includes: S101, collecting corresponding ADC signals based on multiple collection modes set by the ADC platform, and filtering out target ADC signals from the ADC signals; the ADC signals are signals collected by the ADC chip; the ADC platform is built based on FPGA technology; S102, matching the target ADC signal with the processing module type of the ADC platform to determine the target processing type of the target ADC signal, and calling the target processing method corresponding to the target processing type; different processing types correspond to different processing methods; S103, processing the target ADC signal by the target processing method, so as to search for a target data point based on the phase of the processed target ADC signal; S104: Convert the ADC signal based on the target data point to obtain ADC data, and upload the ADC data to the application layer module in the ADC platform to complete the processing of the ADC signal.

[0023] In step S101, the ADC platform is built based on FPGA technology, that is, it is an ADC platform built based on FPGA technology to realize data acquisition and processing. Figure 2As shown, HOST is a terminal, the ADC platform includes an ADC chip, and the ADC signal is a signal collected by the ADC chip. The specific model of the ADC chip is not limited here, but the ADC chip used can achieve high-speed collection. The specific model of the ADC chip is determined based on collection requirements, ADC performance indicators, target signal types, characteristics, etc., and the ADC platform of the present application also builds an interface drive control function for ADC chips commonly used in the market, wherein the interface mode is determined by the ADC chip, different ADC chips have different interface types, and different ADC interface types have different operating requirements when driving the chip, in order to maximize the performance of the ADC chip, based on the acquisition mode in the ADC chip The ADC signal is collected in a digital mode. The collection mode is represented by different classification types. When the classification type is a channel type, it includes a single-channel collection mode and a multi-channel collection mode, wherein the number of channels in the multi-channel collection mode can be 2^n; when the classification type is a number type, it includes a single-time collection mode, a multiple-time collection mode, and a streaming collection mode. According to different collection modes, the address continuous cache mode and the ping-pong read-write cache mode are respectively adopted to ensure the integrity of data transmission. After the collection is completed, the ADC signal is already in a digital state. At this time, the ADC signal in the digital state can also be displayed to the user. The code value displayed to the user is quantized. Quantization is a necessary process for converting the ADC signal from the analog state to the digital state. After obtaining the ADC signal, the ADC signal in the target state is also output to the constructed processing module, and the target ADC signal is screened out from the ADC signal. The target ADC signal is the one that needs to be processed. Not all ADC signals need to be processed, so it is necessary to screen out the target ADC signal to be processed for the next step of processing.

[0024] In order to achieve high-speed acquisition, the present application also builds a driving module for the ADC platform, which includes an ADC driving module, a clock system driving module and an AFE (analog front end) circuit driving module, wherein the ADC driving module and the clock system driving module include a common chip control bus timing unit for generating the bus driving timing required for the chip configuration. In addition, it is necessary to build respective chip register management units for the ADC driving module and the clock system driving module respectively, which are used to control the working modes of all chips in the system including the ADC chip and the clock chip, so as to drive the acquisition platform to realize the most basic data acquisition function, wherein the chip register management unit is configured through a program, and after the program is solidified, it will start with a preset function each time the ADC platform is powered on; the AFE circuit driving module has multiple control units, including a bias circuit control unit, a gain attenuation circuit control unit and a data branch selection unit, which are used to drive and control the operation of the analog circuit.

[0025] The present application also selects an interface control mode compatible with the ADC chip from the interface control modes corresponding to the constructed interface control module according to the model of the ADC chip. The interface control module includes an LVDS interface control unit or a JESD204 interface control unit. The LVDS interface control unit implements LVDS interface timing control, supports SDR, DDR, and QDR timing restoration, and completes LVDS signal alignment training to ensure the accuracy of interface data; the JESD204 interface control unit includes a JESD204 receiver, a transmitter, and a Serdes physical layer control, which meet the JEDEC STANDARD standard communication protocol. According to the standard communication protocol, it shakes hands with the other end in stages and verifies the correctness of the data. If all processes are correct, a connection is established to achieve interface link establishment, data verification, and data transmission; in addition, the interface control module also includes a data deframing unit, which is used to complete interface data deframing according to specific rules, and deframe and restore the data from the transmission protocol format to the user format.

[0026] In step S102, after the target ADC signal is screened out, the target ADC signal is matched with the processing module type of the ADC platform. If matched, the processing module of the ADC platform needs to process the target ADC signal, and the processing type of the target ADC signal is judged based on the processing module type of the ADC platform to obtain a judgment result, that is, since the acquisition environments of different target ADC signals are different, the noise or interference to which the target ADC signal is subjected is different, so the processing types required for different target ADC signals are different, and different processing types correspond to different processing methods, so it is necessary to confirm the processing type of the target ADC signal, thereby determining the processing method for the target ADC signal, and calling the processing method corresponding to the processing module type of the ADC platform to achieve targeted processing of the target ADC signal, thereby ensuring the accuracy of processing the target ADC signal. After calling the corresponding processing method, the target ADC signal is processed by the corresponding processing method, that is, if the processing type is filtering, the target filtering method is selected in the filtering dimension to filter the target ADC signal, and when the filtered target ADC signal is obtained, the processed target ADC signal is obtained. If the target ADC signal satisfies the above four dimensions, the target ADC signal is transmitted to the processing method corresponding to each dimension in turn for processing. After the processing of the above four dimensions is completed, the target ADC signal is processed in the next step.

[0027] In the specific implementation process of step S102, there is an embodiment: Figure 3 As shown, determining the target processing type of the target ADC signal includes: S1021, judging whether the target ADC signal meets the processing conditions preset by the ADC platform based on multiple dimensions, and generating a corresponding judgment result; S1022. Integrate the judgment results of multiple dimensions to select a target processing type for the target ADC signal from a plurality of processing types preset by the ADC platform. In steps S1021-S1022, when the processing type of the ADC signal of the target state is judged, it is not judged from a single dimension, but from multiple dimensions, that is, the processing module type of the ADC platform also corresponds to the dimension, and has multiple dimensions, so as to ensure the accuracy of the judgment of the target ADC signal. The dimensions include test data generation dimension, digital gain and offset dimension, filtering dimension and sampling point sliding dimension. The above four dimensions are judged in turn. If they match the corresponding processing module type, the corresponding dimension is processed, otherwise the processing of this processing module is skipped and the next processing module type is matched directly, and each dimension The corresponding preset processing conditions are set, and the specific preset processing conditions can be set according to the actual situation. For example, the preset processing condition of the filtering dimension is whether the target ADC signal has interference. If it meets the requirements, the corresponding judgment result is yes, and if it does not meet the requirements, the corresponding judgment result is no. The preset processing condition corresponding to the sampling point sliding dimension can be to confirm whether the size of the sliding window is appropriate, which can smooth the signal without introducing too much delay. It can also check whether the sliding algorithm used (such as mean filtering, median filtering, etc.) is suitable for the current signal characteristics, and the signal waveform after sliding processing can also be observed to evaluate whether the signal becomes smoother and has no obvious mutation points. After the target ADC signal is judged in the above dimensions in turn, four judgment results are obtained. In order to determine the final processing type, the judgment results corresponding to multiple dimensions are fused to obtain a fusion result. The specific fusion method can be determined according to the actual situation. Here, the dimension with the judgment result of yes is set as the processing type of the target ADC signal. At this time, the ADC signal of the target state is the target ADC signal, so that the target ADC signal is processed accordingly.

[0028] In the specific implementation process of step S1022, there is an embodiment in which: the fusion of the judgment results of multiple dimensions to confirm the target ADC signal and the processing type of the target ADC signal includes: S10221. Determine, based on a fusion result generated by the judgment results of the multiple dimensions, a processing module type of the ADC platform corresponding to the target ADC signal; S10222. Filter out a processing type corresponding to the target ADC signal according to a mapping relationship between a processing module type of the ADC platform and a processing type of the target ADC signal.

[0029] In steps S10221-S10222, after obtaining the judgment result corresponding to each dimension, the judgment result is processed again, that is, the judgment result corresponding to each dimension is merged. If the judgment result corresponding to each dimension is no, it indicates that the target ADC signal does not need to be processed, and the target ADC signal can be directly processed in the next step and the link of the processing module of the ADC platform processing the target ADC signal is skipped. If it is determined that the judgment result corresponding to at least one dimension is yes, it indicates that the target ADC signal needs to be processed, and according to the dimension with the judgment result of yes, according to the mapping relationship between the processing module type of the ADC platform and the processing type of the target ADC signal, that is, each dimension corresponds to a processing type of the target ADC signal, and the processing type of the target ADC signal is the matching processing module type of the ADC platform, so that the processing type corresponding to the target ADC signal is screened out based on the processing module type of the ADC platform, so as to determine the processing type required for the target ADC signal, that is, for which dimension the judgment result corresponds to is yes, the target ADC signal is processed in the corresponding dimension, and the processing corresponding to the above four dimensions is performed in sequence.

[0030] In the specific implementation process of step S10222, there is an embodiment in which: the dimension at least includes a filtering dimension; The filtering out the processing type corresponding to the target ADC signal includes: S102221. Match the target ADC signal with a plurality of filtering methods respectively to obtain a matching result; S102222. Determine a target filtering method for the target ADC signal based on the matching result, and call the target filtering method.

[0031] In steps S102221-S102222, the filtering dimension is realized based on a filtering unit set in the processing module of the ADC platform. The filtering unit has a built-in digital filter and supports switching of multiple filter types, including a low-pass filter, a high-pass filter or a band-pass filter. The target ADC signal can be low-pass filtered, high-pass filtered or band-pass filtered. Based on the target ADC signal, it is matched with multiple filtering methods respectively to obtain corresponding matching results, that is, if the noise or interference in the target ADC signal is high-frequency, the matching result is low-pass filtering, and the low-pass filter is selected as the target filtering method. The low-pass filter is selected to perform low-pass filtering on the target ADC signal, and the user can also choose not to use the digital filtering module and select the bypass filtering module to perform corresponding filtering processing on the target ADC signal.

[0032] The test data generation dimension is realized based on the test data generation dimension unit set in the processing module. The test data generation dimension unit is the front-end designed digital signal generation unit with standard signal characteristics. It can realize the functional module of outputting standard digital signals by bypassing the ADC acquisition signal data path. In layman's terms, the digital signal generation unit does not output the ADC acquisition signal to the back end, or discards the ADC acquisition signal, and then outputs a standard ADC acquisition signal to the back end, which is used to verify the correctness of the platform function in a certain scenario. The test data generation unit is placed at the front end of the digital signal input and can be output after signal processing; the digital gain and offset dimensions are based on the digital signal generation unit set in the processing module. The digital gain and offset adjustment unit is implemented, and the digital gain and offset adjustment unit is a functional unit for performing gain, attenuation and offset adjustment on the collected target ADC signal in the digital domain, wherein the offset is the movement of the digital threshold signal up and down in the time domain, and the gain is the amplification and reduction of the signal. In conjunction with the offset adjustment of the analog circuit, the error calibration of the target ADC signal offset is performed in the digital domain. In addition, through digital gain and attenuation control, the function of amplifying and reducing the digital domain quantization value of the target ADC signal is provided; and the sampling point sliding dimension is implemented based on the sampling point sliding unit set in the processing module, and the sampling point sliding unit is used to process the discontinuity or mutation point in the target ADC signal to improve the smoothness of the target ADC signal. In step S103, after the processing module based on the ADC platform processes the target ADC signal, the target ADC signal is output to the data processing module and the trigger module built in the ADC platform. The trigger module generates a trigger signal based on the processed target ADC signal. The trigger module generates a trigger event according to the working mode set by the ADC platform and the requirements, and provides a trigger signal to the data processing module. Generally speaking, it is the moment when the trigger event is generated, indicating the specific acquisition position. For example, if the start of work is 0 time, the trigger event is generated at the position of 200 nanoseconds, then this time is the trigger time, and this position and The subsequent data is output to the user, and there is a certain phase relationship between the external trigger signal and the target ADC signal. When facing a high sampling rate ADC, the target ADC signal will be processed in parallel to cope with hardware performance limitations. Faced with parallel target ADC signals, it is difficult to find the true phase relationship between the external trigger signal and the target ADC signal. The error caused by a slight phase jitter will increase in units of the parallel number, and the error is extremely large. Therefore, the data point in the parallel sample point that is closest to the phase of the external trigger signal is used as the target data point with the same effect as the external starting signal, that is, the target data point is generated based on the phase difference between the processed target ADC signal and the external trigger signal.

[0033] The trigger module working at the same level of the data processing module includes a trigger control and management module and an external trigger IO control module. The combination of the trigger control and management module and the external trigger IO control module realizes the data trigger function. According to the ADC platform, the starting position of the ADC signal acquisition is located to generate the target data point, and the target data point is fed back to the data processing module. The target data point at this time is the trigger signal generated inside the ADC platform. In addition to the management and control of the trigger mode, the trigger module also realizes the trigger function of the ADC platform, including pre-trigger, delayed trigger and high-precision trigger functions. These trigger functions can realize the pre- or delayed output of the ADC acquisition data according to the starting position of the ADC signal acquisition described above, wherein the delayed output is caused by the delay of the cache / trigger event. The trigger module includes a trigger mode state machine unit, a pre-trigger data cache unit and a trigger delay unit, and the external trigger IO control module includes a high-precision trigger unit.

[0034] The trigger mode state machine unit needs to drive the ADC chip to work according to the acquisition instruction. The acquisition instruction includes necessary acquisition control instructions such as acquisition start, trigger mode, and trigger length. In addition to generating effective trigger events, the trigger mode state machine unit also cooperates with the data processing module to prompt the working status, and assists the data processing module to work by outputting a trigger status signal. For example, when an effective trigger event arrives, a busy sign is provided during the acquisition process to remind other modules that they are currently working and no new trigger signals are received; the pre-trigger data cache unit is a data cache area opened up inside the ADC platform for storing trigger data. When the pre-trigger function is enabled, the data before the trigger event occurs will be sent to the back-end module according to information such as the trigger position and the pre-trigger length. The back-end module is the data reordering module; the delay trigger unit is different from the pre-trigger unit. The trigger unit works in conjunction with the data processing module. The delay trigger unit works in conjunction with the trigger mode state machine unit to delay the position of the effective trigger event according to the instruction requirements. The ADC platform outputs the acquired data to the user's effective instructions, and each acquisition takes time. If a trigger is generated during the acquisition process, the current work cannot be interrupted and the data is lost, so this trigger must be shielded.

[0035] The high-precision trigger unit is based on a tapped delay line and implements a trigger function with a precision several times higher than the working clock at a lower working clock frequency, thereby assisting the trigger mode state machine unit in generating a high-precision external pulse trigger event.

[0036] In step S104, after searching for the target data point, the data processing module reads the position of the trigger event corresponding to the target data point, converts the ADC signal to obtain ADC data, the conversion specifically includes bit width conversion and insertion of data frame header, and manages and encapsulates the ADC data frame, and finally packages it into the data format required by the back-end high-speed interface control module, and uploads the ADC data to the application layer module in the ADC platform. The terminal can refer to the application layer module connected to the ADC platform, the application layer module includes a variety of software, and can also be a terminal device connected to the ADC platform to complete the processing of the ADC signal.

[0037] The high-speed interface control module in the ADC platform transmits the ADC data to the terminal through the constructed high-speed interface control module, thereby completing the data transmission between the ADC platform and the terminal, wherein the terminal also includes the terminal in the ADC platform, and the high-speed interface control module includes a DMA control unit, a memory interface control unit and a PCIe / Eth interface control unit.

[0038] The DMA control unit controls DMA to realize data movement and is subordinate to the high-speed interface module. It implements the bridge unit for configuring the DMA working mode and DMA data acquisition in the ADC platform described in the present invention, and cooperates with the memory interface control unit to realize data read and write address control, and accurately realizes the address continuous cache mode and ping-pong read and write cache mode described above.

[0039] The ADC platform described in the present invention needs to have the function of command transmission while realizing data transmission, that is, the host computer or computer sends commands to the ADC platform. Therefore, when constructing the high-speed interface control module, it is also necessary to design and build a bus management module, a bus distribution management unit and a bus register management unit of the bus management module. The bus management module is used for bus data management and distribution. The terminal and the lower-level ADC platform send and receive data and instructions through the bus, wherein the bus distribution management unit realizes the master-slave control of the bus during the data flow and instruction flow transmission process, and the bus register management unit is responsible for managing the base address and offset address of the allocation control register, and realizing the control of the terminal to the connected lower-level ADC platform at the same time. The base address is the basic address range of bus communication, and each base address range represents a functional class, such as PCIe interrupt control, board information storage, etc.; the offset address represents a specific functional register address, and the mapped register can realize the terminal sending instruction data to the lower-level ADC platform, and realize the switching and control of the working mode of the ADC platform.

[0040] The ADC platform described in the present invention is also designed with an independent status monitoring module, which includes monitoring of key elements such as board status, chip status, DMA status, cache status, data link status and working clock frequency, and reports the monitoring results to the terminal in real time through the bus. The bus register management unit is used to update the status of each monitored element to the bus register so that the terminal can obtain the monitoring results in real time in the form of data received by the host computer software, and the host computer software then decodes the specific error information included in the monitoring results.

[0041] In the specific implementation process of step S104, there is an embodiment in which: converting the ADC signal based on the target data point to obtain ADC data includes: S10411, reordering the target ADC signal based on the target data point, and transferring the bit width of the reordered target ADC signal to the target bit width; S10412. Add a data frame header to the reordered target ADC signal at the target bit width to obtain ADC data corresponding to the target ADC signal.

[0042] In steps S10411-S10412, after obtaining the target data point, the data processing module reorders the data points in the data stream corresponding to the ADC signal based on the position corresponding to the target data point, so that the data point corresponding to the position of the trigger event can be located at the front end of the transmission data stream, wherein the reordering is implemented based on the data reordering unit in the data processing module, specifically, the reordering is based on the trigger position / time. The ultra-high frequency acquisition action has multiple parallel sampling points. For example, the 10Gsps sampling rate outputs data through 40 sampling points and receives data through a 250MHz clock. However, at the same time, 40 sampling points output data. How to distinguish which point is the real trigger position? The position of the target data point is identified through a high-precision trigger function. Then, the first triggered point is reordered and placed at the position of the first point, thus completing the reordering; the bit width of the reordered data stream is transferred to the target bit width according to the bit width conversion unit in the data processing module, wherein the target bit width refers to the bit width required for transmission by the high-speed interface control module; after obtaining the reordered target ADC signal at the target bit width, a data frame header is added to each frame of data in the reordered target ADC signal at the target bit width according to the frame header control unit in the data processing module, wherein the frame header is composed of a plurality of customizable fields, which are not limited here, thereby obtaining the ADC data, realizing frame management and encapsulation of the ADC data, and also ensuring the accuracy and validity of the ADC data transmitted to the high-speed interface control module.

[0043] In the specific implementation process of step S10411, there is an embodiment in which: the reordering of the target ADC signal based on the target data point includes: S104111, determining the position of the target data point according to a preset mapping relationship between the target data point and the target ADC signal; S104112. Adjust the ordering method of the data stream in the target ADC signal based on the position of the target data point.

[0044] In steps S104111-S104112, once the data processing module identifies the target data point, it is necessary to mark the target data point in the data stream in the target ADC signal, which is usually achieved by adding a mark or label next to the target data point. The mark or label indicates that the data point is associated with a trigger event. The mark may include information such as the type of trigger event, a timestamp, and a serial number for subsequent analysis and processing. According to the preset mapping relationship between the target data point and the target ADC signal, the position of the target data point is determined, that is, the mapping relationship is the phase relationship between the target ADC signal and the external trigger signal. The target data point is the first data point after ADC quantization when a valid external trigger event is generated based on the mapping relationship. In practice, the position of the target data point is generally not in the first place, so the data points are reordered according to the preset adjustment method. , the reordering is performed according to a preset adjustment method, which is to adjust the ordering method of the data stream of the entire target ADC signal so that the target data point when a valid external trigger event is generated is at the first point of the converted target ADC data, and does not change the ordering method of the overall data stream, so as to analyze or respond to the target ADC signal more quickly. After reordering, the data processing module can also verify the data stream corresponding to the reordered target ADC signal to ensure the integrity and consistency of the data, which can include checking the order of data points, the correctness of markings, and whether the data is lost or repeated. If errors are encountered during data marking, reordering or verification, the data processing module identifies and processes these errors, and the processing methods include recording error logs, triggering alarms, attempting automatic repair or rolling back to a previous state, and processing the ADC signal again based on the trigger signal.

[0045] In the specific implementation process of step S104, there is another embodiment: uploading the ADC data to the application layer module in the ADC platform includes: S10421. Determine a target interface type based on the ADC data and an interface type of the ADC platform; S10422. Determine an upload method for uploading the ADC data based on the target interface type, and call the upload method to upload the ADC data to the application layer module.

[0046] In steps S10421-S10422, the interface type of the ADC platform is divided into two types, one is that an accumulation control unit is built, and the accumulation control unit is used to analyze weak ADC signals, in which the accumulation operation unit can be bypassed, and the other is that no accumulation control unit is built. For the former, the accumulation function is enabled based on the accumulation control unit, and the ADC data will upload the accumulation result to the terminal after completing the set accumulation times. For the latter, the ADC data generated by each trigger event is normally uploaded to the terminal. After generating ADC data based on the signal, the data processing module determines the type of the ADC platform. If it is determined that the ADC platform does not have an accumulation control unit, a corresponding upload instruction is generated. Based on the upload instruction, the high-speed interface control module normally uploads the ADC data generated by each trigger event to the terminal. If it is determined that the ADC platform has an accumulation control unit, a corresponding upload instruction is generated. Based on the upload instruction, the high-speed interface control module enables the accumulation function, and the ADC data will upload the accumulation result to the terminal after completing the set accumulation times.

[0047] Example 2 The present application also provides an ADC signal processing device, such as Figure 4 The block diagram of an ADC signal processing device is shown. The functions implemented by the ADC signal processing device correspond to the steps of executing an ADC signal processing method on the terminal. The device can be understood as a component of a server including a processor. The ADC signal processing device described in the present application is applied to an ADC platform, and the device includes: The acquisition module 401 is used to acquire corresponding ADC signals based on multiple acquisition modes set by the ADC platform, and filter out target ADC signals from the ADC signals; the ADC signals are signals acquired by the ADC chip; the ADC platform is built based on FPGA technology; A matching module 402 is used to match the target ADC signal with the processing module type of the ADC platform to determine the target processing type of the target ADC signal and call the target processing method corresponding to the target processing type; different processing types correspond to different processing methods; A processing module 403, configured to process the target ADC signal by the target processing method, so as to search for a target data point based on a phase of the processed target ADC signal; The uploading module 404 is used to convert the ADC signal based on the target data point to obtain ADC data, and upload the ADC data to the application layer module in the ADC platform to complete the processing of the ADC signal. In a feasible implementation, the screening module includes: A first judgment module, used to judge whether the target ADC signal meets the processing conditions preset by the ADC platform based on multiple dimensions, and generate a corresponding judgment result; The fusion module is used to fuse the judgment results of multiple dimensions to select a target processing type of the target ADC signal from a plurality of processing types preset by the ADC platform.

[0048] In a feasible implementation manner, the screening module further includes: A first determination module, configured to determine a processing module type of the ADC platform corresponding to the target ADC signal based on a fusion result generated by the judgment results of the multiple dimensions; The screening module is used to screen out the processing type corresponding to the target ADC signal according to the mapping relationship between the processing module type of the ADC platform and the processing type of the target ADC signal.

[0049] In a feasible implementation manner, the upload module includes: A transfer module, configured to reorder the target ADC signal based on the target data point, and transfer the bit width of the reordered target ADC signal to the target bit width; The adding module is used to add a data frame header to the reordered target ADC signal on the target bit width to obtain ADC data corresponding to the target ADC signal.

[0050] In a feasible implementation manner, the upload module further includes: A second determination module, configured to determine the position of the target data point according to a preset mapping relationship between the target data point and the target ADC signal; The adjustment module is used to adjust the ordering mode of the data stream in the target ADC signal based on the position of the target data point.

[0051] In a feasible implementation manner, the upload module also includes: A generating module, configured to determine a target interface type based on the ADC data and an interface type of the ADC platform; A calling module is used to determine an uploading method for uploading the ADC data based on the target interface type, and call the uploading method to upload the ADC data to the application layer module.

[0052] In a feasible implementation, the screening module further includes: A first matching module, used for matching the target ADC signal with a plurality of filtering modes respectively to obtain a matching result; A filtering module is used to determine a target filtering mode for the target ADC signal according to the matching result, and call the target filtering mode.

[0053] Example 3 The present application also provides an electronic device, such as Figure 5 As shown, it includes: a processor 501, a memory 502 and a bus 503, the memory 502 stores machine-readable instructions executable by the processor 501, when the electronic device is running, the processor 501 and the memory 502 communicate through the bus 503, and when the machine-readable instructions are executed by the processor 501, any one of the steps of the ADC signal processing method is performed.

[0054] Example 4 The present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any one of the ADC signal processing methods are executed.

[0055] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the method embodiment, and will not be repeated in this application. In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0056] The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0057] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0058] When the above-mentioned function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a non-volatile computer-readable storage medium executable by a processor. Based on such an understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a platform server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical discs that can store program codes.

[0059] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed by this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. An ADC signal processing method, characterized in that: Applied to an ADC platform, the method comprises: The corresponding ADC signals are collected based on the multiple collection modes set by the ADC platform, and the target ADC signals are screened out from the ADC signals; the ADC signals are signals collected by the ADC chip; the ADC platform is built based on FPGA technology; Matching the target ADC signal with the processing module type of the ADC platform to determine the target processing type of the target ADC signal, and calling the target processing method corresponding to the target processing type; different processing types correspond to different processing methods; Processing the target ADC signal by the target processing method to search for a target data point based on the phase of the processed target ADC signal; The ADC signal is converted based on the target data point to obtain ADC data, and the ADC data is uploaded to the application layer module in the ADC platform to complete the processing of the ADC signal.

2. The method according to claim 1, characterized in that The determining the target processing type of the target ADC signal includes: Determine whether the target ADC signal meets the processing conditions preset by the ADC platform based on multiple dimensions, and generate a corresponding determination result; The judgment results of multiple dimensions are integrated to select a target processing type of the target ADC signal from a plurality of processing types preset by the ADC platform.

3. The method according to claim 2, characterized in that The fusion of the judgment results of multiple dimensions to select the target processing type of the target ADC signal from the multiple processing types preset by the ADC platform includes: Determine the processing module type of the ADC platform corresponding to the target ADC signal based on the fusion result generated by the judgment results of the multiple dimensions; According to the mapping relationship between the processing module type of the ADC platform and the processing type of the target ADC signal, the processing type corresponding to the target ADC signal is screened out.

4. The method according to claim 1, characterized in that The converting the ADC signal based on the target data point to obtain ADC data includes: reordering the target ADC signal based on the target data point, and shifting the bit width of the reordered target ADC signal to the target bit width; A data frame header is added to the reordered target ADC signal at the target bit width to obtain ADC data corresponding to the target ADC signal.

5. The method according to claim 4, characterized in that The reordering of the target ADC signal based on the target data point comprises: Determine the position of the target data point according to a preset mapping relationship between the target data point and the target ADC signal; Based on the location of the target data point, the ordering manner of the data stream in the target ADC signal is adjusted.

6. The method according to claim 1, characterized in that The uploading of the ADC data to the application layer module in the ADC platform includes: Determining a target interface type based on the ADC data and an interface type of the ADC platform; An uploading method for uploading the ADC data is determined based on the target interface type, and the uploading method is called to upload the ADC data to the application layer module.

7. The method according to claim 3, characterized in that The dimensions include at least a filtering dimension; The filtering out the processing type corresponding to the target ADC signal includes: Based on the target ADC signal, the target ADC signal is matched with a plurality of filtering modes to obtain a matching result; A target filtering mode for the target ADC signal is determined according to the matching result, and the target filtering mode is called.

8. An ADC signal processing device, characterized in that: Applied to an ADC platform, the device comprises: An acquisition module, used for acquiring corresponding ADC signals based on multiple acquisition modes set by the ADC platform, and filtering out target ADC signals from the ADC signals; the ADC signals are signals acquired by the ADC chip; the ADC platform is built based on FPGA technology; A matching module, used for matching the target ADC signal with the processing module type of the ADC platform to determine the target processing type of the target ADC signal and call the target processing method corresponding to the target processing type; different processing types correspond to different processing methods; A processing module, configured to process the target ADC signal by the target processing method, so as to search for a target data point based on a phase of the processed target ADC signal; An uploading module is used to convert the ADC signal based on the target data point to obtain ADC data, and upload the ADC data to the application layer module in the ADC platform to complete the processing of the ADC signal.

9. An electronic device, characterized in that: include: A processor, a memory and a bus, wherein the memory stores machine-readable instructions executable by the processor, and when the electronic device is running, the processor and the memory communicate via the bus, and when the machine-readable instructions are executed by the processor, the steps of an ADC signal processing method as described in any one of claims 1 to 7 are performed.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of an ADC signal processing method as claimed in any one of claims 1 to 7 are executed.

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