Analog front-end circuit, electronic equipment, successive approximation analog-to-digital converter and method

Abstract

The invention provides an analog front-end circuit, electronic equipment, a successive approximation type analog-to-digital converter and a method, and the analog front-end circuit comprises a digital-to-analog conversion capacitor array which comprises a first digital-to-analog conversion unit and a second digital-to-analog conversion unit, in the conversion process, the capacitor lower polar plate is switched between the reference voltage and the reference ground to realize charge redistribution; the second digital-to-analog conversion unit samples the reference voltage, and the capacitor lower polar plate is switched between the reference voltage and the reference ground in the conversion process to realize charge redistribution; the comparison module is used for comparing output signals of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit; the clock generation module generates a clock signal based on the comparison result; the successive approximation logic module outputs a digital signal based on a clock signal and generates a switching control signal. According to the invention, the requirement on the power supply voltage is reduced, the power consumption and the area are reduced, and the chip cost is saved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design, and in particular to an analog front-end circuit, electronic equipment, a successive approximation analog-to-digital converter and a method. Background Art

[0002] In biomedical and sensor applications, analog-to-digital converters usually need to work all the time to continuously sense input signals. Therefore, power consumption becomes particularly important when powered by batteries. In order to minimize the power consumption and area of ​​the analog-to-digital converter, single-ended SAR ADC (successive approximation register) is the preferred solution for analog-to-digital converters.

[0003] like Figure 1 The figure shows a single-ended successive approximation analog-to-digital converter 1, which includes a sampling capacitor CS, a binary weighted capacitor array 11, a comparator 12, a clock generating circuit 13 and a successive approximation logic generating circuit 14. Among them, the non-inverting input terminal of the comparator 12 is connected to the input voltage Vin and the upper plate of the sampling capacitor CS, and the lower plate of the sampling capacitor CS is grounded to VSS. The inverting input terminal of the comparator 12 is connected to the output terminal of the binary weighted capacitor array 11. The binary weighted capacitor array 11 includes a sampling switch smp1 and two groups of capacitor arrays; one end of the sampling switch smp1 is connected to the reference voltage Vref, and the other end is connected to the upper plates of each capacitor in the two groups of capacitor arrays; during the conversion process, the lower plates of the capacitors of the two groups of capacitor arrays are switched between the reference voltage Vref and the reference ground VSS to realize successive approximation. The clock generating circuit 13 is connected to the output terminal of the comparator 12, and generates a clock signal based on the output signal of the comparator 12. The successive approximation logic generation circuit 14 is connected to the output end of the clock generation circuit 13, outputs the digital signal Dout and generates the switch control signals sp and sn of the two sets of capacitor arrays. In this scheme, a special sampling capacitor needs to be set; for the input signal in the range of 0 to Vref, the common mode voltage at the input end of the comparator ranges from 0 to Vref, so the comparator needs to be designed as a rail-to-rail input structure, and the corresponding power consumption increases; at the same time, it is also necessary to provide a power supply voltage for the voltage buffer (not shown in the figure) that generates the reference voltage Vref. The power supply voltage is greater than the reference voltage Vref, and the reference voltage Vref has high requirements for the establishment speed and accuracy during the conversion process, which increases the complexity of the design.

[0004] like Figure 2Another single-ended successive approximation analog-to-digital converter 2 (Chao Yuan et al. [A 1-V 9.8-ENOB 100-KS / s single-ended SAR ADC with symmetrical DAC switching techniquefor neural signal acquisition]) is shown, including an upper switched capacitor digital-to-analog conversion circuit 21, a lower switched capacitor digital-to-analog conversion circuit 22, a comparator 23, a clock generation circuit 24, and a successive approximation logic generation circuit 25. Among them, the upper switched capacitor digital-to-analog conversion circuit 21 and the lower switched capacitor digital-to-analog conversion circuit 22 adopt upper plate and lower plate mixed sampling, passive single-ended to differential conversion, and symmetrical DAC switching technology. The comparator 23 compares the output signals of the upper switched capacitor digital-to-analog conversion circuit 21 and the lower switched capacitor digital-to-analog conversion circuit 22. The clock generation circuit 24 is connected to the output end of the comparator 23, and generates a clock signal based on the output signal of the comparator 23. The successive approximation logic generation circuit 25 is connected to the output end of the clock generation circuit 24, outputs the digital signal Dout and generates the switch control signals sp and sn of the upper switched capacitor digital-to-analog conversion circuit 21 and the lower switched capacitor digital-to-analog conversion circuit 22. For input signals in the range of 0 to Vref, this scheme switches between the reference voltage Vref and the reference ground VSS through the lower plate during the conversion process, and averages the charge of the lower plate, so that the common mode of the comparator is kept at 1 / 2Vref, and a comparator design with rail-to-rail input is not required; however, the switching logic of the switched capacitor digital-to-analog conversion circuit of this scheme is quite complicated, and a power supply voltage greater than the reference voltage Vref is also required, which further increases the complexity of the design; in addition, in order to significantly reduce the nonlinearity introduced by the sampling switch and improve the spurious-free dynamic range, an N-bit single-ended SARADC requires N gate voltage bootstrap switches (switches connected to the input voltage Vin, Figure 2 In the example, the number of gate voltage bootstrap switches is 4, which greatly increases the area.

[0005] It can be seen that if high-precision conversion in the input range of 0 to Vref is to be achieved, the existing single-ended SAR ADC either requires a rail-to-rail input comparator, or requires a complex DAC switching logic, or requires a power supply voltage greater than the reference voltage Vref, all of which inevitably increase the power consumption and area of ​​the single-ended SAR ADC.

[0006] Therefore, how to reduce the power consumption and area of ​​a successive approximation analog-to-digital converter has become one of the problems that those skilled in the art need to solve urgently.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide an analog front-end circuit, an electronic device, a successive approximation analog-to-digital converter and a method for solving the problems of high power consumption and large area of ​​the successive approximation analog-to-digital converter in the prior art.

[0009] To achieve the above-mentioned object and other related objects, the present invention provides a successive approximation analog-to-digital converter, the successive approximation analog-to-digital converter comprising at least:

[0010] Digital-to-analog conversion capacitor array, comparison module, clock generation module and successive approximation logic module;

[0011] The digital-to-analog conversion capacitor array comprises a first digital-to-analog conversion unit and a second digital-to-analog conversion unit, wherein the input end of the first digital-to-analog conversion unit receives an input voltage, samples the input voltage, and during the conversion process, the lower plate of the capacitor switches between a reference voltage and a reference ground to achieve charge redistribution; the input end of the second digital-to-analog conversion unit receives the reference voltage, samples the reference voltage, and during the conversion process, the lower plate of the capacitor switches between the reference voltage and the reference ground to achieve charge redistribution; wherein the reference voltage is half of the upper limit of the input range of the successive approximation analog-to-digital converter;

[0012] The first input end of the comparison module is connected to the output end of the first digital-to-analog conversion unit, the second input end is connected to the output end of the second digital-to-analog conversion unit, and outputs a comparison result;

[0013] The clock generating module is connected to the output end of the comparing module, and generates a clock signal based on the comparing result;

[0014] The successive approximation logic module is connected to the output end of the clock generation module, outputs a digital signal based on the clock signal and generates a switching control signal of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit.

[0015] Optionally, the first digital-to-analog conversion unit and the second digital-to-analog conversion unit both include a sampling switch and a capacitor array; one end of the sampling switch serves as the input end of the corresponding digital-to-analog conversion unit, and the second end is connected to the upper plate of the corresponding capacitor array; the lower plate of each capacitor in the capacitor array is respectively connected to the reference voltage or reference ground through a switch.

[0016] More optionally, the sampling switch in the first digital-to-analog conversion unit is a gate voltage bootstrap switch.

[0017] More optionally, the weights of the capacitors in the capacitor array are increased in proportion or set to equal values.

[0018] More optionally, the capacitor array is a binary weighted capacitor array.

[0019] More optionally, the first digital-to-analog conversion unit and the second digital-to-analog conversion unit also include redundant capacitors; the upper plate of the redundant capacitor is connected to the upper plate of the corresponding capacitor array, and the lower plate is connected to the reference voltage; the capacitance of the redundant capacitor is equal to the capacitance of the capacitor with the smallest weight in the corresponding capacitor array.

[0020] Optionally, a non-phase input terminal of the comparison module is connected to an output terminal of the first digital-to-analog conversion unit, and an inverting input terminal is connected to an output terminal of the second digital-to-analog conversion unit.

[0021] Optionally, the successive approximation analog-to-digital converter also includes a reference voltage buffer module; the reference voltage buffer module is connected to the power supply voltage to generate the reference voltage, wherein the power supply voltage is greater than the reference voltage and less than or equal to the upper limit of the input range of the successive approximation analog-to-digital converter.

[0022] To achieve the above-mentioned purpose and other related purposes, the present invention further provides an analog-to-digital conversion method, which is implemented based on the above-mentioned successive approximation analog-to-digital converter, and the analog-to-digital conversion method at least includes:

[0023] In the sampling phase, the lower plates of the capacitors in the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are connected to the reference voltage, and the input voltage and the reference voltage are sampled;

[0024] In the conversion stage, the potential of the lower plate of each capacitor is adjusted from high to low according to the comparison result. If the output voltage of the first digital-to-analog conversion unit is greater than the output voltage of the second digital-to-analog conversion unit, the lower plate of the next capacitor in the first digital-to-analog conversion unit is switched to the reference ground, and the potential of the lower plates of other capacitors remains unchanged; if the output voltage of the first digital-to-analog conversion unit is less than the output voltage of the second digital-to-analog conversion unit, the lower plate of the next capacitor in the second digital-to-analog conversion unit is switched to the reference ground, and the potential of the lower plates of other capacitors remains unchanged; and then the quantization results of each bit of the digital signal are obtained in turn.

[0025] To achieve the above-mentioned object and other related objects, the present invention further provides an analog front-end circuit, the analog front-end circuit at least comprising:

[0026] Instrumentation amplifiers, filters and successive approximation analog-to-digital converters as described above;

[0027] The instrument amplifier receives an external input signal and amplifies the external input signal;

[0028] The filter is connected to the output end of the instrument amplifier to filter the output signal of the instrument amplifier;

[0029] The successive approximation analog-to-digital converter is connected to the output end of the filter, performs analog-to-digital conversion on the analog signal output by the filter, and outputs a corresponding digital signal.

[0030] To achieve the above object and other related objects, the present invention further provides an electronic device, which at least includes: the above successive approximation analog-to-digital converter.

[0031] As described above, the analog front-end circuit, electronic device, successive approximation analog-to-digital converter and method of the present invention have the following beneficial effects:

[0032] The successive approximation analog-to-digital converter of the present invention can realize single-ended analog-to-digital conversion in the input range of 0 to Vref, adopts the upper plate sampling method, only requires one gate voltage bootstrap switch, has a simple structure and a small area; the input common mode voltage range is small, and there is no need to set an amplifier module of a rail-to-rail input structure, which reduces the circuit area, complexity and power consumption; the power supply voltage of the reference voltage buffer module that provides the reference voltage is small, which can further simplify the circuit design. The analog front-end circuit, electronic equipment and successive approximation analog-to-digital converter of the present invention have low power consumption, small area and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is a structural schematic diagram of a single-ended successive approximation analog-to-digital converter.

[0034] Figure 2 Shown is a structural schematic diagram of another single-ended successive approximation analog-to-digital converter.

[0035] Figure 3 It is a schematic diagram showing the structure of the successive approximation analog-to-digital converter of the present invention.

[0036] Figure 4 It is a schematic diagram showing the switch switching of the successive approximation analog-to-digital converter of the present invention during the sampling phase.

[0037] Figures 5 to 11 It is a schematic diagram showing the switching of the successive approximation analog-to-digital converter of the present invention during the conversion phase.

[0038] Fig.12 Shown is a schematic structural diagram of the analog front-end circuit of the present invention.

[0039] Component number description

[0040] 1 Single-ended successive approximation analog-to-digital converter

[0041] 11 Binary Weighted Capacitor Array

[0042] 12 Comparator

[0043] 13 Clock generation circuit

[0044] 14 Successive approximation logic generation circuit

[0045] 2 Single-ended successive approximation analog-to-digital converter

[0046] 21 Upper switched capacitor digital-to-analog conversion circuit

[0047] 22 Lower switched capacitor digital-to-analog conversion circuit

[0048] 23 Comparator

[0049] 24 Clock generation circuit

[0050] 25 Successive approximation logic generation circuit

[0051] 3 Successive approximation analog-to-digital converter

[0052] 31 Digital-to-analog conversion capacitor array

[0053] 311 First digital-to-analog conversion unit

[0054] 312 Second digital-to-analog conversion unit

[0055] 32 Comparison module

[0056] 33 Clock generation module

[0057] 34 Successive approximation logic module

[0058] 4 Instrumentation Amplifier

[0059] 5 Filters DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] See also Figure 3 to Figure 12It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] like Figure 3 As shown, the present invention provides a successive approximation analog-to-digital converter 3, and the successive approximation analog-to-digital converter 3 includes:

[0063] A digital-to-analog conversion capacitor array 31 , a comparison module 32 , a clock generation module 33 and a successive approximation logic module 34 .

[0064] like Figure 3 As shown, the digital-to-analog conversion capacitor array 31 samples the input voltage Vin. During the conversion process, the voltage of the lower plate of the capacitor is switched based on the control signal generated by the successive approximation logic module 34, and the successive approximation is achieved by charge redistribution. The digital-to-analog conversion capacitor array 31 includes a first digital-to-analog conversion unit 311 and a second digital-to-analog conversion unit 312. The input end of the first digital-to-analog conversion unit 311 receives the input voltage Vin, samples the input voltage Vin, and during the conversion process, the lower plate of the capacitor is switched at a reference voltage. and the reference ground VSS to realize charge redistribution; the input terminal of the second digital-to-analog conversion unit 312 receives the reference voltage For reference voltage Sampling is performed, and during the conversion process, the lower plate of the capacitor is at the reference voltage The reference voltage VSS is switched between the reference voltage VSS to achieve charge redistribution. It is half of the upper limit Vref of the input range of the successive approximation ADC.

[0065] Specifically, the first digital-to-analog conversion unit 311 and the second digital-to-analog conversion unit 312 each include a sampling switch and a capacitor array; one end of the sampling switch serves as the input end of the corresponding digital-to-analog conversion unit, and the second end is connected to the upper plate of the corresponding capacitor array; the lower plates of each capacitor in the capacitor array are connected to the reference voltage through a switch. Or reference ground VSS.

[0066] More specifically, in this embodiment, the sampling switch K1 in the first digital-to-analog conversion unit 311 is a gate voltage bootstrap switch, so as to reduce the distortion caused by nonlinearity and improve the accuracy of sampling.

[0067] More specifically, in this embodiment, each capacitor array includes a capacitor and a single-pole double-throw switch connected to the lower plate of each capacitor (any switch that can realize the single-pole multi-throw function in an integrated circuit is applicable to the present invention, and the specific switch type is not limited). The upper plates of each capacitor in the same capacitor array are connected together, and the lower plates of each capacitor can be switched to the corresponding voltage (reference voltage) as needed. Or reference ground VSS). The weight of each capacitor in the same capacitor array can be configured as different values ​​or the same value as needed (that is, the capacitance of each capacitor in the capacitor array is unequal or equal); wherein, the weight of each capacitor is configured differently, including but not limited to increasing in proportion from low to high (it may also change irregularly). As an implementation of the present invention, each capacitor array is a binary weighted capacitor array, that is, the weight of each capacitor increases from low to high by a multiple of 2, and the weight of each capacitor satisfies: 2 i-1 , i is the number of bits of the corresponding capacitor. As an example, in this embodiment, each capacitor array includes three capacitors and corresponding switches, wherein the capacitance of the first capacitor (lowest bit) is set to c, the capacitance of the second capacitor is set to 2c, and the capacitance of the third capacitor (highest bit) is set to 4c. It should be noted that the number of capacitors and their corresponding switches in the capacitor array can be set according to actual needs (generally not less than 2), and the more capacitor bits, the higher the accuracy of analog-to-digital conversion, which will not be elaborated here.

[0068] More specifically, as another implementation of the present invention, the first digital-to-analog conversion unit 311 and the second digital-to-analog conversion unit 312 also include redundant capacitors. The upper plate of the redundant capacitor is connected to the upper plate of the corresponding capacitor array, and the lower plate is connected to the reference voltage The capacitance of the redundant capacitor is equal to the capacitance of the capacitor with the smallest weight in the corresponding capacitor array. In this example, the capacitance of the redundant capacitor is set to c.

[0069] like Figure 3 As shown, the first input terminal of the comparison module 32 is connected to the output terminal of the first digital-to-analog conversion unit 311 , and the second input terminal is connected to the output terminal of the second digital-to-analog conversion unit 312 , and the comparison result is output.

[0070] Specifically, in this embodiment, the non-phase input terminal of the comparison module 32 is connected to the output terminal of the first digital-to-analog conversion unit 311, and the inverting input terminal is connected to the output terminal of the second digital-to-analog conversion unit 312. When the output signal of the first digital-to-analog conversion unit 311 is greater than the output signal of the second digital-to-analog conversion unit 312, a high-level signal is output; when the output signal of the first digital-to-analog conversion unit 311 is less than the output signal of the second digital-to-analog conversion unit 312, a low-level signal is output; the magnitude relationship is determined based on the level of the output signal of the comparison module 32. In actual use, the input signal and the input terminal polarity of the comparison module 32 can be interchanged as needed, as long as the magnitude relationship can be obtained, and it is not limited to this embodiment.

[0071] like Figure 3 As shown, the clock generating module 33 is connected to the output end of the comparing module 32, and generates a clock signal based on the comparison result.

[0072] like Figure 3 As shown, the successive approximation logic module 34 is connected to the output end of the clock generation module 33, outputs the digital signal Dout based on the clock signal and generates the switching control signal sp of the first digital-to-analog conversion unit and the switching control signal sn of the second digital-to-analog conversion unit.

[0073] It should be noted that any circuit structure of the clock generation module 33 and the successive approximation logic module 34 that can implement successive approximation analog-to-digital conversion is applicable to the present invention and will not be described in detail herein.

[0074] As another implementation of the present invention, the successive approximation analog-to-digital converter 3 further includes a reference voltage buffer module (not shown in the figure). The reference voltage buffer module is connected to the power supply voltage to generate a reference voltage Among them, the power supply voltage is greater than the reference voltage And it is less than or equal to the upper limit Vref of the input range of the successive approximation type analog-to-digital converter 3.

[0075] The successive approximation analog-to-digital converter 3 of the present invention adopts an upper plate sampling method and only requires one gate voltage bootstrap switch (i.e., K1), which saves area; for input signals in the range of 0 to Vref, the common-mode voltage at the input end of the comparison module during the conversion process is less than Vref, so the comparison module 32 of the present invention can use a common differential input comparator without setting a rail-to-rail input structure; at the same time, the power supply voltage of the reference voltage buffer module that provides the reference voltage can be set to Vref or less than Vref, thereby simplifying the design.

[0076] The present invention also provides an analog-to-digital conversion method, which is implemented based on a successive approximation analog-to-digital converter 3, comprising:

[0077] 1) In the sampling phase, the lower plates of the capacitors in the first digital-to-analog conversion unit 311 and the second digital-to-analog conversion unit 312 are connected to the reference voltage, and the input voltage and the reference voltage are sampled.

[0078] 2) In the conversion stage, the potential of the lower plate of each capacitor is adjusted from high to low according to the comparison result. If the output voltage of the first digital-to-analog conversion unit is greater than the output voltage of the second digital-to-analog conversion unit, the lower plate of the next capacitor in the first digital-to-analog conversion unit is switched to the reference ground, and the potential of the lower plates of other capacitors remains unchanged; if the output voltage of the first digital-to-analog conversion unit is less than the output voltage of the second digital-to-analog conversion unit, the lower plate of the next capacitor in the second digital-to-analog conversion unit is switched to the reference ground, and the potential of the lower plates of other capacitors remains unchanged; and then the quantization results of each bit of the digital signal are obtained in turn.

[0079] The following is based on Figure 3 The switching principle of the successive approximation type analog-to-digital converter of the present invention is explained in detail.

[0080] like Figure 4 As shown, in the sampling phase, the sampling switch K1 in the first digital-to-analog conversion unit 311 is closed, one end of which is connected to the input voltage Vin, and the other end is connected to the upper plate of each capacitor in the first digital-to-analog conversion unit 311; the sampling switch K2 in the second digital-to-analog conversion unit 312 is closed, one end of which is connected to the reference voltage The other end is connected to the upper plate of each capacitor in the second digital-to-analog conversion unit 312; at this time, the lower plate of each capacitor is connected to the reference voltage The input voltage Vin is sampled to the upper plates of each capacitor in the first digital-to-analog conversion unit 311 .

[0081] like Figure 5 As shown, in the conversion phase, the sampling switch K1 in the first digital-to-analog conversion unit 311 and the sampling switch K2 in the second digital-to-analog conversion unit 312 are both disconnected, the positive input voltage of the comparison module 32 is Vin, and the negative input voltage is Vin and By comparison, the highest quantization result is obtained.

[0082] if The switch in the second digital-to-analog conversion unit 312 remains unchanged; the switch in the highest bit of the first digital-to-analog conversion unit 311 is switched from Switch to VSS, and keep other switches unchanged; Figure 6 As shown, after a certain settling time, the voltage at the non-inverting input terminal of the comparison module 32 becomes Vx_p; since the sampling switch K1 in the first digital-to-analog conversion unit 311 is disconnected, the upper plates of the capacitors in the first digital-to-analog conversion unit 311 follow the charge conservation law, and the following equation (1) is established:

[0083]

[0084] Solving for this yields: The voltage at the inverting input terminal of the comparison module 32 is maintained at Will and By comparison, we get Vin and The relative size relationship of is the quantization result of the second highest position. Further, if Then compare Vin with The size relationship, such as Figure 7 As shown; if Then compare Vin with The size relationship, such as Figure 8 shown.

[0085] if The switch in the first digital-to-analog conversion unit 311 remains unchanged; the switch in the highest bit of the second digital-to-analog conversion unit 312 is switched from Switch to VSS, and keep other switches unchanged; Fig. 9 As shown, after a certain settling time, the voltage at the inverting input terminal of the comparison module 32 becomes Vx_n. Since the sampling switch K2 in the second digital-to-analog conversion unit 312 is disconnected, the upper plates of the capacitors in the second digital-to-analog conversion unit 312 follow the charge conservation law, and the following equation (2) is established:

[0086]

[0087] Solving for this yields: The voltage at the non-inverting input terminal of the comparison module 32 is kept at Vin, and Vin is compared with By comparison, we get Vin and The relative size relationship of is the quantization result of the second highest position. Further, if Then compare Vin with The size relationship, such as Fig.10 As shown; if Then compare Vin with The size relationship, such as Fig.11 shown.

[0088] And so on, until the lowest bit quantization result is obtained.

[0089] The maximum input common-mode voltage at the first comparison of the comparator during a conversion process is: The minimum input common mode voltage of the comparison module 32 during the first comparison is: During the entire conversion phase, the input common mode voltage range of the comparison module 32 is

[0090] like Fig.12 As shown, the present invention also provides an analog front-end circuit, the analog front-end circuit comprising:

[0091] Instrumentation amplifier 4, filter 5 and successive approximation analog-to-digital converter 3.

[0092] like Fig.12 As shown, the instrumentation amplifier 4 receives an external input signal IN and amplifies the external input signal IN. The filter 5 is connected to the output end of the instrumentation amplifier 4 and filters the output signal of the instrumentation amplifier 4. The successive approximation analog-to-digital converter 3 is connected to the output end of the filter 5 and performs analog-to-digital conversion on the analog signal output by the filter 5 and outputs a corresponding digital signal. The analog front-end circuit of the present invention can save power consumption and area and is suitable for large-scale production.

[0093] The present invention further provides an electronic device, comprising at least the successive approximation analog-to-digital converter 3 of the present invention. The electronic device includes but is not limited to a sensor. Any electronic device that needs to perform analog-to-digital conversion is suitable for the present invention and will not be described in detail here.

[0094] In summary, the present invention provides an analog front-end circuit, an electronic device, a successive approximation analog-to-digital converter and a method, comprising: a digital-to-analog conversion capacitor array, a comparison module, a clock generation module and a successive approximation logic module; the digital-to-analog conversion capacitor array comprises a first digital-to-analog conversion unit and a second digital-to-analog conversion unit, the input end of the first digital-to-analog conversion unit receives an input voltage, samples the input voltage, and during the conversion process, the lower plate of the capacitor switches between a reference voltage and a reference ground to achieve charge redistribution; the input end of the second digital-to-analog conversion unit receives the reference voltage, samples the reference voltage, and during the conversion process, the lower plate of the capacitor switches between the reference voltage and the reference ground to achieve charge redistribution. The charge redistribution is achieved by switching between the voltage and the reference ground; wherein the reference voltage is half of the upper limit of the input range of the successive approximation analog-to-digital converter; the first input end of the comparison module is connected to the output end of the first digital-to-analog conversion unit, and the second input end is connected to the output end of the second digital-to-analog conversion unit, and the comparison result is output; the clock generation module is connected to the output end of the comparison module, and a clock signal is generated based on the comparison result; the successive approximation logic module is connected to the output end of the clock generation module, and a digital signal is output based on the clock signal and a switching control signal is generated for the first digital-to-analog conversion unit and the second digital-to-analog conversion unit. The successive approximation analog-to-digital converter of the present invention realizes an input range of 0 to Vref through a simple DAC switching logic without the need for a comparator design with rail-to-rail input, and only requires one The reference voltage buffer reduces the requirement for power supply voltage, reduces power consumption and area, and saves chip cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A successive approximation analog-to-digital converter, It is characterized in that The successive approximation analog-to-digital converter comprises at least: Digital-to-analog conversion capacitor array, comparison module, clock generation module and successive approximation logic module; The digital-to-analog conversion capacitor array comprises a first digital-to-analog conversion unit and a second digital-to-analog conversion unit, wherein the input end of the first digital-to-analog conversion unit receives an input voltage, samples the input voltage, and during the conversion process, the lower plate of the capacitor switches between a reference voltage and a reference ground to achieve charge redistribution; the input end of the second digital-to-analog conversion unit receives the reference voltage, samples the reference voltage, and during the conversion process, the lower plate of the capacitor switches between the reference voltage and the reference ground to achieve charge redistribution; wherein the reference voltage is half of the upper limit of the input range of the successive approximation analog-to-digital converter; The first input end of the comparison module is connected to the output end of the first digital-to-analog conversion unit, the second input end is connected to the output end of the second digital-to-analog conversion unit, and outputs a comparison result; The clock generating module is connected to the output end of the comparing module, and generates a clock signal based on the comparing result; The successive approximation logic module is connected to the output end of the clock generation module, outputs a digital signal based on the clock signal and generates a switching control signal of the first digital-to-analog conversion unit and the second digital-to-analog conversion unit.

2. The successive approximation analog-to-digital converter according to claim 1, Features: The first digital-to-analog conversion unit and the second digital-to-analog conversion unit both include a sampling switch and a capacitor array; one end of the sampling switch serves as the input end of the corresponding digital-to-analog conversion unit, and the second end is connected to the upper plate of the corresponding capacitor array; the lower plate of each capacitor in the capacitor array is connected to the reference voltage or reference ground through a switch.

3. The successive approximation analog-to-digital converter according to claim 2, Features: The sampling switch in the first digital-to-analog conversion unit is a gate voltage bootstrap switch.

4. The successive approximation analog-to-digital converter according to claim 2, Features: The weights of the capacitors in the capacitor array are increased in proportion or set to equal values.

5. The successive approximation analog-to-digital converter according to claim 4, Features: The capacitor array is a binary weighted capacitor array.

6. The successive approximation analog-to-digital converter according to any one of claims 2 to 5, Features: The first digital-to-analog conversion unit and the second digital-to-analog conversion unit also include redundant capacitors; the upper plate of the redundant capacitor is connected to the upper plate of the corresponding capacitor array, and the lower plate is connected to the reference voltage; the capacitance of the redundant capacitor is equal to the capacitance of the capacitor with the smallest weight in the corresponding capacitor array.

7. The successive approximation analog-to-digital converter according to claim 1, Features: The non-phase input terminal of the comparison module is connected to the output terminal of the first digital-to-analog conversion unit, and the inverting input terminal is connected to the output terminal of the second digital-to-analog conversion unit.

8. The successive approximation analog-to-digital converter according to claim 1, Features: The successive approximation analog-to-digital converter also includes a reference voltage buffer module; the reference voltage buffer module is connected to a power supply voltage to generate the reference voltage, wherein the power supply voltage is greater than the reference voltage and less than or equal to an upper limit of an input range of the successive approximation analog-to-digital converter.

9. An analog-to-digital conversion method, implemented based on the successive approximation analog-to-digital converter according to any one of claims 1 to 8, It is characterized in that The analog-to-digital conversion method at least comprises: In the sampling phase, the lower plates of the capacitors in the first digital-to-analog conversion unit and the second digital-to-analog conversion unit are connected to the reference voltage, and the input voltage and the reference voltage are sampled; In the conversion stage, the potential of the lower plate of each capacitor is adjusted from high to low according to the comparison result. If the output voltage of the first digital-to-analog conversion unit is greater than the output voltage of the second digital-to-analog conversion unit, the lower plate of the next capacitor in the first digital-to-analog conversion unit is switched to the reference ground, and the potential of the lower plates of other capacitors remains unchanged; if the output voltage of the first digital-to-analog conversion unit is less than the output voltage of the second digital-to-analog conversion unit, the lower plate of the next capacitor in the second digital-to-analog conversion unit is switched to the reference ground, and the potential of the lower plates of other capacitors remains unchanged; and then the quantization results of each bit of the digital signal are obtained in turn.

10. An analog front end circuit, It is characterized in that The analog front end circuit at least comprises: An instrumentation amplifier, a filter, and a successive approximation analog-to-digital converter as claimed in any one of claims 1 to 8; The instrument amplifier receives an external input signal and amplifies the external input signal; The filter is connected to the output end of the instrument amplifier to filter the output signal of the instrument amplifier; The successive approximation analog-to-digital converter is connected to the output end of the filter, performs analog-to-digital conversion on the analog signal output by the filter, and outputs a corresponding digital signal.

11. An electronic device, It is characterized in that The electronic device at least comprises: a successive approximation analog-to-digital converter as claimed in any one of claims 1 to 8.

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