Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof. The preparation method of the semiconductor structure comprises the following steps: providing a substrate; forming a laminated structure on the substrate, wherein the laminated structure comprises a first dielectric layer and a conductive layer which are sequentially stacked from bottom to top; forming a continuously-distributed second dielectric layer on the exposed surface of the laminated structure, and filling the gap region of the laminated structure by using a sacrificial layer; forming a first groove which penetrates the channel region of each layer in the laminated structure; sequentially depositing a channel material layer, an isolation dielectric material layer and a gate conductive layer on the inner wall of the first groove, and the gate conductive layer fills the first groove; forming a second groove which penetrates the sacrificial layer in the gap region on the opposite sides of the channel region along a first direction; removing the sacrificial layer on the side wall of the second groove, and removing the channel material layer and the corresponding isolation dielectric material layer which are in contact with the sacrificial layer. The preparation method of the semiconductor structure can solve the problem of parasitic MOS.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a semiconductor structure and a preparation method thereof. BACKGROUND

[0002] With the development of semiconductor technology, the storage density of memory is getting higher and higher. However, as the feature size is getting closer to the theoretical limit, 3D stacked memory based on oxide material is expected to achieve high-density storage, which is the possible development direction of the next generation of memory. However, 3D stacked memory still faces many difficult challenges, such as the problem of parasitic transistor. The problem of parasitic transistor refers to the interconnection between different capacitors through oxide material, which leads to the failure to achieve information storage. SUMMARY

[0003] Therefore, it is necessary to provide a semiconductor structure and a preparation method thereof for the problem of parasitic transistor in the related art.

[0004] In a first aspect, the present application provides a preparation method of a semiconductor structure, comprising:

[0005] providing a substrate;

[0006] forming a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive layers stacked in turn from bottom to top, each of the conductive layers comprising a main body part extending along a first direction and a plurality of extension parts arranged at intervals along the first direction, each of the extension parts being located on the opposite sides of the main body part, the main body part and each of the extension parts being integrally connected, and the part of the extension part connected with the main body part serving as a channel region; wherein the width of the extension part along the first direction is greater than the width of the first dielectric layer located between the extension parts along the first direction;

[0007] forming a second dielectric layer continuously distributed on the exposed surface of the stack structure, and filling the gap region of the stack structure with a sacrificial layer;

[0008] forming a first trench penetrating the channel region of each layer in the stack structure, so as to remove the first dielectric layer and the conductive layer located in the channel region, and remove the second dielectric layer located on the side surface of the first dielectric layer on the opposite sides along the first direction, and retain the second dielectric layer located on the side surface of the extension part on the opposite sides along the first direction; wherein the side walls of the first trench on the opposite sides along the first direction expose the sacrificial layer and the second dielectric layer stacked in turn and alternately, and the position of each layer of the sacrificial layer corresponds to the position of each layer of the first dielectric layer, and the position of each layer of the second dielectric layer corresponds to the position of each layer of the conductive layer;

[0009] Depositing, in sequence, a channel material layer, an isolation medium material layer and a gate conductive layer on the inner wall of the first trench, wherein the gate conductive layer fills the first trench;

[0010] Forming, in the gap region on the two sides of the channel region opposite to each other along the first direction, a second trench penetrating the sacrificial layer, wherein the two side walls of the second trench opposite to each other along the first direction expose the sacrificial layer and the second medium layer which are alternately and sequentially stacked;

[0011] Removing the sacrificial layer on the side wall of the second trench, and removing the channel material layer and the corresponding isolation medium material layer in contact with the sacrificial layer, to obtain an isolation medium layer and a channel layer which are in contact with the second medium layer and surround the side wall of the gate conductive layer, wherein the isolation medium layer and the channel layer are both located between the gate conductive layer and the conductive layer.

[0012] The method for manufacturing the semiconductor structure includes the following steps. A stack structure is formed on the substrate, and the stack structure includes a first dielectric layer and a conductive layer stacked in sequence from bottom to top. Each of the conductive layers includes a main body part extending in a first direction and a plurality of extension parts arranged at intervals in the first direction. Each of the extension parts is located on opposite sides of the main body part. The main body part is integrally connected with each of the extension parts. A part, where the extension part is connected with the main body part, serves as a channel region. A width of each of the extension parts in the first direction is greater than a width of the first dielectric layer between the extension parts in the first direction. A second dielectric layer is formed on a surface of the stack structure. A gap region of the stack structure is filled with a sacrificial layer. A first trench is formed in the stack structure to pass through the channel region of each layer. The first trench is used to remove the first dielectric layer and the conductive layer in the channel region and to remove a part of the second dielectric layer on opposite sides of the first dielectric layer in the first direction while retaining a part of the second dielectric layer on opposite sides of the extension part in the first direction. A side wall of the first trench on opposite sides in the first direction exposes the sacrificial layer and the second dielectric layer stacked in sequence and alternately. A channel material layer, an isolation dielectric material layer, and a gate conductive layer are sequentially deposited on an inner wall of the first trench. The gate conductive layer fills the first trench. A second trench is formed in the gap region on opposite sides of the channel region to pass through the sacrificial layer. The second trench exposes the sacrificial layer and the second dielectric layer stacked in sequence and alternately on opposite sides in the first direction. The sacrificial layer on the side wall of the second trench is removed, and the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer are removed. As a result, an isolation dielectric layer and a channel layer are obtained, which surround a side wall of the gate conductive layer and are in contact with the second dielectric layer. The isolation dielectric layer and the channel layer are located between the gate conductive layer and the conductive layer. Since the positions of the sacrificial layers correspond to the positions of the first dielectric layers, and the positions of the second dielectric layers correspond to the positions of the conductive layers, the channel material layer covered by the sacrificial layers can be selectively removed by etching based on the second trench, and the channel material layer covered by the second dielectric layers can be retained. Thus, the problem of parasitic MOS of a device is avoided. In this process, the extension part is not etched and removed, so that the integrity of the extension part is ensured. In subsequent processes, a part of the extension part can serve as a first electrode of a capacitor in a memory, so that the available area of the capacitor can be increased.

[0013] In one of the embodiments, the removing the sacrificial layer on the side wall of the second trench includes:

[0014] removing the sacrificial layer located on sidewalls of the second trench by using a vapor etching process;

[0015] the removing exposes part of the channel material layer and part of the isolation medium material layer corresponding to the part of the channel material layer;

[0016] the removing exposes part of the channel material layer and part of the isolation medium material layer corresponding to the part of the channel material layer by using a wet etching process.

[0017] In one of the embodiments, after the removing the channel material layer and the isolation medium material layer in contact with the sacrificial layer, the method further comprises:

[0018] filling the second trench by using a filling layer.

[0019] In one of the embodiments, the forming the stack structure on the substrate comprises:

[0020] forming an initial stack structure on the substrate, the initial stack structure comprising a first medium material layer and a conductive material layer stacked in sequence from bottom to top;

[0021] etching to remove part of the initial stack structure to form a third trench penetrating through the initial stack structure, a sidewall of the third trench exposing a side surface of each layer of the first medium material layer; the extensions in the same layer are separated by the third trench;

[0022] based on the third trench, performing lateral etching on each layer of the first medium material layer to form a fourth trench between each layer of the conductive material layer, so that a width of the extension along the first direction is greater than a width of the first medium layer along the first direction.

[0023] In one of the embodiments, the forming the second medium layer continuously distributed on the exposed surface of the stack structure and filling the gap region of the stack structure by using a sacrificial layer comprises:

[0024] forming a second medium layer continuously distributed on inner walls of the third trench and the fourth trench;

[0025] filling the sacrificial layer in the third trench and the fourth trench.

[0026] In one of the embodiments, after the filling the gap region of the stack structure by using the sacrificial layer and before forming a first trench penetrating through each layer of the channel region in the stack structure, the method further comprises:

[0027] removing the second dielectric layer and the sacrificial layer on the surface of the first electrode to expose the surface of the first electrode;

[0028] forming a second electrode and a capacitor dielectric layer on the exposed surface of the first electrode.

[0029] In one embodiment, the removing the second dielectric layer and the sacrificial layer on the surface of the first electrode to expose the surface of the first electrode comprises:

[0030] forming a fifth trench through the sacrificial layer in the gap region on the opposite sides of the first electrode along the first direction, the sidewall of the fifth trench exposing the sacrificial layer and the second dielectric layer on the opposite sides of the first electrode in each layer alternately;

[0031] performing lateral etching based on the fifth trench to form a sixth trench between the first electrodes in each layer.

[0032] In one embodiment, the forming a second electrode and a capacitor dielectric layer on the exposed surface of the first electrode comprises:

[0033] forming a third dielectric layer continuously distributed on the inner wall of the fifth trench, the inner wall of the sixth trench and the upper surface of the stack structure;

[0034] forming a conductive barrier layer on the surface of the third dielectric layer;

[0035] depositing a conductive filling layer in the fifth trench, in the sixth trench and on the stack structure; wherein the third dielectric layer serves as the capacitor dielectric layer, and the conductive barrier layer and the conductive filling layer together constitute the second electrode.

[0036] Second aspect. The application further provides a semiconductor structure comprising:

[0037] a substrate;

[0038] a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive layers stacked in turn from bottom to top, each of the conductive layers comprising a main body portion extending along a first direction and a plurality of extension portions arranged at intervals along the first direction, each of the extension portions being located on the opposite sides of the main body portion, the main body portion and each of the extension portions being integrally connected, and the portion where the extension portion is connected to the main body portion serving as a channel region;

[0039] a second dielectric layer covering the opposite sides of each of the channel regions along the first direction;

[0040] The device structure penetrates the channel regions, and comprises a gate conductive layer, a plurality of channel layers surrounding sidewalls of the gate conductive layer, and a plurality of isolation medium layers corresponding to surfaces of the channel layers, each of the channel layers and each of the isolation medium layers are located between the gate conductive layer and the conductive layer, and each of the channel layers is in contact with each of the second medium layers.

[0041] The semiconductor structure comprises a substrate, a stack structure, a second medium layer, and a device structure. The stack structure is located on the substrate, and comprises first medium layers and conductive layers which are sequentially stacked from bottom to top. Each of the conductive layers comprises a main body part extending along a first direction and a plurality of extension parts arranged at intervals along the first direction. Each of the extension parts is located on opposite sides of the main body part. The main body part is integrally connected with each of the extension parts. A part of the extension part connected with the main body part is a channel region. The second medium layer covers opposite sides of each of the channel regions along the first direction. The device structure penetrates each of the channel regions, and comprises a gate conductive layer, a plurality of channel layers surrounding sidewalls of the gate conductive layer, and a plurality of isolation medium layers corresponding to surfaces of the channel layers. Each of the channel layers and each of the isolation medium layers are located between the gate conductive layer and the conductive layer. Each of the isolation medium layers is in contact with each of the second medium layers. Since the channel layers are formed by selectively removing the channel material layers, the extension parts are not etched and removed in the process, so that the integrity of the extension parts can be ensured. In subsequent processes, a part of the extension part can be used as a first electrode of a capacitor in the memory, so that the available area of the capacitor can be increased.

[0042] In one of the embodiments, the semiconductor structure further comprises a capacitor, the capacitor comprises a first electrode, and a capacitor medium layer and a second electrode which are sequentially arranged on a surface of the first electrode. A part of the extension part away from the main body part is used as the first electrode of the capacitor. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0044] Figure 1 A flow chart of a preparation method of the semiconductor structure provided in one of the embodiments;

[0045] Figure 2 A step flow chart of step S20 in the preparation method of the semiconductor structure provided in one of the embodiments;

[0046] Figure 3A schematic top view of the structure obtained in step S201 of the method for manufacturing a semiconductor structure according to an embodiment;

[0047] Figure 4 A schematic cross-sectional view of the structure obtained in step S201 according to an embodiment, wherein (a) is a schematic view along the AA' direction, (b) is a schematic view along the BB' direction, (c) is a schematic view along the CC' direction, and (d) is a schematic view along the DD' direction; Figure 3 Figure 3 Figure 3 Figure 3

[0048] Figure 5 A schematic top view of the structure obtained in step S202 of the method for manufacturing a semiconductor structure according to an embodiment;

[0049] Figure 6 A schematic cross-sectional view of the structure obtained in step S202 according to an embodiment, wherein (a) is a schematic view along the AA' direction, (b) is a schematic view along the BB' direction, (c) is a schematic view along the CC' direction, and (d) is a schematic view along the DD' direction; Figure 5 Figure 5 Figure 5 Figure 5

[0050] Figure 7 A schematic top view of the structure obtained in step S203 of the method for manufacturing a semiconductor structure according to an embodiment;

[0051] Figure 8 A schematic cross-sectional view of the structure obtained in step S203 according to an embodiment, wherein (a) is a schematic view along the AA' direction, (b) is a schematic view along the BB' direction, (c) is a schematic view along the CC' direction, and (d) is a schematic view along the DD' direction; Figure 7 Figure 7 Figure 7 Figure 7

[0052] Figure 9 A schematic flow chart of step S30 of the method for manufacturing a semiconductor structure according to an embodiment;

[0053] Figure 10 A schematic top view of the structure obtained in step S302 of the method for manufacturing a semiconductor structure according to an embodiment;

[0054] Figure 11 A schematic cross-sectional view of the structure obtained in step S302 according to an embodiment, wherein (a) is a schematic view along the AA' direction, (b) is a schematic view along the BB' direction, (c) is a schematic view along the CC' direction, and (d) is a schematic view along the DD' direction;​​​​​​​​​​​​Figure 10 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 10 The diagram shown is along the BB' direction. (c) Figure is along... Figure 10 The diagram shown is along the CC' direction. Figure (d) shows the direction along the CC' direction. Figure 10 A schematic diagram showing the DD' direction;

[0055] Figure 12 This is a top view schematic diagram of the structure obtained after forming a framework structure in a semiconductor structure fabrication method provided in one embodiment;

[0056] Figure 13 This is a schematic diagram of the cross-sectional structure of the structure obtained after forming the frame structure in one embodiment, wherein (a) is a cross-sectional view along... Figure 12 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 12 The diagram shown is along the BB' direction. (c) Figure is along... Figure 12 The diagram shown is along the CC' direction. Figure (d) shows the direction along the CC' direction. Figure 12 A schematic diagram showing the DD' direction;

[0057] Figure 14 This is a flowchart of the steps after step S30 and before step S40 in a method for fabricating a semiconductor structure provided in one embodiment.

[0058] Figure 15 This is a flowchart of step S31 in the method for fabricating a semiconductor structure provided in one embodiment;

[0059] Figure 16 This is a top view of the structure obtained in step S311 of one embodiment;

[0060] Figure 17 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S311 of one embodiment, wherein (a) is a cross-sectional view along... Figure 16 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 16 The diagram shown is along the BB' direction. (c) Figure is along... Figure 16 The diagram shown is along the CC' direction. Figure (d) shows the direction along the CC' direction. Figure 16 A schematic diagram showing the DD' direction;

[0061] Figure 18 This is a top view of the structure obtained in step S312 of one embodiment;

[0062] Figure 19 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S312 of one embodiment, wherein (a) is a cross-sectional view along... Figure 18 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 18The diagram shown is along the BB' direction. (c) Figure is along... Figure 18 The diagram shown is along the CC' direction. Figure (d) shows the direction along the CC' direction. Figure 18 A schematic diagram showing the DD' direction;

[0063] Figure 20 This is a flowchart of step S323 in the method for fabricating a semiconductor structure provided in one embodiment;

[0064] Figure 21 This is a top view of the structure obtained in step S323 of one embodiment;

[0065] Figure 22 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S323 of one embodiment, wherein (a) is a cross-sectional view along... Figure 21 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 21 The diagram shown is along the BB' direction. (c) Figure is along... Figure 21 The diagram shown is along the CC' direction. Figure (d) shows the direction along the CC' direction. Figure 21 A schematic diagram showing the DD' direction;

[0066] Figure 23 This is a flowchart of the steps after step S32 and before step S40 in a method for fabricating a semiconductor structure provided in one embodiment.

[0067] Figure 24 This is a top view of the structure obtained in step S33 of one embodiment;

[0068] Figure 25 This is a schematic diagram of the cross-sectional structure of the structure obtained in step S33 of one embodiment, wherein (a) is a cross-sectional view along... Figure 24 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 24 The diagram shown is along the BB' direction. (c) Figure is along... Figure 24 The diagram shown is along the CC' direction. Figure (d) shows the direction along the CC' direction. Figure 24 A schematic diagram showing the DD' direction;

[0069] Figure 26 This is a top view of the structure obtained in step S34 of one embodiment;

[0070] Figure 27 This is a schematic cross-sectional view of the structure obtained in step S34 of one embodiment, wherein (a) is a cross-sectional view along... Figure 26 The diagram shown is along the AA' direction. (b) The diagram is along the AA' direction. Figure 26 The diagram shown is along the BB' direction. (c) Figure is along... Figure 26 The diagram shown is along the CC' direction. Figure (d) shows the direction along the CC' direction. Figure 26schematic view along the direction of AA' shown in (a), (b) is a schematic view along the direction of BB' shown in (a), (c) is a schematic view along the direction of CC' shown in (a), and (d) is a schematic view along the direction of DD' shown in (a);

[0071] Figure 28 a top view schematic diagram of the structure obtained in step S40 provided in an embodiment;

[0072] Figure 29 a cross-sectional schematic diagram of the structure obtained in step S40 provided in an embodiment, wherein (a) is a schematic view along the direction of AA' shown in (a), (b) is a schematic view along the direction of BB' shown in (a), (c) is a schematic view along the direction of CC' shown in (a), and (d) is a schematic view along the direction of DD' shown in (a); Figure 28 Figure 28 Figure 28 Figure 28

[0073] Figure 30 a top view schematic diagram of the structure obtained in step S50 provided in an embodiment;

[0074] Figure 31 a cross-sectional schematic diagram of the structure obtained in step S50 provided in an embodiment, wherein (a) is a schematic view along the direction of AA' shown in (a), (b) is a schematic view along the direction of BB' shown in (a), (c) is a schematic view along the direction of CC' shown in (a), and (d) is a schematic view along the direction of DD' shown in (a); Figure 30 Figure 30 Figure 30 Figure 30

[0075] Figure 32 a top view schematic diagram of the structure obtained in step S60 provided in an embodiment;

[0076] Figure 33 a cross-sectional schematic diagram of the structure obtained in step S60 provided in an embodiment, wherein (a) is a schematic view along the direction of AA' shown in (a), (b) is a schematic view along the direction of BB' shown in (a), (c) is a schematic view along the direction of CC' shown in (a), and (d) is a schematic view along the direction of DD' shown in (a); Figure 32 Figure 32 Figure 32 Figure 32

[0077] Figure 34 a top view schematic diagram of the structure obtained after removing the sacrificial layer located on the side wall of the second trench in step S70 provided in an embodiment;

[0078] Figure 35 a cross-sectional schematic diagram of the structure obtained after removing the sacrificial layer located on the side wall of the second trench in step S70 provided in an embodiment, wherein (a) is a schematic view along the direction of AA' shown in (a), (b) is a schematic view along the direction of BB' shown in (a), (c) is a schematic view along the direction of CC' shown in (a), and (d) is a schematic view along the direction of DD' shown in (a); Figure 34 Figure 34 ​​​​​​​​​​​​​a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 34 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 34 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d).

[0079] Figure 36 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d).

[0080] Figure 37 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 36 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 36 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 36 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 36 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d).

[0081] Figure 38 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d).

[0082] Figure 39 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 38 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 38 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 38 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d). Figure 38 a schematic view along the direction AA' shown in (a), a schematic view along the direction BB' shown in (b), a schematic view along the direction CC' shown in (c), and a schematic view along the direction DD' shown in (d).

[0083] 10-substrate, 101-first trench, 102-second trench, 103-third trench, 104-fourth trench, 105-fifth trench, 106-sixth trench, 20-first dielectric layer, 21-first dielectric material layer, 30-conductive layer, 301-main body part, 302-extension part, 303-channel region, 31-conductive material layer, 40-covering dielectric layer, 401-second dielectric layer, 402-sacrificial layer, 403-frame structure, 404-filling layer, 501-third dielectric layer, 502-conductive barrier layer, 503-conductive filling layer, 601-channel material layer, 611-channel layer, 602-isolating dielectric material layer, 612-isolating dielectric layer, 603-gate conductive layer. DETAILED DESCRIPTION

[0084] For the purposes of the present application, a more complete description of which will follow, reference will be made to the accompanying drawings referenced herein and illustrated in the appended figures. The embodiments illustrated in the figures are intended to exemplify how the present application can be implemented, but the present application is not limited to the embodiments described herein. Rather, these embodiments are provided so that the present disclosure will be more thorough and complete.

[0085] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for describing particular embodiments only and is not intended to be limiting of the application.

[0086] It will be understood that when an element or layer is referred to as being "on" or "adjacent" or "connected" or "coupled" to another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," "directly adjacent," "directly connected" or "directly coupled" to another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0087] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can also be oriented in the other directions (for example, rotated 90 degrees or at other orientations) and the included spatial description terminology is interpreted accordingly.

[0088] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0089] Embodiments of the invention are described herein with reference to cross-sectional views illustrating preferred embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0090] Please see Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:

[0091] S10: Provides a substrate;

[0092] S20: A stacked structure is formed on a substrate. The stacked structure includes a first dielectric layer and a conductive layer stacked sequentially from bottom to top. Each conductive layer includes a main body extending along a first direction and a plurality of extensions spaced apart along the first direction. Each extension is located on opposite sides of the main body. The main body and each extension are integrally connected. The portion where the extension is connected to the main body serves as a channel region. The width of the extension along the first direction is greater than the width of the first dielectric layer located between the extensions along the first direction.

[0093] S30: A continuously distributed second dielectric layer is formed on the exposed surface of the laminated structure, and a sacrificial layer is used to fill the gap region of the laminated structure;

[0094] S40: forming a first trench in the stack structure to remove the first dielectric layer and the conductive layer in the channel region and to remove the second dielectric layer in the portions of the first dielectric layer along the two opposite sides in the first direction and to retain the second dielectric layer in the portions of the first dielectric layer along the two opposite sides of the extension, wherein the first trench exposes the sacrificial layer and the second dielectric layer alternately and sequentially stacked along the two opposite side walls in the first direction, and the position of each layer of the sacrificial layer corresponds to the position of each layer of the first dielectric layer, and the position of each layer of the second dielectric layer corresponds to the position of each layer of the conductive layer;

[0095] S50: sequentially depositing an isolation dielectric material layer, a channel material layer and a gate conductive layer on the inner wall of the first trench, and the gate conductive layer fills the first trench;

[0096] S60: forming a second trench in the gap region along the two opposite sides of the channel region to pass through the sacrificial layer, and the second trench exposes the sacrificial layer and the second dielectric layer alternately and sequentially stacked along the two opposite side walls in the first direction;

[0097] S70: removing the sacrificial layer on the side wall of the second trench, and removing the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer, to obtain a channel layer and an isolation dielectric layer surrounding the side wall of the gate conductive layer and in contact with the second dielectric layer, and the channel layer and the isolation dielectric layer are both located between the gate conductive layer and the conductive layer.

[0098] The semiconductor structure obtained after steps S10-S60 can be referred to Figure 39 . Of course, Figure 39 The examples of the semiconductor structure prepared by the preparation method of the semiconductor structure of the present application are given, and the semiconductor structure prepared by the preparation method of the semiconductor structure of the present application can also have other suitable examples, which are not limited herein.

[0099] In addition, in order to facilitate understanding of the present application, the first direction involved in the present application can be the extension direction of the CC' intercept line or the DD' intercept line in the top view, and the second direction can be the extension direction of the AA' intercept line or the BB' intercept line in the top view. Of course, in other suitable application scenarios, the first direction and the second direction can also have other definitions, which are not limited herein.

[0100] The method for manufacturing the semiconductor structure includes the following steps: forming a stack structure on a substrate, the stack structure comprising first dielectric layers and conductive layers stacked in sequence from bottom to top, each conductive layer comprising a main body portion extending along a first direction and a plurality of extension portions arranged at intervals along the first direction, each extension portion being located on opposite sides of the main body portion, the main body portion being integrally connected with each extension portion, and the portion of the extension portion connected with the main body portion serving as a channel region; wherein the width of each extension portion along the first direction is greater than the width of the first dielectric layer between the extension portions along the first direction; forming a second dielectric layer continuously distributed on the exposed surface of the stack structure, and filling the gap regions of the stack structure with a sacrificial layer; forming a first trench penetrating the channel regions of each layer in the stack structure, so as to remove the first dielectric layer and the conductive layer located in the channel region, and remove part of the second dielectric layer located on the opposite sides of the first dielectric layer along the first direction, and retain part of the second dielectric layer located on the opposite sides of the extension portion along the first direction; wherein the first trench exposes the sacrificial layer and the second dielectric layer alternately stacked in sequence on the opposite side walls along the first direction; sequentially depositing a channel material layer, an isolation dielectric material layer and a gate conductive layer on the inner wall of the first trench, the gate conductive layer filling the first trench; forming a second trench penetrating the sacrificial layer in the gap region on the opposite sides of the channel region along the first direction, the second trench exposing the sacrificial layer and the second dielectric layer alternately stacked in sequence on the opposite side walls along the first direction; removing the sacrificial layer on the side wall of the second trench, and removing the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer, so as to obtain the isolation dielectric layer and the channel layer surrounding the side wall of the gate conductive layer and in contact with the second dielectric layer, the isolation dielectric layer and the channel layer being located between the gate conductive layer and the conductive layer. Since the positions of the sacrificial layers correspond to the positions of the first dielectric layers, and the positions of the second dielectric layers correspond to the positions of the conductive layers, the channel material layer covered by the sacrificial layers can be selectively removed by etching based on the second trench, and the channel material layer covered by the second dielectric layers can be retained, so as to avoid the problem of parasitic MOS of the device. Moreover, the extension portion does not need to be etched and removed in this process, so as to ensure the integrity of the extension portion. In the subsequent process, part of the extension portion can serve as the first electrode of the capacitor in the memory, so as to increase the available area of the capacitor.

[0101] In step S10, please refer to Figure 1 and Figure 4 , a substrate 10 is provided.

[0102] The material of the substrate 10 can be any suitable substrate material known in the art, such as at least one of silicon (Si), germanium (Ge), red phosphorus, silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium-carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures of these semiconductors, etc., or silicon-on-insulator (SOI), silicon-on-silicon-on-insulator (SSOI), silicon-germanium-on-silicon-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or double side polished wafers (DSP), ceramic substrates such as aluminum oxide, quartz, or glass substrates, etc., without limitation.

[0103] In step S20, referring to step S20 in Figure 1 and Figures 7-8 , a stack structure is formed on the substrate 10, which includes a first dielectric layer 20 and a conductive layer 30 stacked in order from bottom to top.

[0104] Each of the conductive layers 30 includes a main body portion 301 extending along a first direction and a plurality of extension portions 302 arranged at intervals along the first direction, each of the extension portions 302 is located on opposite sides of the main body portion 301, the main body portion 301 is integrally connected with each of the extension portions 302, and a portion of the extension portion 302 connected with the main body portion 301 serves as a channel region 303. The width of the extension portion 302 along the first direction is greater than the width of the first dielectric layer 20 located between the extension portions 302 along the first direction.

[0105] In one embodiment, as shown in Figure 2 , the above step S20 includes:

[0106] S201: forming an initial stack structure on the substrate 10, the initial stack structure includes a first dielectric material layer 21 and a conductive material layer 31 stacked in order from bottom to top.

[0107] As shown in Figures 3-4 , the first dielectric material layer 21 and the conductive material layer 31 can be sequentially deposited by a deposition process to form the initial stack structure.

[0108] The material of the first dielectric material layer 21 can include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material can include at least one of silicon oxide, silicon oxynitride, silicon carbon oxide, and silicon carbon oxynitride; and the nitride material can include silicon nitride, etc.

[0109] The material of the conductive material layer 31 can include tungsten, copper, gold, titanium, silver, aluminum, and other metal materials, can also include a multi-layer metal composed of the above-mentioned metal materials, and can also include a metal alloy, and the like, which are not limited in the embodiment.

[0110] Optionally, as shown in Figures 3-4 The material of the covering dielectric layer 40 can include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material can include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxycarbonitride; and the nitride material can include silicon nitride, and the like.

[0111] Further, the material of the covering dielectric layer 40 can be different from the material of the first dielectric material layer 21. For example, the material of the first dielectric material layer 21 can be silicon oxide, and the material of the covering dielectric layer 40 can be silicon nitride.

[0112] It should be understood that the covering dielectric layer 40 is not necessarily required, and in some suitable application scenarios, the first dielectric layer 20 or the conductive layer 30 can be directly used as the covering dielectric layer 40 when the stack of the layer structure is suitable. The covering dielectric layer 40 is shown herein only as a suitable embodiment, and the covering dielectric layer 40 can be omitted in other preparation processes or application scenarios.

[0113] S202: etching and removing part of the initial layer structure to form a third trench 103 penetrating through the initial layer structure, the sidewall of the third trench 103 exposing the side surface of each layer of the first dielectric material layer 21; the same layer of the extension part 302 is separated by the third trench 103.

[0114] As shown in Figures 5-6 The photoresist layer can be formed on the upper surface of the initial layer structure, and then the patterned photoresist layer can be formed through exposure and development steps to define the topography of each layer of the conductive material layer 31 and each layer of the first dielectric material layer 21. Then, part of the initial layer structure can be removed based on the patterned photoresist layer through an etching process to form the third trench 103.

[0115] S203: performing lateral etching on each layer of the first dielectric material layer 21 based on the third trench 103 to form a fourth trench 104 between each layer of the conductive material layer 31, so that the width of the extension part 302 along the first direction is greater than the width of the first dielectric layer 20 along the first direction between the extension parts 302.

[0116] As shown in Figures 7-8As shown, the process of lateral etching can be completed by using a suitable etching process, for example, it can include a wet process or a vapor etching process. Specifically, the third groove 103 can be filled with a corresponding etching liquid or etching gas, and by using the difference of etching selectivity ratio of each layer of material, part of the first dielectric material layer 21 can be selectively etched and removed to form a lateral fourth groove 104, so that the initial stack structure finally forms the morphology of the stack structure in step S20.

[0117] Optionally, as shown in the process of forming the fourth groove 104 by lateral etching, a small part of the substrate 10 can also be over-etched and lost, and a morphology as shown in Figure 8 Figure 8

[0118] In addition, in step 20, the top view morphology of the covering dielectric layer 40 is the same as that of each layer of conductive layer 30, and the first dielectric layer 20 of each layer has lost a part due to lateral etching, so the morphology is different. In order to facilitate the understanding of the scheme, in all top view schematic diagrams in the present application (for example, Figure 5 ), the main body part 301, the extension part 302 and the channel region 303 are drawn in the same layer as the covering dielectric layer 40, but it should be understood that the main body part 301, the extension part 302 and the channel region 303 in the top view of the present application can also represent the positions of the main body part 301, the extension part 302 and the channel region 303 included in each layer of conductive layer 30 below the covering dielectric layer 40.

[0119] In step S30, please refer to step S30 in Figure 1 and Figures 10-11 , a continuously distributed second dielectric layer 401 is formed on the exposed surface of the stack structure, and a sacrificial layer 402 is used to fill the gap region of the stack structure.

[0120] Because the morphology of the first dielectric layer 20 and the conductive layer 30 in the stack structure is not consistent, specifically, due to the existence of the lateral fourth groove 104, this difference causes the second dielectric layer 401 to present an alternating covering feature. A typical figure that can describe this alternating covering feature can be referred to as shown in (c) of Figure 11 . In (c) of Figure 11 , it can be seen that the width of the first dielectric layer 20 is smaller, and the width of the conductive layer 30 is larger, which causes the second dielectric layer 401 corresponding to the surface of the conductive layer 30 to be relatively protruding outward than the second dielectric layer 401 corresponding to the surface of the first dielectric layer 20, which will be helpful to indicate in the subsequent process which material layer corresponds to the position of the conductive layer 30 and which material layer corresponds to the position of the first dielectric layer 20.

[0121] ​​In one embodiment, such as Figure 9 As shown, step S30 above includes:

[0122] S301: A second medium layer 401 is continuously distributed on the inner wall of the third trench 103 and the fourth trench 104.

[0123] like Figures 10-11 As shown, a continuously distributed second dielectric layer 401 can be formed using atomic layer deposition (ALD). The material of the second dielectric layer 401 can include any suitable dielectric material, such as oxide or silicide. Optionally, the deposition temperature of the deposition process for forming the second dielectric layer 401 can be 630°C, and the thickness of the second dielectric layer 401 can be 3 nm. Of course, in other suitable fabrication processes, the deposition temperature of the deposition process for forming the second dielectric layer 401 can be other suitable deposition temperatures; the thickness of the second dielectric layer 401 can also be other suitable thicknesses, and this embodiment does not impose any limitations.

[0124] S302: Sacrificial layer 402 is filled in the third trench 103 and the fourth trench 104.

[0125] like Figures 10-11 As shown, an atomic layer deposition process can be used to form a seed layer, followed by a deposition process to form a thicker sacrificial layer 402. At this point, the sacrificial layer 402 will also cover the upper surface of the stacked structure. Then, a grinding process can be used to remove the excess sacrificial layer 402 located on the upper surface of the stacked structure, ultimately forming the structure shown. Figure 11 The shape shown.

[0126] The material of the sacrificial layer 402 may include any suitable dielectric material, such as an oxide material or a silicide material. Optionally, the material of the sacrificial layer 402 may be different from the material of the second dielectric layer 401. For example, the material of the sacrificial layer 402 may be silicon oxide, while the material of the second dielectric layer 401 may be silicon nitride.

[0127] Optionally, the thickness of the sacrificial layer 402 can be 600 nm.

[0128] In addition, because the second dielectric layer 401 is relatively thin, during plotting... Figure 10 The second dielectric layer 401 is omitted; however, it should be noted that the second dielectric layer 401 will actually cover the inner walls of all third trenches 103 and all fourth trenches 104 (to...). Figure 11 (Subject to)

[0129] In one embodiment, after step S302, the method for fabricating the semiconductor structure further includes: forming a frame structure 403 on both sides of the stacked structure, such as... Figures 12-13 As shown.

[0130] The frame structure 403 can be formed by removing the portions on both sides of the stack structure by a lithography and etching process, and then filling by a deposition process. The material of the frame structure 403 can include a nitride material or an oxide material, for example, silicon oxide.

[0131] In one embodiment, the portion of the extension 302 away from the main body 301 serves as the first electrode. After the gap region of the stack structure is filled by the sacrificial layer 402 in step S30, and before step S40, the surface of the first electrode is exposed, as shown in FIG. 3B. Figure 14 As shown in FIG. 3B, the method for manufacturing the semiconductor structure further includes:

[0132] S31: removing the second dielectric layer 401 and the sacrificial layer 402 on the surface of the first electrode to expose the surface of the first electrode.

[0133] S32: sequentially forming a capacitor dielectric layer and a second electrode on the exposed surface of the first electrode.

[0134] In one embodiment, as shown in FIG. 3B, the step S31 includes: Figure 15

[0135] S311: removing the portion of the sacrificial layer 402 between the first electrodes in the same layer to form a fifth groove 105 penetrating the stack structure, and the sidewall of the fifth groove 105 exposes the second dielectric layer 401 on the opposite sides of the first electrodes in each layer and the sacrificial layer 402 in turn.

[0136] As shown in FIG. 3B, a photoresist layer can be formed on the upper surface of the stack structure first, and then a patterned photoresist layer is formed again through exposure and development steps to expose the gap region on both sides of the first electrode, and then a portion of the sacrificial layer 402 is removed based on the patterned photoresist layer through an etching process to form the fifth groove 105. Figures 16-17

[0137] S312: performing lateral etching on each layer of the first dielectric layer 20 based on the fifth groove 105 to form a sixth groove 106 between the first electrodes in each layer.

[0138] As shown in FIG. 3B, the process of lateral etching can be completed by using a suitable etching process, for example, which can include a wet process or a vapor etching process. Specifically, a corresponding etching liquid or etching gas can be introduced based on the fifth groove 105, and then the etching selectivity difference of each layer of material layer is used to selectively etch and remove a portion of the sacrificial layer 402 to form the lateral sixth groove 106. Figures 18-19 In addition, after S312, in combination with

[0139] It can be seen that the surface of the first electrode will be completely exposed. Figures 18-19 ​​​

[0140] In one embodiment, as shown in Figure 20 S32 comprises:

[0141] S321: Forming a third dielectric layer 501 on the inner wall of the fifth trench 105, the inner wall of the sixth trench 106, and the upper surface of the stack structure.

[0142] As shown in Figures 21-22 , the material of the third dielectric layer 501 can include a dielectric material, such as a high-K material, which is used as a separation layer in the capacitor to separate the first electrode and the second electrode.

[0143] S322: Forming a conductive barrier layer 502 on the surface of the third dielectric layer 501.

[0144] As shown in Figures 21-22 , the conductive barrier layer 502 can include titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or conductive nitrides such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and can be formed by CVD, PVD, ALD, and / or other suitable processes.

[0145] S323: Depositing a conductive fill layer 503 in the fifth trench 105, in the sixth trench 106, and on the stack structure; wherein the third dielectric layer 501 serves as a capacitor dielectric layer, and the conductive barrier layer 502 and the conductive fill layer 503 together form the second electrode.

[0146] As shown in Figures 21-22 , the material of the conductive fill layer 503 can include tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals, and can be formed by CVD, PVD, ALD, electroplating, or other suitable processes.

[0147] In addition, since the capacitor dielectric layer and the conductive fill layer 503 are relatively thin and are wrapped by the conductive fill layer 503, only the capacitor dielectric layer is shown in Figure 21 . The specific positions of the capacitor dielectric layer and the conductive fill layer 503 can be determined in combination with Figure 22 .

[0148] In addition, in some top view drawings, although the first electrode is completely wrapped by the conductive fill layer 503 (for example Figure 21), but in order to more clearly distinguish the position of the first electrode, the position of the first electrode is still marked. In the actual preparation process, the specific structure of the semiconductor structure prepared by the preparation method of the semiconductor structure provided by the application can be based on the cross-sectional structure schematic diagram (for example Figure 22 ), and the top view schematic diagram can assist in understanding the specific position of each structure, so as to more clearly understand the 3D topography of the semiconductor structure provided by the application.

[0149] Of course, in other suitable preparation processes, the second electrode can also be other single-layer conductive materials, which are not limited in the present embodiment.

[0150] In one embodiment, after step S32, as shown in Figure 23 , the preparation method of the semiconductor structure further comprises:

[0151] S33: sequentially removing the conductive filling layer 503, the conductive barrier layer 502 and the third dielectric layer 501 covering the upper surface of the stack structure, to expose part of the surface of the first dielectric layer 20 corresponding to the channel region 303.

[0152] As shown in Figures 24-25 , the conductive filling layer 503, the conductive barrier layer 502 and the third dielectric layer 501 covering the upper surface of the stack structure can be sequentially removed by etching process. During the etching removal process, the first dielectric layer 20 is used as the etching end point, and when part of the surface of the first dielectric layer 20 corresponding to the channel region 303 is exposed, the etching is stopped, which can facilitate the preparation step of the channel region 303 in the subsequent process.

[0153] S34: depositing a filling layer 404 on the surface of the obtained structure.

[0154] As shown in Figures 26-27 , the material of the filling layer 404 can be the same as that of the sacrificial layer 402, and both can be dielectric materials, for example, both can be silicon oxide. In some embodiments, the filling layer 404 has the same function as the sacrificial layer 402, and both are used to support other structures or fill some gap regions. Therefore, in some preparation processes, the filling layer 404 can be equivalent to the sacrificial layer 402, and in some drawings, the filling layer 404 can be directly regarded as the sacrificial layer 402 (it can be seen that in some drawings, the filling shape of the filling layer 404 is also the same as that of the sacrificial layer 402). Of course, in other suitable preparation processes, the material of the filling layer 404 can be different from that of the sacrificial layer 402, and the functions of the two can also be different.

[0155] In addition, Figure 26The filling layer 404 should cover all surfaces of the resulting structure; however, to better illustrate the location of the main structures, additional layers are also included. Figure 26 The diagram illustrates the positions of the first electrode, conductive filling layer 503, and other structures (which are also shown in other top-view structural diagrams). However, a more accurate structure can be... Figure 27 The cross-sectional structural diagram shown is the standard.

[0156] In step S40, please refer to Figure 1 Step S40 and Figures 28-29 A first trench 101 is formed within the stacked structure, penetrating the channel regions 303 of each layer, to remove the first dielectric layer 20 and the conductive layer 30 located in the channel regions 303, and to remove portions of the second dielectric layer 401 located on the two opposing sides of the first dielectric layer 20 along the first direction, while retaining portions of the second dielectric layer 401 located on the two opposing sides of the extension 302 along the first direction; wherein, the sacrificial layer 402 and the second dielectric layer 401 alternately stacked sequentially are exposed on the two opposing sidewalls of the first trench 101 along the first direction, and the position of each sacrificial layer 402 corresponds to the position of each first dielectric layer 20, and the position of each second dielectric layer 401 corresponds to the position of each conductive layer 30.

[0157] like Figures 28-29 As shown, the first direction can be Figure 28 The extension direction of the CC' or DD' cut-out line can first form a photoresist layer on the upper surface of the stacked structure, and then form a patterned photoresist layer again through exposure and development steps. Then, through an etching process, a portion of the stacked structure located in the channel region 303 is removed based on the patterned photoresist layer to form the first trench 101 that penetrates each channel region 303.

[0158] In step S50, please refer to Figure 1 Step S50 and Figures 30-31 A channel material layer 601, an isolation dielectric material layer 602, and a gate conductive layer 603 are sequentially deposited on the inner wall of the first trench 101, and the gate conductive layer 603 fills the first trench 101.

[0159] The channel material layer 601 may be made of metal oxide materials, such as indium gallium zinc oxide (IGZO), ITO, IWO, IGO or IZO (indium-zinc-oxide).

[0160] The material of the isolation dielectric material layer 602 may include a suitable dielectric material, such as a high-k dielectric material.

[0161] The material of the gate conductive layer 603 can include ITO, polysilicon, a metal material, or other suitable conductive material.

[0162] In addition, it can be understood that the step of forming the capacitor (for example, steps S31-S32) is performed before step S50 in the present figure, but in other suitable manufacturing processes, the step of forming the capacitor can also be performed after step S50.

[0163] In step S60, please refer to Figure 1 and Figures 32-33 , a second trench 102 penetrating the sacrificial layer 402 is formed in the gap region on both sides of the channel region 303 along the first direction, and the sidewalls on both sides of the second trench 102 along the first direction expose the sacrificial layer 402 and the second dielectric layer 401 which are alternately stacked in sequence.

[0164] As shown in Figures 32-33 , a photoresist layer can be formed on the upper surface of the stack structure first, and then a patterned photoresist layer is formed again through exposure and development steps to expose the filling layer 404 covering the surface of the channel region 303, and then part of the filling layer 404 is removed based on the patterned photoresist layer through an etching process to form the second trench 102 penetrating the channel region 303 in each layer.

[0165] At this time, since in step S50, the channel material layer 601, the isolation dielectric material layer 602, and the gate conductive layer 603 have been sequentially deposited in the channel region 303, and the second trench 102 is located in the gap region on both sides of the channel region 303. And, please refer to Figure 11 (c) figure, and compare Figure 33As can be understood from the (c) diagram in FIG. 4, it is due to the feature that the second dielectric layer 401 is alternately covered on the surface of the conductive layer 30 and the second dielectric layer 401 that the sidewall of the second trench 102 presents the morphology of the sacrificial layer 402 and the second dielectric layer 401 alternately stacked in sequence when the vertical second trench 102 is formed. The position of the second dielectric layer 401 on the sidewall of the second trench 102 can correspond to the position of each layer of the conductive layer 30, and the position of the sacrificial layer 402 on the sidewall of the second trench 102 can correspond to the position of each layer of the first dielectric layer 20. Alternatively, in other words, after the step S50, the continuous distribution of the channel material layer 601 is deposited on the inner wall of the first trench 101, and only the channel material layer 601 corresponding to each layer of the conductive layer 30 is the target structure and needs to be reserved (i.e., only the channel material layer 601 of each layer of the channel region 303 needs to be reserved), and the channel material layer 601 corresponding to each layer of the first dielectric layer 20 needs to be removed. Otherwise, the channel material layer 601 will be completely connected, resulting in the formation of a parasitic transistor.

[0166] In one embodiment, the above step S60 includes removing the sacrificial layer 402 on the sidewall of the second trench 102 by using a vapor etching process. By directly introducing the corresponding etching vapor into the second trench 102, the sacrificial layer 402 can be easily removed, and the channel material layer 601 corresponding to each layer of the first dielectric layer 20 is exposed. However, the channel material layer 601 corresponding to each layer of the conductive layer 30 is protected by the second dielectric layer 401 and is not exposed.

[0167] In step S70, please refer to Figure 1 and Figures 34-37 , the sacrificial layer 402 on the sidewall of the second trench 102 is removed, and the channel material layer 601 and the corresponding isolation dielectric material layer 602 in contact with the sacrificial layer 402 are removed, to obtain the isolation dielectric layer 612 surrounding the sidewall of the gate conductive layer 603 and in contact with the second dielectric layer 401, and the channel layer 611, both of which are located between the gate conductive layer 603 and the conductive layer 30.

[0168] As shown in Figures 34-35 , it is a schematic diagram of the structure obtained after the sacrificial layer 402 on the sidewall of the second trench 102 is removed.

[0169] As shown in Figures 36-37As shown, the exposed part of the channel material layer 601 and the part of the isolation medium material layer 602 corresponding to the exposed part of the channel material layer 601 can be removed by selective etching, and the channel material layer 601 corresponding to each layer of the conductive layer 30 is protected by the second medium layer 401, and thus will not be removed by etching.

[0170] In addition, as shown in (a) of FIG. 1 and (a) of FIG. 2, the first electrode of the capacitor is not removed by etching by removing the channel material layer 601 in a selective manner, so as to ensure the integrity of the first electrode, thereby increasing the available area of the capacitor. Figure 37 Figure 11 In addition, as shown in (a) of FIG. 1 and (a) of FIG. 2, the first electrode of the capacitor is not removed by etching by removing the channel material layer 601 in a selective manner, so as to ensure the integrity of the first electrode, thereby increasing the available area of the capacitor.

[0171] In one embodiment, the step S70 includes: removing the exposed part of the channel material layer 601 and the part of the isolation medium material layer 602 corresponding to the exposed part of the channel material layer 601 by using a wet etching process.

[0172] The step S70 can be performed more quickly and conveniently by using the wet etching process to selectively remove the channel material layer 601 and the isolation medium material layer 602 corresponding to each layer of the first medium layer 20, while retaining the channel material layer 601 and the isolation medium material layer 602 corresponding to each layer of the conductive layer 30, thereby obtaining the target structure. In addition, the preparation process of the wet etching process is simple, and the process cost can be saved.

[0173] In one embodiment, after the step S70, the semiconductor structure preparation method further includes: filling the second groove 102 by using a filling layer 404.

[0174] The filling layer 404 can support and protect the target structure, and thus the material of the filling layer 404 can be the same as that of the sacrificial layer 402. Alternatively, in other suitable preparation processes, the material of the filling layer 404 can be different from that of the sacrificial layer 402, which is not limited in the present embodiment.

[0175] The present application also provides a semiconductor structure, as shown in (a) of FIG. 1, which includes: a substrate 10, a laminated structure, a second medium layer 401, and a device structure. Figures 38-39

[0176] ​​The substrate 10 can be any suitable substrate material known in the art, such as at least one of the following: silicon (Si), germanium (Ge), red phosphorus, silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), silicon on insulator (SSOI), silicon on insulator (S-SiGeOI), silicon on insulator (SiGeOI), and germanium on insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, quartz, or glass substrate, etc., which are not limited in this embodiment.

[0177] The stacked structure is located on the substrate 10. The stacked structure includes a first dielectric layer 20 and a conductive layer 30 stacked sequentially from bottom to top. Each conductive layer 30 includes a main body portion 301 extending along a first direction and a plurality of extension portions 302 arranged at intervals along the first direction. Each extension portion 302 is located on opposite sides of the main body portion 301. The main body portion 301 and each extension portion 302 are integrally connected. The portion of the extension portion 302 connected to the main body portion 301 serves as a channel region 303.

[0178] The material of the first dielectric layer 20 may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxycarbonide; the nitride material may include silicon nitride, etc.

[0179] The material of the conductive layer 30 may include metals such as tungsten, copper, gold, titanium, silver, and aluminum, or it may include a multilayer metal composed of the above-mentioned metals, or a metal alloy, etc. This embodiment does not impose any limitations.

[0180] The second dielectric layer 401 covers the two opposite sides of the channel region 303 of each layer along the first direction.

[0181] Optional, such as Figures 38-39 As shown, the top of the stacked structure may further include a covering dielectric layer 40, the material of which may include any suitable dielectric material, such as an oxide material or a nitride material. Further, the oxide material may include at least one of silicon oxide, silicon oxynitride, silicon oxycarbide, and silicon oxycarbonide; the nitride material may include silicon nitride, etc.

[0182] Further, the material of the covering dielectric layer 40 can be different from the material of the first dielectric layer 20, for example, the material of the first dielectric layer 20 can be silicon oxide, and the material of the covering dielectric layer 40 can be silicon nitride.

[0183] The device structure penetrates through the channel region 303 of each layer, and includes a gate conductive layer 603, a plurality of layers of isolation dielectric layers 612 surrounding the sidewall of the gate conductive layer 603, and a plurality of layers of channel layers 611 corresponding to the surface of the isolation dielectric layers 612, each layer of the isolation dielectric layers 612 and each layer of the channel layers 611 are located between the gate conductive layer 603 and the conductive layer 30, and each layer of the channel layers 611 is in contact with each layer of the second dielectric layers 401.

[0184] The material of the channel layers 611 can include metal oxide material, for example, can be Indium Gallium Zinc Oxide (IGZO), ITO, IWO, IGO or IZO (indium-zinc-oxide) and the like.

[0185] The material of the isolation dielectric layers 612 can include suitable dielectric material, for example, can include high-K dielectric material.

[0186] The material of the gate conductive layer 603 can include ITO, polysilicon, metal material or other suitable conductive material.

[0187] The semiconductor structure includes a substrate 10, a stack structure, a second dielectric layer 401 and a device structure. The stack structure is on the substrate 10, and includes first dielectric layers 20 and conductive layers 30 stacked in sequence from bottom to top. Each conductive layer 30 includes a main body part 301 extending in a first direction and a plurality of extension parts 302 arranged in the first direction at intervals. Each extension part 302 is located on opposite sides of the main body part 301. The main body part 301 is integrally connected to each extension part 302. The part of the extension part 302 connected to the main body part 301 is a channel region 303. The second dielectric layer 401 covers opposite sides of each channel region 303 in the first direction. The device structure penetrates each channel region 303. The device structure includes a gate conductive layer 603, a plurality of channel layers 611 surrounding the sidewalls of the gate conductive layer 603, and a plurality of isolation dielectric layers 612 corresponding to the surfaces of the channel layers 611. Each channel layer 611 and each isolation dielectric layer 612 are located between the gate conductive layer 603 and the conductive layer 30. Each isolation dielectric layer 612 is in contact with the second dielectric layer 401. Since the channel layer 611 is formed by selectively removing a channel material layer 601, the extension part 302 is not etched and removed in the process, thereby ensuring the integrity of the extension part 302. In subsequent processes, part of the extension part 302 can serve as a first electrode of a capacitor in the memory, thereby increasing the available area of the capacitor.

[0188] In one embodiment, as shown in Figures 38-39 the semiconductor structure further includes a capacitor. The capacitor includes a first electrode, and a capacitor dielectric layer and a second electrode covering the surface of the first electrode in sequence. The part of the extension part 302 away from the main body part 301 serves as the first electrode of the capacitor.

[0189] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features of the above embodiments are described. However, as long as the combinations of the technical features do not contradict each other, they should be considered within the scope of the present disclosure.

[0190] The above embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope. It should be noted that, for those skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A method of fabricating a semiconductor structure, characterized by, The method comprises the following steps: providing a substrate; forming a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive layers stacked in sequence from bottom to top, each of the conductive layers comprising a main body part extending along a first direction and a plurality of extension parts arranged at intervals along the first direction, each of the extension parts being located on opposite sides of the main body part, the main body part being integrally connected with each of the extension parts, and the part where the extension part is connected with the main body part serving as a channel region; wherein the width of each of the extension parts along the first direction is greater than the width of the first dielectric layer located between the extension parts along the first direction; forming a second dielectric layer continuously distributed on the exposed surface of the stack structure, and filling the gap region of the stack structure with a sacrificial layer; forming a first trench through the channel region in each layer of the stack structure to remove the first dielectric layer and the conductive layer located in the channel region, and to remove part of the second dielectric layer located on the side surface of the first dielectric layer opposite along the first direction, while retaining part of the second dielectric layer located on the side surface of the extension part opposite along the first direction; wherein the side walls of the first trench opposite along the first direction expose the sacrificial layers and the second dielectric layers stacked in sequence and alternately, the position of each of the sacrificial layers corresponds to the position of each of the first dielectric layers, and the position of each of the second dielectric layers corresponds to the position of each of the conductive layers; depositing a channel material layer, an isolation dielectric material layer and a gate conductive layer in sequence on the inner wall of the first trench, the gate conductive layer filling the first trench; forming a second trench through the sacrificial layer in the gap region on the opposite sides of the channel region along the first direction, the side walls of the second trench opposite along the first direction exposing the sacrificial layers and the second dielectric layers stacked in sequence and alternately; removing the sacrificial layer located on the side wall of the second trench, and removing the channel material layer and the corresponding isolation dielectric material layer in contact with the sacrificial layer, and filling the second trench with a filling layer to obtain an isolation dielectric layer and a channel layer surrounding the side wall of the gate conductive layer and in contact with the second dielectric layer, the isolation dielectric layer and the channel layer being located between the gate conductive layer and the conductive layer.

2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method further comprises the following steps: removing the sacrificial layer located on the side wall of the second trench by using a vapor etching process; The method further comprises the following steps: removing the exposed part of the channel material layer and the part of the isolation dielectric material layer corresponding to the exposed part of the channel material layer by using a wet etching process.

3. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The method further comprises the following steps: forming an initial stack structure on the substrate, the initial stack structure comprising first dielectric material layers and conductive material layers stacked in sequence from bottom to top; etching the initial stack structure to form a third trench through the initial stack structure, a sidewall of the third trench exposing a side surface of each layer of the first dielectric material layer; based on the third trench, performing lateral etching to form a fourth trench between each layer of the conductive material layer, so that a width of the extension along the first direction is greater than a width of the first dielectric layer along the first direction.

4. The method of claim 3, wherein the semiconductor structure is prepared by a method comprising: forming a second dielectric layer continuously distributed on the exposed surface of the stack structure, and filling a gap region of the stack structure with a sacrificial layer, comprising: forming a second dielectric layer continuously distributed on the inner wall of the third trench and the fourth trench; filling the sacrificial layer in the third trench and the fourth trench.

5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The part of the extension away from the main part as a first electrode, after filling the gap region of the stack structure with a sacrificial layer, before forming a first trench through each layer of the channel region in the stack structure, the method further comprises: removing the second dielectric layer and the sacrificial layer on the surface of the first electrode to expose the surface of the first electrode; forming a capacitor dielectric layer and a second electrode on the exposed surface of the first electrode in sequence.

6. The method of claim 5, wherein the semiconductor structure is prepared by a method comprising: The removing the second dielectric layer and the sacrificial layer on the surface of the first electrode to expose the surface of the first electrode, comprising: forming a fifth trench through the sacrificial layer in the gap region on the opposite sides of the first electrode along the first direction, a sidewall of the fifth trench exposing the second dielectric layer on the opposite sides of each layer of the first electrode in sequence and the sacrificial layer; based on the fifth trench, performing lateral etching to form a sixth trench between each layer of the first electrode.

7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: The forming a capacitor dielectric layer and a second electrode on the exposed surface of the first electrode in sequence, comprising: forming a third dielectric layer continuously distributed on the inner wall of the fifth trench, the inner wall of the sixth trench and the upper surface of the stack structure; forming a conductive barrier layer on the surface of the third dielectric layer; depositing a conductive filling layer in the fifth trench, the sixth trench and on the stack structure; wherein the third dielectric layer as the capacitor dielectric layer, the conductive barrier layer and the conductive filling layer together constitute the second electrode.

8. A semiconductor structure, characterized by comprising: a substrate; a stack structure on the substrate, the stack structure comprising first dielectric layers and conductive layers stacked in sequence from bottom to top, each layer of the conductive layer comprising: a main part extending along a first direction and a plurality of extensions spaced apart along the first direction, each of the extensions being located on the opposite sides of the main part, the main part and each of the extensions being integrally connected, and a channel region being connected between the extension and the main part; a width of the extension along the first direction is greater than a width of the first dielectric layer between the extensions along the first direction; a cover dielectric layer on the top of the stack structure; a second dielectric layer covering both sides of the channel region along the first direction; a device structure penetrating through the channel region, the device structure comprising a gate conductive layer, a plurality of isolation dielectric layers surrounding the sidewall of the gate conductive layer, and a plurality of channel layers corresponding to covering the surface of the isolation dielectric layers, each of the isolation dielectric layers and each of the channel layers are located between the gate conductive layer and the conductive layer, and each of the channel layers is in contact with the second dielectric layer.

9. The semiconductor structure of claim 8, wherein, The semiconductor structure further comprises a capacitor, the capacitor comprising a first electrode and a second electrode in sequence covering the surface of the first electrode, and a capacitor dielectric layer, and the part of the extension away from the main body part as the first electrode of the capacitor.

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