Semiconductor memory device

Abstract

A semiconductor memory device includes: a conductive pattern on a substrate; a lower electrode connected to the conductive pattern and including first and second portions; one or more electrode sidewall supports supporting the lower electrode and contacting sidewalls of the lower electrode; an electrode cover support disposed on the lower electrode and contacting a top surface of the lower electrode; a capacitor dielectric film on the lower electrode, the electrode sidewall support, and the electrode cover support; and an upper electrode on the capacitor dielectric film. The first portion of the lower electrode has an increasing width in the first direction as it is away from the conductive pattern, and a slope of a sidewall of the first portion of the lower electrode is different from a slope of a sidewall of the second portion of the lower electrode.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2023-0161989 filed in the Korean Intellectual Property Office on November 21, 2023, and all benefits arising therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device using a capacitor as a data storage element. Background Art

[0003] In recent years, as semiconductor memories have become larger and more highly integrated, design rules have been reduced. This trend also occurs in dynamic random access memory (DRAM), which is a type of semiconductor memory. In order for a DRAM device to work, each cell is expected to have a certain level of capacitance or more.

[0004] The increase in capacitance may lead to a greater accumulation of charge within the capacitor, thereby improving the refresh characteristics of the semiconductor device. Such enhancement of the refresh characteristics of the semiconductor device may improve the yield of the semiconductor device.

[0005] Efforts to increase capacitance involve employing a dielectric film having a high dielectric constant in the capacitor or increasing the contact area between the lower electrode of the capacitor and the dielectric film. Summary of the invention

[0006] Aspects of the present disclosure provide a semiconductor memory device including a capacitor that can increase capacitance.

[0007] According to aspects of the present disclosure, a semiconductor memory device is provided, comprising: a conductive pattern on a substrate; a lower electrode connected to the conductive pattern, extending in a first direction and comprising a first portion and a second portion, the first portion of the lower electrode being disposed between the conductive pattern and the second portion of the lower electrode; one or more electrode sidewall supports supporting the lower electrode and in contact with the sidewall of the lower electrode; an electrode covering support disposed on the lower electrode and in contact with the top surface of the lower electrode; a capacitor dielectric film on the lower electrode, the electrode sidewall supports and the electrode covering supports; and an upper electrode on the capacitor dielectric film, wherein the first portion of the lower electrode has an increased width in a first direction away from the conductive pattern, and the slope of the sidewall of the first portion of the lower electrode is different from the slope of the sidewall of the second portion of the lower electrode.

[0008] According to aspects of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a conductive pattern on a substrate; a lower electrode connected to the conductive pattern, extending in a first direction and comprising a first portion and a second portion, the first portion of the lower electrode being disposed between the conductive pattern and the second portion of the lower electrode; a plurality of electrode sidewall supports supporting the lower electrode and in contact with the sidewall of the lower electrode; a capacitor dielectric film on the lower electrode and each of the plurality of electrode sidewall supports; and an upper electrode on the capacitor dielectric film, wherein the first portion of the lower electrode has an increasing width in a first direction away from the conductive pattern, the slope of the sidewall of the first portion of the lower electrode is different from the slope of the sidewall of the second portion of the lower electrode, the plurality of electrode sidewall supports comprising an uppermost electrode sidewall support farthest from the conductive pattern, the uppermost electrode sidewall support comprising a bottom surface adjacent to the conductive pattern and an upper surface opposite to the bottom surface of the uppermost electrode sidewall support, and a portion of the first portion of the lower electrode protrudes beyond the upper surface of the uppermost electrode sidewall support in the first direction.

[0009] According to an aspect of the present disclosure, a semiconductor memory device is provided, the semiconductor memory device comprising: a substrate including an active region defined by an element separation film and extending in a first direction, the active region including a first portion and a pair of second portions arranged on opposite sides of the first portion; a word line extending in a second direction parallel to an upper surface of the substrate and different from the first direction, buried in the substrate and the element separation film, and arranged between the first portion of the active region and one of the pair of second portions of the active region; a bit line contact connected to the first portion of the active region; a bit line connected to the bit line contact and extending in a third direction different from the first direction and the second direction, and arranged on the bit line contact; a bonding pad connected to the second portion of the active region; and an electrical A container connected to a bonding pad and disposed on the bonding pad, wherein the capacitor comprises: a lower electrode connected to the bonding pad and extending in a third direction; a plurality of electrode sidewall supports supporting the lower electrode and in contact with the sidewall of the lower electrode; an electrode covering support disposed on the lower electrode and in contact with the top surface of the lower electrode; a capacitor dielectric film on the lower electrode, each of the plurality of electrode sidewall supports, and the electrode covering support; and an upper electrode on the capacitor dielectric film, wherein the lower electrode comprises a first portion of the lower electrode and a second portion of the lower electrode, the first portion of the lower electrode having an increased width in the third direction away from the bonding pad, the electrode covering support in contact with the second portion of the lower electrode, and the slope of the sidewall of the first portion of the lower electrode is different from the slope of the sidewall of the second portion of the lower electrode.

[0010] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is an exemplary diagram for explaining a semiconductor memory device according to some embodiments.

[0012] Figure 2 yes Figure 1 An enlarged view of a portion P of FIG.

[0013] Figures 3 to 8 are diagrams for explaining a semiconductor memory device according to some embodiments.

[0014] Fig. 9 and Fig.10 is a diagram for explaining a semiconductor memory device according to some embodiments.

[0015] Fig.11 is a layout diagram of a semiconductor memory device according to some embodiments.

[0016] Fig.12 It is shown Fig.11 The layout of word lines and cell active areas.

[0017] Fig.13 is along Fig.11 A cross-sectional view taken along line AA.

[0018] Fig.14 and Fig.15 is a diagram for explaining a semiconductor memory device according to some embodiments.

[0019] Fig.16 is a layout diagram for explaining a semiconductor memory device according to some embodiments.

[0020] Fig.17 is a perspective view for explaining a semiconductor memory device according to some embodiments.

[0021] Fig.18 is along Fig.16 A cross-sectional view taken along lines BB and CC.

[0022] Fig.19 is a layout diagram for explaining a semiconductor memory device according to some embodiments.

[0023] Fig. 20 is a perspective view for explaining a semiconductor memory device according to some embodiments.

[0024] Fig.21 is a diagram for explaining a semiconductor memory device according to some embodiments.

[0025] Figures 22 to 33 are diagrams for explaining intermediate steps of a method for manufacturing a semiconductor memory device according to some embodiments. DETAILED DESCRIPTION

[0026] Will refer to Figure 1 and Figure 2 A semiconductor memory device according to some embodiments is described.

[0027] Figure 1 is an exemplary diagram for explaining a semiconductor memory device according to some embodiments. Figure 2 yes Figure 1 An enlarged view of a portion P of FIG.

[0028] Reference Figure 1 and Figure 2 , a semiconductor memory device according to some embodiments may include a conductive pattern 30 , a lower electrode 191 , a capacitor dielectric film 192 , an upper electrode 193 , at least one or more electrode sidewall supporters 50 , 60 , and 70 , and an electrode cover supporter 80 .

[0029] The conductive pattern 30 may be disposed on the substrate 100. Although the conductive pattern 30 is shown as being separated from the substrate 100, this is only for ease of explanation and is not limited thereto. In some embodiments, the conductive pattern 30 may be electrically connected to a conductive region formed on or in the substrate 100.

[0030] The interlayer insulating film 20 may be disposed on the substrate 100. The conductive pattern 30 may be disposed in the interlayer insulating film 20.

[0031] The substrate 100 may be bulk silicon or silicon on insulator (SOI). In some embodiments, the substrate 100 may be a silicon substrate, or may include other materials (for example, but not limited to, silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide). In the following description, the substrate 100 is described as a silicon substrate.

[0032] The interlayer insulating film 20 may include or may be, for example, at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), a silicon carbonitride film (SiCN), or a combination thereof.

[0033] The conductive pattern 30 may include a conductive material or may be formed of a conductive material. The conductive pattern 30 may, for example, include or may be formed of at least one of a doped semiconductor material, a conductive metal nitride, a conductive metal silicon nitride, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a two-dimensional material (2D material), and a metal. In a semiconductor memory device according to some embodiments, the 2D material may be a metal material and / or a semiconductor material. The 2D material may include a 2D allotrope or a 2D compound, and may include, but is not limited to, graphene, molybdenum disulfide (MoS 2 ), molybdenum diselenide (MoSe 2 ), tungsten diselenide (WSe 2 ) and tungsten disulfide (WS 2 ). The above-mentioned 2D materials are listed only by way of example. The 2D materials that may be included in the semiconductor device of the present disclosure are not limited to the above-mentioned materials. Although the peripheral gate structure PG is shown to include a plurality of conductive patterns, the embodiment is not limited thereto.

[0034] The first etch stopper film 25 may be disposed on the interlayer insulating film 20. The first etch stopper film 25 may expose at least a portion of the conductive pattern 30.

[0035] As an example, the first etch stopper film 25 may be disposed on the conductive pattern 30. The first etch stopper film 25 may include a lower electrode hole exposing at least a portion of the conductive pattern 30 (ie, the lower electrode hole may pass through the first etch stopper film 25).

[0036] The first etching stopper film 25 may include or may be formed of, for example, a silicon nitride film, a silicon carbonitride film, a silicon boron nitride film (SiBN), a silicon carbonate film (SiCO), a silicon oxynitride film, and a silicon carbonitride oxynitride film. For example, the silicon carbonate film (SiCO) contains silicon (Si), carbon (C), and oxygen (O), but does not represent the ratio of silicon (Si), carbon (C), and oxygen (O).

[0037] The data storage pattern DSP may be disposed on the conductive pattern 30. The data storage pattern DSP may be electrically connected to the conductive pattern 30.

[0038] As an example, the data storage pattern DSP may be a capacitor. The data storage pattern DSP may include a lower electrode 191 , a capacitor dielectric film 192 , and an upper electrode 193 .

[0039] A plurality of lower electrodes 191 may be disposed on the conductive pattern 30. The lower electrodes 191 may be connected to the conductive pattern 30. A portion of the lower electrode 191 may be disposed in the first etch stopper film 25.

[0040] For example, each lower electrode 191 may have a columnar shape. The lower electrode 191 may extend longitudinally in a fourth direction DR4, which is a thickness direction of the substrate 100. The length of the lower electrode 191 extending in the fourth direction DR4 is greater than the length of the lower electrode 191 extending in directions DR1 and DR2 parallel to the substrate 100. The shape of the lower electrode 191 will be described below.

[0041] For example, the plurality of lower electrodes 191 may be repeatedly arranged along the first direction DR1. Although not shown, the lower electrodes 191 may be repeatedly arranged in the second direction DR2. The first direction DR1 and the second direction DR2 may be orthogonal to each other, but are not limited thereto. The first direction DR1 and the second direction DR2 may be directions parallel to the upper surface of the substrate 100, or may be orthogonal to a fourth direction DR4, which is perpendicular to the upper surface of the substrate 100.

[0042] The lower electrode 191 may include or may be formed of, for example, a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride, tantalum nitride, niobium nitride, or tungsten nitride), a metal (e.g., ruthenium, iridium, titanium, or tantalum), a conductive metal oxide (e.g., iridium oxide or niobium oxide), etc. In a semiconductor memory device according to some embodiments, the lower electrode 191 may include or may be formed of titanium nitride (TiN). In a semiconductor memory device according to some embodiments, the lower electrode 191 may include or may be formed of niobium nitride (NbN).

[0043] At least one or more electrode sidewall supports 50, 60, and 70 may be disposed on the first etch stop film 25. Each of the electrode sidewall supports 50, 60, and 70 may support the lower electrode 191. In one embodiment, each of the electrode sidewall supports 50, 60, and 70 may horizontally support the lower electrode 191. For example, the electrode sidewall supports 50, 60, and 70 may be disposed in a space between two adjacent lower electrodes 191 spaced apart from each other in the first direction DR1. The electrode sidewall supports 50, 60, and 70 may contact facing sidewalls of the two adjacent lower electrodes 191, thereby supporting each of the two adjacent lower electrodes 191.

[0044] For example, a plurality of electrode sidewall supports 50, 60, 70 may be disposed on the first etch stop film 25. The plurality of electrode sidewall supports 50, 60, and 70 may include a first electrode sidewall support 50, a second electrode sidewall support 60, and a third electrode sidewall support 70 sequentially disposed on the first etch stop film 25.

[0045] The first, second and third electrode sidewall supports 50, 60 and 70 may be spaced apart from the first etch stopper film 25 in the fourth direction DR4. The first, second and third electrode sidewall supports 50, 60 and 70 may be spaced apart from each other in the fourth direction DR4.

[0046] The electrode sidewall supporters 50, 60, and 70 may include an uppermost electrode sidewall supporter SP_UM. The uppermost electrode sidewall supporter SP_UM may be an electrode sidewall supporter farthest from the conductive pattern 30 in the fourth direction DR4 among the electrode sidewall supporters 50, 60, and 70. For example, the third electrode sidewall supporter 70 may be the uppermost electrode sidewall supporter SP_UM. The first electrode sidewall supporter 50 may be an electrode sidewall supporter closest to the conductive pattern 30 in the fourth direction DR4.

[0047] The first, second and third electrode sidewall supports 50, 60 and 70 may each contact the lower electrode 191. The first, second and third electrode sidewall supports 50, 60 and 70 may each contact a portion of the sidewall 191SW of the lower electrode.

[0048] Although the number of electrode sidewall supporters contacting the sidewall 191SW of the lower electrode is shown as three, the technical concept of the present disclosure is not limited thereto. A single electrode sidewall supporter may contact the sidewall 191SW of the lower electrode 191, or more than three electrode sidewall supporters may contact the sidewall 191SW of the lower electrode 191.

[0049] The first electrode sidewall supporter 50 may include a top surface 50US (i.e., upper surface) and a bottom surface 50BS (i.e., lower surface) opposite to each other in the fourth direction DR4. The second electrode sidewall supporter 60 may include a top surface 60US and a bottom surface 60BS opposite to each other in the fourth direction DR4. The third electrode sidewall supporter 70 may include a top surface 70US and a bottom surface 70BS opposite to each other in the fourth direction DR4. The bottom surface 50BS of the first electrode sidewall supporter, the bottom surface 60BS of the second electrode sidewall supporter, and the bottom surface 70BS of the third electrode sidewall supporter may face the conductive pattern 30, respectively.

[0050] Each lower electrode 191 protrudes beyond the third electrode side wall supporter 70 as the uppermost electrode side wall supporter SP_UM in the fourth direction DR4. A portion of the lower electrode 191 protrudes beyond the top surface 70US of the third electrode side wall supporter in the fourth direction DR4. For example, the upper surface of each lower electrode 191 may be higher than the upper surface of the uppermost electrode side wall supporter SP_UM.

[0051] Each of the first electrode sidewall support 50, the second electrode sidewall support 60 and the third electrode sidewall support 70 may include an insulating material or may be formed of an insulating material. For example, each of the first electrode sidewall support 50, 60 and 70 may include or may be formed of, for example, at least one of silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride and silicon carbonitride. In one embodiment, the thickness of the third electrode sidewall support 70 in the fourth direction DR4 may be the same as the thickness of each of the first electrode sidewall support 50 and the second electrode sidewall support 60. The embodiment is not limited thereto. In one embodiment, the thickness of the third electrode sidewall support 70 in the fourth direction DR4 may be different from the thickness of the first electrode sidewall support 50. In one embodiment, the thickness of the third electrode sidewall support 70 may be different from the thickness of the second electrode sidewall support 60.

[0052] The electrode covering support 80 may be disposed on the lower electrode 191 . The electrode covering support 80 may be in contact with the lower electrode 191 . The electrode covering support 80 may be in contact with the top surface 191US of the lower electrode. The electrode covering support 80 may support the lower electrode 191 .

[0053] The electrode covering supporter 80 may be disposed on the third electrode sidewall supporter 70. The electrode covering supporter 80 is spaced apart from the uppermost electrode sidewall supporter SP_UM in the fourth direction DR4.

[0054] The electrode covering supporter 80 may include a top surface 80US and a bottom surface 80BS facing each other in the fourth direction DR4. The bottom surface 80BS of the electrode covering supporter may face the conductive pattern 30. The bottom surface 80BS of the electrode covering supporter may face the top surface 70US of the third electrode sidewall supporter.

[0055] The electrode covering support 80 may, for example, include or may be formed of at least one of silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride, and silicon carbonitride oxide. In one embodiment, the electrode covering support 80 may include or may be formed of the same material as the electrode sidewall supports 50, 60, and 70. In one embodiment, the electrode covering support 80 may include or may be formed of a different material than the electrode sidewall supports 50, 60, and 70.

[0056] The lower electrode 191 may include a first portion 191P1 and a second portion 191P2. The first portion 191P1 of the lower electrode may be disposed between the conductive pattern 30 and the second portion 191P2 of the lower electrode.

[0057] The first portion 191P1 of the lower electrode may contact the conductive pattern 30. From a cross-sectional perspective, in the first portion 191P1 of the lower electrode, the width of the lower electrode 191 in the first direction DR1 may increase as it moves away from the conductive pattern 30. For example, the first portion 191P1 of the lower electrode may have an increased width in a fourth direction DR4 away from the conductive pattern 30. In one embodiment, the upper surface of the conductive pattern 30 may be coplanar with the upper surface of the substrate 100 or may be parallel to the upper surface of the substrate 100. In one embodiment, in the first portion 191P1 of the lower electrode, the width of the lower electrode 191 in the first direction DR1 may increase as it moves away from the conductive pattern 30. For example, the first portion 191P1 of the lower electrode may have an increased width in the fourth direction DR4 away from the conductive pattern 30, and the width of the first portion 191P1 may be measured in the first direction DR1.

[0058] The second portion 191P2 of the lower electrode may contact the electrode covering supporter 80. The second portion 191P2 of the lower electrode includes a top surface 191US of the lower electrode.

[0059] The sidewall 191SW of the lower electrode may include a sidewall 191SW1 of a first portion 191P1 of the lower electrode and a sidewall 191SW2 of a second portion 191P2 of the lower electrode. For example, the slope of the sidewall 191SW1 of the first portion of the lower electrode may be different from the slope of the sidewall 191SW2 of the second portion of the lower electrode.

[0060] The slope of the sidewall 191SW2 of the second portion of the lower electrode may be greater than the slope of the sidewall 191SW1 of the first portion of the lower electrode. In other words, the inclination of the sidewall 191SW2 of the second portion of the lower electrode may be steeper than the inclination of the sidewall 191SW1 of the first portion of the lower electrode.

[0061] In one embodiment, the slope of the sidewall 191SW2 of the second portion of the lower electrode may be smaller than the slope of the sidewall 191SW1 of the first portion of the lower electrode.

[0062] In the semiconductor memory device according to some embodiments, the first portion 191P1 of the lower electrode may be in contact with the second portion 191P2 of the lower electrode. The first portion 191P1 of the lower electrode may be directly connected to the second portion 191P2 of the lower electrode.

[0063] For example, the width W11 of the uppermost portion of the lower electrode 191 in the first portion 191P1 of the lower electrode may be equal to the width W12 of the lowermost portion of the lower electrode in the second portion 191P2 of the lower electrode. In one embodiment, the upper surface of the first portion 191P1 may contact the lower surface of the second portion 191P2, and the width W11 of the upper surface of the first portion 191P1 may be equal to the width W12 of the lower surface of the second portion 191P2.

[0064] In the semiconductor memory device according to some embodiments, the boundary between the first portion 191P1 of the lower electrode and the second portion 191P2 of the lower electrode may be located at the same height as the top surface 70US of the third electrode sidewall supporter (i.e., may be coplanar with the top surface 70US of the third electrode sidewall supporter). In other words, the boundary between the first portion 191P1 of the lower electrode and the second portion 191P2 of the lower electrode may be set at the same height as the top surface of the uppermost electrode sidewall supporter SP_UM (i.e., may be coplanar with the top surface of the uppermost electrode sidewall supporter SP_UM).

[0065] The first portion 191P1 of the lower electrode may not protrude beyond the top surface 70US of the third electrode sidewall supporter in the fourth direction DR4. The second portion 191P2 of the lower electrode may protrude beyond the top surface 70US of the third electrode sidewall supporter in the fourth direction DR4.

[0066] The sidewall 191SW1 of the first portion of the lower electrode may be in contact with the third electrode sidewall supporter 70. The sidewall 191SW2 of the second portion of the lower electrode may not be in contact with the third electrode sidewall supporter 70. For example, the entire sidewall of the third electrode sidewall supporter 70 may be in contact with the sidewall 191SW1 of the first portion of the lower electrode without contacting the sidewall 191SW2 of the second portion of the lower electrode. Since the third electrode sidewall supporter 70 may be the uppermost electrode sidewall supporter SP_UM, the first to third electrode sidewall supports 50, 60, and 70 may be in contact with the sidewall 191SW1 of the first portion of the lower electrode. The first to third electrode sidewall supports 50, 60, and 70 may not be in contact with the sidewall 191SW2 of the second portion of the lower electrode. For example, the entire sidewall of each of the first to third electrode sidewall supporters 50 , 60 , and 70 may contact the sidewall 191SW1 of the first portion of the lower electrode without contacting the sidewall 191SW2 of the second portion of the lower electrode.

[0067] In a semiconductor memory device according to some embodiments, the electrode covering support 80 may be in contact with the side wall 191SW of the lower electrode. The electrode covering support 80 may be in contact with the side wall 191SW2 of the second portion of the lower electrode. For example, the side wall of the electrode covering support 80 may be connected to the side wall 191SW2 of the second portion of the lower electrode. The bottom surface 80BS of the electrode covering support may be disposed at the same plane as the top surface 191US of the lower electrode (i.e., may be coplanar with the top surface 191US of the lower electrode).

[0068] The capacitor dielectric film 192 may be disposed on the lower electrode 191. The capacitor dielectric film 192 may be disposed on the electrode sidewall supports 50, 60, and 70 and the electrode cover support 80.

[0069] The capacitor dielectric film 192 may extend along the side wall 191SW of the lower electrode, the top surface 80US of the electrode covering support, and the bottom surface 80BS of the electrode covering support. Since the top surface 191US of the lower electrode contacts the electrode covering support 80, the capacitor dielectric film 192 is not disposed between the top surface 191US of the lower electrode and the bottom surface 80BS of the electrode covering support.

[0070] The capacitor dielectric film 192 may extend along the top surface 50US of the first electrode side wall support, the bottom surface 50BS of the first electrode side wall support, the top surface 60US of the second electrode side wall support, the bottom surface 60BS of the second electrode side wall support, the top surface 70US of the third electrode side wall support, and the bottom surface 70BS of the third electrode side wall support.

[0071] For example, the capacitor dielectric film 192 may, for example but not limited to, include or may be formed from: silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, hafnium silicon oxide, zirconium hafnium oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lead zirconium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or combinations thereof.

[0072] In one embodiment, the capacitor dielectric film 192 may include or may be formed of a stacked film structure in which zirconium oxide, aluminum oxide, and zirconium oxide are sequentially stacked. In one embodiment, the capacitor dielectric film 192 may include or may be formed of a dielectric film containing hafnium (Hf). The contents of the materials of the capacitor dielectric film 192 described above are merely examples, and the technical concept of the present disclosure is not limited thereto.

[0073] The capacitor dielectric film 192 may include or may be formed of at least one of a ferroelectric material, an antiferroelectric material, and a paraelectric material. For example, the capacitor dielectric film 192 may include or may be formed of at least one of a ferroelectric material, an antiferroelectric material, a paraelectric material, a combination of a ferroelectric material and an antiferroelectric material, a combination of a ferroelectric material and a paraelectric material, a combination of a paraelectric material and an antiferroelectric material, and a combination of a ferroelectric material, an antiferroelectric material, and a paraelectric material.

[0074] In one embodiment, the data storage pattern DSP may be a variable resistance pattern that can be switched between two resistance states by an electric pulse applied to the memory element. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material in which a crystal state changes according to an amount of current.

[0075] The upper electrode 193 may be disposed on the capacitor dielectric film 192. The upper electrode 193 may fill the space between the adjacent lower electrodes 191. The upper electrode 193 may fill the space between the electrode cover support 80 and the third electrode side wall support 70 and between the electrode side wall supporters 50, 60 and 70 adjacent in the fourth direction DR4. The upper electrode 193 may fill the space between the first electrode side wall supporter 50 and the interlayer insulating film 20.

[0076] The upper electrode 193 may, for example but not limited to, include the following items or may, for example but not limited to, be formed by the following items: doped semiconductor materials, conductive metal nitrides (for example, titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, etc.), metals (for example, ruthenium, iridium, titanium or tantalum, etc.), conductive metal oxides (for example, iridium oxide or niobium oxide), etc.

[0077] Figures 3 to 8 are diagrams for explaining semiconductor memory devices according to some embodiments. Figure 1 and Figure 2 Interpretation perspective: Interpret from different perspectives.

[0078] As a reference, Figures 3 to 8 They are Figure 1 An enlarged view of a portion P of FIG.

[0079] Reference Figure 3 and Figure 4 In the semiconductor memory device according to some embodiments, a width W11 of an uppermost portion of the lower electrode 191 in the first portion 191P1 of the lower electrode may be different from a width W12 of a lowermost portion of the lower electrode in the second portion 191P2 of the lower electrode. For example, a width W11 of an upper surface of the first portion 191P1 of the lower electrode may be different from a width W12 of a lower surface of the second portion 191P2 of the lower electrode.

[0080] exist Figure 3 , the width W11 of the uppermost portion of the lower electrode 191 in the first portion 191P1 of the lower electrode may be greater than the width W12 of the lowermost portion of the lower electrode in the second portion 191P2 of the lower electrode. For example, the width W11 of the upper surface of the first portion 191P1 of the lower electrode may be greater than the width W12 of the lower surface of the second portion 191P2 of the lower electrode.

[0081] exist Figure 4, the width W11 of the uppermost portion of the lower electrode 191 in the first portion 191P1 of the lower electrode may be smaller than the width W12 of the lowermost portion of the lower electrode in the second portion 191P2. For example, the width W11 of the upper surface of the first portion 191P1 of the lower electrode may be smaller than the width W12 of the lower surface of the second portion 191P2 of the lower electrode. A portion of the second portion 191P2 of the lower electrode may be disposed above the top surface 70US of the third electrode sidewall supporter. The second portion 191P2 of the lower electrode may be in contact with the top surface 70US of the third electrode sidewall supporter.

[0082] Reference Figure 5 In the semiconductor memory device according to some embodiments, a boundary between the first portion 191P1 of the lower electrode and the second portion 191P2 of the lower electrode may be lower than a top surface 70US of the third electrode sidewall supporter.

[0083] A portion of the second portion 191P2 of the lower electrode may be disposed below the top surface 70US of the third electrode sidewall supporter. The third electrode sidewall supporter 70 as the uppermost electrode sidewall supporter SP_UM may contact a portion of the sidewall 191SW2 of the second portion of the lower electrode and a portion of the sidewall 191SW1 of the first portion of the lower electrode.

[0084] Reference Figure 6 , in the semiconductor memory device according to some embodiments, the electrode covering supporter 80 may be in contact with the sidewall 191SW of the lower electrode.

[0085] The electrode covering supporter 80 may be in contact with the sidewall 191SW2 of the second portion of the lower electrode. The electrode covering supporter 80 may cover a portion of the sidewall 191SW2 of the second portion of the lower electrode.

[0086] The bottom surface 80BS of the electrode cover support may include a first region in contact with the top surface 191US of the lower electrode and a second region in contact with the capacitor dielectric film 192. Referring to the conductive pattern ( Figure 1 30), the first area of ​​the bottom surface 80BS of the electrode covering support member may be higher than the second area of ​​the bottom surface 80BS of the electrode covering support member.

[0087] Reference Figure 7 and Figure 8 , in the semiconductor memory device according to some embodiments, the lower electrode 191 may further include a third portion 191P3 disposed between the first portion 191P1 of the lower electrode and the second portion 191P2 of the lower electrode.

[0088] The sidewall 191SW of the lower electrode includes a sidewall 191SW3 of the third portion 191P3 of the lower electrode. The sidewall 191SW3 of the third portion of the lower electrode may connect the sidewall 191SW1 of the first portion of the lower electrode and the sidewall 191SW2 of the second portion of the lower electrode. The sidewall 191SW3 of the third portion of the lower electrode may have a circular shape.

[0089] exist Figure 3 and Figure 7 , the width of the lower electrode 191 in the first direction DR1 in the third portion 191P3 of the lower electrode may decrease as it moves away from the first portion 191P1 of the lower electrode. For example, the third portion 191P3 may have a decreasing width in the fourth direction DR4 away from the first portion 191P1 of the lower electrode. The width of the third portion 191P3 may be measured in the first direction DR1. The third portion 191P3 of the lower electrode may protrude beyond the top surface 70US of the third electrode sidewall supporter in the fourth direction DR4.

[0090] exist Figure 4 and Figure 8 , the width of the lower electrode 191 in the first direction DR1 in the third portion 191P3 of the lower electrode may increase as it moves away from the first portion 191P1 of the lower electrode. For example, the third portion 191P3 of the lower electrode may have an increased width in the fourth direction DR4 away from the first portion 191P1 of the lower electrode. The third portion 191P3 of the lower electrode may be disposed in the third electrode sidewall supporter. The sidewall 191SW3 of the third portion of the lower electrode may contact the third electrode sidewall supporter 70.

[0091] Fig. 9 and Fig.10 is a diagram for explaining a semiconductor memory device according to some embodiments. For ease of explanation, focus is placed on the semiconductor memory device according to some embodiments. Figure 1 and Figure 2 Interpretation perspective: Interpret from different perspectives.

[0092] As a reference, Fig.10 yes Fig. 9 An enlarged view of a portion P of FIG.

[0093] Reference Fig. 9 and Fig.10 , in the semiconductor memory device according to some embodiments, the electrode sidewall supporter may not be disposed near a boundary between the first portion 191P1 of the lower electrode and the second portion 191P2 of the lower electrode.

[0094] The third electrode side wall support ( Figure 1 70 ) is not disposed between the electrode covering support 80 and the second electrode side wall support 60 .

[0095] For example, the second electrode sidewall supporter 60 may be the uppermost electrode sidewall supporter SP_UM. A portion of the first portion 191P1 of the lower electrode may protrude beyond the top surface of the uppermost electrode sidewall supporter SP_UM in the fourth direction DR4. A portion of the first portion 191P1 of the lower electrode may protrude beyond the top surface 60US of the second electrode sidewall supporter in the fourth direction DR4.

[0096] The first electrode sidewall supporter 50 and the second electrode sidewall supporter 60 may contact the sidewall 191SW1 of the first portion of the lower electrode. The first electrode sidewall supporter 50 and the second electrode sidewall supporter 60 may not contact the sidewall 191SW2 of the second portion of the lower electrode.

[0097] although Fig.10 Shown from Figure 2 The shape of the third electrode sidewall support member 70 is removed, but the embodiment is not limited thereto. In one embodiment, Fig. 9 An enlarged view of part P may be as follows Figure 3 , Figure 4 as well as Figures 6 to 8 The shapes of the lower electrode 191 and the electrode covering support member 80 are shown in FIG.

[0098] Fig.11 is a layout diagram of a semiconductor memory device according to some embodiments. Fig.12 It is shown Fig.11 The layout of word lines and cell active areas. Fig.13 is along Fig.11 A cross-sectional view taken along line AA.

[0099] As a reference, although Fig.11 An example layout of a dynamic random access memory (DRAM) in addition to a data storage pattern (DSP) is shown, but the embodiments are not limited thereto.

[0100] although Fig.11 The first direction DR1 can be Figure 1 The first direction DR1 corresponds to, and Fig.11 The second direction DR2 can be Figure 1 The second direction DR2 corresponds to the first direction DR3, but the embodiment is not limited thereto. Different from the above, Fig.11 The first direction DR1 can be Figure 1 The second direction DR2 corresponds to, and Fig.11 The second direction DR2 can be Figure 1 Corresponding to the first direction DR1.

[0101] Reference Fig.11 and Fig.12 , a semiconductor memory device according to some embodiments may include a plurality of cell active regions ACT.

[0102] The cell active region ACT may be formed on the substrate ( Fig.13 The cell active region ACT is defined by the cell element separation film 105 in the substrate 100. As shown, as the design rule of the semiconductor memory device is reduced, the cell active region ACT may be arranged in the form of diagonal lines or opposite lines. For example, the cell active region ACT may extend in a third direction DR3 between the first direction DR1 and the second direction DR2. The third direction DR3 may be parallel to the upper surface of the substrate 100.

[0103] A plurality of gate electrodes extending in a first direction DR1 across the cell active area ACT may be provided. The plurality of gate electrodes may extend parallel to each other. The plurality of gate electrodes may be, for example, a plurality of word lines WL. The word lines WL may be provided at regular intervals in a second direction DR2. The width of the word lines WL or the interval between the word lines WL may be determined according to a design rule.

[0104] Each cell active region ACT may be divided into three parts by two word lines WL extending in the first direction DR1. The cell active region ACT may include a storage connection region (or storage connection portion) 103b and a bit line connection region 103a. The bit line connection region 103a may be located at a central portion of the cell active region ACT, and the storage connection region 103b may be located at an end portion of the cell active region ACT. For example, each of the word lines WL may be disposed between the bit line connection region 103a and one of a pair of storage connection regions 103b.

[0105] For example, the bit line connection region 103a may be a region connected to the bit line BL, and the storage connection region 103b may be a region connected to the data storage pattern ( Fig.13 In one embodiment, the bit line connection region 103a may correspond to the common drain region, and the storage connection region 103b may correspond to the source region. Each word line WL and the bit line connection region 103a and the storage connection region 103b adjacent to each word line WL may constitute a transistor.

[0106] A plurality of bit lines BL extending in a second direction DR2 orthogonal to the word line WL may be disposed on the word line WL. The plurality of bit lines BL may extend parallel to each other. The bit lines BL may be disposed at regular intervals in the first direction DR1. The width of the bit lines BL or the intervals between the bit lines BL may be determined according to a design rule.

[0107] The fourth direction DR4 may be orthogonal to the first direction DR1 , the second direction DR2 , and the third direction DR3 .

[0108] A semiconductor memory device according to some embodiments may include various contact arrangements formed on a cell active area ACT, which may include, for example, a direct contact DC, a buried contact BC, and a landing pad LP.

[0109] Here, the direct contact DC may electrically connect the cell active region ACT to the bit line BL. The buried contact BC may electrically connect the cell active region ACT to the data storage pattern ( Fig.13 The lower electrode of DSP Fig.13 of 191).

[0110] In view of the placement structure, the contact area between the buried contact BC and the cell active area ACT may be small. Therefore, the conductive bonding pad LP may be introduced to increase the contact area with the cell active area ACT and increase the contact with the lower electrode ( Fig.13 The contact area of ​​191).

[0111] In the semiconductor memory device according to some embodiments, a bonding pad LP may be disposed between the buried contact BC and the data storage pattern. By introducing the bonding pad LP to expand the contact area, the cell active area ACT and the lower electrode ( Fig.13 In one embodiment, the introduction of the bonding pad LP can increase the process margin for ensuring the connection between the buried contact BC and the data storage pattern.

[0112] For example, Figure 1 and Fig. 9 The conductive pattern 30 may correspond to the bonding pad LP.

[0113] In a semiconductor device according to some embodiments, a direct contact DC may be disposed in a central portion of the cell active region ACT. A buried contact BC may be disposed at a relatively distal portion of the cell active region ACT. The direct contact DC may be connected to the bit line connection region 103a. The buried contact BC may be connected to the storage connection region 103b.

[0114] Since the buried contact BC is disposed at a relatively distal portion of the cell active area ACT, the bonding pad LP may be disposed to partially overlap the buried contact BC to be adjacent to the relatively distal end of the cell active area ACT. For example, the buried contact BC may be formed to contact the cell active area ACT and the element separation film ( Fig.13 105) are superimposed.

[0115] The word line WL may be formed as a structure buried inside the substrate 100. The word line WL may be disposed between direct contacts DC or between buried contacts BC across the cell active area ACT.

[0116] In one embodiment, two word lines WL may be disposed to extend across one cell active region ACT. Since the cell active region ACT is disposed obliquely, the word line WL may have an angle less than 90 degrees with the cell active region ACT.

[0117] The direct contact DC and the buried contact BC may be disposed symmetrically. Thus, the direct contact DC and the buried contact BC may be disposed on a straight line along the first direction DR1 and the second direction DR2.

[0118] On the other hand, unlike the direct contact DC and the buried contact BC, the bonding pad LP may be arranged in a zigzag form in the second direction DR2 along which the bit line BL extends. In addition, the bonding pad LP may be arranged to overlap the same side portion of each bit line BL in the first direction DR1 along which the word line WL extends.

[0119] For example, each bonding pad LP of the first line overlaps the left side of the corresponding bit line BL, and each bonding pad LP of the second line may overlap the right side of the corresponding bit line BL.

[0120] Reference Figures 11 to 13 , a semiconductor memory device according to some embodiments may include a plurality of bit line structures 140ST, a plurality of storage contacts 120 , a plurality of bit line contacts 146 , and a data storage pattern DSP.

[0121] The cell element separation film 105 may be disposed inside the substrate 100. The cell element separation film 105 may have a shallow trench isolation (STI) structure having excellent element separation characteristics. The cell element separation film 105 may define a cell active region ACT inside the memory cell region.

[0122] like Fig.11 and Fig.12 As shown, the cell active region ACT defined by the cell element separation film 105 may have a long island shape including a short axis and a long axis. The cell active region ACT may have a slant line form to have an angle less than 90 degrees relative to the word line WL formed inside the cell element separation film 105. The cell active region ACT may have a slant line form to have an angle less than 90 degrees relative to the bit line BL formed on the cell element separation film 105.

[0123] The unit element separation film 105 may include, for example but not limited to, or may be formed of, for example but not limited to, at least one of a silicon oxide film, a silicon nitride film, and a silicon nitride oxide film.

[0124] Although the cell element separation film 105 is shown as being formed as a single insulating film, this is only for convenience of explanation and the embodiment is not limited thereto. The cell element separation film 105 may be formed of a single insulating film or may be formed of a plurality of insulating films according to the spacing distance of adjacent cell active regions ACT.

[0125] although Fig.13 It is shown that the top surface of the unit element separation film 105 and the top surface of the substrate 100 are disposed on the same plane, but this is only for convenience of explanation, and the embodiment is not limited thereto.

[0126] The bit line structure 140ST may include a cell conductive line 140 , a cell line capping film 144 , and a bit line spacer 150 .

[0127] The cell conductive line 140 may be disposed on the substrate 100 and the cell element separation film 105 on which the word line WL is formed. The cell conductive line 140 may intersect the cell element separation film 105 and the cell active area ACT defined by the cell element separation film 105. The cell conductive line 140 may be formed to intersect the word line WL. Here, the cell conductive line 140 may correspond to the bit line BL. For example, the cell conductive line 140 may be Fig.11 The bit line BL.

[0128] The unit conductive line 140 may include or may be formed of, for example, at least one of an impurity-doped semiconductor material, a conductive silicide compound, a conductive metal nitride, a two-dimensional (2D) material, and a metal.

[0129] Although the unit conductive line 140 is illustrated as a single film, this is only for convenience of explanation, and the embodiment is not limited thereto. In one embodiment, the unit conductive line 140 may include a plurality of conductive films in which conductive materials are stacked.

[0130] The cell line cover film 144 may be disposed on the cell conductive line 140. The cell line cover film 144 may extend in the second direction DR2 along the top surface of the cell conductive line 140. The cell line cover film 144 may, for example, include or may be formed of at least one of a silicon nitride film, a silicon nitride oxide film, silicon carbon nitride, and silicon carbon nitride oxide.

[0131] In the semiconductor memory device according to some embodiments, the cell line cover film 144 may include or may be a silicon nitride film. Although the cell line cover film 144 is illustrated as a single film, embodiments are not limited thereto.

[0132] The bit line spacer 150 may be disposed on sidewalls of the cell conductive line 140 and the cell line cover film 144. The bit line spacer 150 longitudinally extends in the second direction DR2.

[0133] Although the bit line spacer 150 is shown as a single film, this is only for convenience of explanation, and the embodiment is not limited thereto. In one embodiment, the bit line spacer 150 may have a multi-film structure. The bit line spacer 150 may include or may be formed of, for example, but not limited to, one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film (SiON), a silicon oxycarbonitride film (SiOCN), air, and a combination thereof.

[0134] The cell insulating film 130 may be disposed on the substrate 100 and the cell element separation film 105. For example, the cell insulating film 130 may be disposed on the top surface of the substrate 100 and the cell element separation film 105 “wherein the bit line contact 146 and the storage contact 120 are not formed”. The cell insulating film 130 may be formed between the substrate 100 and the cell conductive line 140 and between the cell element separation film 105 and the cell conductive line 140.

[0135] The unit insulating film 130 may be a single film. In one embodiment, the unit insulating film 130 may be a multi-film including a first unit insulating film 131 and a second unit insulating film 132. For example, the first unit insulating film 131 may include or may be formed of a silicon oxide film, and the second unit insulating film 132 may include or may be formed of a silicon nitride film, but the embodiment is not limited thereto. In one embodiment, the unit insulating film 130 may be, but is not limited to, a triple film including a silicon oxide film, a silicon nitride film, and a silicon oxide film.

[0136] The bit line contact 146 may be disposed between the cell conductive line 140 and the substrate 100. The cell conductive line 140 may be disposed on the bit line contact 146.

[0137] The bit line contact 146 may be disposed between the bit line connection portion 103a of the cell active region ACT and the cell conductive line 140. The bit line contact 146 may electrically connect the cell conductive line 140 and the substrate 100. The bit line contact 146 may be connected to the bit line connection portion 103a.

[0138] The bit line contact 146 may include a top surface 146US connected to the cell conductive line 140. The width of the bit line contact 146 in the first direction DR1 may be constant when the bit line contact 146 is away from the top surface 146US of the bit line contact. For example, the bit line contact 146 may have a constant width in the fourth direction DR4. This is only for convenience of explanation, and the embodiment is not limited thereto.

[0139] The bit line contact 146 may correspond to the direct contact DC. The bit line contact 146 may include or may be formed of, for example, at least one of an impurity-doped semiconductor material, a conductive metal silicide, a conductive metal nitride, a conductive metal oxide, a metal, and a metal alloy.

[0140] In a portion of the cell conductive line 140 where the bit line contact 146 is formed, a bit line spacer 150 may be disposed on the substrate 100 and the cell element separation film 105. The bit line spacer 150 may be disposed on sidewalls of the cell conductive line 140, the cell line capping film 144, and the bit line contact 146.

[0141] In the remaining portion of the cell conductive line 140 where the bit line contact 146 is not formed, the bit line spacer 150 may be disposed on the cell insulating film 130. The bit line spacer 150 may be disposed on the sidewalls of the cell conductive line 140 and the cell line capping film 144.

[0142] The storage contact 120 may be disposed between the cell conductive lines 140 adjacent in the first direction DR1. The storage contact 120 may be disposed on opposite sides of the cell conductive line 140. For example, the storage contact 120 may be disposed between the bit line structures 140ST. The storage contact 120 may be disposed between the word lines WL adjacent in the second direction DR2.

[0143] The storage contact 120 may overlap the substrate 100 and the cell element separation film 105 between the adjacent cell conductive lines 140. The storage contact 120 may be connected to the cell active region ACT. For example, the storage contact 120 may be connected to the storage connection portion 103b. Here, the storage contact 120 may overlap the substrate 100 and the cell element separation film 105 between the adjacent cell conductive lines 140. Fig.11 The buried contact BC corresponds to.

[0144] The storage contact 120 may, for example, include or may be formed of at least one of a semiconductor material doped with impurities, a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a conductive metal carbonitride, a conductive metal oxide, and a metal.

[0145] The storage pad 160 may be disposed on the storage contact 120. The storage pad 160 may be electrically connected to the storage contact 120. The storage pad 160 may be connected to the storage connection portion 103b of the cell active area ACT. Fig.11 corresponding to the bonding pad LP.

[0146] The storage pad 160 may overlap a portion of the top surface of the bit line structure 140ST. The storage pad 160 may include or may be formed of, for example, at least one of a conductive silicide compound, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, and a metal.

[0147] The pad separation insulating film 180 may be disposed on the memory pad 160 and the bit line structure 140ST. For example, the pad separation insulating film 180 may be disposed on the cell line cover film 144.

[0148] The pad separation insulating film 180 may form a plurality of isolation regions to define the storage pad 160. The pad separation insulating film 180 may not cover the top surface 160US of the storage pad. For example, the height of the top surface 160US of the storage pad may be equal to the height of the top surface 180US of the pad separation insulating film with reference to the top surface of the substrate 100. In one embodiment, the top surface 160US of the storage pad may be coplanar with the top surface 180US of the pad separation insulating film.

[0149] The pad separation insulating film 180 may include or may be formed of an insulating material, and may electrically separate the plurality of storage pads 160 from each other. For example, the pad separation insulating film 180 may include, but is not limited to, or may be formed of, but is not limited to, at least one of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon carbon nitride film, and a silicon carbon nitride film.

[0150] The second etch stop film 195 may be disposed on the top surface 160US of the storage pad and the top surface 180US of the pad separation insulating film. Figure 1 and Fig. 9 The first etching stopper film 25 corresponds to the first etching stopper film 25.

[0151] The second etch stopper film 195 may include or may be formed of, for example, at least one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), silicon oxycarbide (SiOC), and silicon boron nitride (SiBN).

[0152] The data storage pattern DSP may be disposed on the memory pad 160. The data storage pattern DSP is electrically connected to the memory pad 160. A portion of the data storage pattern DSP may be disposed in the second etch stopper film 195.

[0153] The data storage pattern DSP may include, for example, a capacitor. The data storage pattern DSP includes a lower electrode 191 , a capacitor dielectric film 192 , and an upper electrode 193 .

[0154] The first to third electrode sidewall supports 50, 60, and 70 may support the lower electrode 191. The first to third electrode sidewall supports 50, 60, and 70 may be in contact with the lower electrode 191.

[0155] The electrode covering supporter 80 may be disposed on the lower electrode 191. The electrode covering supporter 80 may be in contact with a top surface of the lower electrode 191.

[0156] The description of the lower electrode 191, the capacitor dielectric film 192 and the upper electrode 193 can be referred to in Figures 1 to 10 Those described are essentially the same and therefore will not be provided below.

[0157] The description of the first to third electrode side wall supports 50, 60 and 70 and the electrode cover support 80 can be used with Figures 1 to 10 Those described are essentially the same and therefore will not be provided below.

[0158] Fig.14 and Fig.15 is a diagram for explaining a semiconductor memory device according to some embodiments. Figures 11 to 13 Describes different perspectives.

[0159] Fig.14 is a layout of a semiconductor memory device according to some embodiments. Fig.15 is along Fig.14 A cross-sectional view taken along line AA.

[0160] Reference Fig.12 , Fig.14 and Fig.15 , a semiconductor memory device according to some embodiments may include a node pad XP disposed on a substrate 100 .

[0161] NodePad XP can be set up instead of Fig.11 The node pad XP may be a connection pad connecting the cell active area ACT to the lower electrode 191 of the data storage pattern DSP. The node pad XP may be connected to the storage connection region 103b.

[0162] Due to the arrangement structure, the contact area between the node pad XP and the cell active area ACT may be small. Therefore, in order to increase the contact area with the cell active area ACT and the contact area with the lower electrode 191 of the data storage pattern DSP, the conductive bonding pad LP may be introduced.

[0163] Since the node pad XP is disposed at a relatively distal portion of the cell active region ACT, the bonding pad LP may be disposed to at least partially overlap the node pad XP to be adjacent to the relatively distal end of the cell active region ACT. For example, the node pad XP may be formed to overlap the cell active region ACT and the cell element separation film 105 between adjacent word lines WL and between adjacent bit lines BL.

[0164] The word line WL may be disposed to extend across the cell active area ACT between the direct contact DC and the node pad XP. The direct contact DC and the node pad XP may be disposed symmetrically. Therefore, the direct contact DC and the node pad XP may be disposed on a straight line along the first direction DR1 and the second direction DR2.

[0165] The node connection pad 125 may be disposed on the substrate 100 and the unit element separation film 105. The node connection pad 125 may be disposed on the top surface of the unit element separation film 105.

[0166] The bottom surface of the node connection pad 125 may be disposed on the top surface of the unit element separation film 105. The bottom surface of the node connection pad 125 may contact the top surface of the unit element separation film 105. For example, the entire node connection pad 125 may be disposed on the top surface of the substrate 100. Here, the node connection pad 125 may correspond to the node pad XP.

[0167] Referring to the top surface of the cell element separation film 105 , the top surface 125US of the node connection pad may be lower than the top surface 146US of the bit line contact. Referring to the top surface of the cell element separation film 105 , the top surface 125US of the node connection pad may be lower than the bottom surface of the cell conductive line 140 .

[0168] The contact separation structure 145ST may separate the node connection pads 125 adjacent in the first direction DR1 from each other. Although not shown, the contact separation structure 145ST may separate the node connection pads 125 adjacent in the second direction DR2 from each other. The contact separation structure 145ST covers the top surfaces 125US of the node connection pads.

[0169] The contact separation structure 145ST may include a contact separation pattern 145 and an upper unit insulating film 135. The upper unit insulating film 135 may be disposed on the contact separation pattern 145.

[0170] The node connection pads 125 may include first and second node connection pads spaced apart from each other in the first direction DR1, and the contact separation pattern 145 may separate the first and second node connection pads from each other in the first direction DR1. In one embodiment, the contact separation pattern 145 may also separate the node connection pads 125 adjacent to each other in the second direction DR2 from each other.

[0171] The entire top surface 125US of the node connection pad may not contact the entire memory pad 160. For example, the width of the interface between the node connection pad 121 and the memory pad 160 in the first direction DR1 may be smaller than the width of the top surface 125US of the node connection pad in the first direction DR1.

[0172] The bit line spacer 150 may be disposed on the top surface 125US of the node connection pad.

[0173] The upper unit insulating film 135 may cover the top surface 125US of the node connection pad. The node connection pad 125 may include first and second node connection pads spaced apart from each other in the first direction DR1.

[0174] The top surface 135US of the upper unit insulating film may be disposed on the same plane as the top surface 146US of the bit line contact (i.e., may be coplanar with the top surface 146US of the bit line contact). For example, with reference to the top surface of the cell element separation film 105, the height of the top surface 135US of the upper unit insulating film may be the same as the height of the top surface 146US of the bit line contact.

[0175] The cell conductive line 140 may be disposed on the top surface of the contact separation structure 145ST. The cell conductive line 140 may be disposed on the top surface 135US of the upper cell insulating film. The top surface of the contact separation structure 145ST may be the top surface 135US of the upper cell insulating film. The top surface of the contact separation structure 145ST may be disposed on the same plane as the bottom surface of the cell conductive line 140 (i.e., may be coplanar with the bottom surface of the cell conductive line 140).

[0176] The contact separation pattern 145 may include or may be formed of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and at least one of a combination thereof. The upper unit insulating film 135 may be a single film. In one embodiment, the upper unit insulating film 135 may be a multi-film including a first upper unit insulating film 136 and a second upper unit insulating film 137. For example, the first upper unit insulating film 136 may include or may be formed of a silicon oxide film, and the second upper unit insulating film 137 may include or may be formed of a silicon nitride film, but the present disclosure is not limited thereto. Although the width of the upper unit insulating film 135 in the first direction DR1 is shown as decreasing as it moves away from the substrate 100, the embodiment is not limited thereto.

[0177] Fig.16 is a layout diagram for explaining a semiconductor memory device according to some embodiments. Fig.17 is a perspective view for explaining a semiconductor memory device according to some embodiments. Fig.18 is along Fig.16 A cross-sectional view taken along lines BB and CC.

[0178] For convenience of explanation, the first to third electrode side wall supports 50, 60 and 70 and the electrode cover support 80 are Fig.18 is omitted.

[0179] Reference Figures 16 to 18 , a semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420, a channel layer 430, a gate electrode 440, a gate insulating film 450, and a data storage pattern DSP.

[0180] The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT). The vertical channel transistor may refer to a transistor in which a channel length of a channel layer 430 extends from the substrate 100 in a vertical direction.

[0181] The lower insulating layer 412 may be disposed on the substrate 100. The plurality of first conductive lines 420 may be spaced apart from each other in the first direction DR1 on the lower insulating layer 412 and extend in the second direction DR2. The plurality of first insulating patterns 422 may be disposed on the lower insulating layer 412 to fill spaces between the plurality of first conductive lines 420. The plurality of first insulating patterns 422 may extend in the second direction DR2. Top surfaces of the plurality of first insulating patterns 422 may be disposed at the same height as the upper surfaces of the plurality of first conductive lines 420 (i.e., may be coplanar with the top surfaces of the plurality of first conductive lines 420). The plurality of first conductive lines 420 may serve as bit lines.

[0182] The plurality of first conductive lines 420 may include or may be formed of doped semiconductor materials, metals, conductive metal nitrides, conductive metal silicides, conductive metal oxides, or combinations thereof. For example, the plurality of first conductive lines 420 may be formed of, but not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x 、RuO x The plurality of first conductive lines 420 may include a single layer or multiple layers of the above materials. In example embodiments, the plurality of first conductive lines 420 may include graphene, carbon nanotubes, or a combination thereof, or may be formed of graphene, carbon nanotubes, or a combination thereof.

[0183] The channel layers 430 may be arranged in a matrix form and may be disposed to be spaced apart from each other in the first direction DR1 and the second direction DR2 on the plurality of first conductive lines 420. Each of the channel layers 430 may have a first width in the first direction DR1 and a first height in the fourth direction DR4, and the first height may be greater than the first width. Here, the fourth direction DR4 may be a direction intersecting the first direction DR1 and the second direction DR2, and, for example, perpendicular to the top surface of the substrate 100. For example, the first height may be, but is not limited to, about 2 to 10 times the first width. The bottom portion of the channel layer 430 may be used as a third source / drain region (not shown), the upper portion of the channel layer 430 may be used as a fourth source / drain region (not shown), and a portion of the channel layer 430 between the third source / drain region and the fourth source / drain region may be used as a channel region (not shown).

[0184] In one embodiment, the channel layer 430 may include an oxide semiconductor, and the oxide semiconductor may include, for example, In x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O、Hf x In y Zn z O.Ga x Zn y Sn z O、Al x Zn y Sn z O, Yb x Ga y Zn z O、In x Ga y O or a combination thereof. Channel layer 430 may include a single layer or multiple layers of an oxide semiconductor. In some embodiments, channel layer 430 may have a band gap energy greater than the band gap energy of silicon. For example, channel layer 430 may have a band gap energy of about 1.5eV to 5.6eV. For example, a channel layer 430 with a band gap energy of about 2.0eV to 4.0eV may have a desired channel performance. For example, channel layer 430 may be but is not limited to polycrystalline or amorphous. In one embodiment, channel layer 430 may include graphene, carbon nanotubes, or a combination thereof. In one embodiment, channel layer 430 may include a silicon-based semiconductor material. Channel layer 430 may include a single crystal semiconductor material, and may include but is not limited to single crystal silicon or single crystal silicon germanium.

[0185] The gate electrode 440 may extend in the first direction DR1 on the opposite sidewalls of the channel layer 430. The gate electrode 440 may include a first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 and a second sub-gate electrode 440P2 facing the second sidewall opposite to the first sidewall of the channel layer 430. For example, the first sub-gate electrode 440P1 may be adjacent to the first sidewall of the channel layer 430, and the second sub-gate electrode 440P2 may be adjacent to the second sidewall of the channel layer 430 opposite to the first sidewall. Since the single channel layer 430 is disposed between the first sub-gate electrode 440P1 and the second sub-gate electrode 440P2, the semiconductor device may have a dual-gate transistor structure. However, the technical idea of ​​the present disclosure is not limited thereto. In one embodiment, the second sub-gate electrode 440P2 may be omitted, and only the first sub-gate electrode 440P1 facing the first sidewall of the channel layer 430 may be formed to realize a single-gate transistor structure.

[0186] The gate electrode 440 may include or be formed of at least one of a metal, a conductive metal nitride, a conductive metal carbonitride, a conductive metal carbide, a metal silicide, a doped semiconductor material, a conductive metal oxynitride, and a conductive metal oxide. The gate electrode 440 may include or be formed of, for example, but not limited to, at least one of TiN, TaC, TaN, TiSiN, TaSiN, TaTiN, TiAlN, TaAlN, WN, Ru, TiAl, TiAlC-N, TiAlC, TiC, TaCN, W, Al, Cu, Co, Ti, Ta, Ni, Pt, Ni-Pt, Nb, NbN, NbC, Mo, MoN, MoC, WC, Rh, Pd, Ir, Ag, Au, Zn, V, RuTiN, TiSi, TaSi, NiSi, CoSi, IrOx, RuOx, and combinations thereof.

[0187] The gate insulating film 450 surrounds the sidewall of the channel layer 430 and may be disposed between the channel layer 430 and the gate electrode 440. Fig.16 As shown in , the entire sidewall of the channel layer 430 may be surrounded by the gate insulating film 450, and a portion of the sidewall of the gate electrode 440 may contact the gate insulating film 450. In some embodiments, the gate insulating film 450 may extend in an extension direction (i.e., a first direction DR1) of the gate electrode 440, and only two sidewalls of the sidewalls of the channel layer 430 facing the gate electrode 440 may contact the gate insulating film 450.

[0188] The gate insulating film 450 may include, for example, or may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, and at least one of a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, and at least one of a combination thereof.

[0189] The plurality of second insulating patterns 432 may extend on the plurality of first insulating patterns 422 along the second direction DR2. The channel layer 430 may be disposed between two adjacent second insulating patterns 432 among the plurality of second insulating patterns 432. The first buried layer 434 and the second buried layer 436 may be disposed in a space between two adjacent second insulating patterns 432 and between two adjacent channel layers 430. The first buried layer 434 may be located at a bottom portion of the space between the two adjacent channel layers 430. The second buried layer 436 may be formed to fill the remaining portion of the space between the two adjacent channel layers 430 on the first buried layer 434. The top surface of the second buried layer 436 may be disposed at the same height as the top surface of the channel layer 430 (i.e., may be coplanar with the top surface of the channel layer 430), and the second buried layer 436 may cover the top surface of the second gate electrode 440. The plurality of second insulating patterns 432 may be formed of a material layer continuous with the plurality of first insulating patterns 422 , or the second buried layer 436 may be formed of a material layer continuous with the first buried layer 434 .

[0190] The capacitor contact 460 may be disposed on the channel layer 430. The capacitor contact 460 may be disposed to overlap the channel layer 430 in a vertical direction, and may be arranged in a matrix form and may be spaced apart from each other in the first direction DR1 and the second direction DR2. The capacitor contact 460 may be made of, but not limited to, doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or a combination thereof. The upper insulating film (or upper insulating layer) 462 may surround the sidewalls of the capacitor contact 460 on the plurality of second insulating patterns 432 and the second buried layer 436.

[0191] The third etch stop film 470 may be disposed on the upper insulating layer 462. The data storage pattern DSP may be disposed on the third etch stop film 470. The data storage pattern DSP may include a lower electrode 191, a capacitor dielectric film 192, and an upper electrode 193. The lower electrode 191 may pass through the third etch stop film 470 and may be electrically connected to a top surface of the capacitor contact 460.

[0192] In some embodiments, the lower electrode 191 is disposed to vertically overlap the capacitor contact 460, and may be disposed in the form of a matrix in which the capacitor contact 460 is spaced apart in the first direction DR1 and the second direction DR2. A bonding pad (not shown) may also be disposed between the capacitor contact 460 and the lower electrode 191, and the lower electrode 191 may be disposed in a hexagonal shape.

[0193] The description of the lower electrode 191, the capacitor dielectric film 192 and the upper electrode 193 can be used with Figures 1 to 10 Those described are essentially the same and therefore will not be provided below.

[0194] Despite Fig.18 The first to third electrode side wall supports 50, 60 and 70 and the electrode cover support 80 are not shown in the figure, but the description of the first to third electrode side wall supports 50, 60 and 70 and the electrode cover support 80 can be referred to. Figures 1 to 10 The description is basically the same.

[0195] Fig.19 is a layout diagram for explaining a semiconductor memory device according to some embodiments. Fig. 20 is a perspective view for explaining a semiconductor memory device according to some embodiments. Fig.21 is a diagram for explaining a semiconductor memory device according to some embodiments.

[0196] Reference Fig.19 and Fig. 20 , a semiconductor memory device according to some embodiments may include a substrate 100, a plurality of first conductive lines 420A, a channel structure 430A, a contact gate electrode 440A, a plurality of second conductive lines 442A, and a data storage pattern DSP. The semiconductor memory device according to some embodiments may be a memory device including a vertical channel transistor (VCT).

[0197] A plurality of active regions AC may be defined in the substrate 100 by the first element separation pattern 412A and the second element separation pattern 414A. A channel structure 430A may be disposed in each active region AC. The channel structure 430A may include a first active pillar 430A1 and a second active pillar 430A2, both extending in a vertical direction, and a connecting portion 430L connected to a bottom portion of the first active pillar 430A1 and a bottom portion of the second active pillar 430A2. A first source / drain region SD1 may be disposed in the connecting portion 430L. A second source / drain region SD2 may be disposed above the first active pillar 430A1 and the second active pillar 430A2. The first active pillar 430A1 and the second active pillar 430A2 may each constitute an independent unit memory cell.

[0198] A plurality of first conductive lines 420A may extend in a direction intersecting each of a plurality of active regions AC, and may extend, for example, in a second direction DR2. One first conductive line 420A among the plurality of first conductive lines 420A may be disposed on a connection portion 430L between a first active pillar 430A1 and a second active pillar 430A2. One first conductive line 420A may be disposed on a first source / drain region SD1. Another first conductive line 420A adjacent to one first conductive line 420A may be disposed between two channel structures 430A. One of the plurality of first conductive lines 420A may be used as a common bit line in two unit memory cells composed of a first active pillar 430A1 and a second active pillar 430A2 disposed on opposite sides of one first conductive line 420A.

[0199] One contact gate electrode 440A may be disposed between two channel structures 430A adjacent to each other in the second direction DR2. For example, the contact gate electrode 440A may be disposed between a first active pillar 430A1 included in one channel structure 430A and a second active pillar 430A2 of the channel structure 430A adjacent to the first active pillar 430A1. One contact gate electrode 440A may be shared by the first active pillar 430A1 and the second active pillar 430A2 disposed on the opposite sidewalls thereof. The gate insulating film 450A may be disposed between the contact gate electrode 440A and the first active pillar 430A1, and between the contact gate electrode 440A and the second active pillar 430A2. A plurality of second conductive lines 442A may extend in the first direction DR1 on the top surface of the contact gate electrode 440A. A plurality of second conductive lines 442A may be used as word lines of a semiconductor memory device.

[0200] The capacitor contact 460A may be disposed on the channel structure 430A. The capacitor contact 460A may be disposed on the second source / drain region SD2, and the data storage pattern DSP may be disposed on the capacitor contact 460A.

[0201] Reference Fig.21 , a semiconductor memory device according to some embodiments may have a cell on periphery (COP) structure in which a cell array region CA is disposed on a peripheral structure region PA.

[0202] The cell array region CA may include Figures 16 to 20 The vertical channel transistor VCT is connected to Figures 16 to 20 A sensing transistor, a transfer transistor, a driving transistor, etc. of a vertical channel transistor may be disposed in the peripheral structure area PA.

[0203] Figures 22 to 33is an intermediate step diagram for explaining a method of manufacturing a semiconductor memory device according to some embodiments. Figures 1 to 10 Partially repeated portions of the description will be briefly described or omitted.

[0204] Reference Fig. 22 , an interlayer insulating film 20 may be formed on the substrate 100 .

[0205] The conductive pattern 30 may be formed in the interlayer insulating film 20. The first etch stopper film 25 may be formed on the conductive pattern 30 and the interlayer insulating film.

[0206] A first mold insulating film 31 , a first electrode supporting film 50L, a second mold insulating film 32 , a second electrode supporting film 60L, a third mold insulating film 33 , and a third electrode supporting film 70L may be sequentially formed on the first etch stopper film 25 .

[0207] Each of the first, second, and third mold insulating films 31 , 32 , and 33 may include or may be formed of, but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric (low-k) material having a dielectric constant less than that of silicon oxide.

[0208] Each of the first electrode support film 50L, the second electrode support film 60L, and the third electrode support film 70L may include, but is not limited to, or may be formed of, at least one of silicon nitride, silicon carbonitride, silicon boron nitride, silicon carbonate, silicon oxynitride, and silicon carbonitride oxide.

[0209] In one embodiment, the third electrode supporting film 70L may not be formed.

[0210] The capacitor mask film CAP_MASK may be formed on the third electrode supporting film 70L. The capacitor mask film CAP_MASK may include a plurality of films sequentially formed on the third electrode supporting film 70L.

[0211] For example, the capacitor mask film CAP_MASK may include first, second, third, and fourth mask films MASK1, MASK2, MASK3, and MASK4, which may be sequentially formed on the third electrode supporting film 70L.

[0212] Each of the first mask film MASK1 and the third mask film MASK3 may include or may be formed of a semiconductor material. For example, each of the first mask film MASK1 and the third mask film MASK3 may include but is not limited to or may be formed of at least one of polycrystalline silicon, amorphous silicon, polycrystalline silicon germanium, amorphous silicon germanium, polycrystalline germanium, and amorphous germanium.

[0213] The second mask film MASK2 may include or may be formed of a conductive material. For example, the second mask film MASK2 may include or may be formed of the same material as that of the lower electrode 191 .

[0214] The fourth mask film MASK4 may include, for example, but not limited to, silicon oxide or may be formed of, for example, but not limited to, silicon oxide.

[0215] Reference Fig. 22 and Fig.23 , the lower electrode mask hole 191_H1 may be formed in the capacitor mask film CAP_MASK.

[0216] The lower electrode mask hole 191_H1 may pass through the capacitor mask film CAP_MASK. The lower electrode mask hole 191_H1 may expose the third electrode supporting film 70L. When the third electrode supporting film 70L is not formed, the lower electrode mask hole 191_H1 may expose the third mold insulating film 33.

[0217] Reference Fig.23 and Fig.24 The lower electrode hole 191H may be formed inside the first to third electrode supporting films 50L, 60L, and 70L, the first to third mold insulating films 31, 32, and 33 by using the lower electrode mask hole 191_H1.

[0218] The lower electrode hole 191H may penetrate the first etch stopper film 25. The lower electrode hole 191H may expose the conductive pattern 30.

[0219] The lower electrode hole 191H may include a portion of the lower electrode mask hole 191_H1. When forming the lower electrode hole 191H, a portion of the third mask film MASK3 and the fourth mask film MASK4 in the capacitor mask film CAP_MASK may be removed. In one embodiment, when forming the lower electrode hole 191H, the entire third mask film MASK3 may be removed.

[0220] The slope of the sidewall of the lower electrode hole 191H may vary according to the properties of the material forming the lower electrode hole 191H. For example, the slope of the sidewall of the lower electrode hole 191H in the first mask film MASK1 including a semiconductor material may be different from the slope of the sidewall of the lower electrode hole 191H in the third electrode supporting film 70L and the third mold insulating film 33 including an insulating material. The slope of the sidewall of the lower electrode hole 191H may vary near the boundary between the third electrode supporting film 70L and the first mask film MASK1.

[0221] Reference Fig.24 and Fig.25 , the third mask film MASK3 on the second mask film MASK2 may be removed to expose the top surface of the second mask film MASK2.

[0222] In one embodiment, the top surface of the second mask film MASK2 may be exposed while forming the lower electrode hole 191H.

[0223] Reference Fig.25 and Fig.26 , a lower electrode film 191P may be formed on the conductive pattern 30 .

[0224] A lower electrode film 191P may be formed in the lower electrode hole 191H. The lower electrode film 191P may be formed on a top surface of the second mask film MASK2.

[0225] Reference Fig.26 and Fig. 27 , the lower electrode 191 may be formed by removing the lower electrode film 191P on the top surface of the second mask film MASK2 and the second mask film MASK2.

[0226] Since the second mask film MASK2 includes or is formed of the same material as the lower electrode film 191P, a portion of the second mask film MASK2 and the lower electrode film 191P may be removed simultaneously. Therefore, the top surface of the first mask film MASK1 may be exposed.

[0227] The lower electrode 191 may be formed in the first to third electrode supporting films 50L, 60L, and 70L and the first to third mold insulating films 31, 32, and 33. The lower electrode 191 may be formed in the first mask film MASK1.

[0228] Reference Fig. 27 and Fig.28 , the first mask film MASK1 on the third electrode supporting film 70L may be removed.

[0229] The top surface of the third electrode supporting film 70L may be exposed. When the first mask film MASK1 is removed, a portion of the lower electrode 191 may protrude beyond the third electrode supporting film 70L in the fourth direction DR4.

[0230] Reference Fig.28 and Fig.29 , the fourth mold insulating film 34 may be formed on the third electrode supporting film 70L.

[0231] The fourth mold insulating film 34 may wrap the sidewall of the lower electrode 191 protruding beyond the third electrode supporting film 70L. The fourth mold insulating film 34 does not cover the top surface 191US of the lower electrode.

[0232] Subsequently, an electrode covering support film 80L may be formed on the fourth mold insulating film 34 and the lower electrode 191. The electrode covering support film 80L may be in contact with the top surface 191US of the lower electrode.

[0233] Reference Fig.29 and Fig.30 , a fifth mask film MASK5 may be formed on the electrode covering support film 80L.

[0234] Subsequently, the electrode cover support film 80L, the fourth mold insulating film 34 , the third electrode support film 70L, and the third mold insulating film 33 may be patterned by using the fifth mask film MASK5 as an etching mask.

[0235] The electrode covering support 80 may be formed by patterning the electrode covering support film 80L. The third electrode sidewall support 70 may be formed by patterning the third electrode supporting film 70L.

[0236] The fourth mold insulating film 34 may be patterned to form a fourth mold insulating pattern 34P between the electrode covering supporter 80 and the third electrode sidewall supporter 70. The third mold insulating film 33 may be patterned to form a third mold insulating pattern 33P between the third electrode sidewall supporter 70 and the second electrode supporting film 60L.

[0237] Reference Fig.30 and Fig.31 , the second electrode supporting film 60L may be patterned by using the fifth mask film MASK5 as an etching mask.

[0238] The second electrode sidewall supporter 60 may be formed by patterning the second electrode supporting film 60L. Thus, the second mold insulating film 32 may be exposed.

[0239] Reference Fig.31 and Fig.32 , the second mold insulating film 32 can be removed using wet etching.

[0240] The second mold insulating film 32 may be removed to expose the first electrode supporting film 50L. When the second mold insulating film 32 is removed, the fourth mold insulating pattern 34P between the electrode cover supporter 80 and the third electrode sidewall supporter 70 may be removed. When the second mold insulating film 32 is removed, the third mold insulating pattern 33P between the third electrode sidewall supporter 70 and the second electrode sidewall supporter 60 may be removed.

[0241] Reference Fig.32 and Fig.33 , the first electrode supporting film 50L may be patterned by using the fifth mask film MASK5 as an etching mask.

[0242] The first electrode sidewall supporter 50 may be formed by patterning the first electrode supporting film 50L. During the formation of the first electrode sidewall supporter 50, the first mold insulating film 31 may be exposed, and then the first mold insulating film 31 may be removed using wet etching.

[0243] The fifth mask film MASK5 may be removed.

[0244] Next, refer to Figure 1 , a capacitor dielectric film 192 and an upper electrode 193 may be formed.

[0245] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments and can be implemented in various different forms. A person of ordinary skill in the art to which the present disclosure belongs will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical ideas or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive but illustrative in all aspects.

Claims

1. A semiconductor memory device, comprising: a conductive pattern, on a substrate; a lower electrode connected to the conductive pattern, extending in a first direction perpendicular to the upper surface of the substrate, and comprising a first portion and a second portion, the first portion of the lower electrode being disposed between the conductive pattern and the second portion of the lower electrode; one or more electrode sidewall supports supporting the lower electrode and contacting the sidewall of the lower electrode; An electrode covering support is disposed on the lower electrode and in contact with the top surface of the lower electrode; a capacitor dielectric film on the lower electrode, each of the one or more electrode sidewall supports, and the electrode cover support; as well as The upper electrode, on the capacitor dielectric film, wherein the first portion of the lower electrode has an increasing width in a first direction away from the conductive pattern, the width of the first portion of the lower electrode is measured in a second direction parallel to the upper surface of the substrate, and The slope of the side wall of the first portion of the lower electrode is different from the slope of the side wall of the second portion of the lower electrode.

2. The semiconductor memory device according to claim 1, in, The one or more electrode sidewall supports are in contact with the sidewalls of the first portion of the lower electrode, and The uppermost surface of the one or more electrode side wall supports is coplanar with the boundary between the first portion and the second portion of the lower electrode.

3. The semiconductor memory device according to claim 1, in, The one or more electrode sidewall supports include an uppermost electrode sidewall support farthest from the conductive pattern, The uppermost electrode side wall support includes an upper surface and a bottom surface opposite to each other in a first direction, The bottom surface of the uppermost electrode side wall support faces the conductive pattern, The first portion of the lower electrode and the second portion of the lower electrode are directly connected, and A boundary between the first portion of the lower electrode and the second portion of the lower electrode is located at the same height level as an upper surface of the uppermost electrode sidewall supporter.

4. The semiconductor memory device according to claim 1, in, The one or more electrode sidewall supports include an uppermost electrode sidewall support farthest from the conductive pattern, The uppermost electrode sidewall support is spaced apart from the electrode covering support in the first direction, and A portion of the sidewall of the first portion of the lower electrode and a portion of the sidewall of the second portion of the lower electrode are in contact with the uppermost electrode sidewall supporter.

5. The semiconductor memory device according to claim 1, in, The electrode covering supporter covers a portion of the side wall of the second portion of the lower electrode.

6. The semiconductor memory device according to claim 1, in, A width of an upper surface of the first portion of the lower electrode is greater than a width of a lower surface of the second portion of the lower electrode.

7. The semiconductor memory device according to claim 6, in, The lower electrode includes a third portion disposed between the first portion of the lower electrode and the second portion of the lower electrode, and A side wall of the third portion of the lower electrode has a rounded shape.

8. The semiconductor memory device according to claim 1, in, A width of an upper surface of the first portion of the lower electrode is smaller than a width of a lower surface of the second portion of the lower electrode.

9. The semiconductor memory device according to claim 8, in, The lower electrode includes a third portion disposed between the first portion of the lower electrode and the second portion of the lower electrode, and A side wall of the third portion of the lower electrode has a rounded shape.

10. The semiconductor memory device according to claim 1, in, The width of the upper surface of the first portion of the lower electrode is the same as the width of the lower surface of the second portion of the lower electrode.

11. A semiconductor memory device comprising: a conductive pattern, on a substrate; a lower electrode connected to the conductive pattern, extending in a first direction perpendicular to the upper surface of the substrate, and comprising a first portion and a second portion, the first portion of the lower electrode being disposed between the conductive pattern and the second portion of the lower electrode; a plurality of electrode side wall support members, supporting the lower electrode and contacting the side wall of the lower electrode; a capacitor dielectric film on the lower electrode and each of the plurality of electrode sidewall supports; as well as The upper electrode, on the capacitor dielectric film, wherein the first portion of the lower electrode has an increasing width in a first direction away from the conductive pattern, and the width of the first portion of the lower electrode is measured in a second direction parallel to the upper surface of the substrate, wherein the slope of the side wall of the first portion of the lower electrode is different from the slope of the side wall of the second portion of the lower electrode, The plurality of electrode side wall support members include an uppermost electrode side wall support member that is farthest from the conductive pattern in the first direction, wherein the uppermost electrode sidewall supporter comprises a bottom surface facing the conductive pattern and an upper surface opposite to the bottom surface of the uppermost electrode sidewall supporter in the first direction, and Part of the first portion of the lower electrode protrudes beyond the upper surface of the uppermost electrode sidewall support in the first direction.

12. The semiconductor memory device according to claim 11, further comprising: The electrode covers the support member, is disposed on the lower electrode and contacts the upper surface of the lower electrode.

13. The semiconductor memory device according to claim 12, in, The electrode covering supporter covers a portion of the side wall of the second portion of the lower electrode.

14. The semiconductor memory device according to claim 11, in, A width of an upper surface of the first portion of the lower electrode is greater than a width of a lower surface of the second portion of the lower electrode.

15. The semiconductor memory device according to claim 14, in, The lower electrode includes a third portion disposed between the first portion of the lower electrode and the second portion of the lower electrode, and A side wall of the third portion of the lower electrode has a rounded shape.

16. The semiconductor memory device according to claim 11, in, A width of an upper surface of the first portion of the lower electrode is smaller than a width of a lower surface of the second portion of the lower electrode.

17. The semiconductor memory device according to claim 16, in, The lower electrode includes a third portion disposed between the first portion of the lower electrode and the second portion of the lower electrode, and A side wall of the third portion of the lower electrode has a rounded shape.

18. A semiconductor memory device comprising: a substrate including an active region defined by an element separation film and extending in a first direction, the active region including a first portion and a pair of second portions provided on opposite sides of the first portion, and the first direction is parallel to an upper surface of the substrate; a word line extending in a second direction parallel to the upper surface of the substrate and different from the first direction, buried in the substrate and the element separation film, and disposed between the first portion of the active region and one of the pair of second portions of the active region; a bit line contact connected to the first portion of the active region; a bit line connected to the bit line contact and extending in a third direction different from the first direction and the second direction, and disposed on the bit line contact; a bonding pad connected to the second portion of the active area; as well as a capacitor connected to and disposed on the bonding pad, Among them, capacitors include: a lower electrode connected to the bonding pad and extending in a fourth direction, wherein the fourth direction is perpendicular to the upper surface of the substrate, A plurality of electrode side wall support members, supporting the lower electrode and contacting the side wall of the lower electrode, an electrode covering support disposed on the lower electrode and in contact with the top surface of the lower electrode, a capacitor dielectric film on the lower electrode, each of the plurality of electrode sidewall supports, and the electrode cover support, and The upper electrode, on the capacitor dielectric film, The lower electrode includes a first portion of the lower electrode and a second portion of the lower electrode. wherein the first portion of the lower electrode has an increasing width in a fourth direction away from the bonding pad, wherein the electrode covering support is in contact with the second portion of the lower electrode, and The slope of the side wall of the first portion of the lower electrode is different from the slope of the side wall of the second portion of the lower electrode.

19. The semiconductor memory device according to claim 18, in, The electrode side wall support comprises an uppermost electrode side wall support which is farthest from the bonding pad in the fourth direction, wherein the uppermost electrode sidewall support member comprises a bottom surface facing the bonding pad and an upper surface opposite to the bottom surface of the uppermost electrode sidewall support member, wherein the uppermost electrode sidewall support is in contact with the sidewall of the first portion of the lower electrode, and Part of the first portion of the lower electrode protrudes beyond the upper surface of the uppermost electrode side wall support in the fourth direction.

20. The semiconductor memory device according to claim 18 or 19, in, A width of an upper surface of the first portion of the lower electrode is different from a width of a lower surface of the second portion of the lower electrode.

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