Manufacturing method of memory device and memory device

Abstract

The invention discloses a memory device manufacturing method and a memory device, and the method comprises the steps: providing a semiconductor base material which comprises a substrate and a hard mask layer; a plurality of first grooves are formed in the semiconductor base material and distributed in the storage area and the lead-out area, and the parts, in the substrate, of the first grooves are defined as base body grooves; a gate insulating layer and a semi-floating gate are formed in the groove of the base body, one part of the semi-floating gate is in contact with the substrate, and the other part of the semi-floating gate is isolated from the substrate through the gate insulating layer; an inter-gate dielectric layer and a control gate layer are formed in the first groove, a connection improvement layer is formed on the control gate layer, one part of the control gate layer serves as a control gate of the storage unit, the other part of the control gate layer serves as a leading-out end of the storage unit, and the leading-out end is connected with the control gates of the storage units in the same row; the connection improvement layer is formed on the control gate layer, so that the resistance of the control gate corresponding to the control gate layer is effectively reduced, the operation speed of the semi-floating gate array is improved, and the performance of the memory device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a manufacturing method of a memory device and a memory device. Background Art

[0002] In the application process of integrated circuits, the performance of various devices will be affected by the resistance of each layer of material, especially memory devices. The resistance of the control gate affects the performance of the memory device.

[0003] In actual operation, the researchers of this application discovered that in current semiconductor device manufacturing schemes, especially in the manufacture of memory devices, in the back-end process of the buried gate structure formed, the resistance corresponding to the memory cell is relatively large, and a follow-up voltage point needs to be set at a specific distance, which affects the operating speed of the semi-floating gate array and further affects the performance of the memory device. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a manufacturing method of a memory device and a memory device, which can effectively reduce the resistance of the control gate of the memory unit in the memory device, increase the operating speed of the semi-floating gate array, and thus improve the performance of the memory device.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: to provide a method for manufacturing a memory device, comprising: providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a hard mask layer on the substrate; opening a plurality of first grooves in the semiconductor substrate, wherein a portion of the plurality of first grooves is located in a storage area and a portion is located in a lead-out area, wherein the portion of the first groove in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate in the base groove, wherein a portion of the semi-floating gate is in contact with the substrate and the other portion is isolated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a control gate layer in the plurality of first grooves, and forming a connection improvement layer on the control gate layer, wherein the control gate layer in the first groove in the storage area serves as a control gate of a memory cell, and the control gate layer in the first groove in the lead-out area serves as a lead-out terminal of the memory cell, and the lead-out terminal is connected to the control gates of a plurality of memory cells in the same row.

[0006] In one embodiment of the present application, providing a semiconductor substrate includes: providing a substrate, and forming a first dielectric layer and a second dielectric layer on the substrate; opening a plurality of second grooves in the active area of ​​the substrate from the second dielectric layer, wherein the second grooves are arranged at intervals along the first direction and extend along the second direction; filling the second grooves with an isolation material to form a shallow trench isolation structure, and performing ion implantation on the substrate to form a first well region in the substrate; removing the second dielectric layer and exposing a portion of the shallow trench isolation structure; performing ion implantation on the substrate using the first dielectric layer as a barrier layer to form a second well region on one side of the substrate; wherein the second well region is located on the first well region, and the doping type is different from the doping type of the first well region; forming a filling covering layer on the first dielectric layer, and using the first dielectric layer and the filling covering layer as the hard mask layer, wherein the filling covering layer is filled between two adjacent shallow trench isolation structures and covers the shallow trench isolation structure.

[0007] In one embodiment of the present application, the forming of the gate insulating layer and the semi-floating gate in the substrate groove comprises: forming a first insulating layer on the inner wall of the substrate groove, forming a sacrificial material on the first insulating layer, and the sacrificial material filling the first groove; removing part of the sacrificial material and the first insulating layer to form a contact window; removing the remaining sacrificial material and filling the first groove with gate material; removing part of the gate material and the first insulating layer to form a gate insulating layer and a semi-floating gate in the substrate groove; wherein the remaining gate material serves as the semi-floating gate, the remaining first insulating layer serves as the gate insulating layer, and a part of the semi-floating gate contacts the substrate through the contact window; or, forming a first insulating layer on the inner wall of the substrate groove, and filling the first groove with the first gate material; removing part of the first gate material and the first insulating layer to form a contact window, and forming a second gate material above the contact window; removing part of the first gate material, the second gate material and the first insulating layer, and the remaining first gate material, the second gate material and the first insulating layer serve as the first gate, the second gate and the gate insulating layer respectively, and the first gate and the second gate cooperate to form the semi-floating gate.

[0008] In an embodiment of the present application, the upper surface of the semi-floating gate is not higher than the upper surface of the substrate groove.

[0009] In one embodiment of the present application, a shallow trench isolation structure is provided in the substrate, wherein a portion of the shallow trench isolation structure is provided in the substrate and another portion is exposed from the substrate, and the shallow trench isolation structure is provided at intervals along a first direction and extends along a second direction; after a gate insulation layer and a semi-floating gate are formed at the bottom of the substrate groove, a portion of the shallow trench isolation structure is removed to form a first isolation portion, wherein an upper surface of the first isolation portion is not higher than an upper surface of the semi-floating gate.

[0010] In one embodiment of the present application, the forming of an inter-gate dielectric layer and a control gate layer in the plurality of first grooves, and the forming of a connection improvement layer on the control gate layer, include: forming the inter-gate dielectric layer, wherein the inter-gate dielectric layer at least covers the semi-floating gate; covering the inter-gate dielectric layer with a third gate material, wherein the third gate material is flush with the highest point of the first groove; removing part of the third gate material in the first groove, and using the remaining third gate material as the control gate layer, wherein the upper surface of the control gate layer is higher than the upper surface of the substrate groove; and forming the connection improvement layer on the control gate layer.

[0011] In one embodiment of the present application, it also includes: removing part of the third gate material in the first groove to form a vacant area, and forming a second insulating layer in the vacant area of ​​the first groove; removing the hard mask layer; forming an isolation sidewall to cover the sidewall of the second insulating layer and the sidewall of the control gate layer.

[0012] In one embodiment of the present application, it also includes: performing ion implantation on the substrate to form a source and a drain, respectively; forming a connection improvement layer located on the source, the drain and the control gate layer; forming an interlayer dielectric layer to cover the connection improvement layer and the isolation sidewall, and forming a control gate lead-out structure in the interlayer dielectric layer, wherein the control gate lead-out structure is located in the lead-out area.

[0013] In order to solve the above technical problems, the present application provides a memory device, comprising: a substrate, a substrate groove, a gate insulating layer, a semi-floating gate, an inter-gate dielectric layer, a control gate layer and a connection improvement layer, wherein the substrate groove is provided with a plurality of substrate grooves from the surface of the substrate toward the substrate, a part of the plurality of substrate grooves is located in a storage area, and a part of the plurality of substrate grooves is located in a lead-out area; a gate insulating layer and a semi-floating gate are formed in the substrate groove, a part of the semi-floating gate is in contact with the substrate, and the other part is isolated from the substrate by the gate insulating layer; the inter-gate dielectric layer covers the semi-floating gate, and the control gate layer is arranged on the inter-gate dielectric layer; the connection improvement layer covers the control gate layer, the control gate layer in the storage area serves as a control gate of a storage unit, and the control gate layer in the lead-out area serves as a lead-out end of the storage unit, and the lead-out end is connected to the control gates of a plurality of storage units in the same row.

[0014] In an embodiment of the present application, at least the contact portion between the half-floating gate and the substrate is made of single crystal material.

[0015] In an embodiment of the present application, an upper surface of the semi-floating gate is not higher than an upper surface of the substrate groove.

[0016] In one embodiment of the present application, a shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure is arranged at intervals along the second direction and extends along the first direction; wherein the shallow trench isolation structure includes a first isolation part and a second isolation part arranged at intervals, the first isolation part is arranged in the substrate, and the second isolation part protrudes from the substrate; the control gate and the lead-out terminal are connected through the control gate layer on the first isolation part.

[0017] In an embodiment of the present application, in the second direction, at least one corresponding lead-out terminal is provided for every preset number of control gates, and the lead-out terminal serves as a connection point for realizing the connection between the control gates in the same row and the outside world.

[0018] In an embodiment of the present application, an upper surface of the control gate layer is higher than an upper surface of the substrate groove.

[0019] In one embodiment of the present application, it also includes: a connection improvement layer, an interlayer dielectric layer and a control gate lead-out structure; wherein the connection improvement layer covers the substrate and the control gate layer; the interlayer dielectric layer covers the connection improvement layer; the control gate lead-out structure is located in the interlayer dielectric layer in the lead-out area, and the control gate lead-out structure is connected to the lead-out end.

[0020] Different from the prior art, the manufacturing method of the memory device provided in the present application includes: providing a semiconductor substrate, the semiconductor substrate including a substrate and a hard mask layer on the substrate; opening a plurality of first grooves in the semiconductor substrate, wherein a portion of the plurality of first grooves is located in the storage area and a portion is located in the lead-out area, wherein the portion of the first groove in the substrate is defined as a substrate groove; forming a gate insulating layer and a semi-floating gate in the substrate groove, wherein a portion of the semi-floating gate is in contact with the substrate, and the other portion is isolated from the substrate by the gate insulating layer; forming an inter-gate dielectric layer and a control gate layer in the plurality of first grooves, and forming a connection improvement layer on the control gate layer, wherein the control gate layer in the first groove in the storage area serves as a control gate of a memory cell, and the control gate layer in the first groove in the lead-out area serves as a lead-out terminal of the memory cell, and the lead-out terminal is connected to the control gates of a plurality of memory cells in the same row; that is, in the present application, forming the connection improvement layer on the control gate layer can effectively reduce the resistance of the control gate of the memory cell corresponding to the control gate layer, improve the operation speed of the semi-floating gate array in the memory cell, and thereby improve the performance of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0022] Figure 1 is a flow chart of an embodiment of a method for manufacturing a memory device in the present application;

[0023] Figure 2a and Figure 2b It is a schematic diagram of the structure of the semiconductor substrate in the second direction and the first direction in an embodiment of the present application;

[0024] Figure 3a and Figure 3b It is a schematic diagram of the second direction and the first direction structure of an embodiment of opening a second groove into the substrate in the present application;

[0025] Figure 4a and Figure 4b It is a schematic diagram of the second direction and the first direction structure of an embodiment of forming a shallow trench isolation structure in the present application;

[0026] Figure 5a and Figure 5b It is a schematic diagram of the second direction and the first direction structure of an embodiment of forming a second well region in the present application;

[0027] Figure 6a and Figure 6b It is a schematic diagram of the second direction and the first direction structure of an embodiment of forming a hard mask layer in the present application;

[0028] Figure 7a and Figure 7b It is a structural schematic diagram of the second direction and the first direction of an embodiment of providing a first groove in the present application;

[0029] Figure 8a and Figure 8b It is a schematic structural diagram of the second direction and the first direction of an embodiment of filling the first gate material in the present application;

[0030] Figure 9a and Figure 9b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming a contact window in the present application;

[0031] Fig.10a and Fig.10b It is a schematic diagram of the structure of the second direction and the first direction of an embodiment of filling the second gate material in the present application;

[0032] Fig.11a and Fig.11b It is a schematic diagram of the structure in the second direction and the first direction of an embodiment of forming a semi-floating gate and a gate insulating layer in the present application;

[0033] Fig.12a and Figure 12b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming the first isolation part in the present application;

[0034] Fig.13a and Fig.13b It is a schematic diagram of the structure of the second direction and the first direction of the shallow trench isolation structure in the present application;

[0035] Fig.14a and Fig.14b It is a schematic structural diagram of the second direction and the first direction of an embodiment of forming an inter-gate dielectric layer in the present application;

[0036] Fig.15a and Fig.15b It is a schematic diagram of the structure in the second direction and the first direction of an embodiment covering the third gate material in the present application;

[0037] Fig.16a and Fig.16b It is a schematic diagram of the structure of the second direction and the first direction of an embodiment of forming a control gate in the present application;

[0038] Fig.17a and Fig.17bIt is a structural schematic diagram of the second direction and the first direction of an embodiment of forming a second insulating layer in the present application;

[0039] Fig.18a and Fig.18b It is a structural schematic diagram of the second direction and the first direction of an embodiment of removing the hard mask layer in the present application;

[0040] Fig.19a and Fig.19b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming the first isolation side wall in the present application;

[0041] Fig.20a and Fig.20b It is a schematic structural diagram of the second direction and the first direction of an embodiment of forming the second isolation side wall in the present application;

[0042] Fig.21a and Figure 21b It is a schematic diagram of the structure of the second direction and the first direction of an embodiment of forming a connection improvement layer in the present application;

[0043] Fig.22a and Figure 22b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming an interlayer dielectric layer in the present application;

[0044] Fig.23 1 is a top view of an embodiment of a storage device in the present application.

[0045] In the accompanying drawings, a substrate 100, a second groove 101, a shallow trench isolation structure 102, a first groove 103, a vacant area 1031, a first insulating layer 104, a gate insulating layer 1041, a first gate material 105, a first gate 1051, a second gate material 106, a second gate 1061, a first well region 110, a second well region 120, a first dielectric layer 200, a second dielectric layer 300, a hard mask layer 400, a filling layer 410, and a protective layer 42 0, inter-gate dielectric layer 500, third gate material 600, control gate layer 610, second insulating layer 700, isolation sidewall 800, first isolation sidewall 810, second isolation sidewall 820, connection improvement layer 900, source connection improvement layer 910, drain connection improvement layer 920, control gate connection improvement layer 930, silicon nitride layer 940, interlayer dielectric layer ILD, lead-out structure V, source lead-out structure V1, control gate lead-out structure V2, drain lead-out structure V3. DETAILED DESCRIPTION

[0046] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0047] In the current memory device manufacturing process, especially the memory device manufacturing, in the manufacturing of the buried gate structure formed by the semi-floating gate, in its back-end process, the resistance corresponding to the memory cell is relatively large, and it is necessary to set a follow-up voltage point at a specific distance, such as setting a follow-up voltage point every 32 columns or 16 columns, which affects the operating speed of the semi-floating gate array and further affects the performance of the memory device.

[0048] Therefore, a method for manufacturing a memory device is provided, in which a connection improvement layer is formed on a control gate layer, which can effectively reduce the resistance of the control gate of the memory cell corresponding to the control gate layer, increase the operating speed of the semi-floating gate array in the memory cell, and thereby improve the performance of the memory device.

[0049] See also Figure 1 , Figure 1 It is a flow chart of an embodiment of a method for manufacturing a memory device in the present application.

[0050] like Figure 1 As shown, the manufacturing method of the memory device of the present application includes:

[0051] S11. Provide a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a hard mask layer on the substrate.

[0052] The semiconductor substrate in step S11 is as follows Figure 7a , 7b As shown, the operation flow of step S11 in the embodiment is as follows:

[0053] A substrate is provided, and a first dielectric layer and a second dielectric layer are sequentially formed on the substrate.

[0054] The substrate may be any suitable base material known in the art, for example, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI) and germanium on insulator (GeOI).

[0055] See also Figure 2a and Figure 2b , Figure 2a and Figure 2b It is a schematic diagram of the structure of the second direction and the first direction of an embodiment of a semiconductor substrate in the present application.

[0056] Specifically, a substrate 100 is provided, and a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate.

[0057] In some embodiments, the first dielectric layer 200 may be an oxide layer, such as a silicon oxide layer, and the second dielectric layer 300 may be a nitride layer, such as a silicon nitride layer.

[0058] Second grooves are opened from the second dielectric layer toward the substrate, wherein the second grooves are arranged at intervals along the second direction and extend along the first direction.

[0059] like Figure 2a As shown, in the second direction, a substrate 100 is provided, and a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on the substrate 100; Figure 2b As shown, in a first direction, a first dielectric layer 200 and a second dielectric layer 300 are sequentially formed on a substrate 100 .

[0060] Among them, the second direction is the word line extension direction (wordline, WL), the second direction is also the X direction, and the X direction is the row direction; the first direction is the bit line extension direction (bitline, BL), the first direction is also the Y direction, and the Y direction is the column direction; that is, the first direction and the second direction are perpendicular to the same horizontal plane.

[0061] In some embodiments, a shallow trench isolation structure may be further provided in the substrate, as described below.

[0062] See also Figure 3a and Figure 3b , Figure 3a and Figure 3b It is a schematic diagram of the second direction and first direction structures of an embodiment of opening a second groove into a substrate in the present application.

[0063] like Figure 3a As shown in FIG. 1 , in the second direction, a second groove 101 is opened from the second dielectric layer 300 to the substrate 100. Figure 3b As shown, keep Figure 2b structure.

[0064] In some embodiments, a plurality of second grooves 101 are sequentially spaced apart along the second direction (X direction), and the bottom of the second groove 101 is higher than the bottom of the substrate 100 , that is, the second groove 101 extends to a portion of the substrate 100 .

[0065] Furthermore, an isolation material is filled in the second groove to form a shallow trench isolation structure; and ion implantation is performed to form a first well region in the substrate.

[0066] See also Figure 4a and Figure 4b , Figure 4a and Figure 4b It is a schematic diagram of the second direction and first direction structures of an embodiment of forming a shallow trench isolation structure in the present application.

[0067] like Figure 4a As shown, in the second direction, an isolation material is filled in the second groove 101 to form a shallow trench isolation structure 102, and then ion implantation is performed on the substrate 100 to form a first well region 110 in the substrate 100; wherein the shallow trench isolation structure 102 penetrates into the first well region 110, and the bottom of the shallow trench isolation structure 102 is higher than the bottom of the first well region 110 and lower than the top of the first well region 110; as shown in FIG. Figure 4b As shown, ion implantation is performed on the substrate 100 in a first direction to form a first well region 110 in the substrate 100 .

[0068] In some embodiments, the lowest point of the first well region 110 is higher than the lowest point of the substrate 100 , and the highest point of the first well region 110 is lower than the highest point of the substrate 100 , that is, the first well region 110 is located in the substrate 100 .

[0069] In some embodiments, a portion of the shallow trench isolation structure 102 is disposed in the substrate 100 and a portion protrudes from the substrate 100 to define a plurality of active areas (AA) in the substrate. The shallow trench isolation structure 102 extends along a first direction and is spaced apart in a second direction.

[0070] After the shallow trench isolation structure 102 is formed, the second dielectric layer 300 is removed to expose a portion of the shallow trench isolation structure 102 .

[0071] The first dielectric layer 200 is used as a barrier layer to perform ion implantation on the substrate 100 to form a second well region 120 on a side of the substrate 100 close to the first dielectric layer 200 ; wherein the doping type of the second well region 120 is different from the doping type of the first well region 110 .

[0072] See also Figure 5a and Figure 5b , Figure 5a and Figure 5b It is a schematic diagram of the second direction and first direction structure of an embodiment of forming the second well region in the present application.

[0073] like Figure 5aAs shown, in the second direction, the second dielectric layer 300 is removed to expose part of the shallow trench isolation structure 102, and the first dielectric layer 200 is used as a barrier layer to perform ion implantation on the substrate 100 to form a second well region 120 on a side of the substrate 100 close to the first dielectric layer 200; Figure 5b As shown, in a first direction, the second dielectric layer 300 is removed to expose the first dielectric layer 200 , and ion implantation is performed on the substrate 100 using the first dielectric layer 200 as a barrier layer to form a second well region 120 on a side of the substrate 100 close to the first dielectric layer 200 , wherein the second well region 120 is above the first well region 110 .

[0074] In some embodiments, the doping types of the first well region 110 and the second well region 120 are different, that is, the doping types of the first well region 110 and the second well region 120 are opposite; for example, the first well region 110 is an N-type doped well region, and the second well region 120 is a P-type doped well region; conversely, the first well region 110 is a P-type doped well region, and the second well region is an N-type doped well region.

[0075] Next, a filling covering layer is formed on the first dielectric layer, and the first dielectric layer and the filling covering layer are used as a hard mask layer 400, wherein the filling covering layer is filled between two adjacent shallow trench isolation structures 102 and covers the shallow trench isolation structure 102, and can be a multi-layer structure or a single-layer structure. In the case of a multi-layer structure, the filling covering layer can include a filling layer 410 and a protective layer 420, and then: a filling layer 410 is formed on the first dielectric layer 200, wherein the filling layer 410 is filled between two adjacent shallow trench isolation structures 102; and a protective layer 420 is formed on the filling layer 410 and the shallow trench isolation structure 102. Alternatively, the filling covering layer is a single-layer structure, such as a silicon nitride layer, which is filled between two shallow trench isolation structures 102 and formed on the shallow trench isolation structure 102, and the first dielectric layer 200 is also used as a part of the hard mask layer 400.

[0076] See also Figure 6a and Figure 6b , Figure 6a and Figure 6b It is a schematic diagram of the second direction and first direction structure of an embodiment of forming a hard mask layer in the present application.

[0077] like Figure 6a As shown, in the second direction, a filling layer 410 is formed on the first dielectric layer 200, and the filling layer 410 is filled between two adjacent shallow trench isolation structures 102, and then a protection layer 420 is formed on the filling layer 410 and the shallow trench isolation structure 102, wherein the filling layer 410 and the protection layer 420 constitute a filling cover layer, and the first dielectric layer 200, the filling layer 410 and the protection layer 420 are used as a hard mask layer 400. Figure 6bAs shown, in the first direction, a filling layer 410 is formed on the first dielectric layer 200 , and then a protection layer 420 is formed on the filling layer 410 .

[0078] In some embodiments, the filling layer 410 may be a polycrystalline material filling layer, such as polysilicon, and the protective layer 420 may be an ON structure composed of a nitride layer and an oxide layer, such as an ON structure protective layer composed of a silicon nitride layer and a silicon oxide layer.

[0079] S12. A plurality of first grooves are formed in the semiconductor substrate, wherein a portion of the plurality of first grooves is located in the storage area and a portion of the plurality of first grooves is located in the lead-out area, wherein a portion of the first groove in the substrate is defined as a base groove.

[0080] Then, a plurality of first grooves are opened in the active area of ​​the substrate 100 from the hard mask layer 400, wherein a portion of the plurality of first grooves is located in the storage area and another portion is located in the lead-out area, wherein the portion of the first groove in the substrate is defined as a base groove. Figure 7a and 7b shown.

[0081] The operation flow of the embodiment of step S12 is as follows:

[0082] See also Figure 7a and Figure 7b , Figure 7a and Figure 7b It is a structural schematic diagram of the second direction and the first direction of an embodiment of opening a first groove in the present application.

[0083] like Figure 7a As shown, in the second direction, a portion of the hard mask layer 400 on the shallow trench isolation structure 102 between two adjacent first grooves 103 is removed to expose a portion of the shallow trench isolation structure 102, and then a first groove 103 is opened in the active area between the shallow trench isolation structures 102; Figure 7b As shown, in the first direction, a plurality of first grooves 103 are opened from the hard mask layer 400 to the active area of ​​the substrate 100 at intervals; wherein, in the second direction, the first grooves 103 are separated by shallow trench isolation structures 102, and a plurality of first grooves 103 are arranged at intervals in the first direction.

[0084] In some embodiments, the first groove 103 sequentially penetrates the protective layer 420, the filling layer 410, the first dielectric layer 200 and the second well region 120, that is, penetrates the hard mask layer 400 and the second well region 120, that is, the bottom of the first groove 103 contacts the first well region 110, so that the first well region 110 is exposed through the first groove 103.

[0085] S13, forming a gate insulating layer and a semi-floating gate in the substrate groove, wherein a portion of the semi-floating gate is in contact with the substrate, and the other portion is isolated from the substrate by the gate insulating layer.

[0086] Because the portion of the first groove in the substrate is defined as a base groove, a gate insulating layer and a semi-floating gate are formed in the base groove, a portion of the semi-floating gate contacts the substrate, and the other portion is isolated from the substrate by the gate insulating layer.

[0087] The operation flow of step S13 in an embodiment is as follows:

[0088] A gate insulating layer and a semi-floating gate are formed in the substrate groove.

[0089] See also Figure 8a and Figure 8b , Figure 8a and Figure 8b It is a structural schematic diagram of the second direction and the first direction of an embodiment of filling the first gate material in the present application.

[0090] like Figure 8a As shown, in the second direction, a first insulating layer 104 is formed on the inner wall of the substrate groove. The first insulating layer 104 can be formed on the exposed substrate by a thermal oxidation process, and a first gate material 105 is filled in the first groove 103, and the first gate material 105 covers the first groove 103; Figure 8b As shown, in the first direction, a first insulating layer 104 is formed on the inner wall of the substrate groove, and a first gate material 105 is filled in the first groove 103 , so that the first gate material 105 is flush with the hard mask layer 400 , that is, flush with the protection layer 420 .

[0091] In some embodiments, the first gate material 105 may be a polycrystalline material, such as polysilicon. After the first gate material 105 is filled, the first gate material 105 is chemically mechanically polished so that the first gate material 105 is flush with the protection layer 420 .

[0092] In some embodiments, when forming the first insulating layer 104 on the inner wall of the first groove 103 and filling the first gate material 105 in the first groove 103, the first gate material 105 also covers the shallow trench isolation structure 102. Figure 8a .

[0093] Next, a portion of the first gate material 105 and a corresponding portion of the first insulating layer 104 in the first groove 103 are removed to form a contact window; wherein at least a portion of the first insulating layer in the substrate groove is removed.

[0094] See also Figure 9a and Figure 9b , Figure 9a and Figure 9b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming a contact window in the present application.

[0095] like Figure 9b As shown, in the first direction, a portion of the first gate material 105 and a corresponding portion of the first insulating layer 104 in the first groove 103 are removed, and a portion of the first gate material 105 and a portion of the first insulating layer 104 in the base groove close to the substrate 100 are removed to form a contact window with the substrate 100; Figure 9a As shown, in the second direction, keep Figure 8a The structure shown; wherein, the removal method can be photolithography or etching.

[0096] Then, the second gate material is filled in the idle area of ​​the first groove 103, that is, the second gate material is formed above the contact window; wherein the second gate material in the base groove contacts the substrate through the contact window.

[0097] See also Fig.10a and Fig.10b , Fig.10a and Fig.10b It is a structural schematic diagram of the second direction and the first direction of an embodiment of filling the second gate material in the present application.

[0098] like Fig.10a As shown, in the second direction, keep Figure 9a The structure shown; Fig.10b As shown, in the first direction, after removing part of the first gate material 105 and the corresponding part of the first insulating layer 104 in the first groove 103, an idle area of ​​the first groove 103 is formed, and the second gate material 106 is filled in the idle area of ​​the first groove 103, that is, the second gate material 106 is formed above the contact window, and chemical mechanical polishing is performed after filling to make the surface after filling flat; and because at least part of the first insulating layer 104 in the substrate groove is removed to form a contact window, the second gate material 106 in the substrate groove can contact the substrate 100 through the contact window, such as contacting the second well region 120.

[0099] In some embodiments, the second gate material 106 may be formed by an epitaxial or deposition process. In one embodiment, the second gate material 106 is formed by an epitaxial process so that at least the second gate material 106 in contact with the substrate 100 is a single crystal material.

[0100] After filling the second gate material 106 , a semi-floating gate and a gate insulating layer are formed.

[0101] See also Fig.11a and Fig.11b , Fig.11a and Fig.11b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming a semi-floating gate and a gate insulation layer in the present application.

[0102] In one embodiment, the manufacturing process of the semi-floating gate is as follows:

[0103] like Fig.11b As shown, in the first direction, part of the first gate material 105, the second gate material 106 and the first insulating layer 104 in the first groove 103 are removed, and the first gate material 105, the second gate material 106 and the first insulating layer 104 in the substrate groove are retained, and the retained first gate material 105 is used as the first gate 1051, the retained second gate material 106 is used as the second gate 1061, and the retained first insulating layer 104 is used as the gate insulating layer 1041. The first gate 1051 and the second gate 1061 cooperate to form a semi-floating gate, and at least the contact portion between the semi-floating gate and the substrate 100 is made of single crystal material.

[0104] In some embodiments, the upper surface of the semi-floating gate is not higher than the upper surface of the substrate groove, that is, the upper surface of the semi-floating gate may be lower than the upper surface of the substrate groove, forming a buried gate structure, such as Fig.11b As shown; the upper surface of the semi-floating gate can also be flush with the upper surface of the substrate groove or higher than the upper surface of the substrate groove, forming a non-buried gate structure, which can reduce the etching depth and thus reduce the process difficulty.

[0105] In some embodiments, when performing the step of removing a portion of the first gate material 105, the second gate material 106 and the first insulating layer 104 in the first groove 103, a portion of the first gate material 105 covering the shallow trench isolation structure 102 is removed at the same time, thereby continuing to expose a portion of the shallow trench isolation structure 102.

[0106] like Fig.11a As shown, in the second direction, the portion of the first gate material 105 covering the shallow trench isolation structure 102 is removed simultaneously, so that the shallow trench isolation structure 102 continues to be exposed.

[0107] In another embodiment, the manufacturing process of the half floating gate is as follows:

[0108] A first insulating layer 104 is formed on the inner wall of the substrate groove, and a sacrificial material is formed on the first insulating layer 104, so that the sacrificial material fills the first groove 103; a portion of the sacrificial material and the first insulating layer 104 are removed to form a contact window on the side wall of the substrate groove; the sacrificial material is removed and the gate material is filled; a portion of the gate material and the first insulating layer 104 in the first groove 103 is removed so that the upper surface of the gate material is not higher than the upper surface of the substrate groove, so as to form a semi-floating gate and a gate insulating layer in the substrate groove.

[0109] The remaining gate material is a semi-floating gate, the remaining first insulating layer is a gate insulating layer, a portion of the semi-floating gate contacts the substrate through a contact window, and another portion of the semi-floating gate is isolated from the substrate by the gate insulating layer. At least the contact portion between the semi-floating gate and the substrate is made of single crystal material.

[0110] The material of the sacrificial material is, for example, a silicon-rich composite material or other suitable dielectric material, wherein the gate material remaining in the substrate groove is a semi-floating gate, and the first insulating layer 104 remaining in the substrate groove is a gate insulating layer.

[0111] Next, the height of the shallow trench isolation structure is reduced to form a first isolation portion.

[0112] See also Fig.12a and Figure 12b , Fig.12a and Figure 12b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming the first isolation part in the present application.

[0113] like Fig.12a As shown, in the second direction, based on Fig.11a , removing the exposed portion of the shallow trench isolation structure 102, that is, lowering the height of the shallow trench isolation structure 102 so that the height of the shallow trench isolation structure 102 is not higher than the height of the half-floating gate, so as to form a first isolation portion; Figure 12b As shown, in the first direction, it is possible to maintain Fig.11b structure.

[0114] In some embodiments, when the height of the shallow trench isolation structure 102 is reduced to form the first isolation portion, the remaining shallow trench isolation structure 102 may be flush with the half-floating gate to serve as the first isolation portion.

[0115] In some embodiments, the height of the shallow trench isolation structure may be further reduced.

[0116] See also Fig.13a and Fig.13b , Fig.13a and Fig.13b It is a structural schematic diagram of the second direction and the first direction of the shallow trench isolation structure that are further reduced in the present application.

[0117] like Fig.13a As shown, in the second direction, based on Fig.12a , removing a portion of the shallow trench isolation structure 102 so that the height of the shallow trench isolation structure 102 is lower than the height of the half-floating gate, and using the remaining portion of the shallow trench isolation structure 102 as the first isolation portion; Fig.13b As shown, in the first direction, the protection layer 420 may be removed.

[0118] The removal process here may be wet etching first and then dry etching.

[0119] Furthermore, the manufacturing process of the control gate layer is as follows.

[0120] S14, forming an inter-gate dielectric layer and a control gate layer in the plurality of first grooves, and forming a connection improvement layer on the control gate layer, wherein the control gate layer in the first groove of the storage area serves as a control gate of the storage unit, and the control gate layer in the first groove of the lead-out area serves as a lead-out terminal of the storage unit, and the lead-out terminal is connected to the control gates of the plurality of storage units in the same row.

[0121] The operation flow of step S14 in an embodiment is as follows:

[0122] An inter-gate dielectric layer is formed, wherein the inter-gate dielectric layer at least covers a half floating gate.

[0123] See also Fig.14a and Fig.14b , Fig.14a and Fig.14b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming an inter-gate dielectric layer in the present application.

[0124] like Fig.14a As shown, in the second direction, based on Fig.13a , forming an inter-gate dielectric layer 500, so that the inter-gate dielectric layer 500 covers the first isolation portion and the semi-floating gate in the substrate groove, forming a tooth structure, thereby increasing the coupling area between the semi-floating gate and the control gate; Fig.14b As shown, in the first direction, an inter-gate dielectric layer 500 is formed so that the inter-gate dielectric layer 500 covers the first groove 103 portion above the semi-floating gate composed of the first gate 1051 and the second gate 1061 , and covers the residual hard mask layer 400 on the area between two adjacent first grooves 103 .

[0125] Then, the third gate material is covered on the inter-gate dielectric layer, and the excess third gate material is removed until it is flush with the highest point of the first groove, that is, the upper surface of the third gate material is flush with the highest point of the first groove.

[0126] See also Fig.15a and Fig.15b , Fig.15a and Fig.15b It is a schematic diagram of the structure of the second direction and the first direction covering an embodiment of the third gate material in the present application.

[0127] like Fig.15a As shown, in the second direction, based on Fig.14a, covering the inter-gate dielectric layer 500 with a third gate material 600, and removing excess third gate material 600, so that the upper surface of the third gate material 600 is flush with the highest point of the first groove 103; Fig.15b As shown, in the first direction, based on Fig.14b , covering the inter-gate dielectric layer 500 with the third gate material 600 , and removing excess third gate material 600 , so that the upper surface of the third gate material 600 is flush with the highest point of the first groove 103 .

[0128] A portion of the third gate material in the first groove is removed, and the remaining third gate material is used as a control gate layer, and the upper surface of the control gate layer is higher than the upper surface of the substrate groove. Then, a control gate of the storage area and an extraction terminal of the extraction area are formed respectively.

[0129] See also Fig.16a and Fig.16b , Fig.16a and Fig.16b It is a schematic diagram of the structure of the second direction and the first direction of forming an embodiment of the control gate in the present application.

[0130] like Fig.16b As shown, in the first direction, based on Fig.15b , remove part of the third gate material 600 in the first groove 103 to form a vacant area 1031, so that the upper surface of the remaining third gate material 600 is higher than the upper surface of the substrate groove, and the remaining third gate material 600 is used as the control gate layer 610, wherein the control gate layer 610 in the first groove of the storage area is used as the control gate of the storage unit, and the control gate layer 610 in the first groove of the lead-out area is used as the lead-out end of the control gate of the storage unit. Fig.16a As shown, in the second direction, part of the third gate material 600 of the first groove 103 is removed, that is, the thickness of the third gate material 600 in the first groove 103 is thinned, and the remaining third gate material 600 is used as the control gate layer 610, wherein the control gate layer 610 is located on the first isolation portion, and the control gate layers 610 of adjacent rows are isolated by the second isolation portion.

[0131] In some embodiments, the upper surface of the semi-floating gate away from the substrate is lower than the upper surface of the base groove away from the substrate, that is, when the semi-floating gate does not fill the base groove, part of the control gate layer is in the base groove. At this time, the control gate layer 610 in the base groove of the storage area also serves as the control gate of the storage unit, and the control gate layer 610 in the base groove of the lead-out area also serves as the lead-out end of the control gate of the storage unit.

[0132] In other embodiments, the upper surface of the semi-floating gate away from the substrate is flush with or higher than the upper surface of the substrate groove away from the substrate. In this case, the control gate layer 610 above the substrate groove in the storage area serves as the control gate of the storage unit, and the control gate layer 610 above the substrate groove in the lead-out area serves as the lead-out end of the control gate of the storage unit.

[0133] In some embodiments, in the first direction, the first isolation portions and the second isolation portions are alternately arranged at intervals; the upper surface mentioned in the present application is a surface away from the substrate in the axial direction.

[0134] In order to more completely represent the structure of the device, Fig.16b The left side of the dotted line is a cross-sectional view of a vacant area 1031 formed in the first direction, located in the storage area, as follows Fig.23 A cross-sectional view of the storage area in the Y2 direction; Fig.16b The right side of the dotted line is a cross-sectional view of the third gate material 600 in the first groove 103 that is retained in the first direction, and the retained third gate material 600 is used as the lead-out end of the control gate of the storage unit, which is located in the lead-out area, as follows Fig.23 The cross-sectional view of the region Y3 is shown in FIG. Fig.16b As shown, a portion of the third gate material 600 in the first groove in the storage area is removed to form a control gate layer 610, which serves as a control gate, and the upper surface of the control gate layer 610 is higher than the upper surface of the substrate groove; a portion of the third gate material 600 in the first groove in the lead-out area is removed to form a control gate layer 610, which serves as a lead-out terminal, and the upper surface of the control gate layer 610 is higher than the upper surface of the substrate groove. Fig.16a As shown, viewed from the second direction, the thickness of the third gate material 600 is reduced to form a control gate layer 610 .

[0135] Next, a second insulating layer 700 is formed on the vacant area 1031 of the first groove 103 and the third gate material remaining on the first isolation portion.

[0136] See also Fig.17a and Fig.17b , Fig.17a and Fig.17b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming the second insulating layer in the present application.

[0137] like Fig.17a As shown, in the second direction, based on Fig.16a , forming a second insulating layer 700 on the third gate material 600; Fig.17b As shown, in the first direction, based on Fig.16bA second insulating layer 700 is formed in the vacant area 1031 of the first groove 103, and chemical mechanical polishing is performed to make the surface flat. The thickness of the second insulating layer 700 can be 300A, and the material of the second insulating layer 700 is, for example, silicon oxide.

[0138] In some embodiments, in a first direction (as described below) Fig.23 In the Y2 direction), a portion of the third gate material 600 in the first groove 103 of the storage area and the third gate material 600 in the first groove 103 of the lead-out area are removed, that is, the thickness is reduced, and the thinning thickness range can be 300A-400A, 1A=0.1 nanometers, such as thinning by 350A, to form a control gate layer 610, and chemical mechanical polishing is performed after the second insulating layer 700 is formed, so that the thickness of the second insulating layer is 300A-400A, and the upper surface of the control gate layer 610 is higher than the upper surface of the substrate groove; wherein, the control gate layer 610 in the first groove 103 of the storage area serves as the control gate of the storage unit, and the control gate layer 610 in the first groove 103 of the lead-out area serves as the lead-out end of the control gate of the storage unit, and the lead-out end is connected to the control gates of multiple storage units in the same row.

[0139] In some embodiments, in the second direction, the third gate material 600 retained in the first groove of the lead-out region of the same row serves as a connection point for all control gates in the memory cells of the row, and is used to realize the connection between the control gates in the memory cells of the same row and the outside world; a lead-out terminal of the control gate can be set at a fixed distance BL, such as every 64 columns BL or 80 columns or a larger distance, that is, the lead-out terminal corresponding to the lead-out region, so that the control gate is connected to the outside world through the lead-out terminal, thereby increasing the setting distance of the lead-out terminal and improving the area utilization rate of the storage device.

[0140] In addition, the method also includes removing all hard mask layers on the memory device.

[0141] See also Fig.18a and Fig.18b , Fig.18a and Fig.18b It is a structural schematic diagram of the second direction and the first direction of an embodiment of removing the hard mask layer in the present application.

[0142] like Fig.18a As shown in FIG. 1 , in the second direction, because it corresponds to the cross-sectional view of the first groove in the second direction, that is, the cross-sectional view corresponding to the first isolation portion, the second insulating layer 700 is thinned while maintaining the structure of FIG. 17a , and the first insulating layer 104 and the hard mask layer 400 corresponding to the second isolation portion are removed; Fig.18bAs shown, in the first direction, the first insulating layer 104 and the hard mask layer 400 in the area between two adjacent substrate grooves, as well as a portion of the inter-gate dielectric layer above the substrate grooves are removed, wherein phosphoric acid can be used to remove the protective layer 420, and dry etching can be used to remove the filling layer 410, and phosphoric acid is used to remove a portion of the inter-gate dielectric layer above the substrate groove to expose the side walls of the control gate layer 610 and the second insulating layer 700; at the same time, the thickness of the second insulating layer 700 is thinned to, for example, 200A.

[0143] Next, an isolation sidewall is formed on the sidewall of the control gate layer 610 , and the isolation sidewall may include a first isolation sidewall and a second isolation sidewall, wherein one side of the first isolation sidewall covers the sidewall of the control gate layer 610 , and the other side contacts the second isolation sidewall.

[0144] See also Fig.19a and Fig.19b , Fig.19a and Fig.19b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming the first isolation side wall in the present application.

[0145] like Fig.19a As shown, in the second direction, keep Fig.18a Based on the structure of , the second insulating layer 700 can be thinned; Fig.19b As shown, in the first direction, the sidewall of the control gate layer 610 is oxidized by rapid thermal oxidation (RTO) to form a first isolation sidewall, and the first isolation sidewall may be an oxidation protection layer, and the thickness of the oxidation protection layer may be 50 Å.

[0146] In some embodiments, a first rapid thermal oxidation (RTO) is performed on the side wall of the control gate layer 610 to form a 50A oxide protection layer, which is then cleaned away by hydrofluoric acid (HF), and then a second rapid thermal oxidation (RTO) is performed to form a 50A oxide protection layer, i.e., the first isolation side wall 810.

[0147] In some embodiments, the second insulating layer 700 on the control gate layer 610 may be thinned, so that the thickness of the thinned second insulating layer 700 is, for example, 100 Å.

[0148] See also Fig.20a and Fig.20b , Fig.20a and Fig.20b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming a second isolation side wall in the present application.

[0149] like Fig.20a As shown, in the second direction, keep Fig.19a structure; such as Fig.20bAs shown, in the first direction, a second isolation sidewall 820 is deposited and etched to form an isolation sidewall on the sidewall of the control gate layer 610; wherein the second isolation sidewall 820 covers the first isolation sidewall 810, and the second isolation sidewall 820 and the first isolation sidewall 810 cooperate to form an isolation sidewall 800, and the thickness of the second isolation sidewall 820 can be 50A.

[0150] In some embodiments, the first isolation sidewall may be a silicon oxide layer, and the second isolation sidewall may be a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be deposited by deposition to form the isolation sidewall 800 .

[0151] In some embodiments, the second insulating layer 700 on the control gate layer 610 may be thinned again, so that the thickness of the thinned second insulating layer 700 is, for example, 50 Å.

[0152] Furthermore, a connection improving layer is formed.

[0153] See also Fig.21a and Figure 21b , Fig.21a and Figure 21b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming a connection improvement layer in the present application.

[0154] like Fig.21a As shown, in the second direction, a connection improvement layer 900 is formed on the control gate layer 610, so that the connection improvement layer 900 is directly in contact with the control gate layer 610; Figure 21b As shown, in the first direction, a connection improvement layer is formed on the substrate 100 and the control gate layer 610 , so that the connection improvement layer 900 on the substrate 100 is directly connected to the substrate 100 , and the connection improvement layer 900 on the control gate layer 610 is directly connected to the control gate layer 610 .

[0155] In some embodiments, before forming the connection improvement layer, ion implantation is performed in the substrate on both sides of the first groove 103 in the storage area in the first direction to form a source and a drain respectively, and then the source and the drain are respectively led out through the lead-out structure formed subsequently.

[0156] In some embodiments, the connection improvement layer 900 may include a source connection improvement layer 910, a drain connection improvement layer 920 and a control gate connection improvement layer 930; wherein the source connection improvement layer 910 is formed on the source, the drain connection improvement layer 920 is formed on the drain, and the control gate connection improvement layer 930 is formed on the control gate layer 610 in the lead-out area.

[0157] The connection improvement layer can be a metal silicide layer, which can be formed by removing the first dielectric layer 200 on the substrate 100, forming a source connection improvement layer and a drain connection improvement layer on the source and the drain respectively, and removing the second insulating layer 700 on the control gate layer 610 to form a control gate connection improvement layer; for example, after removing the first dielectric layer 200 on the substrate 100, metal is deposited, and the deposited metal is annealed so that the metal reacts with the substrate silicon, thereby forming a metal silicide layer.

[0158] Next, an interlayer dielectric layer is formed.

[0159] See also Fig.22a and Figure 22b , Fig.22a and Figure 22b It is a structural schematic diagram of the second direction and the first direction of an embodiment of forming an interlayer dielectric layer in the present application.

[0160] like Fig.22a As shown, in the second direction, an interlayer dielectric layer ILD is formed on the connection improvement layer, and a lead structure V is formed in the interlayer dielectric layer ILD; as shown Figure 22b As shown, in the first direction, an interlayer dielectric layer ILD is formed, the interlayer dielectric layer ILD covers the connection improving layer 900 , and a lead-out structure V is formed in the interlayer dielectric layer ILD.

[0161] In some embodiments, a silicon nitride layer (SIN) 940 may be first formed on the connection improving layer, that is, the silicon nitride layer (SIN) 940 covers the connection improving layer 900 , and then an interlayer dielectric layer ILD is formed on the silicon nitride layer (SIN) 940 .

[0162] In some embodiments, the lead-out structure includes a source lead-out structure V1, a control gate lead-out structure V2 and a drain lead-out structure V3. The source lead-out structure V1 corresponds to being connected to the source connection improvement layer 910, that is, corresponding to being connected to the source electrode; the control gate lead-out structure V2 corresponds to being connected to the control gate connection improvement layer 930, that is, corresponding to being connected to the lead-out end of the lead-out area; the drain lead-out structure V3 corresponds to being connected to the drain connection improvement layer 920, that is, corresponding to being connected to the drain electrode.

[0163] In order to more completely illustrate the structure of the memory device, the description is made from a top view perspective.

[0164] See also Fig.23 , Fig.23 It is a top view of an embodiment of a storage device in the present application.

[0165] like Fig.23As shown, in the first direction, it can be divided into three types of regions, among which Y1 is the first type of region in the first direction, which is a cross-sectional view corresponding to the shallow trench isolation structure exposing the substrate 100; Y2 is the second type of region in the first direction, which is a cross-sectional view corresponding to the source lead-out structure and the drain lead-out structure; Y3 is the third type of region in the first direction, which is a cross-sectional view corresponding to the lead-out end, that is, a cross-sectional view corresponding to the control gate lead-out structure; the left side of the dotted line of the aforementioned Xb figure is a cross-sectional view in the Y2 direction, and the right side of the dotted line of the aforementioned Xb figure is a cross-sectional view in the Y3 direction.

[0166] Among them, the shallow trench isolation structure (STI) in the X1 direction is the second isolation part, exposing the substrate, and the shallow trench isolation structure in the X3 direction is the first isolation part. The first isolation part and the second isolation part are alternately arranged in the first direction, and a control gate layer corresponds to the first isolation part, and a lead-out terminal is set in the lead-out area, which is led out through the control gate lead-out structure V2, so that the control gate of the storage unit is connected to the outside world through the lead-out terminal.

[0167] In the second direction, it can be divided into three types of regions, among which X1 is the first type of region in the second direction, which is the cross-sectional view corresponding to the source; X2 is the second type of region in the second direction, which is the cross-sectional view corresponding to the drain; X3 is the third type of region in the second direction, which is the cross-sectional view corresponding to the control gate layer, and the aforementioned Xa figures are all cross-sectional views in the X3 direction.

[0168] Among them, the shallow trench isolation structure defines a plurality of active areas (Active Area, AA) on the substrate, that is, the shallow trench isolation structure (STI) and the active area (AA) are alternately arranged in the second direction, and the active area (AA) can be provided with a source and a drain respectively. For example, if there is a control gate layer corresponding to the X3 direction, the source can be provided in the X1 direction, and the drain can be provided in the X2 direction to form a storage unit, and the source can be shared, that is, the control gate layers on both sides of the X1 direction can share the source in the X1 direction.

[0169] In this embodiment, the upper surface of the control gate layer is set to be higher than the upper surface of the substrate groove, and then a connection improvement layer is formed on the control gate layer. This can effectively reduce the resistance of the control gate of the storage unit in the storage device, increase the operating speed of the semi-floating gate array, and thus improve the performance of the storage device. It can also reduce the etching depth of the control gate layer, thereby reducing the process difficulty.

[0170] The above description is only an implementation mode of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for manufacturing a memory device, It is characterized in that include: Providing a semiconductor substrate, the semiconductor substrate comprising a substrate and a hard mask layer on the substrate; A plurality of first grooves are formed in the semiconductor substrate, wherein a portion of the plurality of first grooves is located in the storage area and a portion of the plurality of first grooves is located in the lead-out area, wherein a portion of the first groove in the substrate is defined as a base groove; forming a gate insulating layer and a semi-floating gate in the substrate groove, wherein a portion of the semi-floating gate contacts the substrate, and another portion of the semi-floating gate is isolated from the substrate by the gate insulating layer; An inter-gate dielectric layer and a control gate layer are formed in the plurality of first grooves, and a connection improvement layer is formed on the control gate layer, wherein the control gate layer in the first groove of the storage area serves as a control gate of a storage unit, and the control gate layer in the first groove of the lead-out area serves as a lead-out terminal of the storage unit, and the lead-out terminal is connected to the control gates of the plurality of storage units in the same row.

2. The method according to claim 1, It is characterized in that The semiconductor substrate is provided, comprising: Providing a substrate, and forming a first dielectric layer and a second dielectric layer on the substrate; Opening a plurality of second grooves in the active area of ​​the substrate from the second dielectric layer, wherein the second grooves are arranged at intervals along the first direction and extend along the second direction; Filling the second groove with an isolation material to form a shallow trench isolation structure, and performing ion implantation on the substrate to form a first well region in the substrate; removing the second dielectric layer to expose a portion of the shallow trench isolation structure; Using the first dielectric layer as a barrier layer, ion implantation is performed on the substrate to form a second well region on one side of the substrate; wherein the second well region is located on the first well region, and the doping type is different from the doping type of the first well region; A filling covering layer is formed on the first dielectric layer, and the first dielectric layer and the filling covering layer are used as the hard mask layer, wherein the filling covering layer is filled between two adjacent shallow trench isolation structures and covers the shallow trench isolation structures.

3. The method according to claim 1, It is characterized in that The forming of a gate insulating layer and a semi-floating gate in the substrate groove comprises: forming a first insulating layer on the inner wall of the substrate groove, and forming a sacrificial material on the first insulating layer, wherein the sacrificial material fills the first groove; removing a portion of the sacrificial material and the first insulating layer to form a contact window; removing the remaining sacrificial material and filling the first groove with a gate material; Removing part of the gate material and the first insulating layer to form a gate insulating layer and a semi-floating gate in the substrate groove; wherein the remaining gate material serves as the semi-floating gate, the remaining first insulating layer serves as the gate insulating layer, and a part of the semi-floating gate contacts the substrate through the contact window; Alternatively, a first insulating layer is formed on the inner wall of the substrate groove, and a first gate material is filled in the first groove; removing a portion of the first gate material and the first insulating layer to form a contact window, and forming a second gate material above the contact window; Part of the first gate material, the second gate material and the first insulating layer are removed, and the remaining first gate material, the second gate material and the first insulating layer are used as the first gate, the second gate and the gate insulating layer respectively, and the first gate and the second gate cooperate to form the semi-floating gate.

4. The method according to claim 1, It is characterized in that The upper surface of the semi-floating gate is not higher than the upper surface of the substrate groove.

5. The method according to claim 1, It is characterized in that A shallow trench isolation structure is disposed in the substrate, wherein a portion of the shallow trench isolation structure is disposed in the substrate and another portion is exposed from the substrate, and the shallow trench isolation structure is disposed at intervals along a first direction and extends along a second direction; After forming a gate insulating layer and a semi-floating gate at the bottom of the substrate groove, a portion of the shallow trench isolation structure is removed to form a first isolation portion, wherein an upper surface of the first isolation portion is not higher than an upper surface of the semi-floating gate.

6. The method according to claim 1, It is characterized in that The step of forming an inter-gate dielectric layer and a control gate layer in the plurality of first grooves, and forming a connection improvement layer on the control gate layer, comprises: forming the inter-gate dielectric layer, wherein the inter-gate dielectric layer at least covers the semi-floating gate; Covering the inter-gate dielectric layer with a third gate material, wherein the third gate material is flush with the highest point of the first groove; Removing part of the third gate material in the first groove, and using the remaining third gate material as the control gate layer, wherein the upper surface of the control gate layer is higher than the upper surface of the substrate groove; The connection improving layer is formed on the control gate layer.

7. The method according to claim 6, It is characterized in that Also includes: Removing a portion of the third gate material in the first groove to form a vacant area, and forming a second insulating layer in the vacant area; An isolation sidewall is formed to cover the sidewall of the second insulating layer and the sidewall of the control gate layer.

8. The method according to claim 7, It is characterized in that Also includes: Performing ion implantation on the substrate to form a source electrode and a drain electrode respectively; forming a connection improvement layer located on the source electrode, the drain electrode and the control gate layer; An interlayer dielectric layer is formed to cover the connection improvement layer and the isolation sidewall, and a control gate lead-out structure is formed in the interlayer dielectric layer, wherein the control gate lead-out structure is located in the lead-out region.

9. A memory device, It is characterized in that include: substrate; Base grooves, a plurality of base grooves are opened from the surface of the substrate toward the substrate, and a part of the plurality of base grooves is located in the storage area, and a part of the plurality of base grooves is located in the lead-out area; A gate insulating layer and a semi-floating gate are formed in the substrate groove, wherein a portion of the semi-floating gate is in contact with the substrate, and another portion of the semi-floating gate is isolated from the substrate by the gate insulating layer; An inter-gate dielectric layer and a control gate layer, wherein the inter-gate dielectric layer covers the semi-floating gate, and the control gate layer is arranged on the inter-gate dielectric layer; The connection improvement layer covers the control gate layer, wherein the control gate layer in the storage area serves as the control gate of the storage unit, and the control gate layer in the lead-out area serves as the lead-out end of the storage unit, and the lead-out end is connected to the control gates of multiple storage units in the same row.

10. The memory device according to claim 9, It is characterized in that At least the contact portion between the semi-floating gate and the substrate is made of single crystal material.

11. The memory device according to claim 9, It is characterized in that The upper surface of the semi-floating gate is not higher than the upper surface of the substrate groove.

12. The memory device according to claim 9, It is characterized in that A shallow trench isolation structure is formed in the substrate, and the shallow trench isolation structure is arranged at intervals along the second direction and extends along the first direction; wherein the shallow trench isolation structure includes a first isolation part and a second isolation part arranged at intervals, the first isolation part is arranged in the substrate, and the second isolation part protrudes from the substrate; the control gate and the lead-out terminal are connected through the control gate layer on the first isolation part.

13. The memory device according to claim 9, It is characterized in that In the second direction, at least one corresponding lead-out terminal is provided for every preset number of control grids, and the lead-out terminal is used as a connection point to realize the connection between the control grids in the same row and the outside world.

14. The memory device according to claim 9, It is characterized in that The upper surface of the control gate layer is higher than the upper surface of the substrate groove.

15. The memory device according to claim 9, It is characterized in that Also includes: a connection improving layer covering the substrate and the control gate layer; an interlayer dielectric layer, covering the connection improving layer; A control gate lead-out structure is located in the interlayer dielectric layer in the lead-out region, wherein the control gate lead-out structure is connected to the lead-out terminal.

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