Manufacturing method of MOS (Metal Oxide Semiconductor) device

Abstract

The invention provides a manufacturing method of a metal oxide semiconductor (MOS) device, which improves the stability of threshold voltage of a product by reducing dangling bonds of a silicon nitride layer in a self-aligned silicide barrier layer, according to the mode of reducing dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer, the annealing step used for activating ions in the source-drain injection region can be adjusted to be before the silicon nitride layer is formed, and N-H bonds in the silicon nitride layer are prevented from being damaged by high temperature in the annealing process, so that the dangling bonds are reduced; the mode of reducing dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer can also be that a forming method of the silicon nitride layer is changed from a PECVD (Plasma Enhanced Chemical Vapor Deposition) method to an LPCVD (Low Pressure Chemical Vapor Deposition) method, so that N-H bonds in the silicon nitride layer are reduced from the source, and the dangling bonds generated due to breakage of the N-H bonds are further reduced. In addition, the two modes can be adopted at the same time, that is, the annealing step is preposed, the silicon nitride is formed through the LPCVD method, and the threshold voltage drift range can be further improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a method for manufacturing a MOS device. Background Art

[0002] Threshold voltage (Vt) is one of the important parameters of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). For MOS tubes, when the device changes from depletion to inversion, it will experience a state where the electron concentration on the silicon (Si) surface is equal to the hole concentration. At this time, the device is in a critical conduction state, and the gate voltage of the device is defined as the threshold voltage. The threshold voltage of a MOS tube is equal to the gate-to-source bias voltage required to form a channel when the back gate and the source are connected together. If the gate-to-source bias voltage is less than the threshold voltage, there will be no channel.

[0003] The stability of the threshold voltage of a MOS device is an important indicator for evaluating its performance. The smaller the drift of the threshold voltage Vt with changes in physical conditions, the more reliable the performance of the MOS device. Since there are some free dangling bonds on the surface of the manufactured MOS device, these dangling bonds will cause the stability of the threshold voltage Vt to decrease with changes in physical conditions in the actual application environment. Therefore, in the wafer manufacturing plant, the manufactured MOS device needs to be subjected to high-temperature treatment to simulate the actual application environment in order to test the stability of the threshold voltage Vt in the actual working environment. The test steps are as follows: first test the initial Vt value, recorded as Vt(0); then, place the MOS device to be tested in a high-temperature furnace and bake it at a high temperature of 150°C for 168 hours; then test the Vt value, recorded as Vt(168), and the Vt drift Vtshift can be calculated using the following formula: Vtshift = [Vt(168)-Vt(0)] / Vt(0). The smaller the drift Vt shift is, the better the working stability of the MOS device is and the higher the reliability is. When the Vt shift is greater than a predetermined value, the MOS device fails and its performance does not meet the requirements.

[0004] Generally, after the MOS device is manufactured, an alloying step is required to improve the stability of the device. The alloying step mainly involves placing the MOS device in a high temperature environment and introducing a mixture of hydrogen and nitrogen to allow hydrogen ions to combine with free dangling bonds in the device to form a stable form. At the same time, the stress between the device and the metal layer, the metal layer and the wire layer, etc. is released, thereby improving the stability of the device. However, the threshold voltage stability of the MOS device processed by the existing method is not high, and the Vt drift is high, which seriously affects the yield of the product.

[0005] In addition, generally speaking, when dealing with threshold voltage-related issues, certain parameters of ion implantation will be adjusted, or the device channel will be enlarged or reduced accordingly, but such changes will increase the risk of wafer fabrication.

[0006] Therefore, how to improve the stability of product threshold voltage has become an important technical problem that technical personnel in this field need to solve urgently.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for manufacturing a MOS device, so as to solve the problem in the prior art that the stability of the threshold voltage of the product needs to be improved.

[0009] To achieve the above object and other related objects, the present invention provides a method for manufacturing a MOS device, comprising the following steps:

[0010] Providing a semiconductor layer, and forming a gate structure on the semiconductor layer;

[0011] Performing ion implantation to form source-drain implantation regions in the semiconductor layer on both sides of the gate structure;

[0012] forming a silicon oxide self-aligned silicide barrier layer on the semiconductor layer, wherein the silicon oxide self-aligned silicide barrier layer covers the gate structure;

[0013] Performing annealing to activate ions in the source-drain implantation region;

[0014] A silicon nitride salicide barrier layer is formed on the silicon oxide salicide barrier layer.

[0015] Optionally, the thickness of the silicon nitride self-aligned silicide barrier layer is in the range of 300 angstroms to 500 angstroms, and the method for forming the silicon nitride self-aligned silicide barrier layer comprises a plasma enhanced chemical vapor deposition method, and the source gas used in forming the silicon nitride self-aligned silicide barrier layer comprises SiH 4 With NH 3 .

[0016] Optionally, a method of forming the silicon nitride salicide barrier layer includes a low pressure chemical vapor deposition method.

[0017] Optionally, the thickness of the silicon nitride self-aligned silicide barrier layer is in the range of 300 angstroms to 500 angstroms, and the source gas used to form the silicon nitride self-aligned silicide barrier layer includes Cl 6 Si 2 With NH 3 , the carrier gas used includes N 2 , Cl 6 Si 2 The flow rate range is 30sccm-50sccm, NH 3 The flow rate range is 1600sccm-2000sccm, N 2 The flow rate range is 100sccm-400sccm, the reaction temperature range is 500℃-700℃, and the gas pressure range in the reaction chamber is 0.1T-0.5T.

[0018] Optionally, the thickness of the silicon oxide self-aligned silicide barrier layer is in the range of 50 angstroms to 120 angstroms, and the source gas used to form the silicon oxide self-aligned silicide barrier layer includes TEOS and O 3 , the flow rate range of TEOS is 100sccm-200sccm, O 3 The flow rate range is 15000sccm-20000sccm, the reaction temperature range is 300℃-500℃, and the gas pressure range in the reaction chamber is 20T-40T.

[0019] Optionally, the annealing method includes rapid thermal annealing, the annealing temperature ranges from 900° C. to 1100° C., and the annealing time ranges from 5 seconds to 30 seconds.

[0020] The present invention also provides a method for manufacturing a MOS device, comprising the following steps:

[0021] Providing a semiconductor layer, and forming a gate structure on the semiconductor layer;

[0022] Performing ion implantation to form source-drain implantation regions in the semiconductor layer on both sides of the gate structure;

[0023] forming a silicon oxide self-aligned silicide barrier layer on the semiconductor layer, wherein the silicon oxide self-aligned silicide barrier layer covers the gate structure;

[0024] Forming a silicon nitride self-aligned silicide barrier layer on the silicon oxide self-aligned silicide barrier layer by low pressure chemical vapor deposition;

[0025] Annealing is performed to activate ions in the source / drain implantation regions.

[0026] Optionally, the thickness of the silicon nitride self-aligned silicide barrier layer is in the range of 300 angstroms to 500 angstroms, and the source gas used to form the silicon nitride self-aligned silicide barrier layer includes Cl 6 Si 2 With NH 3 , the carrier gas used includes N 2 , Cl 6 Si 2 The flow rate range is 30sccm-50sccm, NH 3 The flow rate range is 1600sccm-2000sccm, N 2 The flow rate range is 100sccm-400sccm, the reaction temperature range is 500℃-700℃, and the gas pressure range in the reaction chamber is 0.1T-0.5T.

[0027] Optionally, the thickness of the silicon oxide self-aligned silicide barrier layer is in the range of 50 angstroms to 120 angstroms, and the source gas used to form the silicon oxide self-aligned silicide barrier layer includes TEOS and O 3 , the flow rate range of TEOS is 100sccm-200sccm, O 3 The flow rate range is 15000sccm-20000sccm, the reaction temperature range is 300℃-500℃, and the gas pressure range in the reaction chamber is 20T-40T.

[0028] Optionally, the annealing method includes rapid thermal annealing, the annealing temperature ranges from 900° C. to 1100° C., and the annealing time ranges from 5 seconds to 30 seconds.

[0029] As described above, the manufacturing method of the MOS device of the present invention improves the stability of the product threshold voltage by reducing the dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer, wherein the method of reducing the dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer can be to adjust the annealing step for activating the ions in the source and drain injection region to before the silicon nitride layer is formed, so as to avoid the high temperature of the annealing process from destroying the NH bonds in the silicon nitride layer, thereby reducing the generation of dangling bonds; the method of reducing the dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer can also be to change the formation method of the silicon nitride layer from the PECVD method to the LPCVD method, thereby reducing the NH bonds in the silicon nitride layer from the source, thereby reducing the dangling bonds generated by the breakage of the NH bonds. In addition, the present invention can also adopt the above two methods at the same time, that is, to adjust the annealing step for activating the ions in the source and drain injection region to before the silicon nitride layer is formed, and to change the formation method of the silicon nitride layer from the PECVD method to the LPCVD method, so as to further improve the threshold voltage drift range. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 FIG. 1 is a process flow chart of a method for manufacturing a MOS device of the present invention in one embodiment.

[0031] Figure 2 FIG. 1 is a schematic diagram showing a structure obtained after forming a gate structure on a semiconductor layer in an embodiment of a method for manufacturing a MOS device of the present invention.

[0032] Figure 3 The schematic diagram of the structure obtained after ion implantation is performed in one embodiment of the manufacturing method of the MOS device of the present invention to form source and drain implantation regions in the semiconductor layer on both sides of the gate structure.

[0033] Figure 4 FIG. 1 is a schematic diagram showing a structure obtained after a silicon oxide salicide barrier layer is formed on a semiconductor layer in an embodiment of a method for manufacturing a MOS device of the present invention.

[0034] Figure 5 The schematic diagram shows a structure obtained after a silicon nitride salicide barrier layer is formed on a silicon oxide salicide barrier layer in a method for manufacturing a MOS device according to an embodiment of the present invention.

[0035] Figure 6 FIG. 4 is a process flow chart of a method for manufacturing a MOS device of the present invention in another embodiment.

[0036] Figure 7 It shows the experimental effect comparison chart of the control group scheme, embodiment 1 scheme, embodiment 2 scheme and embodiment 3 scheme.

[0037] Description of Reference Numerals

[0038] Steps S101 to S105, S201 to S205

[0039] 1 Semiconductor layer

[0040] 2 Gate structure

[0041] 201 gate dielectric layer

[0042] 202 gate conductive layer

[0043] 3 Source and drain injection region

[0044] 4 Silicon oxide self-aligned silicide barrier layer

[0045] 5 Silicon Nitride Self-Aligned Salicide Barrier DETAILED DESCRIPTION

[0046] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] See also Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] Embodiment 1

[0049] The present invention provides a method for manufacturing a MOS device. Figure 1 , shown as a process flow chart of the method, comprising the following steps:

[0050] S101: providing a semiconductor layer, and forming a gate structure on the semiconductor layer;

[0051] S102: performing ion implantation to form source-drain implantation regions in the semiconductor layer on both sides of the gate structure;

[0052] S103: forming a silicon oxide self-aligned silicide barrier layer on the semiconductor layer, wherein the silicon oxide self-aligned silicide barrier layer covers the gate structure;

[0053] S104: performing annealing to activate ions in the source / drain implantation region;

[0054] S105: forming a silicon nitride salicide barrier layer on the silicon oxide salicide barrier layer.

[0055] Each step of the method for manufacturing the MOS device of the present invention is described in detail below with reference to the accompanying drawings.

[0056] First see Figure 2 , perform the step S101 : provide a semiconductor layer 1 , and form a gate structure 2 on the semiconductor layer 1 .

[0057] As an example, the semiconductor layer 1 may be a silicon substrate, a silicon germanium substrate, a silicon-on-insulator substrate or other suitable semiconductor substrates.

[0058] In one embodiment, the semiconductor layer 1 uses a P-type silicon substrate. Before forming the gate structure 2, it also includes an N-well ion implantation step and an N-well annealing step to obtain an N-well in the P-type silicon substrate. The gate structure 2 is formed above the N-well. The threshold voltage of the MOS transistor corresponding to the gate structure 2 is mainly determined by the doping concentration of the N-well. The specific doping concentration can be adjusted according to actual needs and is not specifically limited here.

[0059] As an example, the gate structure 2 includes a gate dielectric layer 201 and a gate conductive layer 202 formed on the gate dielectric layer 201 . The material of the gate dielectric layer 201 may be, for example, but not limited to, silicon oxide, and the material of the gate conductive layer 202 may be, for example, but not limited to, polysilicon.

[0060] As an example, it also includes the steps of forming a lightly doped drain (LDD) (not shown) in the semiconductor layer 1 on both sides of the gate structure 2 by ion implantation, and forming sidewalls (not shown) on both sides of the gate structure 2, wherein the doping type of the lightly doped drain is opposite to the doping type of the partial area of ​​the semiconductor layer 1 directly below the gate structure 2, for example, when the semiconductor layer 1 includes a P-type silicon substrate and an N-well located in the P-type silicon substrate, and the gate structure 2 is located on the N-well, the doping type of the lightly doped drain is opposite to the doping type of the N-well, which is P-type. The lightly doped drain serves as a low-doping extension area between the source and drain below the boundary of the gate, and forms an impurity concentration gradient between the source and drain and the channel, which is beneficial to reducing the peak electric field near the drain, thereby achieving the purpose of improving the HCI effect and device reliability.

[0061] Please see again Figure 3 , executing the step S102 : performing ion implantation to form source-drain implantation regions 3 in the semiconductor layer 1 on both sides of the gate structure 2 .

[0062] Specifically, the doping type of the source and drain injection regions 3 is opposite to the doping type of the partial region of the semiconductor layer 1 directly below the gate structure 2. For example, P-type ion implantation is performed in the N-well, and the dose of the P-type ion implantation is controlled so that the final source and drain regions (after activation) are heavily P-type doped. The specific doping dose can be adjusted according to the actual device, and no specific limitation is made here.

[0063] Please see again Figure 4 , performing the step S103 : forming a silicon oxide self-aligned silicide barrier layer 4 on the semiconductor layer 1 , wherein the silicon oxide self-aligned silicide barrier layer 4 covers the gate structure 2 .

[0064] Specifically, a salicide block layer (SAB) is used to protect the surface of the semiconductor layer 1. Under its protection, the silicon in the semiconductor layer 1 does not form undesirable metal silicides with other metals such as nickel (Ni), titanium (Ti), and cobalt (Co). The silicide block layer used in this embodiment includes the silicon oxide self-aligned silicide block layer 4. The role of the silicon oxide self-aligned silicide block layer 4 is to cooperate with the silicon nitride self-aligned silicide block layer formed subsequently to solve the problem of peeling caused by the large lattice constant of silicon nitride.

[0065] As an example, the thickness of the silicon oxide salicide barrier layer 4 is in the range of 50 angstroms to 120 angstroms. In one embodiment, the thickness of the silicon oxide salicide barrier layer 4 is 85 angstroms.

[0066] As an example, the silicon oxide self-aligned silicide barrier layer 4 is formed by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD), and the obtained silicon oxide layer has good coverage and uniformity.

[0067] As an example, the source gases used to form the silicon oxide self-aligned silicide barrier layer 4 include tetraethoxysilane (Tetraethoxysilane, referred to as TEOS) and ozone (O 3 ), where TEOS is a silicon organic compound with the chemical formula Si(OC 2 H 5 ) 4 , which means that one silicon atom is bonded to four ethoxy groups (OC 2 H 5) groups are connected, with the silicon atom at the center of these four groups, forming a geometric structure called a regular tetrahedron. In the present invention, TEOS is used as a silicon source for chemical vapor deposition of silicon oxide.

[0068] Specifically, TEOS and O 3 The reaction formula for obtaining silicon oxide is: TEOS+O 3 →SiO 2 .

[0069] As an example, the flow rate range of TEOS is 100 sccm-200 sccm. 3 The flow rate range is 15000sccm-20000sccm, the reaction temperature range is 300℃-500℃, and the pressure range in the reaction chamber is 20T-40T. In one embodiment, the flow rate of TEOS is 160sccm, O 3 The range is 17500sccm, the reaction temperature is 400℃, and the gas pressure in the reaction chamber is 30F.

[0070] Next, the step S104 is performed: annealing is performed to activate the ions in the source-drain implantation region 3 .

[0071] Specifically, when ion implantation is performed in the aforementioned step S102 to form the source-drain implantation region 3 , the ion implantation will knock atoms out of the lattice structure. The annealing in this step can repair the lattice and activate the ion implanted elements.

[0072] As an example, the annealing method includes rapid thermal annealing (RTA), the annealing temperature range is 900° C.-1100° C., and the annealing time range is 5 seconds-30 seconds. In one embodiment, the annealing includes maintaining the structure obtained in step S103 at 1015° C. for 10 seconds.

[0073] Please see again Figure 5 , executing the step S105: forming a silicon nitride salicide blocking layer 5 on the silicon oxide salicide blocking layer 4.

[0074] As an example, the thickness of the silicon nitride salicide barrier layer 5 is in the range of 300 angstroms to 500 angstroms. In one embodiment, the thickness of the silicon nitride salicide barrier layer 5 is 400 angstroms.

[0075] As an example, the method for forming the silicon nitride self-aligned silicide barrier layer 5 includes a plasma enhanced chemical vapor deposition method (PECVD), and the source gas used when forming the silicon nitride self-aligned silicide barrier layer 5 includes SiH 4 With NH 3 .

[0076] Specifically, SiH 4(e.g. 2% in the mixed gas) and NH 3 The silicon nitride film generated under the action of plasma mostly exists in the form of NH. The NH bond is easy to break in the subsequent high-temperature operation, resulting in the generation of dangling bonds. On the one hand, the dangling bonds are easy to cause the lattice to change, thereby affecting the input resistance Ri to become larger. On the other hand, the dangling bonds can generate more positive charges, thereby causing the threshold voltage to drift. In this embodiment, the annealing step for activating ions in the source and drain injection regions is adjusted to before the formation of the silicon nitride layer, which can avoid the high temperature of the annealing process from destroying the NH bonds in the silicon nitride layer, thereby reducing the generation of dangling bonds, which is conducive to improving the stability of the product threshold voltage and improving the yield.

[0077] Embodiment 2

[0078] This embodiment and the first embodiment adopt basically the same technical scheme, the difference being that in the first embodiment, after annealing is performed to activate the ions in the source-drain injection region 3, the PECVD method is used to form the silicon nitride self-aligned silicide barrier layer 5, while in this embodiment, after annealing is performed to activate the ions in the source-drain injection region 3, the LPCVD method is used to form the silicon nitride self-aligned silicide barrier layer 5.

[0079] As an example, the thickness of the silicon nitride salicide barrier layer 5 is in the range of 300 angstroms to 500 angstroms. In one embodiment, the thickness of the silicon nitride salicide barrier layer 5 is 400 angstroms.

[0080] As an example, the source gas used to form the silicon nitride self-aligned silicide barrier layer 5 by LPCVD includes hexachlorodisilane (Cl 6 Si 2 ) and ammonia (NH 3 ), the carrier gas used includes N 2 , Cl 6 Si 2 The flow rate range is 30sccm-50sccm, NH 3 The flow rate range is 1600sccm-2000sccm, N 2 The flow rate range is 100sccm-400sccm, the reaction temperature range is 500℃-700℃, and the gas pressure range in the reaction chamber is 0.1T-0.5T.

[0081] Specifically, Cl 6 Si 2 With NH 3 The reaction formula for the formation of silicon nitride is: 3Cl 6 Si 2 +4NH 3 +N 2 →Si 3 N 4+By-products.

[0082] In one embodiment, Cl 6 Si 2 The flow rate is 40sccm, NH 3 The flow rate is 1800sccm, N 2 The flow rate is 250sccm, the reaction temperature is 580℃, and the gas pressure range in the reaction chamber is 0.27T.

[0083] In this embodiment, based on the annealing step of the pre-source and drain injection regions in the first embodiment, the method for forming the silicon nitride self-aligned silicide barrier layer 5 is further adjusted from the PECVD method to the LPCVD method. Compared with the PECVD method, the silicon nitride self-aligned silicide barrier layer formed by the LPCVD method has a lower NH bond content, thereby reducing dangling bonds caused by the breaking of NH bonds, and further improving the threshold voltage drift range on the basis of the first embodiment.

[0084] Embodiment 3

[0085] This embodiment and the first embodiment adopt basically the same technical solution, the difference is that in the first embodiment, the generation of dangling bonds is reduced by advancing the annealing step for the source and drain injection regions before the step of forming the silicon nitride self-aligned silicide barrier layer 5 by the PECVD method, and avoiding the high temperature of the annealing process from destroying the NH bonds in the silicon nitride layer. In the present embodiment, without changing the process sequence (that is, the annealing step for the source and drain injection regions is still after the step of forming the silicon nitride self-aligned silicide barrier layer 5), the method of forming the silicon nitride self-aligned silicide barrier layer 5 is adjusted from the PECVD method to the LPCVD method, which can also reduce the generation of dangling bonds, which is beneficial to improving the stability of the product threshold voltage and improving the yield.

[0086] For details, please refer to Figure 6 , which is a process flow chart of the method for manufacturing the MOS device in this embodiment, includes the following steps:

[0087] S201: providing a semiconductor layer, and forming a gate structure on the semiconductor layer;

[0088] S202: performing ion implantation to form source-drain implantation regions in the semiconductor layer on both sides of the gate structure;

[0089] S203: forming a silicon oxide self-aligned silicide barrier layer on the semiconductor layer, wherein the silicon oxide self-aligned silicide barrier layer covers the gate structure;

[0090] S204: forming a silicon nitride self-aligned silicide barrier layer on the silicon oxide self-aligned silicide barrier layer by using a low pressure chemical vapor deposition method;

[0091] S205: performing annealing to activate ions in the source / drain implantation region.

[0092] As an example, in this embodiment, the thickness of the silicon oxide self-aligned silicide barrier layer is in the range of 50 angstroms to 120 angstroms, and the source gas used to form the silicon oxide self-aligned silicide barrier layer includes TEOS and O 3 , the flow rate range of TEOS is 100sccm-200sccm, O 3 The flow rate range is 15000sccm-20000sccm, the reaction temperature range is 300℃-500℃, and the pressure range in the reaction chamber is 20T-40T. The thickness range of the silicon nitride self-aligned silicide barrier layer is 300 angstroms-500 angstroms. The source gas used to form the silicon nitride self-aligned silicide barrier layer includes Cl 6 Si 2 With NH 3 , the carrier gas used includes N 2 , Cl 6 Si 2 The flow rate range is 30sccm-50sccm, NH 3 The flow rate range is 1600sccm-2000sccm, N 2 The flow rate range is 100sccm-400sccm, the reaction temperature range is 500℃-700℃, and the pressure range in the reaction chamber is 0.1T-0.5T. After the silicon nitride self-aligned silicide barrier layer is formed by low-pressure chemical vapor deposition, the annealing method for the source and drain injection region includes rapid thermal annealing, the annealing temperature range is 900℃-1100℃, and the annealing time range is 5 seconds-30 seconds.

[0093] As an example, see Figure 7, which is a comparison diagram of the experimental effects of the control group scheme (silicon oxide + PECVD silicon nitride + annealing), the first embodiment scheme (silicon oxide + annealing + PECVD silicon nitride), the second embodiment scheme (silicon oxide + annealing + LPCVD silicon nitride) and the third embodiment scheme (silicon oxide + LPCVD silicon nitride + annealing). It can be seen that compared with the control group scheme, neither the source and drain injection region annealing step is performed in advance, nor the method for forming the silicon nitride self-aligned silicide barrier layer is adjusted from the PECVD method to the LPCVD method, the threshold voltage range is improved compared with the control group scheme by adopting the first embodiment scheme (pre-annealing the source and drain injection region) or the third embodiment scheme (adjusting the method for forming the silicon nitride self-aligned silicide barrier layer from the PECVD method to the LPCVD method), and the threshold voltage drift range is less than 50 mV, and the threshold voltage drift range is further improved by adopting the second embodiment scheme (both the source and drain injection region annealing step is performed in advance, and the method for forming the silicon nitride self-aligned silicide barrier layer is adjusted from the PECVD method to the LPCVD method).

[0094] In summary, the manufacturing method of the MOS device of the present invention improves the stability of the product threshold voltage by reducing the dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer, wherein the method of reducing the dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer can be to adjust the annealing step for activating the ions in the source and drain injection region to before the silicon nitride layer is formed, so as to avoid the high temperature of the annealing process from destroying the NH bonds in the silicon nitride layer, thereby reducing the generation of dangling bonds; the method of reducing the dangling bonds of the silicon nitride layer in the self-aligned silicide barrier layer can also be to change the formation method of the silicon nitride layer from the PECVD method to the LPCVD method, thereby reducing the NH bonds in the silicon nitride layer from the source, thereby reducing the dangling bonds generated by the breakage of the NH bonds. In addition, the present invention can also adopt the above two methods at the same time, that is, to adjust the annealing step for activating the ions in the source and drain injection region to before the silicon nitride layer is formed, and to change the formation method of the silicon nitride layer from the PECVD method to the LPCVD method, so as to further improve the threshold voltage drift range. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0095] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a MOS device, It is characterized in that The following steps are involved: Providing a semiconductor layer, and forming a gate structure on the semiconductor layer; Performing ion implantation to form source-drain implantation regions in the semiconductor layer on both sides of the gate structure; forming a silicon oxide self-aligned silicide barrier layer on the semiconductor layer, wherein the silicon oxide self-aligned silicide barrier layer covers the gate structure; Performing annealing to activate ions in the source-drain implantation region; A silicon nitride salicide barrier layer is formed on the silicon oxide salicide barrier layer.

2. The method for manufacturing a MOS device according to claim 1, Features: The thickness of the silicon nitride self-aligned silicide barrier layer is in the range of 300 angstroms to 500 angstroms. The method for forming the silicon nitride self-aligned silicide barrier layer includes a plasma enhanced chemical vapor deposition method. The source gas used in forming the silicon nitride self-aligned silicide barrier layer includes SiH 4 With NH 3 .

3. The method for manufacturing a MOS device according to claim 1, Features: The method of forming the silicon nitride salicide barrier layer includes a low pressure chemical vapor deposition method.

4. The method for manufacturing a MOS device according to claim 3, Features: The thickness of the silicon nitride self-aligned silicide barrier layer is in the range of 300 angstroms to 500 angstroms. The source gas used to form the silicon nitride self-aligned silicide barrier layer includes Cl 6 Si 2 With NH 3 , the carrier gas used includes N 2 , Cl 6 Si 2 The flow rate range is 30sccm-50sccm, NH 3 The flow rate range is 1600sccm-2000sccm, N 2 The flow rate range is 100sccm-400sccm, the reaction temperature range is 500℃-700℃, and the gas pressure range in the reaction chamber is 0.1T-0.5T.

5. The method for manufacturing a MOS device according to claim 1, Features: The thickness of the silicon oxide self-aligned silicide barrier layer is in the range of 50 angstroms to 120 angstroms. The source gas used to form the silicon oxide self-aligned silicide barrier layer includes TEOS and O 3 , the flow rate range of TEOS is 100sccm-200sccm, O 3 The flow rate range is 15000sccm-20000sccm, the reaction temperature range is 300℃-500℃, and the gas pressure range in the reaction chamber is 20T-40T.

6. The method for manufacturing a MOS device according to claim 1, Features: The annealing method includes rapid thermal annealing, the annealing temperature range is 900° C.-1100° C., and the annealing time range is 5 seconds-30 seconds.

7. A method for manufacturing a MOS device, It is characterized in that The following steps are involved: Providing a semiconductor layer, and forming a gate structure on the semiconductor layer; Performing ion implantation to form source-drain implantation regions in the semiconductor layer on both sides of the gate structure; forming a silicon oxide self-aligned silicide barrier layer on the semiconductor layer, wherein the silicon oxide self-aligned silicide barrier layer covers the gate structure; Forming a silicon nitride self-aligned silicide barrier layer on the silicon oxide self-aligned silicide barrier layer by low pressure chemical vapor deposition; Annealing is performed to activate ions in the source / drain implantation regions.

8. The method for manufacturing a MOS device according to claim 7, Features: The thickness of the silicon nitride self-aligned silicide barrier layer is in the range of 300 angstroms to 500 angstroms. The source gas used to form the silicon nitride self-aligned silicide barrier layer includes Cl 6 Si 2 With NH 3 , the carrier gas used includes N 2 , Cl 6 Si 2 The flow rate range is 30sccm-50sccm, NH 3 The flow rate range is 1600sccm-2000sccm, N 2 The flow rate range is 100sccm-400sccm, the reaction temperature range is 500℃-700℃, and the gas pressure range in the reaction chamber is 0.1T-0.5T.

9. The method for manufacturing a MOS device according to claim 7, Features: The thickness of the silicon oxide self-aligned silicide barrier layer is in the range of 50 angstroms to 120 angstroms. The source gas used to form the silicon oxide self-aligned silicide barrier layer includes TEOS and O 3 , the flow rate range of TEOS is 100sccm-200sccm, O 3 The flow rate range is 15000sccm-20000sccm, the reaction temperature range is 300℃-500℃, and the gas pressure range in the reaction chamber is 20T-40T.

10. The method for manufacturing a MOS device according to claim 7, Features: The annealing method includes rapid thermal annealing, the annealing temperature range is 900° C.-1100° C., and the annealing time range is 5 seconds-30 seconds.

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