MOS element and preparation method thereof
By forming a P-type well region and HV N-type well region on the semiconductor substrate of the MOS device and adjusting its doping concentration, the problem that the P/N junction cannot withstand the burn caused by large current during the ESD phenomenon of the MOS device is solved, and the effect of improving the collapse voltage and improving the ESD capability is achieved.
Patent Information
- Application Number
- CN202311537495.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-16
- Publication Date
- 2025-05-23
AI Technical Summary
During the ESD phenomenon of existing MOS devices, the P/N junction cannot withstand high currents and lead to burning. The existing solutions may change the electrical parameters of the chip and affect reliability.
By forming a P-type well region and an HV N-type well region on the semiconductor substrate, and implanting a low-doping concentration of N-type ions into the HV N-type well region, and implanting a conventional doping concentration of P-type ions into the P-type well region, adjusting the doping concentration of the P/N junction to increase the collapse voltage.
The P/N junction collapse voltage of MOS devices is improved, its ESD capability is improved, and the burning problem caused by high ESD current is avoided, while the electrical parameters of the chip are not changed.
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Figure CN120035184A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a MOS element and a preparation method thereof. Background Art
[0002] Electrostatic discharge (ESD) is one of the main factors that cause most chips to be damaged by excessive electrical stress. ESD is currently divided into two categories: chip-level ESD and system-level ESD. Chip-level ESD is divided into the following four categories: human body mode (HBM), machine mode (MM), component charge mode (CDM) and field induced mode (FIM); system-level ESD is mainly divided into two categories: contact mode and air mode.
[0003] In general ESD protection circuits, GDPMOS or GGNMOS are commonly used to protect the internal circuits of the chip from ESD damage, and the commonly used ESD MOS is often "off" when the circuit is working normally. Figure 1 As shown in the figure, taking GDPMOS as an example, when used in ESD circuits, the source (S), gate (G) and body (B) of PMOS need to be short-circuited to VDD. Due to the parasitic effect that the source and body of ESD MOS are connected to the same power supply voltage, the insufficient P / N junction breakdown voltage generated in the middle of MOS is generally ignored when designing P-well and N-well. The large substrate avalanche current will trigger the conduction of parasitic BJT, which will cause the body, guard ring and internal MOS device to burn out.
[0004] When an ESD phenomenon occurs, the parasitic BJT in the ESD MOS will be triggered by the pulse current to turn on and burn the chip. The chip damage comes from the large ESD current flowing through the P / N junction (located on the ESD discharge path), but the P / N junction cannot withstand the large ESD current and causes burning. The existing solutions to this ESD-induced burning effect are mostly to change the doping concentration of the well and adjust the depth of the STI, but this may change the electrical parameters of the chip and affect the reliability of the chip. Therefore, it is necessary to find a way to increase the P / N junction breakdown voltage of the MOS device. Summary of the invention
[0005] The object of the present invention is to provide a MOS element and a method for preparing the same, so as to improve the P / N junction breakdown voltage of the MOS element.
[0006] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a MOS element, which includes a semiconductor substrate, a P-type well region and an HV N-type well region formed in the semiconductor substrate, an STI region located between the P-type well region and the HV N-type well region, a gate located on the surface of the semiconductor substrate, and a source region and a drain region formed in the P-type well region or the HV N-type well region.
[0007] Optionally, the P-type well region has a P-type doping concentration, and the HV N-type well region has an N-type doping concentration.
[0008] Optionally, the gate is located between the source region and the drain region.
[0009] Optionally, the source region and the drain region have P-type impurities or N-type impurities.
[0010] Optionally, the semiconductor substrate is a P-type substrate or an N-type substrate.
[0011] A second aspect of the present invention provides a method for preparing a MOS element, the method comprising the following steps:
[0012] forming an STI structure on a semiconductor substrate;
[0013] Forming a P-type well region and a HV N-type well region by ion implantation on a semiconductor substrate having an STI structure; N-type ions are implanted into the HV N-type well region, and P-type ions are implanted into the P-type well region, wherein the concentration of the N-type ions is lower than the concentration of the P-type ions;
[0014] A gate structure is formed on the P-type well region or the HV N-type well region, and a source region and a drain region are respectively formed on both sides of the gate structure.
[0015] Optionally, the N-type ion implantation conditions include: an implantation energy of 100-900 KeV, preferably 300-600 KeV; an implantation dose of 100×10 12 -500×10 13 atoms / cm 2 , preferably 300×10 12 -800×10 12 atoms / cm 2 .
[0016] Optionally, the implantation conditions of the P-type ions include: an implantation energy of 10-500 KeV, preferably 20-300 KeV; an implantation dose of 500×10 11 -600×10 12 atoms / cm 2 , preferably 600×10 11 -400×10 12 atoms / cm 2 .
[0017] Optionally, the method further comprises: before forming the STI structure on the semiconductor substrate, forming an oxide layer on the surface of the semiconductor substrate, and depositing a barrier layer on the surface of the oxide layer.
[0018] Optionally, the STI structure is formed by a method comprising the following steps: using the barrier layer as a mask, sequentially applying photoresist, exposing and developing, then etching to form grooves, and depositing oxide in the grooves to form the STI structure.
[0019] Optionally, the P-type well region and the HV N-type well region are formed by a method comprising the following steps: forming a sacrificial oxide layer on the semiconductor substrate having the STI structure; performing photolithography, development, and ion implantation on the surfaces of the P-type well region and the HV N-type well region; removing the sacrificial oxide layer, and annealing the P-type well region and the HV N-type well region.
[0020] Through the above technical scheme, the MOS element of the present invention contains a P-type well region and a HV N-type well region. By injecting N-type ions with a low doping concentration into the HV N-type well region and injecting P-type ions with a normal doping concentration into the P-type well region, the P / N junction concentration can be adjusted to increase its breakdown voltage, thereby improving its ESD capability.
[0021] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention, but do not constitute a limitation of the present invention. In the accompanying drawings:
[0023] Figure 1 This is the ESD circuit diagram of GDPMOS and GGNMOS devices;
[0024] Figure 2 It is a structural diagram of the breakdown voltage occurring at the P / N junction;
[0025] Figure 3 This is the layout diagram of the GDPMOS device;
[0026] Figure 4 This is a picture of the internal burnout of the GDPMOS device caused by ESD phenomenon;
[0027] Figure 5 It is a schematic diagram of the cross-sectional structure of the existing PMOS and the PMOS of the present invention;
[0028] Figure 6 It is a schematic diagram of the structure of an existing MOS component;
[0029] Figure 7 It is a schematic diagram of the structure of the MOS element of the present invention;
[0030] Figure 8It is a schematic diagram of the circuit structure of the existing MOS element and the MOS element of the present invention;
[0031] Fig. 9 It is the electric field diagram of the PN junction in the space charge region.
[0032] Description of Reference Numerals
[0033] 100 - semiconductor substrate; 101 - P-type well region; 102 - HV N-type well region; 103 - source region; 104 - drain region; 105 - STI; 106 - gate; 107 - N-type well region. DETAILED DESCRIPTION
[0034] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.
[0035] Because the large ESD current flows through the P / N junction (located on the ESD discharge path), the P / N junction cannot withstand the large ESD current and causes the device to burn out (such as Figure 2-4 As shown in FIG. 1 , it is necessary to increase the breakdown voltage of the P / N junction to improve the damage caused by ESD and improve the ESD capability. Figure 5 As shown, the breakdown voltage of the MOS device can be improved by adjusting the doping concentration of the P / N junction.
[0036] A first aspect of the present invention provides a MOS element, such as Figure 7 As shown, the MOS element includes a semiconductor substrate 100, a P-type well region 101 and a HV N-type well region 102 formed in the semiconductor substrate 100, an STI 105 region located between the P-type well region 101 and the HV N-type well region 102, a gate 106 located on the surface of the semiconductor substrate 100, and a source region 103 and a drain region 104 formed in the P-type well region 101 or the HV N-type well region 102.
[0037] According to the present invention, optionally, the P-type well region has a P-type doping concentration, and the HV N-type well region has an N-type doping concentration. The P-type doping concentration may range from 500×10 11 -600×10 12 atoms / cm 2 , the HV N-type doping concentration range can be 100×10 12 -500×10 13 atoms / cm 2 .
[0038] In the present invention, P-type doping forms a P-type semiconductor, and N-type doping forms an N-type semiconductor. P-type semiconductor refers to an intrinsic semiconductor doped with boron (B) or indium (In). P-type semiconductor is also called hole-type semiconductor, which is a semiconductor that mainly conducts electricity with positively charged holes. Since these trivalent elements are surrounded by 3 valence electrons, one electron is missing when forming a covalent bond with the surrounding 4-valent silicon atoms, forming a hole, which replaces the position of the silicon atom in the lattice; in P-type semiconductors, holes are majority carriers and free electrons are minority carriers. Holes are equivalent to positively charged particles and play a major role in the conduction of this type of semiconductor. N-type semiconductor refers to an intrinsic semiconductor doped with phosphorus (P), arsenic (As) or antimony (Sb) as impurities. N-type semiconductors conduct electricity by electrons. After trace amounts of phosphorus, arsenic, antimony and other elements are doped into semiconductor materials, many negatively charged electrons will be generated in the semiconductor materials. When a P-type semiconductor and an N-type semiconductor come into contact, due to the different types and concentrations of doped atoms in the two semiconductors, diffusion movement of electrons and holes will occur. Due to the diffusion movement of electrons and holes, a potential difference is formed between the P-type semiconductor and the N-type semiconductor, and an electric field is generated (such as Fig. 9 As shown in the figure). From the following electric field formula, we can know that the PN junction electric field is related to the doping concentration (N a &N d ), so the present invention reduces the ion concentration injected into the HV N-type well region, which can improve its maximum electric field and further increase its breakdown voltage.
[0039]
[0040] According to the present invention, optionally, the gate is located between the source region and the drain region. The source region and the drain region have P-type impurities or N-type impurities. If the well is an N-well, the source region and the drain region are implanted with P-type impurities, and if the well is a P-well, the source region and the drain region are implanted with N-type impurities.
[0041] According to the present invention, optionally, the semiconductor substrate is a silicon substrate, and the silicon substrate can be a wafer of common size, such as 4 inches, 6 inches, 8 inches or 12 inches. Before use, the silicon substrate is cleaned with a mixed solution of concentrated sulfuric acid and hydrogen peroxide to remove impurities and organic matter on the surface.
[0042] According to the present invention, optionally, the semiconductor substrate is a P-type substrate or an N-type substrate, and its specific doping concentration is not limited by the present invention. In a preferred embodiment of the present invention, the semiconductor substrate is a P-type substrate.
[0043] A second aspect of the present invention provides a method for preparing a MOS element, the method comprising the following steps:
[0044] forming an STI structure on a semiconductor substrate;
[0045] Forming a P-type well region and a HV N-type well region by ion implantation on a semiconductor substrate having an STI structure; N-type ions are implanted into the HV N-type well region, and P-type ions are implanted into the P-type well region, wherein the concentration of the N-type ions is lower than the concentration of the P-type ions;
[0046] A gate structure is formed on the P-type well region or the HV N-type well region, and a source region and a drain region are respectively formed on both sides of the gate structure.
[0047] According to the present invention, optionally, the N-type ions are phosphorus ions, arsenic ions or antimony ions; the implantation conditions of the N-type ions include: an implantation energy of 100-900 KeV, preferably 300-600 KeV; an implantation dose of 100×10 12 -500×10 13 atoms / cm 2 , preferably 300×10 12 -800×10 12 atoms / cm 2 .
[0048] According to the present invention, optionally, the P-type ions are boron ions, aluminum ions or indium ions; the implantation conditions of the P-type ions include: an implantation energy of 10-500 KeV, preferably 20-300 KeV; an implantation dose of 500×10 11 -600×10 12 atoms / cm 2 , preferably 600×10 11 -400×10 12 atoms / cm 2 .
[0049] According to the present invention, optionally, the method further comprises: before forming the STI structure on the semiconductor substrate, forming an oxide layer on the surface of the semiconductor substrate, and depositing a barrier layer on the surface of the oxide layer. The oxide layer may be a silicon dioxide layer, and the barrier layer may be a silicon nitride layer.
[0050] According to the present invention, optionally, the STI structure is formed by a method comprising the following steps: using the barrier layer as a mask, sequentially applying photoresist, exposing and developing, then etching to form a groove, and depositing oxide in the groove to form the STI structure. The oxide may be silicon dioxide.
[0051] According to the present invention, optionally, the P-type well region and the HV N-type well region are formed by a method comprising the following steps: forming a sacrificial oxide layer on the semiconductor substrate having the STI structure; performing photolithography, development, and ion implantation on the surface of the P-type well region and the HV N-type well region; removing the sacrificial oxide layer, and annealing the P-type well region and the HV N-type well region. The present invention uses a standard well implantation process to form a P-type well region and a HV N-type well region in a semiconductor substrate. For example, the P-type well region and the HV N-type well region can be formed by a high-energy implantation process, or by a low-energy implantation combined with a high-temperature thermal annealing process to form the P-type well region and the HV N-type well region.
[0052] According to the present invention, optionally, a dielectric layer is formed on the semiconductor substrate having the well region after thermal growth, and the dielectric layer may be SiO 2 , or other suitable oxides, a layer of polysilicon is formed on the dielectric layer, and then part of the polysilicon is removed by doping, alignment and etching, thereby forming a polysilicon gate structure. The deposition method of the polysilicon layer can be chemical vapor deposition (CVD), physical vapor deposition (PVD) or plasma enhanced chemical vapor deposition (PECVD), etc. In order to obtain better electrical properties, impurity particles are usually doped in the polysilicon material. The etching process of the polysilicon layer and the dielectric layer is a conventional technology well known to those skilled in the art, for example: forming a photoresist on the polysilicon layer, and then using exposure and development processes to remove the photoresist on the set area to form a photoresist opening, and finally using the photoresist as a mask to sequentially etch the polysilicon layer and the dielectric layer, thereby completing the preparation of the polysilicon gate structure. A source region and a drain region are respectively formed on both sides of the polysilicon gate structure. If the well is an N-well, P-type impurities are implanted in the source region and the drain region. If the well is a P-well, N-type impurities are implanted in the source region and the drain region. The doping concentrations of the source region and the drain region can be the same, and the doping concentration range can be the commonly used doping concentrations of the source region and the drain region.
[0053] According to the present invention, optionally, Figure 8 As shown, an interlayer dielectric layer is deposited on a semiconductor substrate, and corresponding through holes are formed on the interlayer dielectric layer. Metals are introduced into the corresponding through holes to connect the gate, source region, drain region with the corresponding gate G, source S, and drain D. The steps of depositing a dielectric layer, etching contact holes, depositing a metal layer in the contact holes, etching metal wires, and passivation are all well-known technical means to those skilled in the art, and will not be described in detail here.
[0054] According to the present invention, optionally, Figure 8As shown, the working principle of the MOS element of the present invention is: when a large current flows into the MOS from the external circuit, since the MOS source (S), gate (G) and body (B) need to be short-circuited to VDD in the ESD circuit, parasitic effects will occur. The present invention ion-implants a well with a lighter doping concentration (such as HVNW) below the STI at the junction of the pickup and the peripheral guardring, reduces the concentration at the PN junction, improves its electric field, and increases its tolerable breakdown voltage. A large substrate avalanche current will not trigger the conduction of the parasitic BJT, thereby avoiding component burnout.
[0055] The present invention is further illustrated by the following examples, but the present invention is not limited thereto.
[0056] Example
[0057] A method for preparing a MOS element comprises the following steps:
[0058] S1, forming an oxide layer of silicon dioxide on the surface of a silicon substrate, and depositing a barrier layer of silicon nitride on the surface of the silicon dioxide;
[0059] S2, using the silicon nitride layer as a mask, sequentially applying photoresist, exposing and developing, then etching to form a groove, and depositing silicon dioxide in the groove to form an STI structure;
[0060] S3, forming a sacrificial oxide layer on the silicon substrate with the STI structure; performing photolithography, development, and ion implantation on the surface of the P-type well region and the HV N-type well region; implanting phosphorus ions into the HV N-type well region, and the implantation conditions of the phosphorus ions include: an implantation energy of 500 keV; an implantation dose of 600×10 12 atoms / cm 2 , boron ions are injected into the P-type well region. The injection conditions of boron ions include: injection energy of 400 keV; injection dose of 300×10 12 atoms / cm 2 ; removing the sacrificial oxide layer, and annealing the P-type well region and the HVN-type well region;
[0061] S4, forming SiO on the semiconductor substrate with the well region after thermal growth 2 layer, in the SiO 2 A layer of polysilicon is formed on the SiO2 layer by CVD, a photoresist is formed on the polysilicon layer, and then the photoresist on the set area is removed by exposure and development process to form a photoresist opening. Finally, the polysilicon layer and SiO2 are etched in sequence using the photoresist as a mask. 2 layer, thereby forming a polysilicon gate structure;
[0062] S5. Form a source region and a drain region on both sides of the polysilicon gate structure respectively, and implant P-type impurity boron ions into the source region and the drain region in the HV N-type well.
[0063] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.
[0064] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further describe various possible combinations.
[0065] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.
Claims
1. A MOS component, It is characterized in that The MOS element includes a semiconductor substrate, a P-type well region and an HV N-type well region formed in the semiconductor substrate, an STI region located between the P-type well region and the HV N-type well region, a gate located on the surface of the semiconductor substrate, and a source region and a drain region formed in the P-type well region or the HV N-type well region.
2. The MOS device according to claim 1, in, The P-type well region has a P-type doping concentration, and the HV N-type well region has an N-type doping concentration.
3. The MOS device according to claim 1, in, The gate is located between the source region and the drain region.
4. The MOS device according to claim 1, in, The source region and the drain region have P-type impurities or N-type impurities.
5. The MOS device according to claim 1, in, The semiconductor substrate is a P-type substrate or an N-type substrate.
6. A method for preparing a MOS element, It is characterized in that The method comprises the following steps: forming an STI structure on a semiconductor substrate; Forming a P-type well region and a HV N-type well region by ion implantation on a semiconductor substrate having an STI structure; implanting N-type ions into the HV N-type well region and implanting P-type ions into the P-type well region; A gate structure is formed on the P-type well region or the HV N-type well region, and a source region and a drain region are respectively formed on both sides of the gate structure.
7. The method according to claim 6, in, The implantation conditions of the N-type ions include: an implantation energy of 100-900 KeV, preferably 300-600 KeV; an implantation dose of 100×10 12 -500×10 13 atoms / cm 2 , preferably 300×10 12 -800×10 12 atoms / cm 2 .
8. The method according to claim 6, in, The implantation conditions of the P-type ions include: an implantation energy of 10-500 keV, preferably 20-300 keV; an implantation dose of 500×10 11 -600×10 12 atoms / cm 2 , preferably 600×10 11 -400×10 12 atoms / cm 2 .
9. The method according to claim 6, in, The method further includes: before forming the STI structure on the semiconductor substrate, forming an oxide layer on the surface of the semiconductor substrate, and depositing a barrier layer on the surface of the oxide layer.
10. The method according to claim 9, in, The STI structure is formed by a method comprising the following steps: using the barrier layer as a mask, sequentially performing photoresist coating, exposure and development processing, then etching to form a groove, and depositing oxide in the groove to form the STI structure.
11. The method according to claim 6, in, The P-type well region and the HV N-type well region are formed by a method comprising the following steps: forming a sacrificial oxide layer on the semiconductor substrate having the STI structure; Performing photolithography, development, and ion implantation on the surfaces of the P-type well region and the HV N-type well region; The sacrificial oxide layer is removed, and the P-type well region and the HV N-type well region are annealed.